IV YEAR ELECTRONICS AND INSTRUMENTATION ENGINEERING

EC1461-VLSI Design (2mark questions and answers)

Unit I
1. Define Thresh !" # !t$ge The threshold voltage VT for a MOS transistor can be defined as the voltage between the gate and the source terminals below which the drain to source current effectively dro s to !ero" Define % "& effe't r s(%str$te %i$s effe't. The threshold voltage VT is not a constant with res ect to the voltage difference between the substrate and the source of the MOS transistor" This effect is called the body effect or substrate bias effect" ). Gi#e the "ifferent * "es f +er$ti n f MOS tr$nsist r #ut off mode $inear mode Saturation mode ,. -h$t $re the "ifferent regi ns f +er$ti n f $ MOS tr$nsist r. $. C(t ff regi n %ere the current flow is essentially !ero (accumulation mode) %. Line$r regi n &t is also called weak inversion region where the drain current is de endent on the gate and the drain voltage w" r" to the substrate" '. S$t(r$ti n regi n #hannel is strongly inverted and the drain current flow is ideally inde endent of the drain'source voltage (strong'inversion region)" 4. Gi#e the e/+ressi ns f r "r$in '(rrent f r "ifferent * "es +er$ti n f MOS tr$nsist r. a" #ut off region &( )* b" $inear region f

&( ) kn +(V,S - VT) V(S - V(S2.2/ c" Saturation region &( ) (kn .2) (V,S - VT)2 0. 1! t the '(rrent-# !t$ge 'h$r$'teristi's f $ nMOS tr$nsist r.

6. Define $''(*(!$ti n * "e. The initial distribution of mobile ositive holes in a ty e silicon substrate of a mos transistor for a voltage much less than the threshold voltage 2. -h$t $re the se' n"$r& effe'ts f MOS tr$nsist r. a" Threshold voltage variations b" Source to drain resistance c" Variation in &'V characteristics d" Subthreshold conduction e" #MOS latchu 3. -h$t is CMOS !$t'h(+. 4 5 it '$n %e +re#ente". The MOS technology contains a number of intrinsic bi olar transistors"These are es ecially troublesome in #MOS rocesses0 where the combination of wells and subtrates results in the formation of 'n' 'n

structures" Triggering these thyristor like devices leads to a shorting of V(( 1 VSS lines0 usually resulting in a destruction of the chi " The re*e"ies f r the !$t'h-(+ +r %!e* in'!("e6 (i) an increase in substrate do ing levels with a consequent dro in the value of 2 subs" (ii) reducing 2nwell by control of fabrication arameters and ensuring a low contact resistance to V((" (iii) by introducing guard rings" 7. -h$t $re the "ifferent f$%ri'$ti n +r 'esses $#$i!$%!e t CMOS te'hn ! g&. a" 'well rocess b" n'well rocess c" Twin'tub rocess d" Silicon On &nsulator (SO&) . Silicon On Sa hire (SOS) rocess 18. -h$t is intrinsi' $n" e/trinsi' se*i' n"('t r. The ure silicon is known as &ntrinsic Semiconductor" 3hen im urity is added with ure silicon0 it is electrical ro erties are varied" This is known as 45trinsic semiconductor" 1). -h$t $re the ste+s in# !#e" in *$n(f$'t(ring f IC. 66 i" wafer re aration ii" 4 ita5ial growth iii" O5idation iv" hoto lithogra hy v" (iffusion and &on &m lantation vi" &solation vii" Metalli!ation 1,. -h$t is *e$nt %& 9 e+it$/& : . 4 ita5y means arranging atoms in single crystal fashion u on a single crystal substrate" 14. 5h$t $re the +r 'ess in# !#e" in +h t !ith gr$+h&. i" making rocess ii" hoto etching rocess these are im ortant rocess involved in hotolithogra hy"

10. 5h$t is the +(r+ se f *$s;ing in f$%ri'$ti n f IC. Masking is used to identify the lace in which &on &m lantion should not be occurred" 16. 5h$t $re the *$teri$!s (se" f r *$s;ing. 7hoto resist0 Sio20 Si80 oly Silicon" 12.5h$t $re the t&+es f et'hing . 3et etching and dry etching are the ty es of hoto etching" 13. 5h$t is "iff(si n +r 'ess . 5h$t $re " +ing i*+(rities. (iffusion is a rocess in which im urities are diffused in to the silicon chi at 9****# tem erature" :2O; and 72O< are used as im urities" 17. 5h$t is is !$ti n. &t is a rocess used to rovide electrical isolation between different com onents and interconnections" )8. 5h$t $re the #$ri (s CMOS te'hn ! gies. Various #MOS technologies are i" n'well rocess or n'tub rocess ii" 'well rocess or 'tub rocess iii" twin'tub rocess iv" Silicon on &nsulator (SO&) rocess" )1. 5h$t is 'h$nne! st + i*+!$nt$ti n. &n n'well fabrication0 n'well is rotected with resist material" :ecause0 it should not be affected by :oron im lantation" The boron is im lane5ce t n'well" &t is done using hotoresist mask" This ty e of im lantation is known as channel im lantation" )). 5h$t is LOCS. $O#OS means $ocal O5idation Of Silicon" This is one ty e of o5ide construction" ),. 5h$t is S-AMI. S3=M& means Side 3all Masked &solation" &t is used to reduce bird>s beak effect"

)4. 5h$t is LDD. $(( means $ight (o ed (rain Structures" &t is used for im lantation of n' in n'well rocess" )0. 5h$t is t5in-t(% +r 'ess. -h& it is '$!!e" s . Twin'tub rocess is one of the #MOS technology" There are two wells are available in this rocess" The other name of well is tub" So0 because of these two tubs0 this rocess is known as twin'tub rocess"

Unit II
1. Dr$5 the 'ir'(it f $ nMOS in#erter.

" ). Gi#e the e/+ressi n f r +(!!-(+ t +(!!-" 5n r$ti < Zpu/Zpd= f r $n nMOS in#erter "ri#en %& $n ther nMOS in#erter.

" "

,. Dr$5 the 'ir'(it f $ CMOS in#erter.

4. -h$t $re the $"#$nt$ges f CMOS in#erter #er the ther in#erter ' nfig(r$ti ns. a" The steady state ower dissi ation of the #MOS inverter circuit is negligible" %. The voltage transfer characteristic (VT#) e5hibits a full out ut voltage wing between *V and V((" This results in high noise margin" 0. -h$t $re sti'; "i$gr$*s. Stick diagrams are used to convey layer information through the use of a color code" = stick diagram is a cartoon of a chi layout" They are not e5act models of layout" The stick diagram re resents the rectangles with lines which re resent wires and com onent symbols" 6. -h$t $re the "ifferent ' ! r ' "es (se" f r sing!e + !& si!i' n nMOS te'hn ! g&. n'diffusion (n'diff") and other thino5ide regions 'green 7olysilicon ( oly") ' red Metal 9 (metal) ' blue &m lant ' yellow #ontacts ' black or brown (buried) 2. -h$t $re "esign r(!es. (esign rules are the communication link between the designer s ecifying requirements and the fabricator who materiali!es them" (esign rules are used to roduce workable mask layouts from which the various layers in silicon will be formed or atterned"

3. Define $ s(+er%(ffer. = su erbuffer is a symmetric inverting or noninverting gate that can su ly or remove large currents and switch large ca acitive loads faster than a standard inverter" 7.-h$t $re >iCMOS G$tes. 3hen bi olar and MOS technology are merged0 the resulting circuits are referred to as bi#MOS circuits" %igh gain vertical n n transistors with their collectors tied to the ositive rail0 and medium'gain lateral n n transistors are both com atible with conventional #MOS rocessing" :i#MOS gates can be used to im rove the erformance of line drivers and sense am lifiers" 18. 5h$t is the s+e'i$! fe$t(re f t5in-t(% +r 'ess. &n twin'tub rocess0 threshold voltage0 body effect n and inde endently o timi!ed" 11. 5h$t $re the $"#$nt$ge f t5in-t(% +r 'ess. =dvantages of twin'tub rocess are i" Se arate o timi!ed wells are available" ii" :alance erformance is obtained for n and devices are

transistors"

1). 5h$t is SOI. -h$t is the *$teri$! (se" $s Ins(!$t r. SO& means Silicon'on'&nsulator" &n this rocess0 Sa hire or SiO2 is used as insulator" 1,. 5h$t $re the #$ri (s et'hing +r 'ess (se" in SOI +r 'ess. Various etching rocess used in SO& are i" &sotro ic etching rocess" ii" =nisotro ic etching rocess" iii" 7referential etching rocess" 14. 5h$t $re the $"#$nt$ges $n" "is$"#$nt$ges 8f SOI +r 'ess. A"#$nt$ges f SOI +r 'ess i" There is no well formation in this rocess" ii" There is no field'&nversion roblem"

iii" There is no body effect roblem" Dis$"#$nt$ges f SOI +r 'ess i" &t is very difficult to rotect in uts in this rocess" ii" (evice gain is low" iii" The cou ling ca acitance between wires always e5ist" 10. 5h$t $re the + ssi%!e * "es in nMOS enh$n'e*ent tr$nsist r. i" accumulation mode ii" de letion mode ii" &nversion mode 16. In s$t(r$ti n regi n? 5h$t $re the f$'t rs th$t $ffe't I"s. i" distancebetween source and drain" ii" channel width iii"Threshold oltage iv"thickness of o5ide layer v" dielectric constant of gate insulator vi" #arrier mobility" 12. -h$t is > "& effe't. The threshold voltage VT is not a constant w" r" to the voltage difference between the substrate and the source of MOS transistor" This effect is called substrate'bias effect or body effect" 13.-h$t is Ch$nne!-!ength * "(!$ti n. The current between drain and source terminals is constant and inde endent of the a by the a lied voltage over the terminals" This is not entirely correct" The effective length of the conductive channel is actually modulated lied V(S0 increasing V(S causes the de letion region at the drain ?unction to grow0 reducing the length of the effective channel" 17.Define Thresh !" # !t$ge in CMOS. The Threshold voltage0 VT for a MOS transistor can be defined as the voltage a lied between the gate and the source of the MOS transistor below

which the drain to source current0 &(S effectively dro s to !ero" )8. Define Rise ti*e 2ise time0 tr is the time taken for a waveform to rise from 9*@ to A*@ of its steady'state value" )1. Define @$!! ti*e @all time0 tf is the time taken for a waveform to fall from A*@ to 9*@ of its steady'state value" )). Define De!$& ti*e (elay time0 td is the time difference between in ut transition (<*@) and the <*@ out ut level" This is the time taken for a logic transition to ass from in ut to out ut" ),. -h$t $re t5 ' *+ nents f 1 5er "issi+$ti n. There are two com onents that establish the amount of ower dissi ated in a #MOS circuit" These areB i) Static dissi ation due to leakage current or other current drawn continuously from the ower su ly" ii) (ynamic dissi ation due to ' Switching transient current ' #harging and discharging of load ca acitances" )4. Gi#e s *e f the i*+ rt$nt CAD t !s. Some of the im ortant #=( tools areB i) $ayout editors ii) (esign 2ule checkers ((2#) iii) #ircuit e5traction

)0.-h$t is Veri! g. Verilog is a general ur ose hardware descri tor language" &t is similar in synta5 to the # rogramming language" &t can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the switch level"

Unit III 1. -h$t $re the st$ti' +r +erties f ' *+!e*ent$r& CMOS G$tes. a" They e5hibit rails'to'rail swing with VO% ) V(( and VO$ ) ,8(" b" The circuits have no static ower dissi ation0 since the circuits are designed such that the ull'down and ull'u networks are mutually e5clusive" c" The analysis of the (# voltage transfer characteristics and the noise margins is more com licated than for the inverter0 as these arameters de end u on the data in ut atterns a lied to the gate" ). Dr$5 the eA(i#$!ent RC * "e! f r $ t5 -in+(t NAND g$te.

,. -h$t $re the *$B r !i*it$ti ns $ss 'i$te" 5ith ' *+!e*ent$r& CMOS g$te. a" The number of transistors required to im lement an 8 fan'in gate is 28" This can result in a significantly large im lementation area" b" The ro agation delay of a com lementary #MOS gate deteriorates ra idly as a function of the fan'in"

4. -h$t is *e$nt %& r$ti e" ! gi'. &n ratioed logic0 a gate consists of an nMOS ull'down network that reali!es the logic function and a sim le load device0 which re lace the entire ull'u network" = ratioed logic which uses a grounded MOS load is referred to as a seudo'nMOS gate 0. -h$t is tr(e sing!e +h$se '! ';e" register. The True single' hase clocked register (TS7#2) uses a single clock0 #$C" Dor the ositive latch0 when #$C is high0 the latch is in the trans arent mode and corres onds to two cascaded invertersE the latch is non'inverting0 and ro agates the in ut to the out ut" On the other hand0 when #$C)*0 both inverters are disabled0 and the latch is in the hold mode" 6. Define $ t$!!& 'ir'(it. = tally circuit counts the number of in uts that are high and out uts the answer" &f there are 8 in uts there are 8 F9 ossible out uts0 corres onding to *0 90 20 G" 8 in uts that are high" 2. Gi#e the NAND-1C1DEL1SO414F-D-LRFERIE GHEEED<=ELFEV-L@NEIRU1E E EC

3. DUDIE-J4E6-D-L@EC)?EH8)6EKD-4VE-REU4DOLL4E E EEC GEEEHDEE

A" Dr$5 the CMOS i*+!e*ent$ti n f 4-t -1 MUM (sing tr$ns*issi n g$tes "

18. -h$t $re the #$ri (s * "e!ing (se" in Veri! g. 9" ,ate'level modeling 2" (ata'flow modeling ;" Switch'level modeling H" :ehavioral modeling 11. -h$t is the str('t(r$! g$te-!e#e! * "e!ing. Structural modeling describes a digital logic networks in terms of the com onents that make u the system" ,ate'level modeling is based on using rimitive logic gates and s ecifying how they are wired together" 1).-h$t is S5it'h-!e#e! * "e!ing. Verilog allows switch'level modeling that is based on the behavior of MOSD4Ts" (igital circuits at the MOS'transistor level are described using the MOSD4T switches"

1,. -h$t $re the t&+es f +r gr$**$%!e "e#i'e. 7rogrammable logic structure 7rogrammable &nterconnect 2e rogrammable gate arry 14. -h$t is CL>. #$: means #onfigurable $ogic :lock" 10.-h$t $re the t5 t&+es f MOS@ET. Two ty es of MOS4T are n'channel MOS4T and 'channel MOSD4T" These are known as n'MOS and 'MOS" 16.5hi'h MOS '$n +$ss ! gi' 1 $n" ! gi' 8 str ng!&. 'MOS can ass strong logic 9 n'MOS can ass strong logic * 12. -h$t is AOI ! gi' f(n'ti n. =8( O2 &nvert logic function (=O&) im lements o eration in the order of =8(0 O20 8OT o erations" So this logic function is known as =O& logic function" 13. -h$t is %(%%!e +(shing. =ccording to (e Morgan>s laws0 ) F F ) So 8=8( gate may be drawn as bubbled O2 gate" :ubbles are introduced in the in ut side" This conce t is known as bubble ushing" 17. I*+!e*ent & N (sing %(%%!e +(shing ' n'e+t. I) can be im lemented using bubbled =8( gate" ) F )8. -h$t is OAI ))1 G$te. O=& 2290 here 229 refers to number of in uts in each section" )1. -rite the fe$t(res f CMOS D *in L gi'. These structures occu y small area com ared with conventional logic structure"

 7arasitic ca acitance is to be small to increase the s eed" 4ach gate can make one Jlogic 9> to Jlogic *> transition" )). -h$t $re the t$!!& 'ir'(its. Tally circuits one of the a lications of the ass transistor logic" &t is used to count the number of in uts which are high and the out ut is roduced" ),. -h$t $re the #$ri (s f r*s f in#erter %$se" CMOS ! gi'. i" 7seudo 8'MOS logic ii" (ynamic #'MOS logic iii" #locked #'MOS logic iv" #'MOS domino logic v" n' #'MOS logic )4. -h$t is 1I1 in MILINIM. 7&7 means 7rogrammable &nterconnect 7oint in K&$&8&K" )0. -h$t $re the $"#$nt$ges $n" "is$"#$nt$ges f 1LA. A"#$nt$ges f 1LA Sim licity Small si!e Dis$"#$nt$ges f 1LA S eed roblem occur ( ull'u s may become slow on large terms )

Unit IV 1. Gi#e the %$si' nMOS 1LA str('t(re.

The basic 7$= structure consists of an =8( lane driving an O2 lane" The terminology corres onds to a sum of roducts (SO7) reali!ation of the desired function" The SO7 reali!ation converts directly into a 8=8(' 8=8( im lementation" 3hen a roduct of sums (7OS) reali!ation is desired0 it can be im lemented in O2'=8( or 8O2'8O2 logic" &n either case0 the first array is referred to as the =8( lane0 and the second array as the O2 lane" The line connecting the =8( lane to the O2 lane are called the roduct lines" ). -h$t " & ( *e$n %& CMOS 1LA. The basic #MOS 7$= is obtained by roviding a well and re lacing the ull'u devices in the 8=8('8=8( array or in the 8O2' 8O2 array with enhancement mode MOS devices" The #MOS array can be recharged or not0 and can be clocked 2 =8( lane O2 lane 2egister 2egister &n uts Out uts 9 with the same two' hase clocking scheme as used for the MOS 7$=" #MOS 7$= design offers many more varieties of layout than does nMOS" ,. Define finite st$te *$'hine.

3hen feedback is added to the =8( O2 7$= structure0 the 7$= becomes a finite state machine (DSM)" =n DSM can be designed as a Mealy Machine or a Moore Machine" The Mealy machine has out uts0 which may change with in ut changes in an asynchronous manner and cause erroneous behavior" %ence0 the Mealy machine should be avoided whenever ossible" The Moore machine has out uts which de end u on and change only with state changes0 since all the out uts of the :oolean'logic block go through a state register0 and are synchronously clocked" 4. -h$t $re the i*+ rt$n'e f the 1LAO@SM in VLSI. (i) 2egularity B &t has a standard0 easily e5 andable layout" (ii) #onvenience B $ittle design effort is required" (iii) #om acted B &t is efficient for small circuits" (iv) Modularity B &t makes it ossible to design hierarchical 7$=s and DSMs into large sequential systems" (v) Suitability to being com uter generated" 0. Gi#e the str('t(re f $ C1LD. = #7$( com rises multi le circuit blocks on a single chi 0 with internal wiring resources to connect the circuit blocks" 4ach circuit block is similar to a 7$= or a 7=$"&t includes four 7=$ like blocks that are connected to a set of interconnection wires" 4ach 7=$ like block is also connected to a sub circuit labeled &.O block0 which is attached to a number of the chi >s in ut and out ut ins"

6. Gi#e the C1LD +$';$ges $#$i!$%!e. $" 1LCC +$';$geB The 7$## ackage has ins that Lwra aroundM the edges of the chi on all four of its sides" The socket that houses the 7$## is attached by solder to the circuit board0 and the 7$## is held in the socket by friction" %. A($" f!$t +$'; +$';$ge6 The ND7 ackage has ins on all four sides0 and they e5tend outward from the ackage0 with a downward'wiring sha e" The ND7>s ins are much thinner than those on a 7$##0 which means that the ackage can su ort a larger number of insE ND7s are available with more than 2** ins" 2. Gi#e the str('t(re f MAM 2888 C1LD.

3. -h$t is *e$nt %& @1GA. = field rogrammable gate array (D7,=) is a rogrammable logic device that su orts im lementation of relatively large logic circuits" D7,=s can be used to im lement a logic circuit with more than 2*0*** gates whereas a #7$( can im lement circuits of u to about 2*0*** equivalent gates" D7,=s are quite different from #7$(s because D7,=s do not contain =8( or O2 lanes" &nstead0 they rovide logic blocks for im lementation of the required functions"

A" Gi#e the gener$! str('t(re f @1GA"

18. -h$t $re the "ifferent ' **er'i$! @1GA +r "('ts. Manufacturer D7,= roducts www $ocator =ctel =ct 902 and ;0MK0SK www"actel"com =ltera D$4KO***0P*** and 9*k =74K 2*kwww"altera"com =tmel =TO***0 =TH*k www"ateml"com $ucent O2#= 902 and ; www"lucent"com Nuick$ogic =S&# 902 and ; www"quicklogic"com Vantis VD& www"vantis"com Kilin5 K#;***0K#H***0K#<2**0Virte5www"5ilin5"com 11. -h$t $re the t&+es f re+r gr$**$%!e GA. =d'hoc =rray and Structured =rray are the two ty es of 2e rogrammable ,ate =rray" 1). -h$t is the t&+e:s @1LA. &" 72OM +7rogrammed 2ead'Only Memory/ &&" 7=$ +7rogrammed =rray $ogic/

1,. -h$t $re the $++!i'$ti ns f 1AL. i" #ontrol logic a lication ii" &n ut.Out ut iii" (ata' ath logic 10. -h$t is finite st$te *$'hine <@SM=. 3hen feedback is added to =8('O2 7$= structure0 then it becomes DSM" 16. -h$t $re the 'h$r$'teristi's f 1LAO@SM. i" 2egularity ii" Modularity iii" Suitability iv" 4fficiency 12. -h$t is CL>. #$: means #onfigurable $ogic :lock" 13. Define *e$!& *$'hine. &n mealy machine0 out ut may change with the change in the in ut asynchronously" 17. Define * re *$'hine. &n moore machine0 out ut can be changed when state is changed" )8. -h$t is 4DL. V%S&# %ardware descri tion $anguage" )1. -h$t is V4SIC. Very %igh S ed &ntegrated #ircuits" )). -h$t $re the #$ri (s +er$t rs in V4DL. i" $ogical o erators ii" 2elational o erators iii" Shift o erators iv" =dding o erators v" Multi lying o erators

vi"

Miscellaneous o erators

),. -h$t $re the "$t$ t&+es $#$i!$%!e in V4DL. i" Scalar ty e ii" #om osite ty e iii" =ccess ty e iv" Dile ty e )4. -h$t $re the t&+es f s(%+r gr$*s. Dunctions and 7rocedures are ty es of sub rograms" )0. -h$t is the (se f $'t($!. =ctual in a sub rogram call is used to ass the values from and to a sub rogram"

UNIT 0 V4DL 1=-rite the $'r n&* f r V4DL. V4DL is an acronym for V4SIC %ardware (escri tion $anguage (V%S&# is an acronym for Very %igh S eed &ntegrated #ircuits)" )= -h$t $re the "ifferent t&+es f * "e!ing V4DL. 9) Structural modeling 2) (ata flow modeling ;) behavioral modeling H) Mi5ed ty e of modeling ,= -h$t is +$';$ges $n" 5h$t is the (se f these +$';$ges = ackage declaration is used to store a set of common declaration such as com onents ty es rocedures and functions these declaration can then be im orted into others design units using a use caluse" 4= -h$t is #$ri$%!e '!$ss ?gi#e e/$*+!e f r #$ri$%!e =n ob?ect of variable class can also hold a single value of a given ty e 0 %owever in this case different values can be assigned to a variable at different time" 45Bvariable ssB integerE 0= N$*e t5 s(%+r gr$*s $n" gi#e the "ifferen'e %et5een these t5 . 9) Dunction 2) rocedure Only one out ut is ossible in function"" Many out uts ossible using rocedure 6= -h$t is s(%+r gr$* O#er! $"ing &f two or more sub rogram to be e5ecuted in a same name" overloading of sub rogram should be erformed" 2= 5rite the V4DL ' "ing f r $ seA(enti$! st$te*ent <"-f!i+f! + = entity dff is ort(clk0dBin stdQlogicE qBout stdQlogic)E endE

architecture dff of dff is begin rocess(clk0d) begin if clk> event and clk)> 9> then qR)dE end rocessE endE 3= -h$t $re the "ifferent ;in"s f The test %en'h Stimulus only Dull testbench Simulator s ecific %ybrid testbench Dast testbench 7= -h$t is M re @SM The out ut of a Moore finite state machine(DSM) de ends only on the state and not on its in uts" This ty e of behaviour can be modeled using a single rocess with the case statement that switches on the state value" 18= -rite the test%en'h f r $n" g$te entity testand2 is end entity architecture io of testand2 is signal a0b0cBstdQlogicE begin g9Bentity work"and2(e52) ort ma (a0b0c) aR)> *> 0> 9> after 9** nsE bR)> *> 0 J9> after 9<* nsE endE 11. 5rite the s&nt$/ f +r 'e"(re % "&. 7rocedure rocedure name ( arameterlist) 1). -h$t is test %en'h. = test bench is a model which is used to e5ercise and verify the correctness of a hardware model"

1,. -h$t $re the t5 *eth "s t gener$te sti*(!(s #$!(es. i" To create waveforms and a ly stimulus at discrete time intervals" ii" To generate stimulus based on the state of the entity or out ut of the entity" 14. Differenti$te %et5een 'h$nne!e" H 'h$nne! !ess g$te $rr$&. #hanneled ,ate =rray #hannel less ,ate =rray 9" Only the interconnect is customi!ed only the to few mask layers are customi!ed" 2" The interconnect uses redefined s aces between rows of base cells" 8o redefined areas are set aside for routing between cells" ;" 2outing is done using the s aces 2outing is done using the area of transistors unused" H" $ogic density is less $ogic density is higher" 10. -h$t is $ @1GA. = field rogrammable gate array (D7,=) is a rogrammable logic device that su orts im lementation of relatively large logic circuits" D7,=s can be used to im lement a logic circuit with more than 2*0*** gates whereas a #7$( can im lement circuits of u to about 2*0*** equivalent gates" 16. -h$t $re the "ifferent *eth "s f +r gr$**ing f 1ALs. The rogramming of 7=$s is done in three main waysB S Dusible links S TV - erasable 472OM S 4472OM (4272OM) - 4lectrically 4rasable 7rogrammable 2OM 12.-h$t is $n $ntif(se. =n antifuse is normally high resistance (U9**M3)" On a lication of a ro riate rogramming voltages0 the antifuse is changed ermanently to a low' resistance structure (2**'<**3)" 13. -h$t $re the "ifferent !e#e!s f "esign $%str$'ti n $t +h&si'$! "esign. S =rchitectural or functional level

S 2egister Transfer'level (2T$) S $ogic level S #ircuit level 17.-h$t $re *$'r s. The logic cells in a gate'array library are often called macros" )8. -h$t $re 1r gr$**$%!e Inter' nne'ts. &n a 7=$0 the device is rogrammed by changing the characteristics if the switching element" =n alternative would be to rogram the routing" )1. Gi#e the ste+s inASIC "esign f! 5. a" (esign entry b" $ogic synthesisSystem artitioning c" 7relayout simulation" d" Dloor lanning e" 7lacement f" 2outing g" 45traction )). -rite n tes n f(n'ti n$!it& tests. Dunctionality tests verify that the chi erforms its intended function" These tests assert that all the gates in the chi 0 acting in concert0 achieve a desired function" These tests are usually used early in the design cycle to verify the functionality of the circuit" ),. -rite n tes n *$n(f$'t(ring tests. Manufacturing tests verify that every gate and register in the chi functions correctly" These tests are used after the chi is manufactured to verify that the silicon is intact" )4. Menti n the "efe'ts th$t ''(r in $ 'hi+. a) layer'to'layer shorts b) discontinuous wires c) thin'o5ide shorts to substrate or well )0. Gi#e s *e 'ir'(it *$!$"ies t #er' *e the "efe'ts. a" nodes shorted to ower or ground b" nodes shorted to each other

c" in uts floating.out uts disconnected