18-240: Structure and Design of Digital Systems

Using Quartus II to Congure the DE2-115 FPGA Board ! Version 1.3

Modern digital designs are specied in a hardware description language such as SystemVerilog. In order to ensure the description is correct, simulation software is used to see how the design reacts to di!erent test inputs. After assuring oneself that the design is correct, the engineer will synthesize the SystemVerilog and congure an FPGA (alternatively, the synthesized design can be used to create layout for an ASIC). For the purposes of 18-240, this design ! test ! synthesize ! congure cycle is performed using software tools provided by the FPGA manufacturer, Altera. The Quartus II software is an integrated design environment where you can edit your SystemVerilog, synthesize it, and congure the FPGA. Simulation is done with a di!erent software tool, VCS. This tutorial will walk you through the process of creating a Quartus II project, editing a SystemVerilog description and programming the DE2-115 Board. Quartus II version 12.1 is used in this tutorial, though the exact version probably doesnt matter much for what we are doing.

Getting started
1. Log into one of the Linux machines in Hamerschlag Hall 1305. Before executing Quartus, you need to have its le location included in your path as well as having an environment variable set to help nd the Quartus license. Assuming you are using bash, you can simply > source /afs/ece/class/ece240/lib/setup_quartus Feel free to include this line in your .bashrc le.1 Now, execute Quartus with: > quartus &

If you are using a shell other than bash, youll need to translate yourself. This one is pretty easy. Or, you can execute bash as a sub-shell and run this from inside.

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A Quartus II "splash screen" will appear, as shown in Figure 1. Press the "Create a New Project" button. A project is the collection of all les, databases, and information about your design. You will use separate projects for each of your labs, as well as this tutorial. A "New Project Wizard" window will appear. You will go through 5 steps in order to dene your new project. New Project Wizard, Step 1: Directory, Name, Top-Level Entity. This window lets you choose a directory for your project. The default is your home directory, which is not a very good place to put class work. Instead, navigate to a work directory that is specic for this lab or tutorial. You can actually have several projects in a directory. The name you specify on the second line is the project name. Name your project "Tutorial." The Top-Level Entity is the name of the module that is the top-level of your design. It is your "top" module. Name the top-level design entity "top" for this project. Beware that this name must match the name of your SystemVerilog module exactly -- case matters. Press the "Next" button.

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New Project Wizard, Step 2: Add Files. In case you happened to have some SystemVerilog le (or other design le) that you wanted to include in this project, you could add it here. Later in the semester, you will be developing a "library" of SystemVerilog components. This is the step where you can add that library le to the project. For now, just press the "Next" button.

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New Project Wizard, Step 3: Family and Device Settings. In this step, we need to tell the tool which particular FPGA we are working with. In our case, this is a pretty easy decision, as the FPGA has been chosen by the fact that we are using the DE2-115 boards. We just need to choose the exact FPGA that exists on the board. Ours is the "EP4CE115F29C7." Yeah, I'm sure that was the one you were going to guess. Choose the Family and Available devices to match Figure 2, then press the "Next" button. Alternatively, you can (after selecting Cyclone IV E Family) type the device name into the "Name Filter" eld.

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New Project Wizard, Step 4: EDA Tool Settings. Please, please, don't touch anything on this window except for the "Next" button. New Project Wizard, Step 5: Summary. Is it really a step if you can't do anything? Just press the "Finish" button. Congratulations, you now have a project. It is a pretty lame project, as there isn't much in it at the moment. Let's x that by creating a SystemVerilog le. Quartus II has an editor that you can use to create your les. It isn't a particularly good editor, though it does do some SystemVerilog syntax highlighting. Feel free to use another editor if you wish.

10. To create a le using the built in editor: File ! New ! SystemVerilog HDL File ! OK. An editing pane will open in the middle-right section of the Quartus II window. This is a tabbed editing area, where various les and reports will be displayed. For now, your new (empty) le is called "SystemVerilog1.sv." 11. An empty le isn't very interesting. Let's put some major, awesome functionality in our circuit -- something like the circuit shown below? Type the following (or cut-n-paste) into the editor window. Note that the module name ("top") must match the "Top-level Entity Name" that we supplied when we created the project (in step 4.2).

a b f c d
module top (output logic f, input logic a, b, c, d); nand g1(f, f1, f2) g2(f1, a, b) g3(f2, c, d) endmodule : top

12. You will notice that the editor colors keywords with blue text and numbers each line. Depending on the preferences set at the moment, you also will probably get dots in each space character (i.e visible whitespace) and dotted vertical lines every two characters (i.e. indentation guide). You can change these preferences by pressing the buttons in the editor window toolbar. Now that you have something to lose, you'd better save it. Press <ctrl> S to save your SystemVerilog code. Save it with a lename of top.sv (as the Save dialog will suggest) and ensure that the "Add le to current project" checkmark is selected.

Change editor preferences here

13. At any time that you'd like to see what les there are in your project, you can get a list in the "Project Navigator" pane. The "Project Navigator" is on the left column of the Quartus II application. It will show the components of your project, either by design hierarchy, les or design units. Click the "Files" tab at the bottom of the Project Navigator and make sure that top.sv is listed as being part of your project (at this point, it should be the only such le). Im showing here the screenshot from the windows version of Quartus, as it nicely displays just the lename portion of the les. Under Linux, youll get the entire path, starting with a bunch of ../../../ junk that makes this almost unusable. If anyone can gure out how to get Quartus to just display lenames and not complete paths, youll make me very happy!

14. Now it is time to compile the design. Quartus II takes care of a great deal of individual analysis tasks, much like how a makele can guide the build process for a complicated piece of software. Start the compilation with the aptly named Processing ! Start compilation (see what I did there?). You can also use <ctrl> L or push the purple triangle button in the toolbar. 15. You should discover, thanks to an error dialog, that "Full Compilation was NOT successful" with 3 errors. Looks like I gave you faulty SystemVerilog code. Can you nd the errors? If not, here is a hint: ,,; 16. By the way, you will notice that your source code window has been covered up with a "Compilation Report" window. Right now, there isn't much useful information in the report (since the compilation process failed pretty early on). Simply close the Compilation Report by clicking the small "X" box on the window's tab. 17. Did you x the source code? In all three places? Good. Start the compilation again. You will be prompted to save your code before the process starts. That seems like a good idea, so press the "Yes" button. 18. Compilation should take a bit longer this time around. Even though it seems we have a pretty small design (which is true), Quartus II is running a full suite of industrial strength analysis tools on it. You can track the progress in the "Tasks" pane on the left side, below the Project Navigator. 19. You should get a dialog box announcing that "Full Compilation was successful." You probably also had a bunch of warnings (10?). Celebrate a moment, then press the "OK" button to make the dialog box go away. If you didn't get successful compilation, go nd more errors to x and try again. 20. Another compilation report window has popped up to obscure your source code. This one is a bit more interesting. It reports the number of logic elements used (should be 1), number of logic registers (should be 0 until Lab 2b), total pins used (should be 5, one each for f, a, b, c, and d), etc.

21. You can look at the Messages pane at the bottom of the window to discover what the details of the 10 warnings were. The buttons with red circle, purple triangle and yellow triangle let you choose to display Error messages, Critical Warnings or Warnings. Most are ignorable ("No clocks dened in design" which is completely true for this circuit) or of moderate interest ("created implicit net for f1"). This later warning is given because we never dened logic signals for f1 and f2. We just used them to connect our nand gates. Perhaps it would be better style to have dened them (and thus have a known type for them). 22. There is one warning that, with a little thought, should bother you. That warning is in the Critical Warning list: "No exact pin location assignment(s) for 5 pins of 5 total pins." Quartus II doesn't know we are using the DE2-115 board. All it knows is that we are using a particular FPGA. Thus, it doesn't know what pins should be connected to the input and output signals (f, a, b, c, and d). We should probably specify that the inputs are connected to some switches and the outputs to an LED. Right now, as the project stands, the input and output signals were decided upon by Quartus II without knowing where the switches and LEDs are. You can check Quartus II's choices in the Compilation Report (did you already get rid of it? Bring it back with Processing ! Compilation Report or <ctrl> R). You'll have to dig into the Compilation Report by selecting sections from the Table of Contents on the left side of the window. Check out Fitter ! Resource Section ! Input Pins (and Output Pins). When I ran this tutorial, the input pin selected for b was Pin #D4, which is actually connected to "ISP1362 DMA Acknowledge 1" a signal to the USB controller. That'll be hard to get to in order to change the input value. 23. Let's assign some pins to the input and output signals then. We will connect the signals according to the following table (note that you have to type in PIN_XXX): Signal f a b c d I/O output input input input input Device Green LED #0 Switch #0 Switch #1 Switch #2 Switch #3 Abbreviation LEDG0 SW0 SW1 SW2 SW3 Pin # PIN_E21 PIN_AB28 PIN_AC28 PIN_AC27 PIN_AD27

24. Open the "Pin Planner" tool with either Assignments ! Pin Planner or the keyboard shortcut <Ctrl+Shift> N. This tool looks a lot messier than you need to worry about. You only need worry about the table at the bottom. You will see that the input and output signal names are already lled in for you, one per row. Unfortunately, the Pin Planner only knows the signal names after a successful compilation, which is why we allowed Quartus II to pick poor pins for us in the rst place. Go ahead and ll in the "Location" column of the table with the values from the table above. Your table should look like this when you are done:

Close the Pin Planner with File ! Close or the "X" in the upper right of the window. 25. Let's take a slight detour to ensure the pins we didn't assign aren't lit up. Go to Assignments ! Device... and select the "Device and Pin Options..." button on the middle right side. Yet another window will open, named "Device and Pin Options." Select the "Unused Pins" Category on the left. In the pane on the right, choose "As input tri-stated". Press OK. Press OK again.

26. Now, re-run the compilation. You should get a successful compilation dialog box with fewer warnings (9 warnings?). Not to worry!

27. Now it is time to send the synthesized design to the DE2-115 board (nally!). This process is called "Conguring" the FPGA, though Quartus II sometimes calls it "Programming." Take a quick look at the DE2-115 board. You should have a USB cable connected to the top of the board on the left side. Be careful, there are two places to plug in the USB cable. It should be in the far left socket (which is labeled with "Blaster" in small type on the board. A power cable should be connected in the upper end of the left side, near a big red button. That big, red button controls power to the board. Press it to turn the board on. You should see lots of blinking lights, counting numbers and the message "Welcome to the Altera DE2-115" on the LCD display. If you don't see all this electronic wonderfulness, you should check the Run/Prog slide switch in the lower-left corner. It should be set to "Run." 28. Open the FPGA Programmer with Tools ! Programmer or click this icon in the toolbar. Or, you can double-click on "Program Device (Open Programmer)" in the Tasks pane. This last is probably easiest, as you will have just been paying attention to the compilation success in the same window. 29. The Programmer window will open. You need to check that the "Hardware Setup..." eld near the top says "USB-Blaster [2-1.5.1.3]" next to it. If the numbers are slightly di!erent, thats okay. If it doesn't at least say USB-Blaster, then click on "Hardware Setup...". In the "Currently selected hardware:" selection eld, choose "USB-Blaster" and close the window. 30. If the hardware is appropriately selected in the Programmer, you simply need to press the "Start" button on the left side. A green progress bar in the upper-right corner should slowly ll up to "100% (Successful)." I love how they must think we wouldn't know that 100% is good and have to tell us we are successful. You may now close the Programmer window. 31. You may now test the circuit on the DE2-115 board. Recall that SW0-3 are the inputs and that LEDG0 (on the far right) is the output. The LED is active high. That is, it will light up whenever it receives a logic 1. The switches provide a logic zero whenever the slider is closest to the bottom edge of the board, pretty much as you would expect. Try all 16 input combinations. The LED should light up for seven of them. 32. Turn the power o! and back on again (big red button). What happens to your circuit? When you program the FPGA in the way we just did, your design is volatile. That is, it only stays in the FPGA while power is available. 33. You have now completed the Quartus II Tutorial. Hope you enjoyed it! Before you go, however, I want to tell you a secret. There is a much easier way to do the Pin Planning work, though it will make more sense after you have learned how to do vectors in SystemVerilog. I'm including it in this tutorial, however, because I'll probably forget to tell you about it later.

I have provided a spreadsheet le (CSV) 2 on Blackboard (in the Lab0 Stu! folder) that includes all pins on the entire FPGA. As long as your top-level module uses the exact names printed on the DE2-115 board (or listed in the DE2-115 User Manual), this le will save you from ever having to look up pin assignments. Merely import it into your design with Assignments ! Import Assignments... The switches and LEDs are dened in this le as vectors, so it'll take a few hoops to dene our signals in ways that map directly to the names in the le. This works:
module top (output logic [0:0] LEDG, input logic [3:0] SW); nand g1(LEDG[0], f1, f2), g2(f1, SW[0], SW[1]), g3(f2, SW[2], SW[3]); endmodule : top

In some rare occasions, the csv le doesn't seem to load properly. I have also included a qsf le on Blackboard. It should load with the same Import Assignments process.