School of Computing & Mathematics.

Plymouth University

Microprocessor Design Project ELEC220: 2012-13

BEng Electronics Specification DRAFT

Contents TOC \o "1-3" \f 1. Introduction PAGEREF _Toc345544729 \h 3 2. Outcomes PAGEREF _Toc345544730 \h 3 3. Assessment PAGEREF _Toc345544731 \h 3 General Marking Criteria PAGEREF _Toc345544732 \h 5 4. Timescales and Planning PAGEREF _Toc345544733 \h 5 5. Specification PAGEREF _Toc345544734 \h 6 6. Circuit Design Notes PAGEREF _Toc345544735 \h 6 6.1 System Design PAGEREF _Toc345544736 \h 6 6.2 Input Amp PAGEREF _Toc345544737 \h 8 6.3 Filter Design PAGEREF _Toc345544738 \h 8 6.4 Serial Link PAGEREF _Toc345544739 \h 8 7. Schematic and PCB Design PAGEREF _Toc345544740 \h 9 7.1 Schematic Design PAGEREF _Toc345544741 \h 10 7.2 PCB Layout PAGEREF _Toc345544742 \h 10 8. Construction and Test PAGEREF _Toc345544743 \h 12 9. Software PAGEREF _Toc345544744 \h 12 9.1 PC Programming

PAGEREF _Toc345544745 \h 12 10. Report PAGEREF _Toc345544746 \h 12 11. Finally PAGEREF _Toc345544747 \h 13 Appendix A - Microsoft Project Gantt Chart PAGEREF _Toc345544748 \h 14

Introduction Students in the spring semester of stage two will undertake a project involving the planning, design, construction and test of a microprocessor based system. The project will enhance skills already learnt as well as introducing some new ones. Students will work as pairs which will therefore require some planning and management of the project. The time allocated to the project will be 3 hours per week for around 10 weeks. Since each module is designed for 90 hours study in total then it is expected that students will need to work outside the timetabled lab slots. Sessions will be timetabled in Smb303, such that CAD tools can be used for design and simulation and development of code and for construction and test purposes. You will be able to use the project lab on a casual basis (if there is space available in the project lab you are welcome to use the facilities). Warning! Dont leave it too late. Every year there is a mad rush to get things working and the project lab simply cant accommodate this. To avoid fighting to get in please get going quickly and get the hardware finished quickly. A large part of achieving a successfully working project is in the planning so make sure you use the most of the time you have available. Youve been warned.... Outcomes The students completing this task will experience all stages of a development process right from initial interpretation of the specification to testing the prototype circuit. This should consequently develop and enhance the following skills:Project planning and management Circuit design and the use of CAD tools Manufacture of PCBs Software development (high and low level) Finding and using data Minute taking and Report writing Team & Communication Skills Assessment It is your responsibility to ensure assessment is done as you progress. This also allows us to pick up any serious problems before its too late and to track your progress. You must schedule a design review such that a member of staff sees and gives feedback of your design before you advance onto building it.

Continual assessment will be made in the following areas:(this is a provisional allocation of marks and is subject to changes accordingly) 3.1. Project Plan (5%) Attempted individually. Each team member should produce their own project plan that demonstrates a reasonable effort at predicting scheme of work with tasks split equally between team members. This should be clearly presented using either project planning software (MS Project), or a table in word or excel. (Evidence required that youve done this after first week by submitting initial plan to the module folder and subsequently documenting any modifications required during project duration and detailing them in the project report)) 3.2. Minute Taking (5%) (Each student must take minutes of at least one meeting and submit them via the student portal before the Easter vacation. Details of any actions arising from group meeting together with the minutes should entered in the log book for continual assessment) 3.3. Circuit design, Schematic Diagram and Simulation (5%) Marked from report and lab books on the simulation results, component values, layout and the philosophy of the design. The Schematic Design should have clearly labelled components and split over several sheets, if required. Most should be correct but marks are lost for any blatant errors. A hardcopy (printout) should be available during testing, failure to provide an adequate schematic will result in loss of marks and possible refusal of technical help. 3.4. PCB Layout (5%) Marks based on general neatness, use of space, minimisation of links 3.5. Construction and Correctness of Design (10%) Quality of soldering, construction of board and cable etc. Marks for errors in layout and schematic also accounted for here (loose a half mark for each of the first 6 bodges). 3.6. Testing Methods (10%) Evidence of systematic testing of both microprocessor board and daughter board using some schedule. A printout of the test schedule, circuit diagrams and layout are essential when testing the PCBs. Students will be asked how they are sure various parts of the system are functioning correctly and how they have been tested adequately (eg method for testing filter). All students will be expected to demonstrate knowledge of the whole circuit operation, in particular, location of key signals (pinout) and the expected voltage levels and waveforms on these pins. These signals should be recorded in the students log book for later reference. 3.7. Code (15%) LEDs should be giving a status indication that all is functioning correctly. Partially

working programs will be awarded marks on the number of completed functions (i.e does the serial link work, is there evidence of signalling and communication, do the leds give information about the systems mode of operation). 3.8. Specification & System Demonstration (10%) Marks will be awarded on how close the circuit operates with respect to the specification Final Demonstration to show the components have been integrated and the system is functioning correctly. Marks will also be awarded for the PC code for general appearance and functionality. 3.9. Project presentation & Peer Assessment (10%) Make a 15 minute presentation with each team member participating. Assessed in lab 3.10. Lab Book (5%) Assessed in Lab, these will need to be taken to all lab sessions and will be signed by the member of staff present. Each student will be required to keep a record of their input to the project (meetings, research info, calculations, measurements, etc) by keeping their own individual up-to-date lab book. A hard bound lab book is required with numbered pages and dated for each entry. Loose leaf pages will not be signed. 3.11. Report (20%) A clear, concise report detailing the design and functionality of the circuit, including tests and calculations. Separate mark scheme for this Marks may be shared equally between the group members. However, in your initial planning you should ensure each has a fair loading and in your final report you should indicate who actually did what. If there is a big discrepancy in the effort made by group members then marks may be adjusted. General Marking Criteria 0-3 Not a hope. Completely inadequate and no sign of effort or cerebral activity. 4 Barely adequate but some sign of effort or progress 5 A reasonable effort but much room for improvement 6 The average student, a good effort & has more or less completed task 7 A very good effort which completely fulfils requirements 8-10 Exceptional work. Completely fulfils the requirements and shows signs of initiative in using novel approaches. Timescales and Planning You are expected to organise your own schedules of work but these are constrained by the following dates.

Week 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38

Date 07Jan 14Jan 21Jan 28Jan 04Feb 11Feb 18Feb 25Feb 04Mar 11Mar 18Mar 25Mar 1Apr 8 Apr 15 Apr PCB Submission deadline Collect & Drill PCB Presentations Select Team & Produce Gantt charts

Demonstration EASTER EASTER EASTER Revision

Specification There is a requirement to control and monitor the output of a buck converter to maintain a constant 5v output from a 24v source. You will employ a low cost microcontroller using Pulse width Modulation at 100 KHz to achieve this task and change the PWM to achieve a stable 5v output. The amplitude of this signal will need to be reduced through a potential divider so that the maximum monitoring voltage, never exceeding 3v, is feed to the ADC. One LED should flash visibly to denote that the system is functioning correctly, whilst the other should be used to indicate when the system is performing out of specification. The LCD should be used to report power measurements. Samples should be sent over the serial port so the waveform can be displayed on a PC. The microcontroller interface board should also the measure the charging/ discharging current in the capacitor. Under normal operation the device produces a 50 KHz triangular wave at 1mV max. This signal will require pre-processing by converting it from bi-polar to a unipolar signal in the range on 0-3v. The incoming signal should be filtered using a 4th Order Butterworth, 24dB/octave filter to avoid aliasing. The system will then digitise the signal at 800ksamples/ sec. Samples should be sent over the serial port so the waveform can be displayed on a PC. Circuit Design Notes The following sections give guidance on various parts of the design. They are by no mean comprehensive but should steer you in the right direction and will alert you to some pit-falls. System Design The general scheme to be used is shown as follows:INCLUDEPICTURE "http://i.cmpnet.com/planetanalog/2008/04/C0295Figure3.gif" \* MERGEFORMATINET

BUCK BASICS The Buck Converter is easy to understand if you look at the two main states of operation: SW1 ON and SW1 OFF. ! SW1 is ON ! L1 delivers current to the load With a voltage (Vin - Vo) across L1, current rises linearly. How fast? The rise (in amps per second) is determined by "I / "T = ( Vin - Vo) / L1 INCLUDEPICTURE "http://www.ecircuitcenter.com/Circuits/smps_buck/ image004.gif" \* MERGEFORMATINET C1 smooths out L1's current changes into a stable voltage at Vo. Also, C1 is big enough such that Vo doesn't change significantly during one switching cycle. Where's D1? Its reversed biased and out of the picture for now. L1 maintains current to ! SW1 is OFF ! the load As L1's magnetic field collapses, current falls linearly through L1. How fast? The fall (amps per second) is again determined by the voltage across L1 and its inductance. "I / "T = ( Vo + VD) / L1 INCLUDEPICTURE "http://www.ecircuitcenter.com/Circuits/smps_buck/ image006.gif" \* MERGEFORMATINET Although L1's current direction is the same, what's happened to L1's voltage? It's reversed! That's L1 maintaining current flow by reversing its voltage when the applied voltage is removed. Also, check out what happens to D1 when the left end of L1 swings negative. Yes, it turns ON providing a path for L1's current to flow. SWITCHING FREQUENCY Given the components above, how do you control the exact output voltage? Typically, by using a Pulse-Width-Modulation (PWM) signal to drive SW1. This implies you need a pulse train that looks like this: # A switching period of TS.

# An adjustable Pulse Width of TON (the time SW1 is ON) Simply adjust the Duty Cycle (D = TON / TS) to get the output voltage you need! At which frequency do you run this pulse train? Typically in the range of 10s to 100s of kHz. Why so high? There are two big benefits here: 1. As frequency goes up, parts usually get smaller, lighter and cheaper - very cool in portable design! You get a lot of power from a small volume of stuff. Or in other words - a high power density (W/in3). 2. The delay from input to output created by the switching time (Ts) becomes smaller. So what's the big deal about delay? Later, when we place the Buck inside of a control loop, this delay can cause dreadful things to happen to the closed-loop response like overshoot, ringing or oscillation! Shorter cycle times (smaller delay times) - compared to the LC or controller response time - means less potential trouble when closing the loop. Input Amp The filter will use two devices from a dual op-amp package. You will require an extra op-amp to amplify the input using the standard inverting or non-inverting op-amp configurations. The filter will have a fixed gain that is determined by its design rules and so it will be desirable use the extra op-amp to ensure that the 1mV input to the system is amplified to make use of the maximum voltage range that the ADC will accept. Since we are using dual op-amp packages this will mean you have one extra op-amp that can be used to correct the DC offset. Filter Design To avoid aliasing we must block any signal above half the sample rate of 800KHz. An 8 bit ADC has a dynamic range of 48dB therefore at 400KHz the filter must have 48dB of attenuation to block any unwanted signals. At 24dB/ octave this will require 2 octaves to achieve the required 48dB. Therefore, you must design a low-pass filter with a cut-off frequency of 100KHz (2 octaves below 400KHz). The filter is to be a 4th order low-pass Butterworth filter using the Sallen and Key circuit. The output voltage should match the maximum input range of the ADC. The circuit will consist of two cascaded 2nd order sections as shown below. EMBED Word.Picture.6 You will require two such sections cascaded in series. The values of RC will be the same in both and the amplifier will be a non-inverting opamp circuit. To

design this see Horowitz and Hill - The Art of Electronics available from the library. Many other books will have sections on active filter design. You will be required to simulate your design. Use the built in simulator in Isis (LISA) to do this and check that the slope in the stop band is 80dB per decade and the cut-off frequency is 100KHz. Also, check the DC gain. Serial Link The serial link to the PC uses pins 0 and 1 of port 3. These signals are converted to RS232 levels using the MAX202 serial driver. The data sheets for this chip are available. This chip needs to produce its own 10V power supply requiring the connection of several 0.1F capacitors (use the non-polarised CERAMIC 100nF capacitors available). Half the chip is unused but the inputs should not be left floating.

The board will have a 9-pin D-type plug connector and the cable will have a 9-pin D-type socket at either end. A cable will need to be made with the following connections 2 3 5 Receive (RXD) Transmit (TXD) Signal ground

Note that the cable crosses over such that RXD at one end is connected to TXD at the other. In addition, the following three signals need to be connected together in the D-Type socket to ensure correct handshaking:8 6 4 Power Supplies The +/-12V Power supplys required to drive the electronics is available from a separate bench power supply. The power supplies should also be decoupled to ground to reduce noise. Schematic and PCB Design Clear to Send Data set ready Data terminal ready

The Proteus (ISIS/ARES) suite is an integrated tool that allows initial production of schematics and then the PCB design that is driven from a netlist produced from the schematic. Automatic routing is possible but is not recommended since the results are poor. It is not wise to edit the schematic once the PCB design has begun but small edits are not usually a problem. Be careful not to rename components once PCB design has started and especially dont use the annotate facility on the schematic. There is considerable work involved to produce the final PCB. Therefore, always keep backups. Note that the hard disks in most of the SECEE machines are wiped daily. Loss of work is not accepted as legitimate reason for special consideration; it is your responsibility to backup your work often. Schematic Design The whole circuit might not fit easily onto one sheet. Therefore split the design onto several sheet, each showing a different part of the circuit (e.g. Processor and LCD, ADC, Filter etc.).To produce a new sheet or switch between sheet use the options in the design menu. To connect signals between sheets simply label them with the same name. However, to show a signal does come from or goes to another sheet place an input or output pin at the edge of the sheet and label this. Note that buses are drawn thicker. The wires coming from a bus must be labelled to identify which bus signal it is. It is suggested that thicker (T25) tracks are used for power lines. To indicate to the PCB tool which signals are power lines highlight the track in ISIS and add the label STRAT=POWER. This should be implied for Vcc and Gnd wires and need not be applied but for the 12V lines and any other lines which need to be thicker this is required to be done. MostAll the components required reside in the library K:\Proteus\Samples\Beng2. Most can be placed and thats it but for capacitors you must edit the components attributes to set the package style as follows:100nF CAP20C 10nF CAP20R 10 47F/10F EL-R8X20 Note that for the op-amps there are two schematic symbols per package. Ensure labelling is something like U4:A, U4:B, U5:A and U5:B where we have two packages (here U4 and U5) and each op-amp within is labelled A and B. Note that power pins only occur on one of the op-amp symbols per package. Wire these to the 12V rails even if the op-amp is unused since others in the package may be in use.

Each digital chip must have a 100nF capacitor placed near it across the power supplies for decoupling. The capacitor and the IC must be physically close on the PCB but in the schematic can be drawn just as a string of parallel capacitors for convenience. Use the ground symbol for all grounded connections. The Vcc symbol can be used as the regulated +5V supply. Therefore, the output of the regulator connects to a Vcc symbol. An Electrical Rule Check (ERC) will look for any problem such as connecting two outputs together, undriven inputs and so on. It may report warnings when connecting to the process port that are bi-directional pins (I/O). The ERC expects these to connect to other I/O type pins but this is not always the case (e.g. output of ADC converter are defined as outputs which connect to port on processor). PCB Layout When the schematic is complete start ARES from ISIS (TOOLS>Netlist to ARES). Components can then be placed and a rats-nest is shown indicating which pins need to be connected. Place the devices using the data bus first and arrange them such that the bus is easily wired up. Place all routing on the blue (bottom) side of the board. The board is only single sided but if a wire link is required over the top then draw this in using the top (Red) side of the board. This is necessary to ensure the netlist from the PCB matched the one from the schematic. You view the layout from the top (component side) of the board. Power lines should be thick (T25) and signal lines thinner (T15). Signals can be squeezed between IC pins but power lines cannot. Try to keep corners to 45. Check the Set Strategies to ensure the signal and power lines are drawn the correct width. Always work in Imperial measurements, not metric and ensure the grid is set to 50 (0.05in or 50thou.). Periodically perform a design rule check. The rules should be set as follows:pad to pad 15 pad to track 10 track to track 15 Perform a connectivity check once complete to ensure the board matches the schematic. Add your names to the bottom copper so the board can be identified. The board dimensions are set to allow the daughterboard to fit neatly the

microcontroller board. Try and keep the number of wire links as low as possible without spending hours of obsessive fiddling over it.

Construction and Test The PCB design should be submitted to the project lab store on disk with the appropriate signed authority. The finished board will need drilling and drill kits are available from the project lab stores. Once the board is soldered first test the resistance between the various power lines to check for shorts. Then power up the board without the ICs in their sockets and check the power regulator output. Then board can then be populated with ICs if you are happy (remember, you need to pay for replacement parts if things blow up!). You can then start testing the various sections of the circuit to check they function. Make notes of your tests and the results for the report. Try and be systematic and write a test schedule that should examine each element of the specification before the board is completed. E.g. 1. Fail 2. Fail 3. Fail . Any modifications will need to be made on the original PCB, you dont get a second chance at the PCB unless things are really desperate. To test the serial link write a program in assembler to continuously send information up the line to the PC and see if it is received. Software There is considerable work involved in the development and so it should take place in parallel with the hardware development. It is not necessarily impossible to test software before the hardware is complete. For example, the PC software can be got running using dummy data from a routine which emulates data coming from the serial port. When the hardware is ready this routine is the only part which then needs modifying such that it really does take data from the port. Check reset pin voltage on manual reset. Pass/ Check clock pin on Micro for 12mhz signal Pass/ Test Power on Micro is 5V Pass/

PC Programming You may use whatever programming language you like to create a visual front end display for this project. Visual Basic or Labview is recommended for providing a nice graphical interface. However this is NOT the main part of the project so dont spend to much time getting this right. You can use a terminal emulator to provide a text based interface and use the ARM to generate the text to send or use ANSI chars to generate block graphics. Report The final report should be written to highlight what you have achieved and learnt and should not simply be a technical description of the circuit padded with dozens of data sheets. Although the format is of your choosing it should contain at least the following. Abstract Contents page Planning discussed Design where approp. Test Conclusions References them here Appendices Brief description of what report contains Details of Plan and how well you kept to it should be Minutes of meetings should be reference in appendices Details of major design decisions with calculations Test schedule for hardware and software with results Improvements, mistakes made, what youve learnt Sources used. Dont include data sheets but reference Code listings etc.

There is obviously more that can go in the report but this should guide you in the right sort of direction. There will be marks for presentation so use a reasonable word-processor and bind the final report. Finally You will get out of this exercise what you put in. In the past opinions have varied from students saying This is the most useful thing we have done to completely irrelevant. Needless to say that those who said the latter were the people who left it too late, didnt succeed and got very frustrated. It must be emphasised that you do not have a lot of time and so do not put this module on the back-burner. It is your job to satisfy the requirements of the specification with the materials

available. Although this booklet contains many suggestions you are responsible for ensuring the methods you use are appropriate and the information you are given is correct. If you choose to try something which is a radical deviation from what is suggested then this is OK but we suggest you check it is feasible first with staff. We have not had any real problems with group dynamics in the past but it is worth sorting out right from the outset who will do what and writing this down on paper when you form the project plan. Remember that as a group you are then on your own. It is expected that you sort out the problems, look for information and manage the project. You will NOT be lead through the exercise by staff. They will simply be on hand to help with any difficult problems and to check youve not made any major mistakes. Good luck and enjoy the experience! Dr Paul Davey, TIME \@ "d MMMM, yyyy" 10 January, 2013

"Success is not final, failure is not fatal: it is the courage to continue that counts. Winston Churchill

Appendix A - Microsoft Project Plan TC "Appendix F - ROM Emulators and EPROM Programming" \f C \l "1" EMBED MSProject.Project.4 \s To enter a task simply type the names and duration in the appropriate boxes. To make a task a heading (bold) simply indent the tasks following it using the rightarrow button. To assign a predecessor to a task click right button on the task bar and under Task Info enter the number of the previous task under predecessors. To assign resources (people in this case) follow the same procedure and enter information under Resources. There is a tutorial on-line with the software but dont spend too much time making it look really fancy.

8031 Design Project Page PAGE 13

24v 5v

Micro Signal conditioning LCD PC