USC University of

Southern California
Department of Electrical Engineering - Systems

EE 477 Laboratory #3

Module Design, Cadence and SPECTRE

Submitted By First Name: KARTHIK Last Name: RAMASAMY

Date: 05/06/2013

USC ID: 5539-4733-38

Area X Delay (Neural Network Layout)

Area (micron square) = 110.2 Delay (ns) = 1.3 ns Area x Delay (um sq x ns) = 14870.388 * 103.8 = 11438.76

NEURON:
Description of the Neuron: There are 10 inputs to the neuron:

6 single-bit data inputs to the neuron, T, U, V, W, Y, Z a single-bit inhibitory input I, Load control signal Reset control signal A clock with 50% duty cycle.

The basic Neuron Function:

The neuron output contains a firing flip-flop you designed in Lab 2, and the output of the flip-flop AP represents the output of the neuron. The neuron "fires" when the Boolean expression (VY+WY+VZ+WZ+YZ+VW) + (/I)[T + U] evaluates to a 1. The Boolean equation = ( VY + WY + VZ + WZ + YZ + VW ) + ( /I )[ T + U ] = ( V [ Y + Z + W ] ) + ( W [ Y + Z ] ) + ( YZ ) + ( /I )[ T + U ] = ( V [ Y + Z + W ] ) + ( W [ Y + Z ] ) + ( YZ ) + ( /I )[ T + U ] = ( V [ Y + Z + W ] ) . ( W [ Y + Z ] ) . ( YZ ) . ( /I )[ T + U ]

The Firing Logic is built using 3 - Compound Gates (designed in Lab 1) 1 - inverter1 (for Input I) 1 - 2-Input NAND Gate 1 - 4-Input NAND Gate

The Block Diagram of the Neuron:

The Neuron is built using 3 - Compound Gates (designed in Lab 1) 3 - inverter1 (for /I, /load, /clk) 1 - 2-Input NAND Gate 1 - 4-Input NAND Gate 1 - Flip Flop Floor Plan of the Neuron: Inverter 1 and 2 as Super Buffers

NEURON: Schematic:

Schematic Simulation: Case (a): Load is set to 1 and kept high. All other inputs except clock are 0. Neuron flip-flop is Resetted. clk=2ns

Case (b): Load is set to 1 and kept high. Then the neuron is tested by sequencing through all combinations of inputs starting with TUVWYZ= 000000 to 111111. I=0. Clk=2ns

Case (c): Set I = 1 (inhibition) and sequence through the same inputs. The output AP is low at some times. Clk=2ns

Case (d): Reset the neuron flip flop. Now load is set to 0 (zero).The 6 data inputs to are set to 111111, and I = 0. The flip flop output remains zero. Clk=2ns

LAYOUT:

Layout Simulations: Case (a): Load is set to 1 and kept high. All other inputs except clock are 0. Neuron flip-flop is Resetted. clk=2ns

Case (b): Load is set to 1 and kept high. Then the neuron is tested by sequencing through all combinations of inputs starting with TUVWYZ= 000000 to 111111. I=0. Clk=2ns

Case (c): Set I = 1 (inhibition) and sequence through the same inputs. The output AP is low at some times. Clk=2ns

Case (d): Reset the neuron flip flop. Now load is set to 0 (zero).The 6 data inputs to are set to 111111, and I = 0. The flip flop output remains zero. Clk=2ns

Description of the Simulation Experiments:

Simulations of Schematics and Layouts:

Case (a): Load is set to 1 and kept high. All other inputs except clock are 0. Neuron flip-flop is Resetted. Clk=2ns Case (b): Load is set to 1 and kept high. Then the neuron is tested by sequencing through all combinations of inputs starting with TUVWYZ= 000000 to 111111. I=0. Clk=2ns Case (c): Set I = 1 (inhibition) and sequence through the same inputs. The output AP is low at some times. Clk=2ns Case (d): Reset the neuron flip flop. Now load is set to 0 (zero).The 6 data inputs to are set to 111111, and I = 0. The flip flop output remains zero. Clk=2ns

NEURON NETWORK: SCHEMATIC:

Schematic Simulation:
To determine the fastest clock: The fastest clock is determined at the worst case inputs. Initially the Flip Flop is given Reset. Set the inputs to 0(zero) except T which is set to 1. The I input is changes from 0 to 1 and 1 to zero, which is the worst case condition.

Here the worst case condition is where the signal travels through the maximum number of gates that has the maximum delay in it, i.e. through the inverter-compound gate and the 4-input NAND gate. The output is given at the negative edge of the clock and it is 90% before the positive edge of the clock. The Fastest clock for the schematic is found to be 1.25ns.

Case (a): Showing the working of the Neuron Network for the fastest clock at 1.25ns, with I changing and T=1,U,Y,Z,V,W=0. Load=1, Reset initially.

Case (b): The Enlarged view showing the Clock (1.25ns), output (AP), Inputs (T, I). The output is produced after the negative edge of the clock and is 90% before the rising of the next clock.

LAYOUT:

The Layout of the Neuron consists of original Neuron that fans out to 24 other empty Neurons. The output is measured from the farthest Neuron Input that includes the worst case delay. The output of the original Neuron goes to the Super Buffer Inverters (2,3), which is fan out to 24 empty Neurons. The Layout is built such that it forms a Square Shape so that to reduce the wire delay. The Inputs ITUVWYZ,clk,rst,load and the output AP pins are brought out to the edges Layout. The wasted area is also included in Area calculation. The Metals 1-4 are used for the entire Neural Network.

Layout Simulation:

To determine the fastest clock: The fastest clock is determined at the worst case inputs. Set the inputs to 0(zero) except T which is set to 1.The I input is changes from 0 to 1 and 1 to zero, which is the worst case condition. Here the worst case condition is where the signal travels through the maximum number of gates that has the maximum delay in it, i.e. through the inverter-compound gate and the 4-input NAND gate. The output is given at the negative edge of the clock and it is 90% before the positive edge of the clock. The clock to Q delay comes out to be 0.467ns The Fastest clock for the schematic is found to be 1.3ns.

Case (a): Showing the working of the Neuron Network for the fastest clock at 1.25ns, with I changing and T=1,U,Y,Z,V,W=0. Load=1, Reset initially.

Case (b): The Enlarged view showing the Clock (1.25ns), output (AP), Inputs (T, I). The output is produced after the negative edge of the clock and is 90% before the rising of the next clock.

Design Changes: 1. 2. 3. The Reset signal mechanism of the Flip Flop is changed from transmission gates to the NAND gate, without changing the MUX structure of the Flip Flop. The Diffusions are merged in the 4-input NAND gate that reduces the diffusion capacitances. The Super Buffers are used at the output of the Firing Logic, that gives the sharp rising and falling of the output due to the use of large fast inverters(Inverter 1 and 2 that is built in lab1) The output of the neuron is connected to 24 other empty neurons. The output of the neuron sees a large capacitance at the input of the 24 empty neurons. As a result, it will take a long time for the circuit to simulate and work. To avoid this, we make use of buffers (inverters) which help in reducing the delay of the circuit. To get the original output, we make use of even number of stages, 2 in this case such that the next one is 4 times the previous one with respect to size. Therefore, the inverter 2 and 3 that is built in lab 1 are used as the super buffers at the output of the firing Neuron, improves the performance of the Neuron Network. Minor changes in the Compound gate to reduce the waste area in the layout. The Metal layers used are from 1-4, for the entire network.

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