Module 5:

Advanced Analog
Design
 Signals and Sensors
PSoC’s enhanced analog features allow users to interface with
the outside world, the analog world. This can take place
through a variety of signal processing and sensor interface
possibilities.

Examples:
Signal Processing Sensor Interfacing
Amplitude detection Thermistors
Frequency detection Passive Infrared Detectors
Modulation/Demodulation Ultrasonic Receivers
Filtering Thermocouples
Analog Multipliers Pressure sensors
FSK Strain Gauges
This tele-training module will equip you with the tools to begin
utilizing PSoC’s powerful analog resources.

2
 Fundamentals
Every electrical interaction is Qenclosed
governed by a simple set of
∫ E ⋅dS = ε0
equations: ∫ B⋅dS = 0
Maxwell's Equations dΦ B
∫ E ⋅dL = dt
and, because we're a Silicon dΦ E
∫ B ⋅ d L = µ 0 I + µ 0ε 0 dt
company, particle movement is
governed by:

The Schrödinger Wave Equation d 2ϕ

2
= −
2m
2
[E − U ( x)]ϕ ( x)
dx ⎛ h ⎞
⎜ ⎟
⎝ 2π ⎠
Don't Panic, it's not that hard.

3
 Fundamental Fundamentals
Replace Maxwell and Schrödinger with simple laws:

Ohm's Law E = I ⋅R
Kirchoff's Law ∑I =0
Simple Algebra y = m⋅ x +b
f −3dB = 1
Simple Physics
2πRC
Nyquist Criterion f sample ≥ 2 ⋅ f signal
4
 Op-amp Algebra
Op-amp behavior follows
two simple rules

1. Inputs draw no current.

2. The output will do whatever

is necessary to make the
voltage difference between
the inputs equal to zero.

5
 Op-amp Negative Gain

Simple op-amp algebra

VIN − VINV VINV − VOUT
= Ri Rf
Ri Rf Vin VINV

VINV is 0 only when

Vout
VIN/Ri = -VOUT/Rf

VOUT/VIN = -Rf/Ri

6
 Op-amp Positive Gain

Inputs draw no current, so

Vneg=Vout * Ri/(Ri+Rf)
Ri Rf
Inputs can only be equal
when Vout
Vin=Vout*(Ri/(Ri+Rf) Vin

Vout/Vin = 1 + Rf/Ri

7
 Sine Wave
Examine signal examples

Sine wave
Single frequency
Zero intentional harmonics

8
 Square Wave

Square wave
Harmonics amplitude 1/n

9
 Triangle Wave
Triangle wave
Harmonic amplitude 1/n2

Sampling data
Harmonics may add in
and distort the result
Aliases at sample rate add
image terms

10
 Sampling
Whether its ADCs or
filters, when we think 1

of analog user
0.5

modules we think of
signals and sampling V(t) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5

-0.5

-1

11
 Sampling
Sampling the signal 1

0.5
Quantize the Signal
Amplitude V(t) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 40 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 56 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5

-0.5

-1

Definitions: t

Range := The allowable input voltage.

Resolution := Range/ Number of Quantization Steps
For a “n” bit Converter:
Number of Quantization Steps := 2n
Resolution also known as “LSB” or “∆”

12
 Sampling
Sampling the signal
1

Quantize the Signal 0.5

Amplitude
V(n) 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5

Quantize the Time Domain -0.5

-1

Definitions:
Sample Rate “fs”
Expressed as samples per second “sps”. Not Hz!

13
 Time Domain Quantization
Nyquist in a Nutshell
The Output Signal Frequencies
all map in the range of : 3KHz Signal Sampled at 10ksps
fs
0 ≤ f out ≤
2
This upper bound is know as the
Nyquist limit.

Any input frequencies meeting

this requirement are accurately
reproduced.
f out = f in , (0 ≤ f in ≤ fs
2
)

14
 Time Domain Quantization
Nyquist in a Nutshell
Input frequencies greater than
the Nyquist limit result in output 7KHz Signal Sampled at 10ksps
frequencies that map (alias) Output mapped to 3kHz
into the 0 to Nyquist limit range.
⎧αf − f in ,
=⎨ s
(0 ≤ (αf − f in ) ≤ fs
)
(0 ≤ ( f )
s 2
f out
⎩ f in − αf s , − αf ) ≤ fs
in 2

Given a sample rate of 10ksps,

input signal with frequencies
of 1kHz, 9kHz,11kHz,19kHz.
& 21kHz are all going to map
to an output frequency of
1kHz.
With the whole spectrum mapped into a small bandwidth, a filter is
required to select the desired input frequency. It is referred to
as an “anti alias” filter.

15
 Sampled Sine Wave I
Example shown using BPF, but results
are same for LPF or DAC generated
signal
Filtered waveform example is sampled
approx 7 times per cycle
PSoC filter adds 0.025% distortion (-72
dB) at 2nd harmonic
Sampling process adds first alias at fsample-
fsignal = -16 dB
Sampling process adds other images

Sampling image

2nd Harmonic

16
 Sampled Sine Wave II
Filtered waveform is sampled approx 17
times per cycle
Harmonic distortion same as waveform
with Over-Sample Ratio (OSR) = 7
First alias reduced by 9 dB
Subsequent aliases are smaller
Alias images occur as sin(x)/x
Increased OSR moves sin(x)/x
function closer to null and lowers
image level -- (simple algebra)

Sampling alias
2nd harmonic

17
 Reconstruction
For output waveform, add R-C filter
(simple physics)
Set R-C corner at half of sample
frequency
Reduces first alias image by 10 dB
(factor of 3)
Reduces subsequent alias images
even more
Technique applies to either filter or DAC
Not necessary when signal is being
digitized for internal use

Sampling alias

2nd Harmonic

18
 PSoC Design Fundamentals
What is THE essential element of PSoC analog design?
• Power Consumption?
• Accuracy?
• Frequency Response?
• Signal to Noise Ratio?

wrong

Topology
Hook it up first.
Then worry about how well it works

19
 Analog Block Organization
4 Continuous Time (CT) Blocks
8 Switched-Cap (SC) Blocks
Programmable I/O
4 input mux per column
1 of 8 mux in two columns
Selectable clocks CBus0 CBus1 CBus2 CBus3

Clock mux per column Analog

CT
Analog
CT
Analog
CT
Analog
CT

Digital block or system clock source Analog Analog Analog Analog

SC C SC D SC C SC D
Buffered out each column Analog Analog Analog Analog

Comparator bus each column SC D SC C SC D SC C

Selectable references
ABuf0 ABuf1 ABuf2 ABuf3

20
 Building Blocks:
Analog User Modules
Programmable controls are SRAM register based
CT: 4 registers per block
SC: 4 registers per block
Functionality controlled by SRAM-based registers
Rapidly updated via software
Turn slow PGA into fast comparator in less than 1 microsecond
Allows for Dynamic Reconfiguration
Multiple configurations supported in design tool
Multiple blocks combine to form complex functions
Amplifiers
Multiple byte DACs
Filters
ADC (with timer and counter)

21
 Continuous Time Analog

CT Block configured from op-

amp, resistors and switch
CBUS
VDD
ABUS

array OUT

DC open loop gain > 80 dB

RESISTOR
MATRIX
Op-amp Unity GBW > 9 MHz
Op-amp slew rate to 8 V/us
References
Resistor matching < 0.5%

22
 PGA Topology
Basic Gain Equation
VOUT R
= 1+ B VIN
VIN RA
VOUT

but, Ground isn't necessarily Zero

RB

PGA ref selectable (Choose in globals – Ref Mux) RA

AGND
VSS (real Zero) GNDRef

⎛ Rb ⎞
VO = (VIN − VGND ) ⋅ ⎜⎜1 + ⎟⎟ + VGND
⎝ Ra ⎠

23
 PGA Gain Range
VIN VIN
VOUT VOUT

RB RB

Gain referenced to Vss RA Gain referenced to AGND RA

Used for Used for

Low-side current measurements AC signals
Vss (0.0V) AGND (2.6V)
Ground referenced signals

6 6

5 5

4 4
V(out) V(out)
3 3

2 G=8 2 G=8
G=2 G=2
1 1

0 0
0 1 2 V(in) 3 4 5 0 1 2 V(in) 3 4 5

24
 PGA Bandwidth
PGA bandwidth determined by VIN
VOUT

Op-amp open loop gain

RB CF
Shunt feedback cap (CF = 1 pF)
and feedback resistor RA

AGND

PGA Freq Response, Pow er=High, Bias=High

35
30 G=48
G=24
25 G=16
G=8
20

Gain (dB)
G=4
G=2
15
10
5
0
-5
1 Freq (kHz) 10 100 1000 10000

25
 INSAMP (2 op-amp)
Differential gain + IN
Out

⎛ Rb ⎞
= (VIN + − VIN − )⎜⎜1 + ⎟⎟ + VREF
- IN Abus
VOUT Out
⎝ Ra ⎠ Ra Rb
AGND
A_Bus
Vss
SC Blk Rb Ra

High input impedance Reference

Vin Range: Vcc=5V, AGND=2*Vbg
5

Common mode rejection > 4

Max Vin
59 dB 3 Agnd
Min Vin
2

0 2.00

2.29

2.67

3.20

4.00

5.33

8.00

16.00
Gain

26
 INSAMP (3 op-amp)
+ IN

Input stage has

High differential gain ASIGN
Switches
omitted for

Unity common mode gain

clarity

⎛ R ⎞C
VOUT = (VIN + − VIN − )⎜⎜1 + b ⎟⎟ a + VAGND
AnalogOut

⎝ Ra ⎠ C f - IN AGnd

Improved performance 10 Vcm=

2.5

Vdiff in max
3.0
over INSAMP(2 opamp) 3.5
4.0
4.5

Slightly Improved CMRR

1

Wider input range

0.1

Synchronize with ADC 0.01

1.00

2.00

3.20

4.00

8.00

16.00

24.00

48.00
Gain

27
 Comparators
Vin

Programmable threshold Vcc

Ref to Vss for P/S current sense CompBus

Zero crossing Vin

FSK and doppler processing

CompBus
AGND
Programmable hysteresis Vin

Noise rejection
CompBus

AGND

Vref

28
 Switched Cap Technology
Resistor is replaced

φ1 φ2

1
R=
fSC
29
 Switched Cap Tutorial
The switched cap block
has two discrete phases of
operation:

φ1 Acquisition of signals φ1

Cf φ2

φ2
V os
Transfer of charge
φ1
V in Ci φ1

Vout
φ2

30
 Switched Cap Tutorial
During Phi 1, switches are
closed to:

Place Vin on one side of Ci

Short the output to the φ1
0

negative input and place Vos Cf φ2

on Ci and Cf Vin V os

φ1
V in Ci φ1
Short the output side of Cf to
ground φ2
Vout

31
 Switched Cap Tutorial
Between Phase 1 and Phase 2

All switches are open.

This stores φ1
0

Vin - Vos on Ci
Cf φ2
and Vin V os

-Vos on Cf φ1
V in Ci φ1

V out
φ2

32
 Switched Cap Tutorial
Phase 2 Transfer of Charge
With φ2 open, the input to
Ci was at Vin
When φ2 is shorted, charge
φ1
equal to Ci*Vin is pulled
out of Ci Cf φ2
V os
The output must supply an
equal amount of charge φ1
Ci φ1
V in
to Cf, so:
Vout = (1/Cf)* Ci * Vin Vout
φ2

Vout/Vin = Ci/Cf

33
 Switched Cap PSoC Block C
Programmable op-amp
Supports ∆−Σ and
Incremental ADC
Supports differential amp CC CF
φ1*AZ

Configurable as input half

0-31 C 16-32 C (φ2+!AZ)*F.IN1
CC
Inputs

of biquad filter C.IN φ1*F.IN0

SN
A.IN CA
φ1 0-31 C φ 2+AZ
CA Inputs
OS*φ2B
REF Inputs OBUS
φ2 φ1*!AZ
A.SIGN
A.REF CS
CB
0-31 C CBUS
φ2
CB Inputs PWR

φ1
B.IN

34
 Switched Cap PSoC Block D
Programmable op-amp
Supports ∆−Σ and
Incremental ADC
CC

Configurable as output half CARR

0-31 C

of biquad filter
φ1*AZ

A.IN CA CF
φ1 0-31 C φ 2+AZ 16-32 C (φ2+!AZ)*F.IN1
CA Inputs

REF Inputs φ1*F.IN0

φ2 φ1*!AZ
A.SIGN
A.REF CB
0-31 C
φ2+!B.SW φ2+!B.SW
CB Inputs
OS*φ2B
OBUS
φ1*B.SW φ 1*B.SW
B.IN

CS
CBUS

PWR

35
 Switched Cap DAC
φ1
CA
VOUT = VAGND + / − VREF CF φ2
CF
φ1
VREF CA
Output is NOT rail to rail
DAC6 example φ2 VOUT
VAGND +/- VREF=VBG +/- VBG
φ2
VOUT(MAX) = VBG + VBG*31/32
= 2.559V

VOUT(MIN) = VBG - VBG*31/32

= 0.041V
Analog column output buffer will further
limit output swing, see AN2089

36
 SCBlock as Comparator
Two Cap Comparator
CB
With feedback capacitor CF φ2 φ1
VinB
removed Vout goes to either φ1
the high or low rail. φ1
CA
VinA
Vout goes high when φ2
Vout
VinACA > VinBCB

Vout goes low when

VinACA < VinBCB
VinB is the inverting input input.

37
 PSoC ADCs
The PSoC offers flexible resources allowing the
construction of several types of ADCs.
Each project’s unique System Requirements:
Resolution
Bandwidth
Hardware Utilization (digital blocks)
CPU loading
Interrupt loading
Determine which ADC (or ADCs) makes for the
best fit.

38
 Choices, choices, choices
Trade-offs
Resolution
Sample Rate
% CPU Usage
Start Latency
Block Count
Power
Interrupt Latency
Gain Errors
Linearity (INL, DNL)
Noise
RAM Consumption
FLASH Consumption

39
 Realistic ADC Types
Three types of PSoC ADCs
SAR (Successive Approximation Register)
Minimum block count
Subject to aliasing errors
Incremental
Integrates noise, slow
Enables multiple instances (Dual, Triple)
Delta Sigma
Integrates noise
Fast, continuous sampling
Uses decimator, "There can be only one . . ."

40
 SAR (Successive Approximation Register)

Single Comparator & DAC

DAC resolution determines ADC Comparator
resolution Vin
Logic determines how quickly DAC
zeros-in on input value VDAC

Binary search allows “n” bit DAC to

reach to best value in “n” DAC logic
attempts
The “Successive Approximation
Register” (SAR) is a binary
search algorithm

41
 Incremental ADC
Constructed from:
SCBlock Analog Modulator SCBlock φ1
Timer to set the number of CF φ2
integration cycles
Counter to accumulate the number φ1 φ1*Reset
CA
of comparator high cycles Vin
φ2 To CPU
Ref+
A 12 bit ADC needs Enable

Counter8
Int

Ref-
12 bit counter Data
12 bit timer Bus

φ1
÷4 Clock generator ÷4
φ1,φ2
ADCINC generator φ2

Uses decimator instead of counter, Int To CPU

only one at a time Timer8

ADCINCVR DataClock

Variable resolution
Dual and triple available

42
 Incremental ADC
ADCINC (12 bit) 0
DataClock =4*409600sps (100sps SampleRate)

Not a 12 bit converter. -3 dB freq.

Average of 4096 single bit Output Rate
Nyquist
Limit
conversions . -20

Nyquist limit determined by the

sampling frequency -40
Sample Rate
(Remember fs =fdataclock/4).
dB
Output Rate
-60
fADCout= fdataclock /16640
Nyquist Frequency
fNyquist= fdataclock /8 -80
25

50

100

200

400

800

1600

3200

6400

12800

25600

51200

102400

204800

409600
Frequency (Hz)
Aliasing not a problem until near
Nyquist rate
-3dB bandwidth = .44*Output Rate

43
 Delta Sigma ADC
Constructed from: SCBlock φ1
SCBlock analog modulator
CF φ2
Single digital block
On-chip decimator replaces Vin
φ1
CA
φ1*Reset

counter in Incremental φ2
Ref+ Data

Ref- Decimator Data

Bus

Pipelined ADC Decimator Latch

φ1
Output rate reduced for ÷4
φ1,φ2
φ2
multiplexed inputs generator

One decimator = one Delta Out Int

Timer8
Sigma ADC per system DataClock

44
 Delta Sigma 2nd Order Modulator
Equivalent to a 2 pole filter

Lower noise
Higher allowed clock rate
Faster conversion
Reset
Reset

φ1 φ2
φ1 φ2
Vin
Cmp
φ2 φ1
φ2 φ1
∼φ 2

Ref+ Ref-
Ref+ Ref-

45
 ADC Summary 26xxx, 24/27/29xxx
Sample Rate vs Resolution, clock = 8.0 MHz
Max SPS
100000
INC_2, DS_2 (double
modulator) not in
25/26xxx

INC_2 6,7,8 bit at 10000

12 MHz clock (in
addition to 8MHz)

1000
INC_1
INC_2
DS_1
DS_2
SAR
29x only
100
5 6 7 8 9 10 11 12 13 14 15
Resolution
46
 ADC Summary 26xxx, 24/27/29xxx
Max CPU Load (%) vs Resolution, FCPU=24 MHz
%
100
Logically, longer sample
times and fixed size
data handling code
mean lower % CPU
usage

SAR stalls CPU 10

INC_2 6,7,8 bit at 12

MHz clock
INC_1
INC_2
DS_1
29xxx decimator saves DS_2
SA R
a lot of CPU overhead 29x only
1
5 6 7 8 9 10 11 12 13 14 15
Resolution

47
 Start Latency
Delta Sigma converters are pipelined
Data is smeared from adjacent samples by
decimator
First two samples after start are in error
Cuts multiplex rate by factor of 3

ADCINC also uses Decimator, but

Reset at start of conversion eliminates
smearing and start latency
Decimator serves counter function, saves a
block

48
 Block Count/Power
Analog and digital block usage listed in User Module
data sheets
ADCINC uses decimator
Saves digital block compared to ADCINCVR
Not available as dual or triple
ADCINCVR has adjustable rate, but more blocks
Most of power consumption in analog blocks
Double modulator ADCs consume double power,
reasonable price to pay for:
Higher speed
Lower noise

49
 ADC Noise
Quantization noise = 0.288*Range/resolution
What's a half bit? . . . . A little higher noise
DelSig decimate by 64 listed as 7.5 bits
Output is 8 bits with higher noise on LSB
DelSig decimate by 256 listed as 10.5 bits
Output is 11 bits with higher noise on LSB

Double modulator ADCs

Lower noise than single modulator types
Higher non-linearity at ends of scale

50
 Selection Process
1. Select chip (25/26xxx or 24,27,29xxx)
Prefer 24/27/29xxx for MUCH lower noise

2. Select resolution

3. Select sample rate

4. Choose: continuous data or triggered data

Continuous data: DelSig
Triggered data: ADCINC
Slow signal, low resolution: SAR6

5. Verify CPU load and interrupt structure

6. Verify block availability

51
 ADC Performance
PSoC ADCs are well characterized
Non-linearities generally lower than quantization noise when
operated at specified clock rates

ADC Acquistion Rates

Consistent with signal processing bandwidth of PSoC

Exact rates (e.g., 1.000 ksps)

Achievable with ADCINCVRs by changing calculation time
ADCINC not adjustable with internal clock

DelSig ADCs with non-integer divider clock rates

Achievable by changing PWM
Causes slight gain error (seeAN2095 on u-Law example)

52
 Clock Considerations

User Modules with both analog and digital

blocks (ADCs and DACs) require same
clock to all blocks.

Clock signal is divided by 4 in the mux to set

sample rate

User Module datasheets’ “Parameters”

section lists equations and explanations to
help guide clock settings

53
 Clock Limitations

User Module Column Clock

DAC8, DAC9, MDAC8 ≤ 500 kHz
DAC6, MDAC6 ≤ 1 MHz
Switch-Cap Comparators ≤ 2 MHz
Filters ≤ 6 MHz
Delta Sigma ADCs ≤ 8 MHz
Incremental ADCs ≤ 8 MHz

54
 DAC Clock Considerations
DAC User Module Datasheets specify that the Column
Clock is 4 times the output update rate.

DAC8, DAC9, and MDAC8

Max output update rate = 125 ksps

DAC6 and MDAC6

Max output update rate = 250 ksps

55
 Clock Considerations
Delta Sigma ADCs ≤ 8.0 MHz
Linearity is improved for ADC clock ≤ 2.0 MHz

DELSIG8 DataClock = SampleRate × 256

DELSIG11 DataClock = SampleRate × 1024

DELSIG8 Example
Max Sample Rate = 31.25 ksps
31,250 × 256 = 8 MHz

DELSIG11 Example
Max Sample Rate = 7.8 ksps
7,800 × 1024 ≈ 8 MHz

56
 Clock Considerations

Incremental ADCs ≤ 8 MHz

Governing Equations:*

ADCINC12 DataClock = SampleRate × 65 × 256

ADCINC14 and ADCINCVR DataClock specified as ≤
8 MHz in User Module Data Sheets

ADCINC12 Example
Max Sample Rate = 480 sps
480 × 65 × 256 ≈ 8 MHz

* See User Module Data Sheets

57
 Reference Structure
PSoC is Single Supply, so ...

Establish Artificial Ground

(called "Analog Ground") at mid-supply

Establish Reference used for ADC, DAC

VBandGap = 1.300 +/- 0.02 V

Selectable ground and reference

VBandGap for absolute voltage systems

Vdd/2 for supply ratiometric systems

External VREF for increased flexibility

58
 Ground + Reference Values
Precision Base Reference
VBandGap Tolerance
Vcc =
1.5% worst case over temp 5.00V
Excellent P/S rejection
Reference Offsets
< 50 mV Vcc =
Sets system accuracy 3.30V

References for "Real Signals"

Scale 0.0 to 4.0V
Agnd= 2.0V
Ref=+/-2.0V
Scale 0.0 to 2.6V
Agnd=VBG (1.3V)
Ref=+/-VBG (1.3V) Vcc/2 Vcc/2 Vcc/2 VBG P2.4 2*VBG Vcc/2 1.6*VBG
+/- +/- +/- +/- +/- +/- +/- +/-
VBG Vcc/2 P2.6 VBG P2.6 VBG Vcc/2 1.6*VBG

59
 Reference / Ground Structure
There is no massive ground plane as in a normal good board design
Distributed ground to eliminate crosstalk
Requires careful system and power design

Ground buffer offset adds to error budget

Vdd

2*Vbandgap RefHI to
Analog

X1.6
P2[4]

X2

X1
Blocks
Vdd/2

AGND

P2[4] (External Cap)

Vbandgap
RefLO to
X1

P2[6] Analog
Blocks

Vss

60
 Analog Ground Bypass
External cap connection VBG Vcc
RefHI

Bypass internal distributed P2.6

ground
RefLO

Vss

Reduces noise to ground buffers

X12
Ground Buffer in
Distributed each Analog Block

in analog blocks
Vcc/2 Ground
AGND
P2.4
40k 2k

Analog block ground buffer noise VNAGND

remains P2.4
i/o Ext
1 uF

dBV/rtHz
Application 10000
0
0.01
Audio to ultrasonic 0.1
1.0
signal processing 10

1000

100
0.001 0.01 0.1 Freq (kHz) 1 10 100

61
 Filters: Application Examples
Transmit Generation
FSK Generation per AN2095
Coin Detector: 1-10 kHz swept BPF

Receive Processing
IR: 38 kHz BPF
Video Sync Detector: 15 kHz BPF
Fish Finder: 180 kHz BPF, 20 kHz LPF
Phone Modem: 1.8-2.2 kHz BPF4
Power Line Modem: 133 kHz BPF4, 12 kHz BPF2, 3 kHz LPF
U/S Motion Detector: 40 kHz BPF, 10 kHz LPF
Coin Detector: Synchronous with transmit

62
 Filters: Design Possibilities
Currently available User Modules:
Low Pass 2 pole
Band Pass 1 pole-pair

Others in work include:

Low Pass 4 pole
Band Pass 2 pole-pair
Elliptical
Notch
High Pass

Select filter design to meet attenuation requirements

Balance design goals with side effects

In-band amplitude and phase performance
Out-of-band amplitude and phase performance
Pulse rise time and overshoot characteristic changes
Sampling alias/images

63
 Continuous Time Filters
PSoC’s Analog System consists of both Switch Cap and Continuous
Time Blocks. There are filter options for both sets of blocks

Continuous Time Filters:

Implement standard Sallen + Key topology
Programmable gain stage simplifies design
Design methodology well known
Requires 4 external passive components
HPF and LPF design spreadsheets in app notes
Especially useful for anti-aliasing filters

64
 Continuous Time
Low Pass Filters
Use PGA as fixed gain block with C4
passive R + C
Design equations VERY standard Vin
R1 R2
+K Vout
Every analog IC company has C3

a filter design program

C4
Vout

Primary use: R1 R2 C3
Vin
Anti-alias filters
Remember aliases in signal
description?
Aliases also occur in ADC,
adding to noise bandwidth --
so it's important to suppress
out-of-band noise

65
 Continuous Time
High Pass Filters
R4
Preferred over switched-cap high pass filter
Wider upper frequency limit C1 C2
Vin Vout
No errors due to low sampling R3
+K

Consider switched-cap BPF

R4 Vout

Filter shape is adjustable Vin

C1 C2 R3
AGND

Uses additional PGA UM

Additional Resources
AN2030 - Adjustable Sallen and Key High-Pass
Filters
AN2031 - Adjustable Sallen and Key Low-Pass
Filters
AN2099 - Single-Pole IIR Filters

66
 Switched Capacitor Filters
Standard Topologies
Low Pass, Band Pass, Notch, High Pass
RC Biquad maps to Switched Capacitor Blocks

R2
C2 φ1 φ2
C4
C4
CA CB
1 R3 CA
Vin R φ2 φ2
CB
1
1 Vout Vin C1
φ1 C3 φ2
φ2 Vout
φ1 φ1
φ2 φ1

Scalable, Programmable, Connectable

67
 Filter Placement
LPF2 BPF2
Input on A Block Input on A Block
Output on B Block Output on A Block
Comparator to Bus

C2 φ1 φ2 C4
C2 φ1 φ2

C4 CB
CA φ1 C3 φ2
CA
CB Vin φ2 C1 φ2
Vin φ2 C1 φ2
φ1 C3 φ2 φ2 φ1
φ2 Vout
φ1 φ1 φ1
φ1 Vout
φ2 φ1
AnalogBus

CompBus

68
 Filter Placement
Input on A-cap
ACA ACA ACA ACA
Allows use of modulator 00 01 02 03

ABUS(1)

ABUS(3)
Enables elliptical or notch filter (UM
delivered later) P2.1 ASA ASB ASA ASB
10 11 12 13
Input on B-cap
No modulator P2.2

Inputs through Mux or direct on P2.x

ASB ASA ASB ASA
20 21 22 23

BPF placements similar

ACA ACA ACA ACA
Output on same block as input 00 01 02 03

ABUS(1)

ABUS(3)
Chainable to BPF or LPF
P2.1 ASA ASB ASA ASB
10 11 12 13
Eliptical and Notch horizontal only
ASB ASA ASB ASA P2.2
20 21 22 23

69
 Low Pass Filter
Programmable -3 dB point ⎛ ⎛ s ⎞2 ⎞ 2
⎜1 − ⎜ ⎟ ⎟f
⎜ ⎜⎝ 2 f S ⎟⎠ ⎟ S
and d −
C1 ⎝
C 2 ⎛ C AC B 1 1 C 4
⎠
⎞
⎜⎜ − − ⎟⎟
300 Hz to 150 kHz Vout
= ⎝ C 2 C3 4 2 C 2 ⎠
2
Vin C4 sf S fS
s2 + +
Scaled to clock C 2 ⎛ C AC B 1 1 C 4
⎜⎜ − −
⎞
⎟⎟
⎛ C AC B 1 1 C 4
⎜⎜ − −
⎞
⎟⎟
⎝ C 2C3 4 2 C 2 ⎠ ⎝ C 2 C3 4 2 C 2 ⎠

C2 φ1 φ 2
C4

CA
CB
Vin φ2 C1 φ2
φ1 C3 φ2
φ2 Vout
φ1 φ1
φ2 φ1

70
 Band Pass Filter
Programmable Q and fc ⎛
s⎜⎜1 +
s ⎞
⎟⎟ f S
⎝ 2 f S ⎠
300 Hz to 150 kHz
C1 C B
−
C 2 C3 ⎛ C A C B 1 1 C 4 ⎞
⎜⎜ − − ⎟⎟
Scaled to clock Vout
Vin
=
C4
⎝ C 2 C3 4 2 C 2 ⎠
sf S fS
2
s2 + +
Zero-crossing output for C 2 ⎛ C AC B 1 1 C 4 ⎞ ⎛ C AC B 1 1 C 4 ⎞
⎜⎜ − − ⎟⎟ ⎜⎜ − − ⎟⎟
energy detector ⎝ 2 3
C C 4 2 C 2 ⎠ ⎝ 2 3
C C 4 2 C 2 ⎠

applications

C2 φ 1 φ2 C4

CB
CA φ1 C3 φ2

Vin φ2 C1 φ2
φ2 φ1

φ1 φ1
Vout
AnalogBus

CompBus

71
 Elliptical Low Pass Filter
Notch can be tuned above or below ⎛ ⎛ s ⎞2 ⎛ C C
⎜1 + ⎜ ⎟ ⎜ PP A
−
1 ⎞ ⎞⎟ 2
⎟ fS
⎜ ⎜ ⎟ ⎜ 4 ⎟⎠ ⎟
low pass corner −
C1 ⎝ ⎝ 2 f S ⎠ ⎝ C1C 3 ⎠
C2 ⎛ C AC B 1 1 C4 ⎞
⎜⎜ − − ⎟⎟
Vout
= ⎝ C 2 C3 4 2 C 2 ⎠
Ratio of fzero to f-3dB limits above Vin
s2 +
C4 sf S
+
fS
2

attenuation above fzero C2 ⎛ C AC B 1 1 C4 ⎞ ⎛ C AC B 1 1 C4 ⎞

⎜⎜ − − ⎟⎟ ⎜⎜ − − ⎟⎟
⎝ C 2 C3 4 2 C 2 ⎠ ⎝ C 2 C3 4 2 C 2 ⎠

Can be combined with additional

sections

C2 φ1 φ 2
C4

CA
CB
Vin φ2 C1 φ2
φ1 C3 φ2
φ2 Vout
φ1 φ1
φ2 φ1

CPP

72
 Notch Filter
Special case of elliptical ⎛ ⎛ s ⎞2 ⎛ C C
⎜1 + ⎜ ⎟ ⎜ PP A
−
1 ⎞ ⎞⎟ 2
⎟ fS
⎜ ⎜ ⎟ ⎜ 4 ⎟⎠ ⎟
C1 ⎝ ⎝ 2 f S ⎠ ⎝ C1C 3
low pass where: −
C2 ⎛ C AC B 1 1 C4 ⎞
⎠
⎜⎜ − − ⎟⎟
ωzero = ωpole Vout
= ⎝ C 2 C3 4 2 C 2 ⎠
2
Vin
Band pass gain of Q in first
C4 sf S fS
s2 + +
C2 ⎛ C AC B 1 1 C4 ⎞ ⎛ C AC B 1 1 C4 ⎞
⎜⎜ − − ⎟⎟ ⎜⎜ − − ⎟⎟
stage limits maximum ⎝ C 2 C3 4 2 C 2 ⎠ ⎝ C 2 C3 4 2 C 2 ⎠

signal

C2 φ1 φ 2
C4

CA
CB
Vin φ2 C1 φ2
φ1 C3 φ2
φ2 Vout
φ1 φ1
φ2 φ1

CPP

73
 Multi-Section Filters
Two poles per block pair
Up to 8 poles using all switched-cap, but leaves
nothing left for ADC or DAC
Can be combined with CT-based Sallen + Key

74
 Design Methods
Filter Wizards included in PSoC Designer
Right click on a filter (once placed) to access the filter wizard

Available as LPF, BPF 2 and 4 pole versions .xls in

Cypress MicroSystems/PSoC Designer/Documentation/Filter Design

75
 Filter Sampling Effects - Warping
Sample rate causes a phase delay, lowers filter corner frequency
Corrected by biasing filter higher by 2*fS/fC*tan-1(πfC/fS)
Over-sample ratios >20 add very little error
Compensation built into design .xls and wizards

1.25

1.20

1.15

1.10

1.05

1.00
1 10 100

76
 Filter Sampling Effects - Peaking
Complex zeros (in numerator of transfer function) peak the
response and limit the asymptotic attenuation
Compensation built into design .xls and wizards

⎛ ⎛ s ⎞2 ⎞ 2
⎜1 − ⎜ ⎟ ⎟f 20
⎜ ⎜⎝ 2 f S ⎟⎠ ⎟ S Peak, Peak, OSR=70
C1 ⎝ ⎠ Peak, OSR=10
− OSR=35
C 2 ⎛ C AC B 1 1 C 4 ⎞ 0
Peak, OSR=140
⎜⎜ − − ⎟⎟
Vout
= ⎝ C 2 C3 4 2 C 2 ⎠
Vin 2 Net, OSR=10
C4 sf S fS -20
s2 + +
C 2 ⎛ C AC B 1 1 C 4 ⎞ ⎛ C AC B 1 1 C 4 ⎞
dB
⎜⎜ − − ⎟⎟ ⎜⎜ − − ⎟⎟ Net, OSR=35
⎝ C 2 C3 4 2 C 2 ⎠ ⎝ C 2 C3 4 2 C 2 ⎠ -40
Net, OSR=70

-60
Net, OSR=140
Nom inal
-80
100 1000 10000 Freq (Hz) 100000 1000000

77
 Switched Capacitor Block
Functions: Examples
Gain Invert Block φ1
Equivalent to MDAC
CF φ2
Invert Signal Polarity
φ2 φ1
When CA=CF then gain is -1 Vin CA
Both samples and outputs on
φ1 Vout
φ2.
Can be strung together
Functions as a bus to route a
signal from one side of the
analog columns to the other.
System Gain Inversion

78
 SCBlock Amplifier Examples
Bi-Directional Current Source• Vset
DAC6
DiffAmp configured with gain of one.
CF=CB=CA=16
Sign = Pos DiffAmp
Buf0
External Resistor and DAC value sets -B Vout
P0.3
current.
Vload P2.1 x1
+A
Independent of load. Rset

i = -Vset / Rset
Vout = Vload − Vset Rload

Vout − Vload Vset

i= =−
Rset Rset

79
 SCBlock as Integrator
SCBlock Integrator
Uses standard gain stage with the
exception that the switch to φ1
discharge CF has been disabled. CF φ2
So:
φ1
Vin CA
CA
Vout = Voutold + Vin φ2 Vout
CF

Vout ⎛ C A ⎞ 1
= ⎜⎜ f s ⎟⎟ ⋅ s = 2πf − 1
Vin ⎝ C F ⎠ s

80
 SCBlock as Integrator
SC Integrator
(Doing an Op Amp’s Job) φ1
CF φ2
Negative Gain Integrator closely
resembles a positive input grounded φ2
open loop op amp. Vin CA
φ1 Vout

⎛ Vout ⎞ ⎛ CA ⎞ 1
⎜⎜ ⎟⎟ = −⎜⎜ f s ⎟⎟
⎝ Vin ⎠ SCInt ⎝ CF ⎠ s
Vin
Vout
⎛ Vout ⎞
≈ −(2πGBW )
1
⎜⎜ ⎟⎟
⎝ Vin ⎠Opamp s

81
 SCBlock Integrator - Faux Op Amp
SC Integrator
Faux Opamp Rf

This circuit is an inverting amplifier

φ1
and single pole low pass filter.
Rin CF φ 2
Its gain is determined with external φ2
resistors. Vin Vin
CA
buf

The bandwidth is determined with φ1 Vout

Switched Capacitor Values.
External Resisters
Sample Frequency

⎛ Vout ⎞ ⎛ Rf ⎞ 1
⎜⎜ ⎟⎟ = −⎜⎜ ⎟⎟
⎝ Vin ⎠ SCInt ⎝ Rin ⎠ 1 + s C A ⎛⎜1 + R f ⎞⎟
f s C F ⎜⎝ Rin ⎟⎠

82
 SCBlock - Opamp

Vin

Rin
100k

Rf 100k

Vout

CT Op Amp can be unstable in this mode

83
 SCBlock - Peak Detector
Dual Input SC Integrator
Feedback through diode and
φ1
capacitor makes a Peak CF φ2
Detector.
φ1
Vin CA
buf
5
φ2 Vout
Vout
4
Vpk
Volts φ2
3 CB
Vin
2
φ1

1
Vpk

0
Cext Reset
using
GPIO

84
 SCBlock - High Current Source
Dual Input SC Integrator •
Or a Single Block
Programmable High Power φ1
Current Source. CF φ2 V

φ1 iload
RefHi CA
buf

φ2
Vout
C
Asign Ref High A + AGND φ2
I load = 31 CB Rset
Rset φ1

85
 SC Modulator
Modulator multiplies by a series +1…-1…+1…-1…
Toggles Sign bit in A-cap input under logic control

sin( n 2πf mod t )

v(t ) = ∑
n = odd n
Generates sum and difference frequencies
PLUS
Sum and difference from multiples of modulator frequency

86
 SCBlock Analog Modulator
φ1
Analog Modulator CF
φ2
ASC10, 12, 21, 23
φ1
CA
φ1
Vin
Digital Connections φ2 Vout

Low (no modulation) ASign

GOE[1] low (no modulation)

GOE[1]

GOE[0] GOE[2]
Row 0 Broadcast Bus
Analog Column Comparator 0

Row 0 Broadcast Row

Analog Column Comparator 1
Analog Column Comparator 2
AMod Analog Column Comparator 3

Analog Column Comparator 0,1,2,3

Enables connection from BPF zero- CBus0 CBus1 CBus2 CBus3

crossing out to BPF or LPF modulator ACB00 ACB01 ACB02 ACB03

input for frequency shift or energy B ASC10 ASC12

P2.3
detector A
ASD11
A
A ASD13

P2.2
P2.1 A
A ASD20 ASD22 A
ASC21 B ASC23
P2.0

ABuf0 ABuf1 ABuf2 ABuf3

87
 SCBlock Analog Modulator
Heterodyne
Heterodyne
Mixing of two or more signals to
Low
produce a different frequency. Pass Vout
Vin
Filter
Analog modulator heterodyne is built
around the property that multiplying two (Modulator)
sinusoids produces:
PWM
Ref GlobalOut0
Output sinusoid with a frequency equal to 10kHz

the difference of the two input

frequencies. sin( f a ) ⋅ sin( f b )
Output sinusoid with a frequency equal to
the sum of the two input frequencies. cos( f a − f b ) cos( f a + f b )
= −
Low pass filter removes sum frequency 2 2
Removed with
low pass filter

88
 SCBlock Analog Modulator
Heterodyne
Heterodyne Example PSoC
10kHz reference frequency is input Cin Buffer1
Low Buf1
P0.7 P0.5 Vout
to the modulator bit of the low Vin Pass
Filter
pass filter. 0.1µF
(Modulator)
Rin
10K PWM
Ref GlobalOut0
11 kHz Input Signal is converted to Buf0
10kHz

a 1kHz Output Signal. P0.3

AGND

FColumnClock ≤ 6 MHz

89
 SCBlock Analog Modulator
Full Wave Detector
PreAmp
Comparator
Gain Stage (Full Wave Detector)

Signal Flow
Signal comes into Preamp
Goes to Gain Stage and
Comparator
Comparator Output used to
control Gain Stage
modulator bit
Example:
4 cycle 20 kHz burst

90
 SCBlock Analog Modulator
Amplitude Demodulator
Comparator
PreAmp
Low Pass Filter (AM Demodulator)

Signal Flow
Signal comes into Preamp
Goes to Low Pass Filter and
Comparator
Column Comparator 1 is used to
control Low Pass Filter
modulator bit
Example:
10 cycle 50 kHz burst

91
 Modulator: Analog or Digital
Analog modulator
Implements function in SC block

Digital modulator
XOR is equivalent

Examine typical system design with modulator

for non-amplitude based signals

92
 Digital Modulator FSK Detector

FSK Examples
HART Modem, Bell202 (Caller ID)
0 = 1200 Hz, 1 = 2200 Hz
Power Line Modem
0 = 131.850 kHz, 1 = 133.050 kHz
v(t ) = VP sin(2π ( f L + data( f H − f L ))t )

Correlator sin(2πft) -cos(2πfd)

Multiplies signal by delayed replica

TIME DELAY, d
Integer cycle delay = positive output Delay Clock sin(2πf(t+d))

Integer + 1/2 cycle delay = negative

Implemented in Modulator in LPF or in sinfl

XOR (in row LUT) followed by LPF

sinfl delay

fl corr

filt fl corr

sinfh

sinfh delay

fh corr

filt fh corr

0 500 1000 1500 2000

93
 SC Analog Modulator
FSK Detector
FSK In
BPF LPF FSK Out

24 bit
Delay S/R Hysteresis
Clock Comparator Input Dig Data
(1200 Baud
Filter / Comparator 1 bit Lo, 2 bits Hi)

Convert to zero-crossing FSK Modulated

Delay Line
Implemented with Shift Register from Comparator Out
PRS block Modulator Out

Out of Phase In Phase

S/R In
S/R Out Shift Reg. Out
`
Delayed Comp.
PRS XOR Output
(Correlator Out)
Delay 5
Clock

Filtered Correlator
Low Pass Filter 6
Bandwidth near baud rate Digital Data Out

Comparator finds the data 7

Detection Delay = 620 usec

94
 Measuring FSK Performance
An "eye pattern" shows transmission
of repetively sampled random data
1: Input data
2: FSK modulated data
3: Correlator output
4: Detected digital data
(Horizontal synced to input data)

"Openess" of the eye indicates quality

of received data
Risetime determined by sum of
correlator delay and filter
bandwidth.
Width of line determined by resolution
of correlator delay clock and
sharpness of filter
Finer resolution takes more blocks
Better filter takes more blocks.

95
 FSK: Customer Example
PSoC in phone application PSoC (CY8C27443) Replaced
Update from Call Waiting/Caller ID app note TL494 PWM P/S controller
MT8870 DTMF decoder
98% Customer Design 80C52 processor
93C46 EEPROM
2 LM324 opamps
Analog filters
TLC555 timer + discretes
Line voltage detect circuit
Enabled Zero Cost Additions
DTMF Dialer
Caller ID
True Sinusoidal Ring Tone
Improved line voltage monitor
Improved audible ringback
Programmable ring voltage

96
 Limited Slew Amplifier
Slow Slew (Volts/sec) is Bad for fast
signals!
...but, there are applications for
slow slew amplifiers

A comparator with and external R C

simulates an opamp with
programmable slew. R
∆Vout V 2 Vout
i=C i ≈ cc
∆t R
C
∆Vout Vcc 2
≈
∆t R ⋅C
R & C determine Slew Rate.

97
 Limited Slew Amplifier Example
Universal AC Motor
Voltage across the Commutator is:
Mains power less the voltage drop across the Com+
field coils.
Mains
Inductive switching pulses for brush switching.
Com-
Amplitude of pulses is:
Proportional to the voltage across the
commutator.
Frequency of pulse is:
Dependent on rate of switch changes.
Proportional to shaft speed. (RPM)
determined by commutator switching
If Mains power component can be
suppressed, the pulses can easily be
Digitized.

98
 Limited Slew Amplifier Example
Slew Rate Limited Pulse Separator
Amplifier allows low frequency
signals (Mains Power) to pass.
Vin
Fast Slewing signals
(Commutator Noise) are
blocked, leaving only the Diff Amp
pulses at the output of the Diff
Amp.
Forms an effective phase neutral Vout Slew Limited
OpAmp
high pass filter.
No distortion of Pulses
No Delay

99
 Limited Slew Amplifier Example
PSoC Implementation of Slew
Rate Limited Pulse 1M 1M

Separator 1k 1k

SENSE+ SENSE-

Presently implemented with: PulseDetect

Compare
6 Analog Blocks
2 Digital Blocks
For Production Implemented with:
27k

5 Analog Blocks
.1uF

1 Digital Block
Remaining Resources:
58% of Analog Blocks
87% of Digital Blocks AGND
InAmpOutVout
Vout

100% of CPU

100
 Limited Slew Amplifier Example
PSoC Implementation of Slew
Rate Limited Pulse
Separator
Scope Traces show that the 60Hz
signal is removed with no visible
distortion of pulses.

Pulses can easily be digitized

(and counted)

Demo’ed to customer!
101
 1/f Noise
Noise example
ADCINCVR direct input from quiet source with
long term average subtracted
Scale is in ADC counts (300 µV per bit)

Note slow wander . . . . 1/f

THE dominant type of noise in most measurement systems

62
RAW(SIG-AVG(REF)}

61

60

59

58

102
 Start with a "nice, clean" signal
Start with a clean signal: 0.015

3.0 mV DC 0.010

Example: output of pitot tube 0.005

Differential pressure
indicator of air speed 0.000

-0.005

Signal
-0.010

Add noise: 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

0.015

10.0 mV 3.0 Hz sine wave

Representative (but much 0.010

larger) of the low 0.005

frequency noises in the

PSoC 0.000

Representative of -0.005

environmental noise Signal

-0.010
Signal+Noise
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

103
 Get Rid of Noise by Averaging
Sample at 100 Hz 0.015

Take average of some 0.010

number of ADC
measurements, but ... 0.005

0.000
4 sample average does
Signal
nearly nothing -0.005
Signal+Noise
Average(4)
-0.010

16 sample average doesn't 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

help much either 0.015

0.010
Logically, we must average
much longer than the noise. 0.005

0.000
Filter for 3 Hz noise will take 10-
12 seconds -- not useful -0.005 Signal
Signal+Noise
Average(16)
-0.010
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

104
 Correlated Double Sample
Sample low frequency noise
Short the inputs
Measure INSAMP out Store VSIGNAL

INSAMP 13 bit ADC

Sample noise + signal
Switch inputs to source
Measure INSAMP out

Compute difference VSIGNAL

Subtract stored noise from noise INSAMP 13 bit ADC
+ signal

Compute running average with easily implemented IIR filter

105
 Voila
Correlated Double Sampling 0.015

Removes common mode low 0.010

frequency noise 0.005

IIR filter over 4 samples 0.000

80% reduction in noise -0.005 Signal

Signal+Noise
CDS:IIR(4)
-0.010
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

IIR over 16 samples 0.015

95% reduction in noise 0.010

0.005

0.000

Signal
-0.005
Signal+Noise
CDS:IIR(16)
-0.010
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8

106
 CDS Antidote to 1/f Noise

Apply lessons of Correlated Double Sample (CDS)

Short inputs, measure offset, subtract instantaneous offset from direct
input
Blue trace shows CDS signal
Average more constant, Std Dev (σ) remains the same
62 RA W(SIG-AVG(REF)}
RA W(SIG-REF)
61

60

59

58

Now, add filtering

107
 CDS + IIR
Correlated Double Sample (CDS) removed most of 1/f
Infinite Impulse Response (IIR) filter provides running
average
Raw Std Dev σ = .816 counts
IIR (25%) on Non CDS σ = .518 counts
IIR (25%) on CDS σ = .224 counts

62 N(avg)=4(SIG-AVG(REF))
N(avg)=4(SIG-REF)
61

60

59

58

108
 CDS + more IIR
Longer IIR filter provides longer running average
Raw Std Dev σ = .816 counts
IIR (5%) on Non CDS σ = .465 counts
IIR (5%) on CDS σ = .085 counts
IIR filters require simple computation, near zero RAM
IIR (like any other filter) reduces data bandwidth
Technique proven in customer applications
App Notes in process

62 N(avg)=20(SIG-AVG(REF))
N(avg)=20(SIG-REF)
61

60

59

58

109
 System Design Example:
X-10 Receiver

Power line communications for consumer applications

Signal
120 kHz 1 msec pulse at zero crossing
Rides on top of AC line (110 V)
Level = 50 mV to 4 V p-p -- requires AGC
Data encoded in presence/absence of pulse

110
 X-10 Receiver Block Diagram
3 kHz LPF takes 120 kHz carrier out of zero x-ing sync
3 kHz HPF takes 50/60 Hz line out of carrier path
Demo shows 120 kHz detection only
Line connections left as exercise for student
Zero x-ing detector and AGC to follow later
3 kHz LPF Zero X-ing
Detector

COMP

PGA DATA
3 kHz HPF 120 kHz Full 10 kHz
Band Pass Wave Low Pass
Filter Detector Filter
COMP

AGC (digital) Gated

ADC

Zero X-ing Detector and AGC

left as exercise fo the student

111
 PSoC Topology
User modules dropped in
Parameters set from spreadsheet calculations
DigBuf used to route comparator output to port

112
 Switched Cap Filter Design
Band Pass Filter Low Pass Filter
Enter parameters Common Clock with BPF
Adjust C2 to align peak High OSR is important to reject 2x
Tighter bandwidth is possible carrier in full wave detector
Mod bit built into ASC A-cap
4 pole filters are possible, but
consume blocks
Cypress MicroSystems 1 Pole Pair Low Pass Filter Design, Rev 2.1 Design Procedure
Cypress MicroSystems 1 Pole Pair Band Pass Filter Design, Rev 2.1 Design Procedure Design Requirements Enter Data fields in yellow
Design Requirements Enter Filter Specification (data fields in yellow) Enter: Corner Frequency (Hz) 11000.0 Verify calculated Cx parameters in range of 1:31
Enter: Center Frequency (Hz) 120000.0 Enter C2 value ( range 1:31) Enter: Gain (dB) 0.00 Verify calculated "d" matches designed "d"
Enter: Bandwidth (Hz) 10000.0 Verify C1-4 values in range 1:31 sample freq 1500000.00 Verify calculated corner frequency matches designed value
Enter: Gain (dB) 0.00 Select Plot Resolution, adjust scales as necessary Enter 0 or 1: Type Butterworth 1 Adjust plot scales as necessary
Enter: Sample Frequency 1500000.0 Verify expected filter performance, adjust C2 and Sample Frequency Enter 0 or 1: .1 dB Cheb. 0 Transfer values for C1,C2,C3,C4,CA,CB User Module Parameter Table
Transfer values for C1,C2,C3,C4,CA,CB to User Module Parameter Table Enter 0 or 1: 1 dB Cheb. 0 Select clock source and dividers (24V1,2 or dig block), set for div by n
Select clock source and dividers (24V1,2 or dig block), set for div by n Enter 0 or 1: Bessel 0
Enter 0 or 1: Custom Complex Poles 0
Derived Filter Section Requirements
Enter 0 or 1: Custom Real Poles 0
Q 12.000 Enter resolution 0 for Narrow Band, 1 for Wide Band 0.000
osr 12.500 Derived Filter Section Requirements Custom Complex Poles
f0 (with pre-warp) 122592.1318 OSR 136.364 Enter Real Part of Pole Location 0.4
Band Pass Frequency Response
Gain (V/V) 1.000 1.0 d (damping ratio) 1.414 Enter Imaginary Part of Pole Location 0.7
User Module Design Parameters d compensated 1.445
0.0 With pre-warp allowance scaled f0 11001.95 Custom Real Poles
Enter: C2 ( to UM) 14
CA (default to UM) 32 Gain (V/V) 1.000 Enter Plow scaled to corner freq. 0.037
-1.0
CB (default to UM) 32 User Module Design Parameters Enter Phigh scaled to corner freq 1
C3 (calculated) 17.74 -2.0 If C2<1 reduce sample freq C2 (calculated) 1.020
Gain (dB)

C2 ( to UM) 1 Low Pass Frequency Response

C3 ( to UM) 18 10
-3.0 CA (default to UM) 32 re im
C4 (calculated) 2.254

Gain (dB)
C4 ( to UM) 2 -4.0
CB (default to UM) 32 0 Bu 0.707107 0.707107
C1 (calculated) 1.125 If C4>>31, reduce sample freq C4 (calculated) 31.368 .1Ch 0.6104 0.7106
-10
C1 ( to UM) 1 -5.0 C4 ( to UM) 31 1 Ch 0.4508 0.7351
C3 (calculated) 2.061 -20 Bess 1.103 0.6368
Calculated Q 13.541 -6.0
Required fs 1500000.000 C3 ( to UM) 2 -30 Custom 0.4 0.7
Divide by n (Calculated for 24 MHz clock) 4.00 -7.0 C1 (calculated) 1.000
Adjusted divide by n -40
4 100000 110000 120000 130000 140000 150000 C1 ( to UM) 1
Sample Clock (Hz) 1500000.000 Nominal Expected Freq (Hz) Caculated d 1.392 -50 real 0.037
Nominal 1
Calculated Gain (V/V) 0.889 Required fs 1500000.000 selected 0.707107 0.707107
Expected
Divide by n (Calculated for 24 MHz clock) 4.000 -60

Adjusted Divide by n 4 -70

Sample Clock (Hz) 1500000.000
-80
Corner Frequency 10633.987
1000 10000 100000 1000000
Gain Calculated (V/V) 1.00 Freq (Hz)

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 Parameters and Resources
Set User Module Parameters
Control LPF polarity in software

Set Global Parameters

Easily limited to ref and clock selections

Set Pin-outs

Use modulator bit to generate full wave detector

Placement limited to ASC10 blocks
Comparator output routed through DigBuf
Modulator built into LPF2 User Module

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 Software
Start analog user modules ;------------------------------------------------
; X-10 Receiver Assembly main line
Enable modulator ;------------------------------------------------
include "m8c.inc" ; part specific constants
AMD_CR1 is in Bank 1 ; and macros
include "memory.inc" ; Constants & macros for
; SMM/LMM and Compiler
include "PSoCAPI.inc" ; PSoC API definitions for
; all User Modules
export _main

_main:

; Set UM power and start

mov A, PGA_1_HIGHPOWER
Compile call PGA_1_Start
mov A, BPF2_1_HIGHPOWER
Build call BPF2_1_Start
Switch to Debugger mov A, LPF2_1_HIGHPOWER
call LPF2_1_Start
Connect to ICE mov A, CMPPRG_1_HIGHPOWER
call CMPPRG_1_Start
Download program ; Enable Modulator in LPF2_1
M8C_SetBank1
mov reg[AMD_CR1], 04h
RUN M8C_SetBank0

.terminate:
jmp .terminate

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 System Test
Signal source: waveform generator in burst mode
120 kHz, 1 msec at 120 Hz rate

120 kHz carrier burst

Band Pass Filter output

Full Wave Detector/LPF output

Detected carrier output

Total design, program, build and test: 2.0 Hours ( + documentation)

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 Advanced Analog Design Summary
PSoC offers flexible resources to accomplish sensor
interfaces, signal processing, and system controls.

PSoC Designer quickly and easily unlocks the Analog

functionality of PSoC
Filters
References
Amplifiers
Clocking Options
Power Concerns
ADCs
…and more

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