Feexch

Fundamental of Digital Transmission, Encoding & Modulation
Techniques, Definition & Discription of Digital hierarchies, Digital

Multiplexing concepts, Signal justification & Control, Jitter & Line
Coding
FUNDAMENTAL OF DIGITAL TRANSMISSION
Introduction
Basically there are two ways in which information of any type can be
transmitted over telecommunication media – analog or digital. Analog means that
the amplitude of the transmitted amplitude signal varies over a continuous range.
Digital transmission means that streams of on/off pulses are sent on the
transmission media. The pulses are referred to as bits. Examples of analog signals
are human voice, hi–fi music, temperature reading, etc. While that of digital are data,
telegraphy signals.
Telecommunication systems started with the transmission of digital signals. In

fact, non–electric signalling systems date back over 2000 years. The Greek General
Polybius is known to have used a scheme based on an array of 10 torches in 300
B.C. and Roman armies made extensive use of a form of samaphore signalling.
Claude Chappe, Sommering, Wheatstone and Cook were all experimenting with
different kinds of Telegraphy till it was perfected by Mores. In all this, only written
message was transmitted and message was converted to a coded signal to match
the characteristics of a transmission line. Gary, Bandot and others developed other
codes which were mainly used in Telegraph network. Thus, we can say, by 1972
most of the basic techniques of digital transmission had been discovered.
In 1876, Alexander Graham Bell invented the Telephone and as means of

communication, the telephone was fast, personal and convenient. It needed no
training in the use of codes and so made electrical communications directly
accessible to the general public. Thus, telephone began to dominate the
development of communications. Telephony involves the transmission of analog
signals and when a practical amplifying service appeared in the form of the
thermionic valve, this also proved suitable for dealing with analog signals. Hence,
after 1880, the developing Telecom networks were basically designed to handle
analog transmissions and to an increasing extent, the digital transmission in the form
of telegraphy had to be adopted to fit in with the characteristics of these networks.
By 1950s, the world's communications systems were based entirely on analog
transmission.
However, interest in the digital transmission received an impetus after the
publications of classic papers of Nyquist and Shannon. With the invention of pulse
code modulation by Reeves in 1938, the basic principles for digitizing analog speech
signals were established. However, the technical means for transmitting digitized
speech signals were not available at that time. It was not until the transistor came
into use that indications of the economic advantages of digital techniques as
compared to analog methods became apparent. LSI and VLSI techniques that are
now available have made digital communications far more economical as compared
to analog methods became apparent. LSI and VLSI techniques that are now
available have made digital communications far more economical as compared to
analog systems. Digital transmission systems are gaining more acceptance in view
of : (1) introduction of digital switching systems, (2) the need to transmit non voice
signals which are increasingly becoming important instead of the plain old
Telephone service, and (3) the introduction of new media like optical fibres,
waveguide which are more suitable for digital transmission systems, will be
introduced in the network and by the turn of the century, most of the countries would
have gone completely digital.
Advantages of Digital Communication

(i) Fig.1 shows the qualitative representation of the signal to noise ratio
along a transmission line. In both analog and digital systems the signal
power P is subject to line attenuation which can be compensated by
repeaters. However, a main difference exists in the accumulated noise
power N. In the transmission of analog signals, this power Na is
amplified in linear repeaters by the same factor as the useful signal
and the noise contributions from the individual repeater section
accumulate. In the digital transmission on the other hand, the signal is
practically achieved of the noise Nd with the aid of regenerative
repeaters. Residual noise may only become effective in the form of
digital errors and jitter due to regeneration, reshaping and retiming (3
Rs.) carrier out section by section, only the digital errors are
accumulated while the noise is not. The need to recognise only
the presence or absence of a pulse makes the system highly immune
from noise. Thus, the transmission quality is almost independent of
distance and method of transmission involved. This is of particular
value in transmission paths subject to extreme interference such as for
instance in space flights or in communications with interplanetary
probes.
Fig. 1
Signal to Noise Ratio Along A X–Mission Path
(ii) Compatibility of different media : Cables, radio links, switching
equipment can be interconnected without decoding the digital signals
by means of relatively cheap interface equipment which contributes
little or no impairment to the signal. There is thus no need to take any
consideration of the particularities of the original signal.
(iii) Compatibility of different traffic : Any digital media of suitable capacity

can carry encoded speech, telephone signalling, telegraphy, digital
data, encode visual information or an arbitrary mixture there of. The
desperate requirements of these signals can be handled in the
terminals and have no mutual interference between different types of
traffic. The introduction of ISDN is thus possible.
(iv) Multiplexing, demultiplexing, branching of digital signals produce no

additional interference as noise in analog communications. Hence,
these can be done as often as necessary. Moreover, all bits are
subject to same interference and hence all TDM channels are treated
equally, i.e. there are no channels of inferior quality as for instance in
FDM transmission certain channels at the edges of the tranmission
bands.
(v) Level fluctuations occurring during transmission have no effect on the

primary signal recovered in the receiver. In FDM, however,
sophisticated equipments are required to maintain the level more or
less constant.
(vi) Economies in certain applications : PCM is inherently cheaper than

the FDM and the investment needed can be made progressively as the
traffic growth justifies it. Economies can be achieved by combining
services already of a digital nature. Digital signals can be switched by
digital exchanges without demodulation.
(vii) Possibility of novel facilities : The digital mode lends itself to such
things as cryptography, storage and various forms of digital processing
not accomplished otherwise.
(viii) Applicability to other transmission media : Optical fibre waveguides

multiple access satellites appear to be more suited digital than to
analog information.
(ix) Applicability to extremely difficult transmission paths.
(x) Simpler equipment : There is no need of complicated filter and analog

amplifiers for various ranges.
(xi) Easy repeatability of design.
Main Obstacles to Digitalisation

(a) Spectrum width : For example the bandwidth required for 2700
channels is 12 MHz in the case of analog systems where as band
width required in the case of 1920 channels is as much as 140 MHz.
Thus, band width required is very large in the case of digital signals,
this results consequently :
(i) Less efficient use of carrier capacity in terms of telephone

channels;
(ii) Working at very high frequencies;
(iii) Need of multi–level modulation for radio transmission;
(iv) Voice interpolation required for satellite communication;
(v) Higher sensitivity to selective transmissions caused by

propagation.
(b) Different transmission of TV signals : Digital transmission of TV signals

requires a very wideband if redundancy reduction is not used which,
however, involve higher cost and quality problems for moving images.
(c) Reliability and power consumption : For the same transmitted signals,
digital transmission equipments are in general more complex than
analog ones.
Eqpt. Analog Digital
Line repeaters
2W 4W
(12 MHz Vs 140 Mb/s)
1+1 Radio repeater
(1800 FDM Vs 140 200 W 600 W
Mb/s)
Means to overcome digital transmission limits :

(a) Evolution of high frequency components and technology
– Hybrid circuits
– High speed integrated circuits
– FET's amplifiers (for radio transmission)
(b) Introduction of large scale integrated components (LSI, VLSI)
– Use of microprocessor (for functions such as adaptive

combination, voice interpolation etc.).
– increased circuit compactness (TV encoding, Signal processing,

etc.).
– reduced power consumption.
Pulse Transmission
Channel Capacity or Information Rate

In general, the capacity of a channel for information transfer is proportional to
its bandwidth. Two major theories that relate to the amount of data that can be
transmitted based upon the bandwidth of a medium are the Nyquist Relationship and
Shannon's Law. Prior to discussing these theories, it is important to understand the
difference between bit and baud due to the confusion that dominates the use of
these terms.
Bit versus baud

The binary digit or bit is a unit of information transfer. In comparison, the term
baud defines a signalling change rate, normally expressed in terms of signal
changes per second.
In a communications system, the encoding of one bit per signal element

results in equivalency between bit and baud. That is, an information transfer rate of
X bits per second is carried by a signalling change rate of X baud, where each baud
signal represents the value of one bit. Now, suppose our communications system
was modified so that two bits are encoded into one signal change. This would result
in the baud rate being half the bit rate, which obviously makes bit and baud non–
equivalent.
The encoding of two bits into one baud is known as dibit encoding.
Nyquist relationship
In 1928, Harry Nyquist developed the relationship between the bandwidth and
the baud rate on a channel as
B = 2W
where B is the baud rate and W the bandwidth in Hz.
The Nyquist relationship was based upon a problem known as intersymbol

interference which is associated with band–limited channels. If a rectangular pulse is
input to a band–limited channel, the bandwidth limitation of the channel results in a
rounding of the corners of the pulse. This rounding results in the generation of an
undesired signal in which the leading and trailing edges formed due to signal
rounding can interfere with both previous and subsequent pulses. This signal
interference is illustrated in Fig.3.
Fig. 3
Pulse response through a band–limited channel. The bandwidth limitation of a

channel causes the leading and trailing edges of a pulse to interfere with other
pulses as the signal change exceeds twice the bandwidth of a channel. This
condition is called intersymbol interference.
The Nyquist relationship states that the rate at which data can be transmitted
prior to intersymbol interference occurring must be less than or equal to twice the
bandwidth in Hz. Thus, an analog circuit with a bandwidth of 3000 Hz can only
support baud rates at or under 6000 signalling elements per second.
Since an oscillating modulation technique such as amplitude, frequency or

phase modulation halves the achievable signalling rate, a twisted pair telephone
circuit supports a maximum signalling rate of 3000 baud.
Shannon's law
In 1948, Claude E. Shannon presented a paper concerning the relationship of
coding to noise and calculated the theoretical maximum bit rate capacity of a
channel of bandwidth W Hz. The relationship developed by Shannon is given by
C = W log2 (1+S/N)
where
C = capacity in bits per second,
W = bandwidth in Hz,
S = Signal power at the receiver input
N = power of thermal noise = No.W
Bit Baud Rate, Symbols

We wish to transmit fb bits/s in a baseband channel having a bandwidth of B
Hz. In most applications, the transmission system is considered to be more cost
effective, if, in a given bandwidth, more bits/sec can be transmitted. If fb, the
transmission rate, is normalized to a Bandwidth B = 1 Hz, then the system efficiency
can be characterised in terms of transmitted bits per second per Hz (b/s/Hz).
Nyquist theorem on minimum Bandwidth transmission systems states that it is

possible to transmit fs independent symbols in a channel (low pass filter) having a
bandwidth of only B = fn = fs/2 Hz.
If the digital signal changes at a rate of N bits/sec, then the modulated phase
would change at a rate of N/2 symbols/sec. This rate of change of symbols is known
as the Baud–rate (R).
Nyquist Criteria, Roll Off Factor

Give an ideal low pass change of Bandwidth Bo Hz, it is possible to transmit
independent binary symbols through the channel at the maximum rate Rb = 2 Bo
bits/sec. Equivalently, given a bit rate Rb = 1/Tb, the Bandwidth Bo = 0.5 Rb defines
the minimum transmission bandwidth acceptable for distortion-less transmission.
The Bandwidth Bo so defined is called Nyquist Bandwidth.
For practical usefulness, however, the minimum Bandwidth Solution has to be

modified. It is done by (1) permitting a channel Bandwidth B in excess of the Nyquist
Bandwidth Bo, and (2) introducing transition region shaped as one–half of a raised–
cosine. The width of the transition region is controlled by the role off factor x, defined
as excess bandwidth (i.e. the amount by which the channel Bandwidth B exceeds
the Nyquist Bandwidth Bo) divided by the Nyquist Bandwidth itself.
In the raised cosine solution, flexibility exists in the selection of the

transmitting and receiving filters. This flexibility can be exploited to provide noise
immunity. In particular, given a base-band channel of transfer function H(f) and a
message source of known waveform, we can optimize the transfer function HT(f) of
the transmitting filter and the transfer function HR(f) of the receiving filter, so that the
following 3 requirements are jointly satisfied.
(i) ISI is Zero.

(ii) Probability of symbol error is minimized.
(iii) Constant power is transmitted.
(iv) Nyquist BW required has been defined as equal to half the symbol
rate, i.e. N.BW = R/2
Thus, for a 140 Mb/s signal, the symbol rate = 70 Mb/s if QPSK is employed.
The minimum BW needed for transmitting so many symbols without ISI is 35 MHz.
This is the one sited filter Bandwidth. The total RF BW would include both sides of
the spectrum and be equal to 70 MHz. This is the theoretical minimum BW.
If 16 PSK is used, then Baud rate = 35 MB/s.
Nyquist BW = 17.5 MHz.
Total channel BW = 35 MHz.
What is Inter Symbol Interference (ISI) ?

Inter symbol interference is interference between adjacent symbols due to
pulse spreading by band limited channels.
Because of the delay (as the band width of channel is finite) the delayed
version of wave form of one sampling interval will extend into the next sampling
interval leading to ISI.
Suppose that binary information is transmitted using a pulse type waveform.
A 1 Volt pulse is used to send a 1 and 0 Volt pulse for a binary 0. When this
waveform goes through the system, it gets distorted. Among other effects, any sharp
corners of the wave are rounded, since the system cannot pass infinite frequency.
Therefore, the values in previous sampling intervals affect the value within the
present interval. If for example, we send a long string of 1s, we would expect the
channel output to eventually settle to a constant 1. Similarly, if we send a long string
of 0's, the output should eventually settle towards 0. If we alternate 1's and 0's, the
output might resemble a sine wave, depending upon the frequency cut off of the
channel.
Therefore, if we examine a single interval in which a binary 1 is being

transmitted, the output waveform within that interval will depend upon the particular
sequence that preceded the interval in question. If we now plot all possible
waveforms within the interval, including those for a 1 and those for a 0 in the interval,
we get a pattern that resembles a picture of an eye.
The following figure (Fig.6) shows some representative transmitted

waveforms and the resulting receiver waveform. The eye pattern is sketched.
The eye pattern is, therefore, the superposition of many waveforms within one
sampling interval, the components of this composite waveform being the signals due
to all possible preceeding data strings. The number of individual waveforms
contributing to the eye pattern depends upon the memory of the system. For
example, if the system transient response extends over six sampling intervals, the
particular pattern of six most recent bits determines the waveform within the interval.
Transmitter Receiver
Superimposition of Received Waveform
Fig. 6 Generation of Eye Pattern
Superposition
of received
waveforms
Encoding & Modulation Techniques
If transmission media were perfect, we would not have to worry about errors
in data communications. Unfortunately, that is not the case. Noise spikes and other
types of interference can change 1s to 0s and 0s to 1s during transmission. A short
20 ms click on a telephone line may be annoying during a telephone conversation,
but it is unlikely to disrupt voice communication. However, if data are being sent over
the line at 4800 b/s, that same click may destroy 240 data bits. A number of
techniques have been developed to detect and sometimes to correct errors.
All of the methods of detecting errors involve the transmission of redundant

data. Redundant data are data that are not necessary to the information content of
the transmission. Redundant data could be omitted and communication would still
take place. Error checking schemes compare the redundant data to see if they
agree. If they do agree, it is likely that no error has occurred. If they do not agree, it
is almost certain that an error has occurred.
The simplest way to deal with errors is to let the receiving operator correct
them. This method takes advantage of the fact that human language itself is
redundant. For example, suppose the following sentence is sent over a news service
communication system as part of a news story :
THE DOWNTOWN BRANCH OF THE BANK OF CENTERVILLE WAS

ROBBED OF MORE THAN $4000 LAST NIGHT.
If the transmission is sent to Baudot, and the first bit of the second W in the
word DOWNTOWN is changed by a noise spike, the message will be received as :
THE DOWNTOAN BRANCH OF THE BANK OF CENTERVILLE WAS

It would not be difficult for the receiving operator to realize that DOWNTOAN
is not a word and to make the necessary correction before publishing the story.
There is enough reduntant information in the message to do that. However, if the
character 4 in the sentence is affected by noise, and the message is received as :
THE DOWNTOWN BRANCH OF THE BANCK OF CENTERVILLE WAS
the receiving operator will know that there is an error in the message but will
probably not know how to fix it. There is enough redundant information in the
message to detect the error, but there is not enough to correct it.
In most of today's data communication systems, the only types of errors that
humans are expected to correct are typing errors. Most communication systems
detect and correct errors that occur after the information leaves the keyboard.
Echoplex
Echoplex is a simple form of error detection that relies on redundant
transmission to help the sending operator make corrections. It is commonly used on
full–duplex communications systems in which each character is sent as it is typed
into the transmitting terminal. Almost anyone who has used a computer and a
modem has used echoplex. As the receiving terminal receives each character, it
retransmits or echoes it back to the transmitting terminal where it appears on that
termianal's screen. The operator checks the character on the screen to see if it has
been echoed correctly. If there is an error, the operator presses the backspace key
to erase the erroneous character and then types the correct one.
The advantage of echoplex is its simplicity. It does not require complex

circuitry, and it is easy to implement. One disadvantage of echoplex is that it relies
on a human operator to detect and correct errors. Another disadvantage is that it
makes inefficient use of the communications channel, because the same information
is transmitted in both directions. Although echoplex is commonly used to correct
typing errors in communication systems that transmit information as the operator
types it into a terminal, it is not used in other types of communications systems.
Parity
Parity is one of the simplest forms of automatic error detection and is
frequently used with the ASCII code. Although ASCII is a 7–bit code, a redundant
bit, called a parity bit, is often added to the ASCII character. The parity bit is placed
in the most significant bit (bit 7) position. There are two types of parity – odd and
even. If even parity is used, every 8–bit data word in a message contains an even
number of binary 1s. If odd parity is used, every word has an odd number of 1s. As
the parity bit is added to the ASCII character by the sending terminal, it is either set
or cleared to form the correct parity.
Neither type of parity has an advantage over the other in most

communications systems, and both are widely used. However, the transmitting and
receiving terminals must use the same type of parity, and all characters sent
between those two terminals must have the same type of parity.
Example 5–6
The following ASCII characters are sent : 110 0001, 111 0010 and 110 0101.
If the characters are transmitted with odd parity, where parity bit is added to each
character, a 1 or a 0? What is the ASCII code for each character in hexadecimal
including theparity bit ?
Solution
For odd parity, the total number of binary 1s in each character, including the
parity bit is odd. The first character, 110 0001 has three 1s, which is already odd
parity. Therefore, a parity bit of 0 is added in the MSB position to make the complete
8–bit data character 0110 0001, or $61. The second character, 111 0010 has an
even number of 1s. The sending terminal adds a binary 1 as a parity bit to make the
total number of 1s odd. The resulting ASCII character, including the parity bit , is
1111 0010, or $F2. The third character, 110 0101, also requires a 1 for odd parity,
which makes the complete data character 1110 0101, or $E5.
The receiver checks the parity of each incoming ASCII character to see if it is
correct. If the receiver is programmed to receive odd parity, every incoming data
word must have odd parity. If it is programmed to receive even parity, every
incoming data word must have even parity. If one bit in a data character gets
changed by noise during transmission, the parity of the received character will be
incorrect. When incorrect parity is received, it is called a parity error. For example,
suppose a communications system uses even parity and that the ASCII character
1011 1000 is sent. If a noise spike changes bit 1, the character will be received as
1011 1010, which has odd parity. This is a parity error.
How a communication system responds to parity errors depends on how the

terminals have been programmed. In a half–duplex or full–duplex system, the
receiving terminal may send a message back to the transmitting terminal requesting
that the entire message containing the error be retransmitted. In a simplex system,
the receiving terminal cannot send messages back to the transmitting terminal, so
there is no way for it to request retransmission. In such a case, the terminal may be
programmed to print a star (*) on the screen to let the receiving operator know that
an error has occurred.
A parity error is generated when an odd number of bits is changed during

transmission, but no parity error is generated when an even number of bits is
changed. For example, suppose 2 bits are changed by noise during transmission so
that the character 1011 1000 is received as 1011 1110. Although the receiver
character contains two errors, both the received character and the character that
was originally sent have even parity. The receiving terminal does not generate a
parity error, and the data error is not detected.
Like all methods of error detection, parity adds redundant information ot the
data stream. A disadvantage of parity is that it detects only errors that affect an odd
number of bits in a data word. An advantage of parity is that it is simple to
implement. Because of its simplicity, parity is widely used.
Horizontal and Vertical Parity Check

A better method of detecting errors involves using a combination of
horizontal and vertical parity checks. The simple parity check discussed in
Section 5–2–2 is a horizontal parity check. Vertical parity is calculated for all of the
bits with the same bit number in a block of data. After a block of data has been sent,
the transmitting terminal calculates a parity bit for bit 0 of all of the characters in the
block, another parity bit for bit 1 of all of the characters, and so on. The vertical parity
bits are transmitted as a block check character (BCC) at the end of the block of
data.
Either even or odd parity may be used for both the horizontal and vertical
parity bits. The same parity may be used for both, or one of them may have even
parity, and the other may have odd parity. However, the transmitting and receiving
terminals must use the same parity scheme. For illustration, the horizontal parity in
Table 1 is even, and the vertical parity is odd. Bits 0 through 6 in the figure are the
ASCII code for the information transmitted. Notice that even the parity bit of the BCC
passes both the vertical and horizontal parity check.
Table 1
A short message using even character and odd column parity
ASCII
P b6 b5 b4 b3 b2 b1 b0
Character
1 1 1 0 0 1 0 0 d
1 1 1 0 0 0 0 1 a
0 1 1 1 0 1 0 0 t
1 1 1 0 0 0 0 1 a
1 0 1 0 0 0 0 0 SP
0 1 1 0 0 0 1 1 c
0 1 1 0 1 1 1 1 o
1 1 1 0 1 1 0 1 m
1 1 1 0 1 1 0 1 m
1 1 0 0 0 0 1 1 BCC
The receiver checks the horizontal parity of each character as it is received.

The receiver also generates its own BCC and compares it with the check character
received at the end of the block of data. The two should be identical. If they are not,
an error has occurred, and the receiver can request that the sending terminal
retransmit the block of data.
However, the combination of horizontal and vertical parity checking does
more than detect errors. It also allows the receiver to correct single–bit errors without
requesting further information from the transmitter, a process known as forward
error correction (FEC). Table 2 shows the data block of Table 1, but bit 1 of the SP,
or space, character has been altered by noise. Both the horizontal parity check for
the space character and the vertical parity check for bit 1 fail. Therefore, bit 1 of the
SP character must be in error. The receiver can correct the error by changing the 1
back to a 0.
Table 2
Bit 1 of the SP character fails both character and column parity checks
and is therefore in error.
ASCII
P b6 b5 b4 b3 b2 b1 b0
Character
1 1 1 0 0 1 0 0 d
1 1 1 0 0 0 0 1 a
0 1 1 1 0 1 0 0 t
1 1 1 0 0 0 0 1 a
1 0 1 0 0 0 1 0 SP
0 1 1 0 0 0 1 1 c
0 1 1 0 1 1 1 1 o
1 1 1 0 1 1 0 1 m
1 1 1 0 1 1 0 1 m
1 1 0 0 0 0 1 1 BCC
Unfortunately, the combination of horizontal and vertical parity can reliably

perform FEC only on single–bit errors. Errors that involve two or more bits cannot
always be corrected. To illustrate, in Table 3, both bit 1 of the SP character and bit 2
of the character c have been changed by noise. Both characters fail horizontal parity
checks, and bits 1 and 2 fail their vertical parity checks, but the receiver cannot
determine which bits are in error. The error could just as easily be bit 2 of the space
character and bit 1 of character c. Even though the receiving terminal cannot
perform FEC, at least the receiving terminal can determine that a transmission error
has occurred, and it can request that the sending terminal retransmit the entire block
of data.
Table 3
Two–bit errors can be detected by a combination of character and column
parity checks, but they usually cannot be corrected
ASCII
P b6 b5 b4 b3 b2 b1 b0
Character
1 1 1 0 0 1 0 0 d
1 1 1 0 0 0 0 1 a
0 1 1 1 0 1 0 0 t
1 1 1 0 0 0 0 1 a
1 0 1 0 0 0 1 0 SP
0 1 1 0 0 1 1 1 c
0 1 1 0 1 1 1 1 o
1 1 1 0 1 1 0 1 m
1 1 1 0 1 1 0 1 m
1 1 0 0 0 0 1 1 BCC
No system of error checking is 100% foolproof. Table 4 contains 4 bit erorrs.

Bits 1 and 2 of both the SP and c characters have been altered during transmission.
Both characters pass their horizontal checks, and both bit positions pass vertical
parity checks. Even the combination of horizontal and vertical parity checks has
failed to detect the errors.
Parity bits can be generated by software routines in the sending terminal, and
they can be checked by software routines at the receiving terminal. However, it is
more efficient to generate and check parity bits in hardware. Figure 11 is the
schematic of a circuit that can be used to generate horizontal parity bits. The 7 bits
of the ASCII character are applied to the inputs labelled bit 0 through bit 6, and a
bias bit is applied to the remaining input. If the bias bit is a 1, the correct horizontal
parity bit will be generated to give the character odd parity. A bias bit of 0 will cause
the circuit to generate the correct horizontal parity bit for even parity. Trace the
circuit by assuming a set of inputs to assure yourself that it works.
Parity generator and checker circuits are part of the DTE circuit. They were
once constructed from discrete, exclusive OR gates as shown in Figure 11 below,
but today they are built into a larger integrated circuit that also performs other
communication tasks, as will be discussed in Chapter 8.
Fig. 11
A Parity Generator Circuit
Table 4
Even the combination of character and column parity checks
will not detect all errors
ASCII
P b6 b5 b4 b3 b2 b1 b0
Character
1 1 1 0 0 1 0 0 d
1 1 1 0 0 0 0 1 a
0 1 1 1 0 1 0 0 t
1 1 1 0 0 0 0 1 a
1 0 1 0 0 1 1 0 SP
0 1 1 0 0 0 1 1 c
0 1 1 0 1 1 1 1 o
1 1 1 0 1 0 1 1 m
1 1 1 0 1 1 0 1 m
1 1 0 0 0 0 1 1 BCC
Checksums
As illustrated in Table 5, a checksum is the least significant byte of the
arithmetical sum of the binary data transmitted. As the data is sent, the transmitting
terminals sums it. At the end of the data block, it sends the least significant byte of
the sum as an extra character, called the checksum. The receiver generates its own
checksum by summing the data as it is received. At the end of the block, it compares
the checksum it generated with the checksum it receives from the transmitter. If the
two are identical, it is likely that no error occurred. If the two checksums are different,
an error has occurred, and the receiver requests that the block of data be resent.
Table 5
The checksum is the least significant byte of the sum of the coded data
Character EBCDIC
T $E3
e $85
r $99
r $99
i $89
b $82
l $93
e $85
Checksum $BD
Cyclic Redundancy Check (CRC)

One of the more effective methods of error detection is the cyclic
redundancy check (CRC). A circuit that can be used to generate a 16–bit CRC
character is shown in Fig.12. Identical CRC circuits are used in the transmitting and
the receiving terminals to generate a check character which is highly dependent on
all the data that were sent in the block. We will use the CRC circuit in the receiving
terminal as our example.
Shift right register Shift right register Shift right register
Data
input
Fig. 12
A CRC circuit
The CRC circuit is initialized with all 0s in the shift registers. Each time a bit is
received, every bit in the shift registers is shifted right. Assume that the first bit
received is a 1. It is exclusively 0Red in G3 with a 0 shifted out of b0 of the shift
register to produce a logical 1 which is in turn shifted into the b15 position of he shift
register and continues to shift right as each subsequent bit is received. Four
received bits later, it will have been shifted to the b11 position where it will influence
the output of exclusive OR gate G1. The output of G1 is shifted to the right until it
arrives at the b4 position and influences the output of G2. The G2 output in turn
shifts right to the b0 position where it is exclusively 0Red with a received bit of data
to influence the output of G3 and thereby the input to the CRC circuit.
The important thing to recognize is that once a bit is received, it continues to

influence the contents of the shift registers in the CRC circuit. If one bit is received
incorrectly, it will cause the contents of the CRC shift registers to be different than
they would have been if all bits had been received correctly.
As mentioned, the transmitting terminal has a CRC circuit identical to the

CRC circuit in the receiver. As each bit is transmitted, a copy of that bit is input into
the CRC circuit. At the end of the block of data, the sending terminal transmits the
contents of its CRC registers. When the receiver receives the CRC character, it
compares it with the contents of its own CRC registers. The two CRC characters
should be identical. If they are not, an error has occurred in transmission, and the
receiver can request that the sending terminal retransmit the block of data.
Although Fig.12 shows a circuit that generates a 16–bit CRC, 32–bit CRCs
are also common in many data communication systems. Twelve–bit and 24–bit
CRCs are used in some systems. Like the parity checker circuit, CRC generators
are usually not separate circuits as shown in the figure. They are included in a larger
integrated circuit that also performs other data communications functions.
Summary
In this chapter, we have looked at codes used in data communications and
methods used to detect and sometimes correct errors. Of the codes presented in
this chapter, the two that are most commonly used in data communications are
ASCII and EBCDIC. Baudot is a 5–bit code, and it was the first code to be widely
used for data communications. Baudot has two modes, a letters mode and a figures
mode, each with its own character set. The LTRS and FIGS characters are used to
shift back and forth between the two modes. Communications systems that once
used Baudot have now almost all switched to the ASCII code.
ASCII is a 7–bit code, although a redundant 8–bit, called a parity bit, is

sometimes added to detect errors. There is also an 8–bit version of ASCII which is
called extended ASCII. ASCII is used both in data communications and to store data
in personal computer memories and disks.
EBCDIC is an 8–bit code that was developed by IBM Corporation for use in
its larger computers. EBCDIC is also used in equipment that was designed to be
compatible with those IBM Computers.
Errors inevitably occur in data transmission. In some systems, those errors

tolerated, and nothing is done to correct them. However, a number of schemes been
developed to detect and sometimes correct errors. All of these methods are
redundant information. In echoplex, the receiving terminal echoes each recent
character back to the sending terminal where it appears on the terminal screen, i.e.
terminal operator visually inspects each character to make sure that it is correct.
Echoplex's main use is to correct typing errors.
Parity is an extra bit that is added to each data character in the MSB position.
The parity bit is set or cleared to ensure that each character either contains an even
number of 1s or that each character contains an odd number of 1s. Parity is
consequently used with the ASCII code.
A combination of horizontal and vertical parity checks cannot only detect

errors, but also allow the receiver to correct single–bit errors, a process known as
forward error correction (FEC). This system, in addition to having a parity bit each
character, uses a binary check character (BCC) which is transmitted at the end of a
block of data.
A checksum is no more than the least significant type of the arithmetical sum
of all the binary characters transmitted in a block of data. Both the transmitter and
the receiver calculate a checksum, and at the end of a transmission, the sending
terminal transmits the checksum which the receiver then compares with its own
checksum.
A cyclic redundancy check (CRC) character can be formed by circulating

transmitted data through a system of shift registers and exclusive OR gates.
Identical circuits are used at the transmitter and receiver. At the end of a block of
data, a sending terminal transmits its CRC character, and the receiver compares it
with the CRC character that it has generated. If the two CRC characters are
different, then error has occurred.
MODULATION TECHNIQUES
1.0 Introduction
In order to transmit digital signals over Radio systems. It is necessary to transfer the information to the Radio
frequency carrier.
Digital, information can be imposed upon the carrier by modifying the

amplitude, frequency, phase or a combination of these characteristics, The
choice of the modulating scheme is made after considering a number of
conflicting requirements, which include susceptibilities to noise interference,
fading, non linearities, spectrum efficiency (i.e. Bits/sec/Hz) and equipment
complexities with associated cost aspect. The spectrum efficiency is a ratio of
bit speed (say R bits per second) and band width say B Hz. This ratio i.e, R/B
is known as the spectrum efficiency for the particular modulation technique
adopted for the purpose of modulation of the RF carrier. The following
sections describe the most commonly adopted digital modulation schemes.
2.0 Amplitude Shift Keying
In general, for amplitude modulation, the amplitude of the carrier is varied in

proportion to the amplitude of the modulating signal and the carrier
frequency does not change The special cases-of digital modulating signals
are referred to as amplitude shift keying. A number is usually added as per
the number of the digital symbol states. Ti&us binary signals produce 2 ASK
and 4 level signals produce 4 ASK. The ASK signals are generally expressed
mathematically as:
X (t) = g (t) x A x cos {2π fc t)
where g ft) is the random digital signal. A binary ASK modulator is

symbolized in Fig. 2.1 where the binary bits cause switching between carrier
'ON’ and 'OFF' states.
Binary input
Fig. 2.1
ASK MODULATOR
FIG. 2.2
SIGNAL CONSTELLATION
BANDWIDTH LIMITED AT 2 ASK AT Q

FIG 2.3 ASK WAVESHAPE
The power spectral density of the resultant 2 ASK signal as the same as that of the random
data signal but mirrored about the carriers.
In the normal ASK signal the presence of DC component in the modulating
signal results in the presence of a carrier component, which contains no information
in the output signal and is a waste of available transmitted power.
2.1 Suppressed Carrier ASK
If the DC component is removed from the random signal, the resultant
Signal is referred to as double side band suppressed carrier amplitude
modulated signal often abbreviated to the word DSB.
2.2 Single Sideband ASK

The modulating process produces both upper and lower sidebands and the
spectrum occupancy of the signal doubles. Since either of the sidebands of
ASK signals contains the information to be transmitted, spectrum efficiency can
be improved considerably by elimination of one of the sidebands, such a system is
known as single sideband suppressed carrier amplitude modulation (SSBSCAM)
usually abbreviated to SSB. To separate the sidebands a perfect high or low pass
filter is required with a cut off at the carrier frequency.
2.3 Vestigial Sideband ASK

An alternative method to overcome the difficulties associated with SSB
signals is to transmit a small part (vestige) of the other sideband. This is
known as vestigial sideband amplitude modulation VSBAM often
abbreviated to VSB.
3.0 Frequency Shift Keying

In frequency modulation, the frequency of the carrier is varied in proportion to the
amplitude of the modulating signal and the carrier amplitude remains
constant; Since for 'digital modulation the baseband signal takes on only one of the
two values, the frequency of the modulation also will take one of the two values and
the modulation prosess can be thought of as a keying operation. In general, the binary
FSK signal can be mathematically expressed by.
X(t) = A Cos (2π fc t+2πfd ∫ g (t) dt + φ).

where A. and fc are the carrier amplitude and frequency, g(t) is a random
binary waveform with levels + 1 and -1 and -0 is an arbitrary phase. The
instantaneous frequency is given by the derivative of the phase of X(t),
namely by fc + fd g(t) which is equal to the two shift frequencies f 1 and f 2
where f1= fc - fd and f2 = fc + fd
Figure 3.1 illustrates a simple modulator consisting of two oscillators and a
switch (key). This form of FM is referred to as Frequency Shift Keying (FSK).
+E
Carrier
0
Wave
-E
+V
Bit Streem
0
-V
FSK +E
The waveform for FSK modulation technique can be represented as in
Fig. 3.2
The power spectral density of FSK waveform is as follows (Fig. 3.3).

3.1 Demodulation of FSK
There are two methods of demodulation of FSK. They are
- Coherent detection
- Incoherent detection.
3.1.1 Coherent detection

The Coherent detection is illustrated in Fig. 3.4
3.1.2 Incoherent Detection
If the phase of the incoming wave is not known, we must resort to

incoherent forms of detection. An incoherent demodulator is illustrated in
Fig. 3.5.
Fig. 3.6. compares the performance of incoherent detector with that of

coherent detector.
Incoherent
Coheren
FIG 3.6
PERFORMANCE COMPARISON OF INCOHERENT AND COHERENT FSK
DETECTOR
It may be seen that for a given BER requirement, the Eb/No (and hence C/N)
requirement is more for incoherent detection compared to that of coherent
detection i.e. Coherent detection is superior to incoherent detection.
3.2 M-ARY FSK
M-ARY FSK (MFSK) -is-a way to trade bandwidth for signaling speed.
Instead of sending data using binary signals with one of two frequencies, the
signaling alphabet is expanded to include M possible frequencies. This
process will normally increase the speed between the lowest and the highest
freq. and therefore the bandwidth can be expected to increase. However,
since increased information is sent with each signal element, the baud rate
can be decreased to partially counteract the increase in bandwidth. For
example, if it were necessary to send 1000 bps of, data, this could be one by
sending a binary FSK pulse every millisecond. Alternatively, a 4 ary FSK
burst could be sent every 2 ms, representing a decrease in baud rate by a
factor of two. (Baud rate is a unit of signaling speed and it is the number of
symbols (pulses)/ second in the Channel. If each symbol represents one bit,
then baud rate is same as bit rate, if each symbol represents more than one bit
then baud rate is less than bit rate.
Baud rate= Bit Rate/No, of Bits per Symbol
The performance of MFSK for the various values of M is shown in Fig.3.7.

In the Fig.3.7 it may please be noted that ordinate is the symbol error
probability and not the bit error probability. This is an important distinction,
since a single symbol error can cause more than one bit error. We should
also note that constant energy (E) does not imply constant signal power. As
Main causes, the symbol period increases, so proportionately less signal
power is required to achieve the same signal to noise ratio. Also shown on
the figure is a theoretical bound for M——>∞ which is obtained from the
Shannon channel capacity theorem.
Fig 3.7 SYMBOL ERROR PERFORMANCE FQR MFSK

C.E. Shannon has shown that a given communication channel has a
maximum rate of information 'C', Known as .the channel capacity. If the
information rate R, is less than C, one can approach arbitrarily small error
probabilities by intelligent coding techniques. If the information rate R is greater
than the channel capacity 'C', errors can not be avoided regardless of the coding
technique employed.
We consider the band limited channel operating in the presence of additive white
Gaussian noise. In this case, the channel capacity is given by:
C= B log2 (1 + S/N)
Where C is the capacity in bits per second, B is the bandwidth of channel in
Hz and S/N is the signal to noise ratio.
The signal power S is the energy per bit multiplied by the number of bits
per second. The noise power is No multiplied by the system bandwidth. If we
take the limit as the bandwidth approaches infinity.
C = Lim B log2 (1+EC/NoB)
B ∞
= Lim (EC/No) Log2 (1+EC/No B/Ec)

B ∞
= (EC/No) Log2 e = 1.44 EC/No

E/No = -1.6dB
This is shown in Fig. 3.7 labeled as M ∞ since the infinite bandwidth

assumption coincides with the infinite value of M.
4.0 PSK Modulation

In general for Phase modulation, the phase of the carrier is varied in
proportion to the amplitude of the input signal and the amplitude and
frequency remains constant. The special cases of Digital Modulation of
signals are referred to as Phase Shift Keying (PSK) Modulation with a number
in the front indicating the number of levels of the digital signal. 2 PSK, 4 PSK
and 8 PSK are modulation methods that have been adopted for some digital
radio systems.
4.1 Correspondence between carrier phase and bit stream state

Since a bit stream is a series of binary digits, it requires a 2 Phase PSK
system, where phases of a ‘O’ and ‘π’ radians correspond to the Os and 1 s of the bit stream.
The number of phases used is limited only by the requirement that each phase be
distinguishable from the others, which result in an increased capacity for information
transmission, n bit streams required 2n combinations of n bits as shown in table below.
Therefore, a system which can distinguish 2n phases can transmit upto n bit
stream.
Table: Correspondence between phases and codes.
a. 2 Phase System
Phase Binary Binary Code Stream 1
0 0 0
π 1 1
b. 4 Phase System
Phase Quaternary Binary Code
Stream 1 Stream 2
0 0 0 0
π/2 1 0 1
π 2 1 0
3π/2 3 1 1
a- 2 Phase System b- 4 Phase System

SIGNAL - SPACE DIAGRAM FOR BINARY CODES
Since the required number of code combinations is the nth power of 2 i.e 2, 4
and 8 phase FSK systems are feasible.
4.2 Principles of Modulation
There are two type of phase modulation.
• Absolute phase modulation
• Differential phase modulation
In the absolute phase modulation system, pulse signals directly modulate a

carrier. Demodulation uses another carrier to synchronize with the carrier and detect
difference in phase. Should the phase of the two sub carriers differ by rt, (for BRSK), the
entire data train will be inverted and every bit will be in error.
For this reason, we often choose differential form of encoding. In such

techniques, the data are represented as changes in levels rather than by the particular signal
level. In other words phase transitions rather than phase states are transmitted.
Two phase differential phase modulation called 2-DPSK, is described with

reference to the following (Fig.4.1).
On the top line, the original bit stream, X is the sequence 0110. The phase
stream on the 2nd line is obtained by
Yi=Xi + Yi-1 ( + exclusive OR)

At the receiving end the following calculation recovers the original bit stream.
Xi=Yi + Y. i 1
4.3 Principles of Demodulation
There are two ways to detect PSK signals :
(1) Coherent detection
(2) Differential) detection (delay detection)
signal, using each of these two methods.
(1) Coherent Detection
The following figure (Fig,4.2) illustrates the coherent detection principle. A
Cos (wt + ψ) represents a PSK signal and contains the information.
The PSK signa! and a synchronous carrier (i.e. having same phase and
frequency of carrier on the transmitter side) are fed to the phase detector.
Detected output after the LPF (Low Pass Filter) is proportional to Cosψ, Since
Cosψassumes values of either +1 or -1 corresponding to ψ = o and π respectively,
the decision circuit judges only polarity (+ or -1) in the 2 phase
PSK system. Bits 0 and 1 correspond to phases 0 and π respectively. The carrier
used in the receiver must be synchronized with that of the carrier on the transmitter
side. Thus, a carrier synchronising circuit called the carrier recovery circuit is also
necessary.
(2) Differential Detection (Delay Detection)
The following figure (Fig.4.3) illustrates the differential! detection principle. The
incoming PSK signal is expressed as E= A Cos (wt+ψ).
The one bit delayed PSK signal E' is expressed as:
E = A Cos (wt +ψi-1), where ψIi and ψi-1 represent the phases corresponding to
the ith and (i-1)th bits respectively. The E and E1 signals are fed to a phase
detector. The output of LPF is Cos (wt +ψI-1), The decision circuit discriminates
between different values of Cos (wi +ψi-1), in the same way as
the decision circuit in the coherent detection case.
Comparison
Differential Detection is not applicable to low speed data streams, However, it
is applicable to high speed data streams, but the detected output contains
twice as much thermal noise as the O/P of coherent detection system. This is
because differential detection uses two separately received PSK signals (with
a time difference of one bit) which are equally noisy, whiie in the coherent
detection case the carrier is assumed to be free of noise.
For these reasons, the coherent detection is the preferred demodulation
method. Unlike differential detection coherent detection needs carrier
recovery.
4.4 Decision circuit {Threshold Comparator)
The detector output, which represents the phase changes of received PSK
signal, includes thermal noise, distortion arid interference, which enter the
signal at repeaters and along propagation paths. Consequently, the detected
output waveforms are considerably distorted as shown in the following figure.
ISI : Intersymbol interference

NRZ : Non return to zero
WAVEFORMS OF DETECTED BASEBAND
Using the clock signal to discriminate between "1" and "0" states, it is
possible to recover the original waveform from the distorted pulse waves.
There are two "decision methods: Instantaneous decision and integral
decision.
The instantaneous decision method determines whether the detected value
belong to the "range 1" (Over the threshold) or the "range 0" (Below the
threshold) by comparing the detected output amplitude to the threshold level
(0 Volts), at sampling points derived from the Clock Frequency. The output is
a pulse stream with the appropriate voltages.
The integral decision method integrates the amplitude of the detected output
for a fixed time interval and compares the result with the threshold. The
integral decision method is more sensitive to inter symbol interference than
the instantaneous decision method, and so the instantaneous decision
method is preferred.
4.4.3 What is Jitter ?
Unwanted phase modulation is termed as jitter, in the decision circuit clock
pulses are generated using PSK signal phase changes as a reference.
These clock pulses may some times be inaccurate due to poor tuning of the
pulse generating circuit causing jitter.
4.5 BPSK Modulation
BPSK Modulator is shown in Fig. 4.6.
2 – PSK MODULATOR
Ring Modulator (MOD)

4.6 Four Phase PSK Systems
The following figure (Fig. 4.7) illustrates a functional block diagram of QPSK
Modulator
I
1 T
H
Input
Data S/P
Con ≈≈ M
M BPF BPF 4 Outp
3 P/S ut
II /2 II /2
T
2
Q H
Transmitter Receiver
1&2 : LPF
3 : Bit Timing Recovery
4 : Carrier
TH : Threshold
Fig. 4.7
BLOCK DIAGRAM OF QPSK MODULATOR
In this system the I/P pulse stream is converted into two bit streams. Their
pulse speed is exactly half that original stream. The serial to parallel converter block
includes a differential encoding function. QPSK modulator can be thought of 2
BPSK modulators in parallel.
As the signal space diagram indicates, the QPSK modulator uses a gray
code arrangement i.e., instead of having (0,1),(1 ( 1 , 1 ) , (0,0) symbols we Be-
having (0,1) , (1,1), (1,0), (0,0) symbols. The reason is explained with reference to
the following figure (Fig.4.8).
FIG. 4.9
Vector Diagram of PSK signals, noise, and sub-carriers
Any noise superimposed in a PSK signal changes the signals vectors. The
noise vector are constantly varying in phase and amplitude and if the vector sum of
the noise and PSK signal cross a carrier vector, a bit error occurs. As a noise vector
increases in magnitude, so does the possibility of mistaking the true PSK signal
vector for an adjacent one. However, the possibility of the noise vector increasing
enough to mistake the true PSK signal vector for the signal vector 1800 opposite
(differing by π) is very low. Gray coding therefore improves bit error rate compared
with natural binary coding, because one symbol error results in a single bit error.
i.e., bit error rate = Symbol error rate / 2
Circuits used for Natural Code to Gray Code conversion (At the transmitter)
and vice versa (At the Receiver) are shown below.
Natural Code to Gray Code Conversion
4.6.1 Coherent Detection
For QPSK demodulation coherent detection is superior to

differential
detection. The block diagram of coherent detection circuit is as follows
(Fig. 4.10).
FIG. 4.10
CONFIGURATION OF COHERENT DETECTION CIRCUIT
4.6.2 Carrier Recovery
The carrier wave required for the coherent detection must be recovered
from 4 PSK signal which does not contain the proper unmodulated frequency
component. The 4 PSK signal is expressed by
E = A Cos (wt+ φ + πn/2)
The π n/2 phase component must be removed because it randomly assumes values
of 0,1, 2, 3. There are many carrier recovery strategies. We will consider
(1) Four multiplication system (2) Costa's Loop method.
4.6.2.1 Four Multiplication System
The derivation of the four multiplication of a 4 PSK signal system is as fallows:
E4 = A4 Cos4 (ωt + ϕ + πn/2)
= A4 /8{3+4Cos2 (ωt + ϕ + πn/2)+ (ωt + ϕ + πn/2)}
A band pass filter extracts the 4ω components called E(4ω).
A4 Cos4 (ωt + ϕ + πn/2)
E(4ω) =
8
= A4 Cos (4ωt + 4ϕ)
Four times frequency division fo E(4ω) recovers a pure carrier. Similarly for BPSK scheme 2
multiplication system can be used.
Fig. 4.11
Costa’s loop
The VCO operates at the carrier frequency fc . The output of upper low pass filter is given
by, 0.5 A (t) sin (θ -φ). This output is therefore proportional to the sine of the phase
difference. If the two frequencies are not matched, the phase difference includes a linearly
varying term.
The output of the lower LPF is given by, 0.5 A (t) sin (θ -φ). This output is therefore
proportional to the cosine of the phase difference.
When these two terms are multiplied together, the result is the error term.
E(t) = 0.25 A2 (t) sin(θ -φ) cos (θ -φ).

= 0.125 A2 (t) sin[2(θ -φ)]
The error term is therefore proportional to the sine of twice the phase difference and
the loop drives this term toward zero.
5.0 16 QAM
The 16 QAM (Quadrature Amplitude Modulation) system carriers twice as much
information as the QPSK system.
5.1 Modulation
The 16 QAM signal is obtained by vector summing two 4 level ASK signals in
quadrature. The following figure shows two 4 level ASK signals in quadrature (Fig. 5.1).
FIG 5.1
TWO 4- LEVEL ASK SIGNALS PERPENDICULAR TO EACH OTHER
The signal space diagram is as shown in the Fig. 5.2

The block diagram of 16 QAM is shown if Fig . 5.3.
The modulator is provided with four data signal inputs S1 to S4 which are
applied to D/A converters. The D/A converter delivers a single data stream
with four amplitude levels from the two data input streams each with two
amplitude levels. The four amplitude level output are applied to modulation
circuits.
The modulator circuits consist of two balanced diode mixers coupled with two
hybrid transformers. The hybrid transformer at the input delivers two outputs
with a 90° phase shift, the I channel and Q channel signals. The hybrid
transformer at the output simply combines the two outputs.
The demodulator block diagram is shown in Fig. 5.4.
The demodulator demodulates the IF signal and produces four data signal
outputs S1 to S4.
The IF amplifier which contains an AGC loop reduce ; IF signal level
changes before applying to the detector. The detector consists of two
balanced diode mixers and hybrid transformer. The hybrid transformer at the
input splits the IF signal into two signals with no phase shifting between them.
The other hybrid transformer produces two signals with a 900 phase shift between
them. The local frequency signal is fed to the two mixers via the hybrid transformer.
The output of the detector, the I channel and the Q channel signals are amplified
separately and applied to cosine roll off filters for spectrum shaping and to A/D converters.
The A/D converters perform the threshold decision.
DEFINITION AND DESCRIPTION OF DIGITAL HIERARCHIES
1.0 INTRODUCTION AND DEFINITION
The term “digital hierarchy” has been created when developing digital
transmission systems. It was laid down when by multiplexing a certain number of
PCM primary multiplexers were combined to form digital multiplexers of higher order
(e.g. second-order multiplex equipments).
Consequently, a digital hierarchy comprises a number of levels. Each level is
assigned a specific bit rate which is formed by multiplexing digital signals, each
having the bit rate of the next lower level. In CCITT Rec. G.702, the term “digital
multiplex hierarchy” is defined as follows :
“A series of digital multiplexes graded according to capability so that
multiplexing at one level combines a defined number of digital signals, each having
the digit rate prescribed for the next lower order, into a digital signal having a
prescribed digit rate which is then available for further combination with other digital
signals of the same rate in a digital multiplex of the next higher order”.
2.0 WHY HIERARCHIES ?
2.1 Before considering in detail the digital hierarchies under discussion we
are going to recapitulate in brief, why there are several digital
hierarchies instead of one only. It has always been pointed out that as
far as the analogue FDM technique is concerned, the C.C.I.T.T.
recommends the world wide use of the 12-channel group (secondary
group). Relevant C.C.I.T.T. Recommendation exists also for channel
assemblies with more than 60 channels so that with certain exceptions
– there is only one world-wide hierarchy for the FDM system (although
the term “hierarchy” is not used in the FDM technique).
2.2 In the digital transmission technique it was unfortunately not possible
to draw up a world-wide digital hierarchy. In practice, equipment as
specified in C.C.I.T.T. Recommendation G.732 and 733, they do not
only differ completely in their bit rates, but also in the frame structures,
in signalling, frame alignment, etc. Needless to say that, as a
consequence, the higher order digital multiplexers derived from the two
different PCM primary multiplexers and thus the digital hierarchies
differ as well.
2.3 Since these two PCM primary multiplexers are available, two digital
heirarchies only would have to be expected. In reality, however, two
digital hierarchies with several variants are under discussion because
the choice of the fundamental parameters of a digital hierarchy
depends not only on the PCM primary multiplex, which forms the basic
arrangement in that hierarchy, but on many other factors such as :
(a) the bit rate of the principal signal sources.
(b) traffic demand, network topology, operational features, flexibility
of the network.
(c) time division and multiplexing plant requirements.
(d) compatibility with analog equipment.
(e) characteristics of the transmission media to be used at the bit
rates for the various levels of the hierarchies.
Since today these factors which are essential for forming digital
hierarchies vary from country to country, it is no wonder that we now
have to consider more than two proposals for digital hierarchies.
3.0 DIGITAL HIERARCHIES BASED ON THE 1544 KBIT/S PCM PRIMARY
MULTIPLEX EQUIPMENT
It was around 1968 that Bell labs. proposed a digital hierarchy based on the
24-channel PCM primary multiplex at the various levels of the hierarchy :
Level in hierarchy Bit rate Trans. line
First level 1544 kbit/s T1
Second level 6312 kbit/s T2
Third level 46304 kbit/s L5 (Jumbo Grp)
Fourth level 280000 kbit/s WT4 (Wave guide)
Fifth level 568000 kbit/s T5
This proposal was modified during the following years. At the end of the study
period 1968/72, the following digital network hierarchy was finally proposed as given
in Fig.1.
Fig. 1
Encoded FDM (Master Group) USA & Canada
3.1 For the various bit rates at the higher levels of the two proposals, different
reasons have been indicated. The bit rate of 44736 kbit/s was selected to
provide a flexibility point for circuit interconnection and because it was a
suitable coding level for the 600 channel FDM mastergroup.
3.2 It is also an appropriate bit rate for inter-connection to radio-relay links
planned for use at various frequencies.
3.3 At the same time, N.T.T. published its PCM hierarchy are concerned (1554
and 6112 kbit/s, respectively), these two proposals are identical. They differ,
however, in the higher levels as shown in Fig.2.
Fig. 2
Encoded TDM (Japanese)
3.4 In the N.T.T. proposal the bit rate of 32064 kbit/s at the third level of the
proposed hierarchy might be considered a suitable bit rate to be used on
international satellite links perhaps for administrations operating different
PCM primary multiplex equipments. It is also a convenient bit rate for
encoding the standardized 300-channel FDM mastergroup. Delta modulation
and differential PCM for 4 MHz visual telephone are also suitable for this bit
rate. Transmission of 32064 kbit/s via a special symmetrical cable of new
design is also possible.
3.5 The above fact shows that the differing bit rates of the third level indicated in
the two hierarchy proposals can, therefore, be justified by technical
arguments. As far as the differing bit rates of the fourth level are concerned,
only a few technical reasons are included in the two proposal. In both cases
coaxial cables are used as a transmission medium so that the medium does
not call for different bit rates.
3.6 Moreover, it seems that at present the specifications of the fourth level (and
higher ones) in the two proposed hierarchies is not yet considered so urgent.
For the time being the third level seems to be more important.
3.7 The C.C.I.T.T. faced with this situation has reached finally the solution which
is covered by CCITT recommendation G.752 as one can see from this
recommendation, two different hierarchical levels are existing in the third level
of this hierarchy, namely 32064 kbits/s and 44736 kbit/s respectively. Higher
level have not been specified so far.
4.0 DIGITAL HIERARCHY BASED ON THE 2048 KBIT/S PCM PRIMARY
MULTIPLEX EQUIPMENT
For this digital hierarchy, two specifications have at present been laid down
only for the first level at 2048 kbit/s and for the second level at 8448 kbit/s.
As for the higher levels, the situation is just contrary to that existing in the
case of digital hierarchies derived from 1544 kbit/s primary multiplex, i.e.
general agreement has more or less been reached on the fourth level having
a bit rate of 139264 kbit/s. 5th order system where bit rate of 565 Mb/s have
also been planned now.
4.1 The critical point in this hierarchy is whether or not the third level at 34368
kbit/s should exist.
4.2 The C.C.I.T.T. has agreed after long discussions on the following
(Recommendation G.751) “that there should be a 4th order bit rate of 139264
kbit/s in the digital hierarchy which is based on the 2nd order bit rate of 8448
kbit/s”.
There should be two methods of achieving the 4th order bit rate :
Method 1 by using a 3rd order bit rate of 34368 kbit/s in the digital hierarchy.
Method 2 by directly multiplexing sixteen digital signals at 8448 kbit/s. The
digital signals at the bit rate of 139264 kbit/s obtained by these two methods
should be identical.
The existence of the above two methods implies that the use of the bit rate of
34368 kbit/s should not be imposed on an Administration that does not wish
to realize the corresponding equipment.
4.3 In accordance with the above two methods the following realizations of digital
multiplex equipments using positive justification are recommended :
Method 1 : Realization by separate digital multiplex equipments : one type
which operates at 34368 kbit/s and multiplexes four digital signals at 8448
kbit/s; the other type which operates at 139264 kbit/s and multiplexes four
digital signals at 34368 kbit/s.
Method 2 : Realization by a single digital multiplex equipment which operates
at 139264 kbit/s and multiplexes sixteen digital signals at 8448 kbit/s.
Method 1 has been put into practice.
4.4 Where the fifth level is concerned, some preliminary proposals (e.g. 565148
kbit/s) have been submitted which were not discussed in detail.
Therefore, the present structure of this digital hierarchy is as given in Fig.3.
139.264
Fig. 3
Encoded TDM (European)
5.0 Most of the administrations favour the specification of a third level at 34368
kbit/s, mainly as a suitable flexibility point for the operation of the network and
as an adequate bit rate for digital line systems which are to be set up either
on new cables (screened symmetrical or micro-coaxial cables) or an radio-
relay links. Other administrations do not consider the specification of a third
level to be advantageous for their networks. On the contrary they regard it to
be more economical to go directly from the second level at 8448 kbit/s so the
fourth level at 139264 kbit/s, is also achieved by multiplexing four digital
signals at 34368 kbit/s, each of which is obtained by multiplexing first four
digital signals at 8448 kbit/s. However, this is a matter of internal multiplexing
only, i.e. digital multiplex equipment of this type has no external input or
output at 34368 kbit/s.
All administrations interested in the third level at 34368 kbit/s would thus be
offered the possibility of using this level. Their digital multiplex equipment
which multiplexes in the same way each of the four digital signals at 8448
kbit/s has to provide external outputs for the resulting signal at 34368 kbit/s.
The digital multiplex equipment which multiplexes each of the four digital
signals at 34368 kbit/s has to provide four inputs for these bit rates and one
output for the resulting bit rate of 139264 kbit/s.
5.1 Outlook
The above context indicates that at the moment the discussion of digital
hierarchies is still underway and is mainly concentrated on the third and fourth
levels. Although certain trends are evident the specification of these and
higher levels will take some time. In the interest of a comprehensive
specification of the digital hierarchies to be drawn up as soon as possible, it is
to be hoped that all parties concerned perform their studies with high priority.
All digital multiplexes and hierarchies proposed till date are operating in an
asynchronous mode (positive justification, “positive stuffing”, bit-interleaved).
It is likely that in the future, synchronous digital multiplex equipment has to be
considered when setting up digital hierarchies. For various digital line systems
being developed in many countries non-hierarchical bit rates have
provisionally been adopted with due regard to the characteristics of the
transmission media used. These non-hierarchical bit rates for digital line
systems have also to be born in mind when defining the digital hierarchies
and may affect the hierarchical bit rates.
6.0 CCITT Recommendations
6.1 Second order digital multiplex equipment operating at 8448 kbit/s and
using positive justification CCITT Rec. G 742.
1. This 2nd order digital multiplex equipment using positive justification is
intended for use on digital paths using 2048 kbit/s primary multiplex
equipments.
2. Bit rates : The nominal bit rate should be 8448 kbit/s. The tolerance on
this rate should be +30 PPM.
3. Frame Structure :
Frame Structure Bit No.
Frame alignment word (1111010000) 1 to 10
Alarm to remote Tml 11 Set I
National use 12 Set I
Bits from tributaries 13 to 212 Set I
Justification Control bits 1 to 4 Set II
Bits from tributaries 5 to 212 Set II
Justification Control bits 1 to 4 Set III
Bits from tributaries 5 to 212 Set III
Justification Control bits 1 to 4 Set IV
Bits for tributaries available for 5 to 8 Set IV
justification
Bits from tributaries 9 to 212 Set IV
Frame Length 848 bits
bits/tributary 206 bits
4. Loss Recovery of Frame alignment and consequent action.

Loss of frame alignment should be assumed to have taken place when four
consecutive frame alignment signals have been incorrectly received in their
predicted positions.
When frame alignment is assumed to be lost, the frame alignment device
should decide that, such alignment has effectively been recovered, when it
detects the presence of three consecutive frame alignment signals.
The frame alignment device having detected the appearance of a single
correct frame alignment signal, should begin a new search for the frame
alignment signal in one of the two following frames.
5. Multiplexing Method
Cyclic bit inter-leaving in the tributary numbering order and positive
justification is recommended. Positive justification should be indicated by the
signal 111, no justification by the signal 000. Majority decision is
recommended.
6.2 Third order digital multiplex equipment operating at 34368 kbit/s.
1. Bit rates :
The nominal bit rate should be 34368 kbit/s. The tolerance on the rate
should be + 20 PPM
2. Frame Structure (Fig. 5)
Frame alignment word (1111010000) 1 to 10 Set I
Alarm to indication to the remote TML 11 Set I
National use 12 Set I
Bits from tributaries 13 to 384 Set I
Justification Control bits 1 to 4 Set II
Bits from tributaries 5 to 384 Set II
Justification Control bits 1 to 4 Set III
Bits from tributaries 5 to 384 Set III
Justification Control bits 1 to 4 Set IV
Bits for tributaries available for 5 to 8 Set IV
justification
Bits from tributaries 9 to 384
Frame length 1536 bits
3. Loss and Recovery of Frame alignment
Same as the 2nd order digital MUX system.
Same as the 2nd order digital MUX system.
Fig. 5
34368 Kb/s Multiplexing Frame Structure

6.3 Fourth order digital multiplex equipment operating at 139264
kbit/s.
1. Bit rates :
The nominal bit rate should be 139264 kb/s. The tolerance on the rate
should be +15 PPM
2. Frame Structure
Frame alignment word (111110100000) 1 to 12
Alarm to indication to the remote digital MUX
13 Set I
tml
Bit reserved for National use 14 to 16
Justification Service bits 1 to 4
Bits from tributaries 5 to 488 Set II to V
Justification Control bits 1 to 4
Bits for tributaries available for justification 5 to 8 Set VI

Frame length 2928 bits
3. Loss and Recovery of Frame alignment
Same as the 2nd and 3rd order digital MUX system.
Same as the 2nd and 3rd order digital MUX system.
7.0 INTERFACES
7.1 Specification for Interfaces at 2048 kb/s.
1. General characteristics :
Bit rate : 2048 kb/s + 50 PPM
Code : HDB3.
2. Specification at Output Port
One Coaxial One Symmetrical
Pair(s) in each direction
Pair Pair
Test Load Impedance 75 ohm (rest.) 120 ohm (rest.)
Nominal peak voltage of a mark
2.37 V 3V
(pulse)
Peak voltage of a space (no pulse) 0+0.237 V 0+0.3 V
Nominal pulse width 244 ns 244ns

Ratio of amplitude of +ve and –ve
0.95 to 1.05 0.95 to 1.05
pulses at the centre of pulse interval
Ratio of widths of +ve and –ve
0.95 to 1.05 0.95 to 1.05
pulses at the nominal half amplitude
3. Specification at I/P Ports
The digital signal presented at the i/p port shall be modified by the
characteristics of the interconnecting pair. The attenuation of this pair shall be
assumed to follow f law and the loss at a frequency of 1024 KHz shall be in the
range of 0 to 6 dB. This attenuation should take into account any losses incurred by
the presence of a digital distribution frame between the equipments.
The input port shall be able to tolerate a digital signal with these electrical
characteristics but modulated by sinusoidal jitter.
7.2 Specification for Interfaces at 8448 kb/s
1. General Characteristics :
Bit rate : 8448 kb/s + 30 ppm
Code : HDB3
2. Specification at o/p Port :
Pair(s) in each direction One Coaxial Pair
Test Load Impedance 75 ohm (rest.)
Nominal peak voltage of a mark (pulse) 2.37 V
Peak voltage of a space (no pulse) 0 + 0.237 V
Nominal pulse width 59 ns
Ratio of amplitude of +ve and –ve pulses at the
0.95 to 1.05
centre of pulse interval
Ratio of widths of +ve and –ve pulses at the
0.95 to 1.05
nominal half amplitude
characteristics of the interconnecting cable. The attenuation of this cable shall be
assumed to follow a f law and a loss at a frequency of 4224 KHz shall be in the
range of 0 to 6 dB. This attenuation should take into account only losses incurred by
the presence of a digital distribution frame between the equipments.
The i/p port shall be able to tolerate digital signal with these electrical
7.3 Interface at 34368 kb/s
1. General Characteristics
Code : HDB–3.
2. Specification at o/p Port
Nominal peak voltage of a mark
1.0 V
(pulse)
Peak voltage of a space (no pulse) 0 + 0.1V
Nominal pulse width 14.55
Ratio of amplitude of +ve and –ve
0.95 to 1.05
pulses at the centre of pulse interval
Ratio of widths of +ve and –ve pulses
0.95 to 1.05
at the nominal half amplitude

characteristics of the interconnecting cable. The attenuation of this pair shall be
assumed to follow f law and the loss at a frequency of 17184 KHz shall be in the
range of 0 to 12 dB.
The i/p port shall be also to tolerate a digital signal with these electrical
7.4 Interface at 139264 kb/s
1. General characteristics
Code : CMI
2. Specification at o/p Port
pk. to pk. voltage 1 + 0.1 V

Rise time between 10% and 90%
< 2 ns
amplitude of measured amplitude
Return loss > 15 dB for 7 MHz to 210 MHz
characteristics of the interconnecting coaxial pair shall be assumed to follow f law
and have a maximum insertion loss of 12 dB at frequency of 70 MHz.
The Return loss characteristic should be same as o/p port. The input port
should be able to tolerate a digital signal with these electrical characteristics but
modulated by sinusoidal jitter.
DIGITAL MULTIPLEXING CONCEPTS, SIGNAL JUSTIFICATION & CONTROL
AND JITTER
1. INTRODUCTION
The functions of digital multiplex equipment are to combine a defined integral
number of digital input signals (called tributaries) at a defined digit rate by time
division multiplexing and also to carry out the reverse process (demultiplexing).
In analogue system, multiplex equipment uses F.D.M. to assemble individual
channels into groups, super group etc. Similarly, in digital systems, hierarchical
levels have been defined using T.D.M. and are identified by their digit rate measured
in bit/sec.
Bit rate Mbit/sec. No. of channels
2.048 30
8.448 120
34.368 480
139.264 1920
2.0 MULTIPLEXING OF DIGITAL SIGNALS
The digital signals which are to be multiplexed may be synchronous to one
clock (called master clock) or they may not be synchronous (called asynchronous
signals).
3.0 MULTIPLEXING OF SYNCHRONOUS DIGITAL SIGNALS
The various tributary bit streams are synchronous and operate at the same
rate defined as T bit/sec. To multiplex ‘n’ such tributaries the rate of multiplex output
should be nT bit/s. The method adopted for multiplexing such n signals into one
stream may be as follows :
(i) Block interleaving :
Bunch of information taken at a time from each tributary and fed to main
multiplex output stream. The memory required will be very large.
(ii) Bit interleaving :
A bit of information taken at time from each tributary and fed to main multiplex
output stream in cyclic order, a very small memory is required.
At the demultiplex end, it is necessary to recognise which bit of information
belongs to which tributary. This could be achieved by transmitting a fixed code after
a fixed number of information bits called “frame”. The fixed code is called frame
alignment signal. It is recognised first and received frame of information is aligned to
this fixed code.
This method of multiplexing is easy but not reliable. If any deviation in
nominal bit rate of a tributary occurs, it will cause loss of time slot and hence loss of
information.
4.0 MULTIPLEXING OF ASYNCHRONOUS SIGNAL
Here, various tributaries operate at different bit rates.
Two signals are asynchronous at their corresponding significant instant occur
at nominally the same rate, any variation in rate being constrained within specified
limits.
When nominal bit rate of tributaries are within specified limit. It is necessary to
synchronize the tributary signal with a common nominal bit rate of multiplexer
derived from timing generator of multiplexer. The synchronization is done in such a
way that there is no loss of information. The process adopted for such
synchronization is called “Pulse stuffing” or justification. Justification is a process of
changing the rate of digital signals in a controlled manner. There are three types of
justification processes :
(a) Positive justification : Common synchronization bit rate offered at each
tributary is higher than the bit rate of individual tributary.
(b) Positive-negative justification : Common synchronization bit rate offers is
equal to the nominal value.
(c) Negative justification : Common synchronization bit rate offered is less than
the nominal value.
Fig. 1(a) shows a configuration where the outputs of two PCM transmitters
A&B are to be multiplexed in the combiner. If A and B are synchronous, they can be
easily multiplexed by the combiner as shown in Fig. 1(b). Generally, however, A&B
are clocked by separate clock sources of asynchronous. In this case multiplexing is
not successively accomplished simply by the use of combiner owing to the
occurrence of pulse phase fluctuations and/or pulse amplitude superposition as can
be seen in Fig.1(c).
5.0 RETIMING ASYNCHRONOUS SIGNALS BY JUSTIFICATION
Figure 2 shows a system for explaining the principle of the multiplexer for
successfully multiplexing plural asynchronous signals. The waveforms appearing at
various points in Fig.2 are shown in Fig.3. An asynch. input pulse train A is written
into MEM I comprising several elements. The writing pulse train C whose bit rate is f
is extracted from A at a clock extraction (CLK EXT I). On the other hand, the written
information is read out of MEM I with a sufficient phase lag with respect to time of
writing in. Through an inhibit gate (INH GATE I), the reading pulse train D is
obtained by dividing the output bit rate nf (1+ ∆) of a common clock generator (CLK
GEN) at a bit rate divider (DIV 1).
n - no. of asynch. signals to be multiplexed.
∆ - clock increase rate.
As the bit rate of the reading pulse train D is set at (f+ ∆ f) which is higher
than any value of f, the time of read out (D) gradually approaches that of write in ©.
The phase difference between C&D is monitored by a phase comparator of COMP I
and just before the difference reaches zero, a pulse is applied to the inhibit input of
INH GATE I from a control circuit (CONT I) to inhibit the gate. At this moment, with
one bit of the reading pulse train D being removed, the reading operation pauses
and an information less pulse (or justification pulse) is inserted into the read out
pulse train E. the time of read out (D) at the same time is again set to a sufficient lag
with respect to time write in (G). As all the signals read out of the respective
memories are now retimed by timing pulses derived from the common CLK GEN,
they are now easily multiplexed as F in Fig.3 at the combiner (COMB).
The information pulses inserted into E (those hatched in Fig. 3) and this sort
of retiming method are respectively called “justification pulses” and “justification”.
The information whether or not justification has been performed, is inserted into F
and COMB and transmitted to the receiving side.
6.0 RECOVERING ORIGINAL SIGNALS BY DEJUSTIFICATION
The justification pulses have to be removed at the receiving side to perfectly
recover the original signals. This operation is called “dejustification”.
The transmitted pulse train F from the line is received and demultiplexed at
distributor (DIST). One of the demultiplexed signal E that corresponds to A, is written
into memory MEM 2. The writing pulse train G whose bit rate is ∆is obtained through
an ingibit grate (INH GATE 2) by dividing the output bit rate nf(1+ ∆ f) of clock
extractor (CLK EXT2). On the other hand, the written information is read out of MEM
2 with a slight phase lag with respect to the time of write in. The reading pulse train
H, whose bit rate is f, is applied from voltage controlled oscillator (VCO). As the bit
rate of the reading pulse train H is lower than that of the writing pulse train G, the
time of read out (H) gradually drifts away from that of write in (G). Just before a
justification pulse in E (ONE of these hatched in Fig.3) is written into MEM 2, the
information, telling that the justification has been performed is applied from DIST to
a control circuit (CONT 2). Then a pulse is applied to the inhibiting input of INH
GATE 2 from CONT 2 to inhibit the gate.
At this moment, with one bit of the writing pulse train G being removed, the
writing operation pauses and the justification pulse is removed or dejustified. At the
same time, the time of read out (H) again set to be very close to the time of write in
(G). As the reading operation does not pause, the original signal is recovered as ‘A’.
The phase difference between G and H is monitored by a phase comparator (COMP
2), and the low frequency components of the output voltage of COMP 2 are applied
to VCO through a low pass filter (LPF). Thus, the jitter introduced due to
dejustification into the read out pulse train ‘A’ is sufficiently suppressed. The loop
formed by VCO, COMP and LPF is called a “Phase controlled loop”.
Figure 4 gives the frame structure for 34 Mbits/sec system.
7.0 JUSTIFICATION CONTROL SIGNAL
Justification control signal indicates at demultiplexer the presence of
justifiable bit in the frame. To avoid errors present in the justification control bit, more
than one bit is transmitted as control bit and majority decision is taken at
demultiplexer.
Normally 3 or 5 bits (3 bits in case of 8 and 34 Mbits systems and 5 bits in
140M bits system) are transmitted per tributary per frame as justification control bits
and 2 or 3 bits present at demultiplexer out of 3 or 5 bits transmitted are taken as
majority decision and it is assumed that justifiable bit is present in the frame. These
3 or 5 bits of justification control bits per tributary per frame are distributed in the
frame. Two or three digital errors are required to cause false information of
justification (loss of one digit or addition of one digit) which results in a loss of frame
alignment in lower hierarchical levels.
8.0 HARDWARE REALIZATION OF DIGITAL MULTIPLEX SYSTEM
System are realized by digital circuits using TTL and ECL ICs. The typical
gate delays and toggling speeds of the different series of ICs are given below :
Propagation delays Toggling speed
(typical) (typical)
LS series TTL 15 ns 25 MHz
S series TTL 5 ns 75 MHz
10,000 series 3 ns 200 MHz
ECL
As is is evident from the above rates that LS series is suitable only till 8 MHz
system, where as S series is suitable for 34 MHz system and 10,000 series is being
used for 140 MHz system.
9.0 TRANSMIT TRIBUTARY
The information from tributary is written in an elastic memory with tributary
clock derived from incoming signal. Elastic memory is read out by a clock which is
faster than the clock of its own. Reading clock is derived from common transmit
clock (Common synchronization clock). The reading clock is of rate F2/n (where n is
the no. of tributaries and F2 is output frequency of multiplexer for ex. 34,368/4 for
34M bit system) with gaps where non information bit occurs in the frame structure
(i.e., for frame alignment signal and justification control bit, service digits). Since
read clock always operates faster than write clock, it is required to stop read clock
for a bit and insert non-information bit-justification bit. The information which read out
from memory contains information bit, justification control bit and justifiable bit. The
decision when to insert the justifiable bit is taken when linearly increasing phase
difference crosses a threshold level. The threshold value is selected in such a way
that average rate of read clock is equal to the write clock rate.
In the demultiplexer, the clock timing of the input multiplex signal enables a
control on the timing of operations. The detection of frame alignment signals enables
the receive frame to be aligned with the transmit frame which enables the receiver to
demultiplex the tributary information. This tributary information is written in elastic
memory as in transmit tributary by the clock derived from receive clock. A phase
locked oscillator is used to read the elastic memory with a timing rate equal to the
average write clock and, therefore, equal to that of the corresponding tributary signal
at the input of the multiplexer.
10.0 JITTER ASPECT OF MULTIPLEX EQUIPMENT
While considering the jitter aspect of the multiplex system, different types of
jitter introduced in the systems are taken into account such as :
(a) Jitter introduced due to the routine insertion of the frame alignment
words and of the service digits and justification instructions.
(b) Justification jitter.
(c) Waiting time jitter.
The first two jitter components are at high frequencies in relation to the pass
band of the P.L.L. and hence filtered out, whereas waiting time jitter which is due to
phase difference between write and read clock and varies from frame to frame, has
a low frequency component and cannot be jittered out by P.L.L. at the demultiplexer
output.
11.0 LINE INTERFACE
The output of multiplexer is purely a unipolar digital signal having D.C.
voltage. Normally cable are balanced, having no DC component, or minimum DC to
avoid cross talk. Any code such as AMI, HDB3, CMI can be chosen, which are
bipolar in nature. These line codes are selected in such a way that :
1. Timing signal at the receiver could be extracted easily, hence it should
contain enough timing information. Timing signal extraction circuit has
limitations because of the “Q factor” of the coil used in the circuit.
Higher the Q of coil, the costlier it is.
2. The bandwidth of the signal is kept small. The energy in the upper part
of the frequency spectrum should be small in order to avoid attenuation
distortion caused by high transmission loss at higher frequency.
3. The energy in the lower part of the frequency spectrum should also be
kept small in order to reduce the interference from voice frequency
circuit in the same cable and vice-versa.
4. It should have no DC component which could be obtained by selecting
a code having minimum digital sum variation.
The output of 2, 8 and 34 MBit systems is in HDB3 code. Rules followed for
HDB3 line code are as follows :
(i) Every sequence of four consecutive zeros is replaced by either 000V
or B00V, where B is a normal bipolar mark and V is a mark violating
the AMI sequence.
(ii) Sequence 000V or B00V is used such that the number of bipolar
pulses between successive violation pulse is odd. This ensures that
violation pulses, form their own bipolar sequence.
The output of 140 MBit system is in CMI code, where the coding rule is
as follows :
Binary element CMI code
1 00 } transmitted
11 } alternately
0 01
Combiner
PCM
FIG. 1 (a)
When A & B are Synchronous
FIG. 1 (b)
FIG. 1 ( c )
Fig. 1
Fig. 2
System for Multiplexing & Demultiplexing Asynchronous Signals
ME
M2
Fig. 3
Waveforms at Respective Points
380 BITS
FIG. 4
LINE CODES
1.0 INTRODUCTION
1.1 The digital output of a PCM equipment contains "1s and 'O's. For transmission
of the digital signals between two points, the '1' s and 'O' s contained by the signal
are transmitted in the form of pulses as shown in Fig. 1.
Fig. 1. Pulse representation of digital signals
The transmission medium normally used for transmitting PCM signals is

the VF cable pair. If the stream of pulses shown in Fig. 1. is transmitted
as it is, the signal undergoes high frequency attenuation distortion and
also suffers from other kinds of distortion such as cross talk etc. This is
because of the electrical characteristics of the VF pair. Moreover the
.signal passed through the cable pair has strong DC content. This is
because of the characteristics of the signal and those of the medium do
not match.
1.2 For distortion free transmission, the PCM output should be converted
into a suitable code which will match the characteristics of the medium.
This code is called the "line code" and the signal converted to the line
code is called a line signal. This handout briefly describes the basic
requirements of a line code, the different types of line codes and the
operation of an HDB3 code decoder.
2.0 REQUIREMENTS OF A LINE CODE.

2.1 The line code used for transmission of PCM signals should meet the
following requirements.
(i) The total band width of the signal should be as small as
possible.
(ii) The energy in the upper part of the signal spectrum should be
small so that the attenuation distortion caused by the high
transmission losses at high frequencies is very low.
The energy in the lower part of the spectrum should also be low to
reduce the interference (cross talk) from VF circuits in the same
cable. This would minimize interference from the PCM signals
to the other VF circuits as well. (It may be recalled that a narrow
pulse has. a wide frequency spectrum, the energy distribution,
i.e. the levels of the various frequency components of the
spectrum should be such that the major chunk of the signal
power is around the centre of the spectrum. The frequency
components in the lower and higher limits of the spectrum should
have low levels).
(iii) There should not be any DC comonent in the line coded sinal
(line signal) so that transformers can be used for coupling
purposes.
(iv) The line code should permit easier designs of repeaters.
(v) The line code should contain adequate timing information
since this is vital for regenerating the signals at repeater stations
and at the receiving station for the purpose of synchronization.
(vi) The line code must have an in-built error monitoring capability.
2.2 Since the invention of PCM by A.M. Reeves in 1938, a number of
line' codes has been designed. A few of them will be discussed in the
following paragraphs.
3.0 NRZ BINARY CODE.

3.1 NRZ stands for "Non-return to Zero" code.
(i) Suppose we have a code 100111011001 In Pulse form this
would appear as in Fig. 2.
.
Here it may be seen that whenever a' 1' is continuously transmitted, the
output continues at 'V level for a duration equal to the number of bits
transmitted. In a30 chl. PCM system, the bit duration is 0.488 micro
second. If three '1' 1 s are transmitted, the output signal is a pulse which
is 3x0.488 micro seconds wide.
(ii) In the example the signal has only one polarity. A 'O1 is O volt and a ' 1 ' is
positive (say-f-5v). Sometimes, however, a ' 1 ' is denoted by a positive
voltage and "O1 is denoted by a negative voltage. A pulse stream
10,0.110111001 in such a case can be represented graphically as in
Fig.3.
FIG.3 BIPOLAR NRZ

Here also when there is a string of% 1' s to be transmitted, the output
continues at * 1' for as many bits as are continuously transmitted.
In both cases, the output does not return to zero after every 'V bit when a number of 1's are
transmitted.- for this reason, this type of code is called a non return to zero or "NRZ" binary.
When the signal has only one polarity, as in the first example, the code is called unipolar or
unbalanced NRZ binary and when the signal has dual polarity, as in the second example it is
called a balanced NRZ binary or bipolar NRZ.
3.2 Limitation of NRZ Binary Code.

Fig 4. Shows the spectrum of an NRZ binary signal.
(i) From the spectrum for the NRZ signal, it can be seen that there is a
strong DC component.
(ii) There is a large low frequency content. This may result in cross talk.
(iii) There is no frequency component at 1/T, 2/T etc. It means that

there is no component corresponding to the clock frequency. This
makes efficient recovery of timing pulses very difficult.
(iv) The high DC component does not permit the use of transformers
for coupling.
(v) Thus the simple NRZ binary code does not satisfy the requirements
of a line code.
4.0 RZ BINARY
4.1 This is a modification of the NRZ code and stands for "Return to zero"
binary. In this '1' bit is represented by a pulse of half the bit duration as
shown in Fig. 5
(b) The spectrum for this code is shown in Fig. 5 (c).

FIG. 5. RZ BINARY - WAVEFORM & SPECTRUM
4.2 Here the '1' bits pulse have only 50% duration. From the spectrum we
can seen that there is a strong component at 1/T, the clock frequency.
Hence clock recovery is possible. But still, because of the strong
DC.component and low frequency content, this code is also not
suitable for transmission.
5.0 BIPOLAR CODING (AMI CODE).

5.1 AMI stands for "Alternate Mark Inversion" This code solves the DC
content problem,. Here, a logic 'O' is represented by o volt and logic '1'
is alternately encoded with positive & negative voltages. Therefore, the
average voltage is maintained very close to zero and hence there is no
DC component. Under steady state conditions a low DC of the order of
0.4 to 0.9 volts only remains.
The waveform for an AMI code is shown in Fig. 6.
FIG. 6. AMI CODE. SIGNAL WAVEFORM
5.2.1 From the AMI wave form is can be seen that this code has a built in
error monitoring facility. Since alternate marks (or *1's) are to be
inverted, any deviation from this would mean an error. This can be
practically achieved by having a comparator network which will check the
polarity of the ' 1' s received. The spectrum of an AMI code signal (after
doing Fourier analysis and plotting the various frequency components of
the signal) has a shape as shown in Fig. 7.
FIG. 7. SPECTRUM OF AMI SIGNAL
(ii) From the spectrum For the AMI code it can be seen that the
maximum power is centred around the half bit rate i.e. 1/2T and
that there is no DC component.
(iii) Although the AMI code satisfies most of the line code requirements,
a series of *O's is encountered, the timing information is likely to be
lost. This is a limitation of the AMI code.
(iv) The AMI code is the one specified for 24 channel PCM systems.
5.3 Generation of AMI code.

Fig. 8. shows the block schematic of the network used to generate the AMI
code.
(i) The serial PCM output in RZ binary form is fed to the flioflop
toggle point and to the gates G1 and G2 as show
(ii) Cricuit operation (A)
First make arrives
Under this condition, the flip flop is set and Q goes HIGH. Consequently Gl
output goes HIGH which triggers the positive generator. The output of this
generator is a positive pluse. The wave forms for this condition are shown
in section I of Fig. 9.
FIG. 9. AMI GENERATION - WAVEFORMS FOR FIG.5
(B) The next mark arrives

This pulse will reset the flip flop. Hence Q goes HIGH. G2 will be also HIGH
and it triggers the -ve generator whose output is a negative pulse as shown in
section II.
(C) Two continuous ‘1 ' s arrive
Under this condition, the flip flop is Set by the first bit and Reset by the second.
Therefore G1 goes HIGH first to generate a positive pulse and G2 goes HIGH
next to generate a negative pulse as shown in section III. The adder network
combines the outputs of negative and positive pulse generators to give the
AMI output. These various wave forms are shown in Fig. 9. from (a) to (h).
6.0 HDB3 CODE

6.1 To overcome the timing difficulties in the AMI code another code called
the HDB3 code has been devised. The abbreviation HDB stands for
HIGH-DENSITY BIPLOAR code.
6.2 (i) The HDB3 code is actually a code from a family of codes derived
from what is called binary N zero substitution or BNZS method.
(ii) In this method, the PCM signal is usually transmitted
according to the AMI code; but when a string of N zeroes is
encountered, the N zeroes are replaced by a special code,
which will deliberately introduce a bipolar deviation or violation.
(Normally in the AMI code, if there are N zeroes, they will be
transmitted as such. But in the BNZS method, a ' 1 ' pulse is
introduced deliberately. The polarity of this " 1 ' depends upon
the polarity of the previous mark encountered. This
additional' 1 ' pulse introduced in place of a '0' is called a
"violation").
(iii) When the substitution of a zero by a violation pulse is done for

4 zeroes, (i.e. N = 4) the BNZS code is called the B4ZS code.
Since this code precludes strings of zeroes greater than three,
it is also referred to as a HDB3 code. Here when the number of
zeroes is more than 3, the fourth bit position is filled with a
violation pulse.
(iv) Consecutive violations are made to be of opposite polarity so

that these violations themselves donot produce any DC
component.
(v) The violation pulse is always placed in the last bit position.
Suppose there are 4 zeroes coming in a row. Then the HDB3
code for this would be BOOV in general where V is the violation
pulse. The polarity of this depends on the polarity of the last '1'
and the number of %1'"encountered prior to the four zeroes.
(vi) The first bit of the code was shown as B in (v) above. B is set to '0' if
the number of '1' s encountered prior to the violation is ODD. If it is
EVEN or ZERO then the "B" bit is filled with a T whose polarity is in
accordance with the AMI code. i.e. if the previous ' 1' was positive +
then B is '1' with negative polarity and vice versa.
(vii) The substitution rules stated above are summarized in table 1.
Table 1. HDB3 Code - Substitution Rules
Number of ' 1 ' since last Violation
Polarity of preceding Odd Even

'1'
Negative 000 V" B+OOV+
Positive 000 V + B" 00 V
From the above Table it can be seen that when the number of Ts is
even, the HDB3 substitution is BOOV; in this, B follows the AMI code
and V follows B. If 'B' is positive, then V is also a positive pulse. Thus
consecutive violations are made to be of opposite polarity so that
there is no DC component added by the violations themselves.
6.3 Examples of HDB3 Code Conversion

Condition 1.
6.3.1. (Number of' 1 's preceding violation is ODD.)

Consider the NRZ binary wave form given in Fig 10 (a). Assume that
there is no previous violation.
[NO of 1 = ODD]
Fig 10 (b) is the RZ binary form for Fig 10 (a).
Fig 10 (c) is the corresponding HDB3 Code.
(i) Notice that upto pulse Z, the HDB3 Code follows the AMI Code.
(ii) After pulse Z, we have four consecutive zeroes. This calls for a
violation.
(iii) Prior to the arrival of these zeroes, three ‘1's were encountered i.e.
number of ‘1 's preceding the violation is ODD.
(iv) This means that the HDB3 substitution for the 4 zeroes will be of
the form 000V.
(v) Also the polarity of the last ' 1 ' before the arrival of the zeroes is
positive. Therefore the violation pulse will also be a positive pulse, as
shown shaded in Fig 10 (c).
(vi) Then the fourth pulse P arrives which is converted according to AMI
code as shown.
EX: Draw the HDB3 code with the first pulse in Fig 10 (c) as a negative
pulse.
6.3.2 Example 1. (b)
Consider the RZ binary wave form shown in Fig 11 (a). In this the first
pulse is a violation pulse resulting from the occurrence of 4 zeroes just
before pulse X.
(i) Here, the first pulse is positive violation pulse. The next pulse (i.e.
pulse X) is converted in accordance with AMI code and is therefore
shown as a negative pulse in Fig 11 (b).
(ii) After pulse X we get 4 Zeroes.
(iii) Now, the total number of '1's SINCE the last violation is one, i.e. ODD.
Therefore the substitution is of the form 000V.
(iv) As the polarity of the last M' before the arrival of zeroes is negative, the
violation pulse is also negative which is shown as a shaded pulse. (V-).
6.3.3 Example 1 (c)
Consider the RZ wave form shown in fig 12 (a), assume that there was no
previous violation.
FIG. 12. EXAMPLE OF HDB3 CODE [1(c)]

(i) Here after pulse X, we have 4 zeroes and again after pulse Y, 4
more zeroes.
(ii) The first pulse goes as a positive pulse. The next four zeroes are
substituted by 000 V because the polarity of the last '1' is positive and
the total number is ODD.
(iii) Then pulse is converted into a negative pulse according to AMI code.
(iv) The next 4 zeroes are substituted by 000V since in this case the total
number of '1' s is again ODD and the polarity of the last '1' is negative.
6.3.4 Condition 2 :Number of T EVEN consider the RZ binary shown in

Fig.13
(a) and assume that there was no previous violation.
(i) In this case the pluses X and Y are converted according to AMI
Code as shown in Fig 13 (b).
(ii) Four zeroes are encountered after pulse Y. Here the number of' 1 's
prior to these zeroes is EVEN and therefore the substitution is of the
form BOOV.
(iii) Since the last "1' is a negative pulse, from Table 1 the substitution
BOOV.
(iv) The HDB3 substitution for the 4 zeroes is shown in Fig 13 (b) as
shaded positive pulses.
(v) The next pulse Z is converted as a negative pulse in accordance with

AMI code.
6.3.5 Example 2 (b)

Consider the RZ wave form shown in Fig 14 (a). Assume there was no
previous violation.
Fig 14. HDB CODE CONVERSION (eg 2b)
(i) In this case, the wave form begin with 4 zeroes. There are
no previous violations. The number of "1's preceding the string of
"0" is zero i.e. EVEN.
(ii) Therefore, The substitution is of the form boov.

(iii) The (AMI) coding network is so designed that the very first bit is
always a positive pulse. Hence the HBD3 code for Fig 14 (a) would be
00 V which is as shown in Fig 14 (b).
(iv) The following " 1's X, Y and 2 are converted according to AMI code.
6.3.6 Example 2 (C)

Consider the RZ wave from in Fig 15 (a). Assume a positive violation pulse to
start with.
Fig. 15 HDB2 code conversion [eg. 2 (c)
(i) Here, as shown in Fig 15 (b), a positive violation pulse is

assumed. Then we have pulses X and Y which are converted
according to AMI code.
(ii) After pulse Y, we get 4 zeroes. Theses should be substituted by

BOOV since the number of' 1 's is EVEN.
(iii) Further since the polarity of the last ' 1 ' is positive, the code would
be B 00V. This is shown as shaded pulsed in Fig 15 (b).
Then pulse Z is converted according to AMI code.
6.3.7 Example 2 (d)

Consider the RZ Wave form in Fig 16 (a)
(i) Here after pulses X and Y, we get eight consecutive zeroes.
(ii) X and Y follow AMI code. Number of T s is Even in this case.
(iii) The first four zeroes are substituted by B 00 V since the last' 1' was
negative.
(iv) After the first 4 zeroes, we have another 4 zeroes coming number
of' 1' in this case zero i.e. EVEN again.
(v) Hence the second set of zeroes is also converted as BOOV. But
the polarity of the last '1' (although it was a violation pulse), was
positive.
Hence, the second set of zeroes is converted, as B 00 V
(vi) Pulse Z, then follows AMI code,
(vii) The substitution pulses are shown in shaded areas in Fig 16 (b).
6.4 But for the insertion of violation pulses, the HDB2 coding is similar to the
AMI code.
The spectrum for the HDB3 code is shown in Fig. 17
From the spectrum it can be seen that there is no DC component and that maximum
power is around 0.46/T. It means that the power in the lower and upper limits of the
spectrum is low. This would minimize high frequency alternation and cross
talk. Although this spectrum also has mulls at 1/T2/T etc, because of the violation
pulse introduced, timing is not lost when a long string of zeroes is encountered. The
HDB3 code satisfies ad the requirements of a line code and is therefore specified
by the CCCTT for 30 channel PCM systems having 2048 kbits/sec, clock.
7.0 HDB3 CODER & DECODER

Fig. 18 shows a simplified block schematic of an HDB3 CODER
Here, the encoder output is passed to the AMI circuit through a A bit shift
register. The shift register output is also fed to a ^4 ZERO DETECTOR'.
Normally, the HDB3 CODER FUNCTIONS as an AMI code generator.
When 4 or more *O's come, they are detected and an output goes to the
violation command circuit during this operation the 0 detector is inhibited for
4 clock periods. The mark counter gives a ' 1 ' when even number of marks
are encountered.
When ODD ' 1 ' are encountered, the AND gate O/P is zero. The pulse from
the violation command circuit is added to AMI output. When even * 1 ' s are
encountered, the AND gate output SETS the first stage of the shift
register. This goes to the AMI circuit and gets coded according to AMI law.
The violation pulse is then added after a delay of 2 bits. After the violation
pulse is added, the inhibit circuit and more counter are cleared.
7.2 HDB3 DECODER
The HDB3 code must be decoded into RZ binaryform at there receiving
end for detecting the analog signal. The HDB3 decoder used for this
purpose has the following function.
(a) Detect an AMI violation
(b) Count the number of zeros preceding the violation
This is done to determine if the last received mark is HBD substitution or an
error.
Fig. 19 shows a simplified block schematic of an HDB3 decoder.
Here the RZ converter converts all negative pulse into positive pulses. These
are then fed to a four bit shift register. When there is no violation. (i.e. when
there are no continuous zeroes present) the shift register gives a serial output
which is RZ binary form.
Simultaneously, The AMI violation detector checks for a deviation from the
AMI code. If alternate N1's are not having opposite polarity, then it gives an
output which will reset all the four bits of the shift register to zero. (This is
done because, at the transmitting end when a number of zeroes are faced
the V bit in BOOV code was inserted with a polarity opposite to that of the
previous mark By resetting the shift register we are converting the BOOV
code back to 0000. This is what is desired).
The output of the shift register is a serial RZ digital signal with the HDB3 code
substitutions removed. This RZ signal is the same as the TDM multiplexed
output of the PCM equipment and this can be further processed through PCM
decoder to retrieve the analog signal. Waveforms Typical HDB code/decoder
wave forms are shown in Fig.20.
8.0 CMI CODE (CODED MARK INVERSION)
8.1 This is a 2 level NRZ code in which a binary '0' is coded as '01' and binary
‘1's are coded alternatively as a logic '0' or T. In case of a binary '0' the two CMI bits
'0' and '1' are for half clock duration whereas for binary Ts the 'O1 and '1' are for full
clock duration. This is illustrates in Fig.21.
This is basically a binary code and the bit rate of the code is twice the bipolar AMI
code.
For this reason CMI code is grouped with 1B2B family of line codes. The CMI code
has a high clock content and for this reason. The CMI code is recommended by
CCITT for 140 Mb/s multiplex equipment (not a line code).
9.0 4B-3T CODE

9.1 This is a redundant ternary line code. In this code, blocks of FOUR
binary input digits are translated into cords of three ternary digits. The
code has following features.
• Reduction of line frequency by 25% compared to AMI signals.
• Provides possibility of Inservice Monitoring of BER by
monitoring RDS (Running Digit sound)
• Code efficiency is a high as 84%
• Rapid block synchronization
This code is used in line systems of 34 Mb/s and 140 Mb/s capacity.
9.2 AB3 T code combination
0000 - + 0 -
0001 - - + 0
0010 - 0 - +
0011 - + - 0
0100 - + + 0
0101 - 0 + +
0110 - + 0 +
0111 - + + +
1000 - + + -
1001 - - + +
1010 - + - +
1011 - + 0 0
1100 - 0 + 0
1101 - 0 0 +
1110 - 0 + -
1111 - - 0 -
A Bit binary 3 Bit Ternary Other Ternary combinations are also possible.
The Exact combination Varies for manufacturer to manufacturer.
10.0 BINARY CODES

10.1 There are 2 level binary codes for used in optical line transmission.
These are called alphabetical codes, these have the form 2N-1) B2NB
where N is an integer.
Some of the codes are :

1B2Bcode(n = 1)
3B 4B code (n = 2)
5B 6B code (n = 3)
11.0 COMPARISON OF LINE CODES
Parameter AMI HDB3 4B3T

Levels 3 3 3
Redundancy 58.5% 58.5% 18.8%
Normalized timing constant 1 1.28 0.76
Normalized average power 1 1.2 1.36
Max. No. Of consecutive 'O's 4 3 4
Input rate O/P rate 1 1 1.33
7
DSV (Digital sum variation) 1 2
11.2 SPECTRAL COMPARISON OF LINECODES
Fig. 22 Shows a comparison of the spectra of various line codes.
12.0 POWER DENSITY OF DIFFERENT CODES

The digital output of the PCM equipment is as such not suitable for
transmission over a cable pair. It has to be converted into a suitable
line code which will match the physical parameters of the medium. A
number of codes have been devised for this purpose of these the
most important are the AMI code and the HDB3 code which meet
almost all the basic requirement of a line code. The working principle
of an HDB3 decoder has also been outlined in this handout.
13.0 5B6B CODE:

13.1 The coding is done as per Table - 1. For 5 bits of input signal to the
code, either state 1 or state 2 of 6 bit code is selected as shown in
figure (23). Disparity information is used to select the state of the
current 6 bit code word as compared with the previous transmitted
state.
For example, if state 1 is selected, the input 5 bit data is converted
into the corresponding 6 bit code in state-1 in Table-1.
If the disparity of the converted 6-bit"code is 0, the next 5-bit data is also converted
into a6-bit code in state-1. if the disparity is +2, the next 5 bit data is converted into a
6 bit code in state 2. Thus state 1 and state 2 are alternated by a detection of
disparity + 2 or - 2.
In 5B6B Decoder, the disparity information is used to decide the state of the
current 6-bit code as compared with the previously recognized state. Normally
disparity+2and -2 are received alternately with disparity 0 ; thus state 1 and
state 2 .are alternated.
If an error detector detects any uncertainty state shown in figure (24) with
reference to violation of 5B6B decoding law or detects no code word, the
error detector generates an error alarm.
5B6B code in used in 34 Mb/s and 140 Mb/s optical line systems. `
`````
Table -1 5B6B Coding Law

Input word State 1 d State 2 d
0 101011 2 010100 -2
1 011100 0 011100 0
2 110001 0 110001 0
3 101001 0 101001 0
4 011010 0 011010 0
5 010011 0 010011 0
6 101100 0 101100 0
7 111001 . 2 000110 -2
8 100110 0 100110 0
9 010101 0 010101 0
10 010111 2 101000 -2
11 100111 2 011000 -2
12 110011 2 000111 0
13 011110 2 100001 -2
14 101110 2 010001 -2
15 110100 0 110100 0
16 OOT011 0 001011 0
17 011101 2 100010 -2
18 011011 2 100100 -2
19 111000 0 001100 -2
20 110110 2 001001 -2
21 111010 2 000101 -2.
22 101010 0 101010 : 0
23 011001 0 011001 0
24 101101 2 010010 -2
25 001101 0 001101 0
26 110010 0 110010 0
27 010110 0 010110 0
28 100101 0 100101 0
29 100011 0 100011 0
30 001110 0 001110 0
31 110101 2 001010 -2
Different Access Techniques
Different Access Techniques
1.0 INTRODUCTION
Across Network, the network between local exchange and subscribers in the
Telecom Network accounts for A major portion of resources both) in terms of capital
and manpower. So far, the subscriber loop has remained in the domain of the
copper cable providing cost effective solution in the past. Need for quick
deployment of subscriber loop, coverage of inaccessible & remote locations and
requirement of more bandwidth for new services coupled with advances in
technology have led to the emergence of new Access Technologies. Modern
access network technologies are discussed here.
2.0 IMPORTANCE OF ACCESS NETWORK
At present the access network represents approximately 45% to 50% of the

total capital investment in the telecom network. It is therefore a very substantial
portion of total network and must be given due attention. If this access network is
properly maintained most of the problems in the telecom network could be avoided.
However the copper pair cables still dominate the subscriber loop (local
network) due to certain reasons primarily based on techno- economic
considerations. This copper based local network is considered to be responsible for
most of the faults in telecom network. The obvious reasons are congestion of
underground facilities, complex network planning and limitation of copper cables to
handle digital signals leading to a network inappropriate for extending broadband
integrated services digital network (ISDN).
Introduction of Digital Technology coupled with radio transmission and optical

fiber cable has revolutionized Telecom Network worldwide. The overall reliability of
network has improved vastly. In India too these concepts have been field tried in the
access network. The implementation of the above technologies in the access
network
can be as follows:
a) Using radio in the access network (WILL Technology)
b) Using fiber in the access network (FITL Technology)
c) Exploiting the existing copper network for higher bandwidths.

(HDSL,ADSL,VDSL Technologies)
Let us discuss above modern technologies which are largely set to replace
copper in subscriber loop.
3.0 WIRELESS IN LOCAL LOOP (WILL)

Radio communication has been employed as a replacement for copper
based cables in the long distance media for several years. More recent
developments of digital radio and advances in micro-electronic circuits have
given rise to wireless in local loop (WILL). It involves using radio to replace the
wired link between PSTN switch and the subscriber. WILL is generally used as
"the last mile solution" to deliver basic phone services expeditiously where
none has existed before. It shall facilitate cordless telephony for residential as
well as commercial complexes where people are highly mobile. It is also used
in remote areas where it is uneconomical to lay cables and for rapid
development of telephone services. The main advantages of this technology
are:
1. Fast deployment and hence early access to revenue.
2. Reduced service interruptions.
3. Low maintenance & operational costs.
The radio technology is able to offer the same level of service quality as that
provided by wire line technology. The subscribers have no knowledge of their
radio connection and may access all the offered PSTN services in exactly the
same way as if they were directly connected by wire line. Application of
wireless local loop has just started worldwide. The technology employed shall
depend upon various radio access techniques like FDMA, TDMA, CDMA.
There is no international standard for this so far. However, a number of

national and regional air interface standards for Digital Cellular Mobile
Telephone system and cordless telephony are available. These are being
adopted for fixed wireless in local loop application. The various technologies
available in International market for WILL application are as follows.
4. TECHNOLOGY OPTIONS FOR WILL
4.1 Basically two types of technology options are available for wireless in
local loop. The first one based on cellular mobile Telephone system can be
adopted for fixed wireless in local loop application. These systems have Macro
cell architecture with cell radius of tens of kilometers ( typically 10-20 Kms),
The second type based on Micro cell architecture are extension of cordless
telephone systems. These systems have cell radius of few hundred meters
(typically 50-200 mts).
4.2 Point to Multi Point (PMP) systems also called Digital MARR systems are
becoming available. These systems can cover long range depending upon line
of sight conditions (LOS) and repeaters. These systems can be found
attractive in hilly areas, isolated islands or largely dispersed habitation where
multiple of subscribers are to be served.
4.3 Satellite media can also be used to extend local loop to subscribers who are
otherwise located at inaccessible places where laying of cables or line of sight
radio media is not economically justified. For example certain villages have
been extended gram panchnyat telephones using satellite media for
providing rural communication. Generally social factors dominate cost
considerations for providing local loops in such cases.
Now a days very small aperture terminals (VSATs) being used for interactive
data communication have proved successful in business/ corporate
applications. Multichannel per carrier VSATs are also used to extend trunk
junctions to remote and inaccessible/ hilly areas.
Through its wide area broadcast capability, a geo stationary earth orbit (GEO)
satellite is able to deliver essentially the same throughput signal throughout the
country or region at an attractive cost per user.Taking advantage of this factor
direct to home (DTH) satellite broadcasting with a smaller antenna at the
subscriber roof top is also an extension of local loop over the satellite.
Many personal communication services (PCN) services have been planned

using low earth orbit ( LEO) satellites which permit users with portable/
handheld terminals to connect themselves directly to the LEO satellites. In the
process the local loop is extended for fixed/mobile application.
4.5 FREQUENCY BAND
The WILL technologies available in different frequency & their important parameter
are indicated below:
SYSTEM
MACRO CELLULAR MICRO CELLULAR
TECHNOLOGY
CT2
GSM DAMPS CDMA DECT PHS
FREQUENCY 864-868
890-915 824-849 824-849 1810- 1895-
Mhz
935-960 869-894 869-894 1900 1918
Mhz Mhz Mhz Mhz Mhz
CELL SIZE LARGE LARGE LARGE SMALL SMALL SMALL
MULTIPLE
TDMA TDMA CDMA FDMA TDMA TDMA
ACCESS
RF CHL 100
200 Khz 30 Khz 1250 Khz 1728 Khz 300 Khz
SPACING Khz
VOICE CHL / 8 3 25-45 1 12 4

CARRIER
PIE/4- PIC/4
MODULATION GMSK CDMA FSK GFSK
QPSK QPSK
GSM Global System for Mobile Communication
DAMPS Digital Advance Mobile Phone Service
CDMA Code Division Multiple Access
CT-2 Cordless Telephony-2
DECT Digital Enhanced Cordless Technology
PHS Personal Handiphone Service
5.0 FIBER IN LOCAL LOOP (FITL)
In order to overcome the limitations of copper cable and to be able to

support value added broadband service like data, cable Video, HDTV and
increased use of computer which require bandwidth on demand, optical fiber
is introduced in the local loop. In light of its infinite bandwidth and high
reliability, optical fiber cable is the automatic choice for the local loop.
5.1 ADVANTAGES OF OPTICAL FIBER IN THE LOOP
(i) Impact of environmental factors is almost negligible on optical fiber cable.
(ii) Optical fiber cables are not susceptible to electromagnetic interference

and hence there is no possibility of intercepting information at any point
(iii) The limitation on loop resistance is eliminated by introduction of active

elements providing appropriate amplification.
(iv) Because of fiber’s unlimited bandwidth capacity up-gradation is very simple

as it can be affected by simply changing the end terminal equipment.
Repeated digging & cable laying is not required.
(v) Small size of fiber cable avoids congestion in ducts & crowding at MDF.
(vi) Due to their inherent wide band width capability optical fiber cable can
support narrow band and broadband ISDN services. They can also support
video transmission, thus bringing the telephone services and cable TV
operations together.
The advantages offered by FITL and limitations of copper access
network can be tabulated as:
Copper Access Network FITL Advantages

Challenges
• Bandwidth Limited • Virtually unlimited bandwidth
• Planning/Engineering • Reduced impact of forecasting

errors
• Simplified engineering with

universal access
• Maintenance • “No maintenance with fiber"

• Security • Requires physical security only
• Reliability • Dielectric media
• Obsolescence • Permanent Outside Plant
5.2 FITL NETWORKING
The long term objective of FITL is to take the fiber right upto the subscriber
premises or else to extend the fiber as close .to subscriber as possible. The various
approaches towards the end goal depending upon its penetration in the access
network can be listed below
(I) Fiber to the Building (FTTB)
(ii) Fiber to the Curb (FTTC)
(iii) Fiber to the Home (FTTH)
IMPLEMENTATION
While the use of fiber optics in the access network is extremely

advantageous and promising but it is still in the initial stages. Currently fiber costs
are higher as compared to copper but there is a trend towards decreasing costs of
opto-electoronics and optical fiber cables. Some of the implementation issues and
limitations of FITL specially in Indian contest are as follows:
(I) The reliable power supply at the remote end other than the exchange end
is a must to exploit the reliability and other advantages promised by FITL
concept.
(II) There is no major identified demand for broad band ISDN service. Thus
unless the cost economics of FITL is justified its application may be some
what slow.
6.0 HIGH BIT RATE DIGITAL SUBSCRIBER LINE (HDSL)
While there is no denying the fact that the fiber will eventually take
over the last mile (access portion) of the network ,it is felt & generally
accepted that it would not be economically justified immediately and, would
take some more time before it penetrates in the access network. The
Telecom Administrations world over have already invested a lot in, terms of
their copper based network and will continue to do so until the fiber becomes
more techno-economically feasible. Till such time there is no alternative but
to exploit the already buried (but not dead) copper to carry more and more
bandwidth.
HDSL is one such1 technology employing a transmission technique which

derives substantial capacity advantage in transporting digital signals in local
network over existing copper pairs by providing clear 64 kb/s channels
supporting voice, FAX and data services with a improved transmission
performance. In other words HDSL is able to convert the copper pairs into
high speed digital line carriers what were essentially individual voice
telephone line carriers. HDSL technology promises following advantages
a) The subscriber connectivity over a. distance of 4.5 Kms on 0.5 mm

copper pairs carrying 2.048 Mb/s data.
b) The adaptive digital signal processing used in HDSL allows near

fiber-quality transmission.
c) Remote power fading over copper wires from exchange to

subscribers.
d) There is no need for any cable conditioning or selection of pairs.
e) It is possible to extend the range of operation to 9 Kms over

single repeater.
HDSL Technology can prove very useful in improving inter exchange

junction working and subscriber access network utilizing The already buried
copper pair cables.
Recently some new technologies Asymmetric Digital Subscriber Line (ADSI.)

and very high Speed Digital Subscriber Line (VDSL) have come up which promise to
implement digital TV broadcast , video on demand interactive distance learning and
home shopping on the same simple existing copper lines. ADSL can carry 6 Mb/s
signal over 3.5 Kms (approx)and VDSL can carry 26 Mb/s to 52Mb/s over a short
distance of 600-1000 meters approximately. Later on it is expected to carry even
620 Mb/s over 100 meters. VDSL may find its use in business applications within a
building. Many Telecom Administrations are beginning to evaluate and install ADSL
services.
8.0 CONCLUSION
Subscriber loops form a very important part of telecom network The

increasing appreciation of draw backs of present copper based network and
introduction of high band width services have necessitated many alternate modern
access technologies. Flexibility and expediency are becoming the key driving factors
behind the deployment of WILL. This is a step towards mobile communications
leading towards personal communication services.(PCS)
The deployment of optical fiber in the access network promises many

advantages as compared to traditional copper cable network. Fiber extension closer
to subscriber premises will provide an economical, flexible and easily up gradable
transport media for carrying existing and emerging range of services including
telephony, distributive video services, high bit rate data and Broadband ISDN
services. HDSL, ADSL and VDSL technologies allow a techno-economically feasible
migration from copper based network to a broad band fiber based network of future.
These modern Access Technologies shall avoid further large scale

deployment of copper cable and shall pave the way for setting up a strong Access
Network infrastructure required to step in the future Telecom Network of 21st
Century.
PLANNING GUIDELINES FOR OFC OVERLAY ACCESS NETWORK
In January 2001 BSNL Board in its meeting has decided to provide

direct fiber to the Commercially Important Customers. Minutes of the meeting have
been issued vide letter number 214-117/2000 TPL ( CX ) dated 31/01/01. Initially
the project was to be taken up in 8 cities, viz Ahmadabad, Bangalore, Chennai,
Coimbatore, Ernakulam, Hyderabad, Kolkata and Pune, where the No of DELs have
exceeded 3 Lakhs. The business cases of Chennai, Hyderabad and Ernakulam
Access Network is planned for 37 cities during this year, where more than 1 Lakh
DELs are existing. These guidelines are issued in order to achieve the following
objectives.
a. Provision of fiber to customers from end to end at a later date.
b. Provide strong fiber infrastructure in an organized manner
c. To achieve convergence
d. Minimise the investment on the outdoor plant.
e. Avoid repeated trenching in the city limits in the same areas.
f. Integrate the needs of all the services/ wings of BSNL requiring the fiber
media.
At present our fiber network is in the Fiber To The Network (FTTN) state. The
Access Network is proposed to reach upto the Curb so that the Fiber to the Curb
(FTTC) can be achieved. Fiber to the Building (FTTB) and Fiber to the Home can be
achieved in the later phases of expansion. Thus Access Network is essential in
every city where data/ leased line customers are in a good number. The last mile to
the customer is the most unreliable link compared to the reliable communication
system we have from one exchange to other. It is more appropriate to call this last
mile as First mile since the customer is always comes first in any direction to the
exchange. Access Network shall strengthen the First mile and also allows us to
deliver the giga bit band width to the customers. It shall also enable us to enter in to
Service Level Agreements with customers to the extent of 99.9%.
The Access Network is proposed to be used as the platform for offering

future services such as Metro Local Area Network (Metro LAN), Wide Area Network
( WAN ), Ethernet over SDH, Ethernet over MPLS ( EoMPLS) and Storage Area
Networks ( SAN).
The planning aspects can be mainly classified under following points
:Network Planning
1. Type of Duct
2. Duct Planning
3. Duct Utilization
4. Detailed Survey
5. Fiber Planning
6. FDMS
7. Project Estimate
8. Duct Laying
10. Cable Laying
11. Preventive Maintenance
1. NETWORK PLANNING
The Network ultimately should provide end to end fiber connectivity for high
bandwidth users. The Network should provide additional fiber connectivity between
BSNL exchanges and Transmission centers. It should also be capable of building
up of leased lines traffic from exchanges to other exchanges or transmission centers
as required. The Network should provide alternate media between exchanges,
RLUs, RSUs and DLCs. Broadband data traffic should have access and aggregate
points in the network. The duct planning should be done in order to cover the
potential customers as listed below. Universities, colleges, schools, hospitals,
hostels, multistoried buildings, cinema theatres, software technology parks, industrial
pockets, exhibition grounds, Air ports, posts, railway station, travel agencies internet
service providers, cable operators, call centers, training institution, research centers,
banks, cellular service providers etc.
The following information is to be collected before planning the Network :-

Existing duct plan
Existing OFC Network (N/W)
DLCs working & planned
Pillar locations
Location of existing exchanges, RLUs, RSUs
Location of TAX, & transmission centers
Route for cable laying where permission is already granted
Routes for which permission applied for
Road map of the city
Location of important places such as Hospitals, Colleges, Business
establishments etc.
All the above data is to be drawn on the road map of the city. This shall be the
starting point for the planning of the network.
2. TYPE OF DUCT :
In order to provide fibers for CICs, DLCs, junction traffic, long distance traffic and
other value added services such as cellular, WILL High Count fibers are to be used.
Provision of fibers for these needs may be required to be done in many phases.
This indicates that multiple pipes are essentially to be laid in city limits. 40 mm
Permanently lubricated HDPE pipes (PLB HDPE pipes) are to be used for laying the
OF cables. Coloured pipes should be used to identify the multiple cables to be laid.
Quality of the pipe is plays very critical role in the Access network. The PLB pipe
being laid is proposed to serve as the permanent reusable duct. The cables are
expected to be deblown and blown in these ducts, when high count fibers are to be
laid in place of the existing cables.
TEC specification is available for 40mm & 32 mm (outer diameter) PLB HDPE
pipes. OF cables with 16 mm Outer diameter, can be easily blown in 40mm Pipe.
The 96 F/ 48F OF cable supplied by M/s Sterlite and M/s Icomm have an outer
diameter of 18 mm. The 96F cable has been successfully blown in 40mm PLB pipe
in Chennai. 96/48F can be also pulled in the PLB pipe subject to the condition that
the pulling force does not exceed 2.5x Weight of cable for 1 KM.
Cable blowing is to be planned in the PLB pipe used in the Access Network. In
general the cable blowing shall be done by the pipe supplier within the agreement
time. Access Work may require more PLB couplers and end plugs. Since pipes
are being laid by other private operators, it becomes essential to identify our pipes.
Accordingly manufacturer may be asked to put BSNL logo, name on the pipe.
Protection arrangements for these multiple PLB ducts should be reconsidered.

When multiple pipes are laid, the trench width shall increase. For protecting these
multiple pipes, RCC slabs or rocky slabs ( eg: cuddapah stones) of width atleast 40
cms may have to be used. ( 40 cm x 50 cm x 4cm ). Use of higher diameter GI and
RCC round pipes are required at the bridges and culverts. A minimum of 7 PLB
pipes can be accommodated in 150 mm GI / RCC pipes.
3. DUCT PLANNING
Trenching and reinstatement in cities is becoming very difficult, time consuming

and highly expensive. Lot of coordination with corporation/municipality and other
infrastructure agencies is required. Apart from this, the inconvenience to public and
other infrastructure agencies imply that the trenching for laying the PLB ducts should
be a one time job. Hence instead of laying one or two pipes, looking at the current
need, it is essential that multiple pipes are to be laid.
In general, the number of ducts may be planned as 8/7/6/5/4. In the core areas
more than 8 number of ducts may be planned. More number of ducts may be
planned within 200 Mtrs of the exchange surroundings.
While doing the duct planning, existing concrete duct is to be considered.

Possibility of removing existing unused copper cables in ducts may have to be
explored. The new duct being planned should cover all the existing pillar locations,
DLC locations. In general polygonal architecture is proposed, with the main
telephone exchanges, RLUs, RSU, Transmission centers as the polygon vertices.
Main The polygon arms are planned with

A
Multiple PLB HDPE Pipes.
RSU
Triangle B
Outer arm
Primary Arm
C Main
A B Inner arms are also proposed in

Polygon each with 12 no. of ducts
Inner arm
Distribution Arm
The polygon by name indicates that the duct can be planned with any number of
arms. A few examples are shown for rectangle and Pentagon.
A B
A B
C D
C D
RECTANGLE PENTAGON
Many places as the geography does not permit such Polygons with the distribution
arms meeting at a place, the polygons may be planned as shown below.
A B
C D
The advantages of planning the ducts in the polygon fashion is as given below.
a. The exchange areas are demarcated automatically
b. OF Cable ring structures are formed inherently.
c. This structure helps in growing towards mesh network.
d. Facilitates direct connectivity among different exchange areas.
e. Transmission Network integration is achieved.
f. The network is scalable as the Polygons can be added externally as well as

internally.
Triangle and rectangular(parallelogram) type polygons may be planned in the

core areas and Pentagons, Hexagons and above may be planned in the areas
surrounding core areas and Peripheral areas.

Feexch

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Feexch

Uploaded by

Copyright:

Available Formats

Fundamental of Digital Transmission, Encoding & Modulation

Techniques, Definition & Discription of Digital hierarchies, Digital

Telecommunication systems started with the transmission of digital signals. In

In 1876, Alexander Graham Bell invented the Telephone and as means of

Advantages of Digital Communication

(iii) Compatibility of different traffic : Any digital media of suitable capacity

(iv) Multiplexing, demultiplexing, branching of digital signals produce no

(v) Level fluctuations occurring during transmission have no effect on the

(vi) Economies in certain applications : PCM is inherently cheaper than

(viii) Applicability to other transmission media : Optical fibre waveguides

(ix) Applicability to extremely difficult transmission paths.

(x) Simpler equipment : There is no need of complicated filter and analog

(xi) Easy repeatability of design.

Main Obstacles to Digitalisation

(i) Less efficient use of carrier capacity in terms of telephone

(ii) Working at very high frequencies;

(iii) Need of multi–level modulation for radio transmission;

(iv) Voice interpolation required for satellite communication;

(v) Higher sensitivity to selective transmissions caused by

(b) Different transmission of TV signals : Digital transmission of TV signals

Eqpt. Analog Digital

Means to overcome digital transmission limits :

– High speed integrated circuits

– FET's amplifiers (for radio transmission)

(b) Introduction of large scale integrated components (LSI, VLSI)

– Use of microprocessor (for functions such as adaptive

– increased circuit compactness (TV encoding, Signal processing,

– reduced power consumption.

Channel Capacity or Information Rate

Bit versus baud

In a communications system, the encoding of one bit per signal element

where B is the baud rate and W the bandwidth in Hz.

The Nyquist relationship was based upon a problem known as intersymbol

Pulse response through a band–limited channel. The bandwidth limitation of a

Since an oscillating modulation technique such as amplitude, frequency or

Bit Baud Rate, Symbols

Nyquist theorem on minimum Bandwidth transmission systems states that it is

Nyquist Criteria, Roll Off Factor

For practical usefulness, however, the minimum Bandwidth Solution has to be

In the raised cosine solution, flexibility exists in the selection of the

(i) ISI is Zero.

If 16 PSK is used, then Baud rate = 35 MB/s.

Nyquist BW = 17.5 MHz.

Total channel BW = 35 MHz.

What is Inter Symbol Interference (ISI) ?

Therefore, if we examine a single interval in which a binary 1 is being

The following figure (Fig.6) shows some representative transmitted

Fig. 6 Generation of Eye Pattern

All of the methods of detecting errors involve the transmission of redundant

THE DOWNTOWN BRANCH OF THE BANK OF CENTERVILLE WAS

THE DOWNTOAN BRANCH OF THE BANK OF CENTERVILLE WAS

The advantage of echoplex is its simplicity. It does not require complex

Neither type of parity has an advantage over the other in most

How a communication system responds to parity errors depends on how the

A parity error is generated when an odd number of bits is changed during

Horizontal and Vertical Parity Check

The receiver checks the horizontal parity of each character as it is received.

Unfortunately, the combination of horizontal and vertical parity can reliably

No system of error checking is 100% foolproof. Table 4 contains 4 bit erorrs.

Cyclic Redundancy Check (CRC)

Shift right register Shift right register Shift right register

The important thing to recognize is that once a bit is received, it continues to