ASIC & FPGA Design

PART A
UNIT -1
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. List any four types of ASICs. What is meant by feed through in cell based ASIC? Construct a Xilinx SRAM cell and explain the programming technology. What is the basic difference between conventional ICs and ASICs? What is an antifuse? Draw the schematic of an Actal antifuse. What is meant by in-system programming CISP? State whether the antifuse programming technology supports this feature. Enlist the salient features of reconfigurable gate array. Mention the difference between channelled gate array and channel less gate array. Define the term effort delay. What are types of Masked Gate Arrays (MGA) or Gate-Array-Based ASICs (GA)? What are the three types of MGA and its important features? Draw the circuit of a Xilinx Static RAM (SRAM) cell. Distinguish full custom and semi-custom ICs.

UNIT-2
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. Differentiate order dependent and independent routing. What are the objectives of detailed routing? What is power routing? What are the steps involved in the physical design of ASICs? List the factors that are to be considered during floor planning. What is goal and objectives of a system partitioning? What is the mean time to failure (MTTF) for a direct current? What are the objectives of placement? Differentiate clock skew and clock latency. What are the objectives of partitioning? What is the meant by local density and global density? Mention the applications of design rule check. Write the role of partitioning in ASIC design.

UNIT -3
1. Define blocking and non-blocking procedural assignments in behavior modelling of VHDL. 2. Define clock latency?

3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21.

What is the IDDQ test? What are the problems associated with cell library? Why is parallel fault simulation necessary in ASIC design? Distinguish between structures and procedures in VHDL. What is logic synthesis? Define the term behavioural simulation. What is PALASM? Give the PALASAM statement examples for a. Combinational Assignment b. Registered Assignment. What is a package in VHDL? List any two VHDL packages. The length of the test sequence is L=7 and the length of the signature register is R=3. What is the probability of aliasing (not detected an error)? List out the types of error identified by Net list screener. Write the syntax for care statement. How does fault occur in VLSI design and classify the different forms of fault? Give any four file types used by Actel Design software and their meanings. What are the errors that can be found by a Net list screener? Define fault and fault model. What are the different approaches to memory synthesis? Give the advantage of hierarchical design. Compare the applications of functional and timing simulation. Write the importance of test in ASIC design.

UNIT-4
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. What is a meander factor? Define Shannons Expansion theorem. State the advantages of Altera MAX 5000 interconnect. What is meant by cow bar current? Why is it important in output drivers and clock buffers? Define channel density. What are local nets and external nets? List any four file type used by Actel design software. Define the term speed grading. Mention the important of back annotation. Write the naming convention of Xilinx part. Give an example.

UNIT-5
1. 2. 3. 4. 5. 6. 7. 8. 9. What are different steps in SoC Design Flow? What is Canonical SoC design?

What is mean by design and reuse?

What is mean by Configurable SoC? What are the advantages CSoC ? What is mean by RTOs? What are the problems in SoC Testing? What is the significance of Testing in SoC ? What are the different modes in embedded core test?

10. What is the role wrapper in Testing? 11. Draw the multilayer software architecture in SoC 12. What is mean by Hardware/software Codesign? 13. What are the codesign tools used in SoC? 14. What are the test issues in SoC ? 15. What is at-speed testing? 16. Differentiate between ASIC and SoC. 17. What are the applications of SoC ?

PART B UNIT-1
1. What are the steps involved in VLSI design flow? Explained in detail.(16)(10)(6) 2. Explain the different types of ASIC with neat diagram. And their application.(8)(10) 3. Explain the following programming tech used in FPGAs.(16)(8) a. Antifuse b. Static RAM c. EPROM d. EEPROM 4. Compare semi-custom and full-custom design in ICS.(6) 5. Explain the two types of anti-fuse. Mention its advantages and disadvantages(10) 6. Explain ASIC design flow with neat diagram.(10) 7. With brief description, explain the function of each step to design an ASIC.(8) 8. Compare and contrast the various programmable ASIC technologies.(8) 9. Write Short notes on SPLDs-PROM,PAL,PLA (8) 10. Write short notes on FPGA. (8)

UNIT-2
1. Explain the various techniques used for global routing between and inside flexible blocks.(16) 2. Explain the following in the context of floor planning and placement a. Cyclic constraints.(6) b. Channel routing.(5) c. Clock planning.(5) 3. Briefly explain left edge and area routing algorithms.(16) 4. Explain the algorithm used for FPGA partitioning.(8) 5. Describe the algorithm used for placement and routing.(8) 6. Discuss in detail DRC and physical design flow.(16) 7. Explain in detail about the Eigen value placement algorithm with an example.(8) 8. Explain in detail about the a. Global routing.(8) b. Detailed routing.(8) 9. Briefly explain power and clock distribution schemes used in floor planning.(16)

10. 11. 12. 13. 14. 15. 16. 17.

With appropriate circuit schematic explain special routing in ASIC design.(16) Illustrate the principle of K-L Algorithm.(8) Write a short note on simulated Annealing(8). Explain the procedure to measure delay in floor planning.(8) Write short notes on any one Special Routing technique.(8) Explain the application of Kernighan-Lin algorithm in partitioning.(10) Compare the principle of constructive and iterative placement improvement algorithms.(6) Compare the goals and objectives of global and detailed routing. Give a brief note on the principle of multi-level and timing-driven routing methods.(8)

UNIT-3
1. Explain how a two variable function can be implemented using 2:1mux in 10 different ways.(16) 2. Write short note on: a. Low level design language.(8) b. Electronic design interchange format.(8) 3. Explain the following. a. Stuck at fault model.(8) b. IDDQ test.(8) 4. Explain the structured test techniques for combinational circuits, sequential circuits and memories.(16) 5. List the importance of testing. What do you mean by fault modelling?(8) 6. What is the importance of port map command? Using port map command writes the VHDL code for full adder using half adder circuit.(10) 7. Write down the importance of 1. If statement 2. Case statement in VHDL.(6) 8. Write a note on FSM synthesis in VHDL.(8) 9. Briefly explain static timing analysis and net capacitance in VHDL.(8) 10. Describe the following terms of schematic entry with diagram wherever required(10) a. Cell name b. Instance name c. Schematic icons and symbols d. Nets e. Vectored instances and buses. 11. Why we go for low level design language instead of schematic entry and describe the basic features of some of the low level design languages?(6) 12. Model a combinational logic in Verilog and VHDL to carry out logic synthesis such that the model created by a synthesis tool is functionally equivalent to your behavioural model.(10) 13. Describe the deterministic and non-deterministic fault simulation algorithm.(6) 14. Explain in detail about the hierarchical nature of an EDIF file.(8) 15. Explain the CFI connectivity model using the EXPRESS language and its graphical equivalent.(8) 16. Write the VHDL code for a full adder using a. Structural modelling.(6) b. Behavioural modelling.(5)

17. 18. 19. 20. 21. 22. 23. 24. 25. 26. 27. 28. 29. 30. 31. 32.

c. Data flow modelling.(5) Write the Verilog code for an odd and even parity generator (for four bit data).(6) With the boundary scan architecture explain the boundary scan test.(10) Discuss in detail about CFI connectivity model.(16) Explain different classification of concurrent statement in VHDL.(8) How full adder is modelled in VHDL.(8) With an example explain ATPG simulation model used in fault analysis.(16) Explain the working principle of logic simulation.(8) Explain the principle of formal verification with an example.(8) Explain any two types of fault simulation(8) Explain the principles of PODEM algorithm(8). Explain the application of schematic entry with neat diagrams.(10) Give a brief note on EDIF syntax.(6) Describe the different types of fault simulation.(10) Give a brief note on switch and gate level simulation.(6) Explain the principle of automatic test pattern generation and describe an algorithm for automatic test vector generation.(10) Give a brief note boundary scan test.(6)

UNIT -4
1. With a neat sketch explain Xilinx LCA interconnect.(8) 2. Discuss the timing model of Actel ACT logic modules.(8) 3. What are the programming technologies required for Actel and Xilinx FPGAs? Explain.(8) 4. Describe the Xilinx LCA interconnect architecture and also determine Elmores time constant for a section of interconnect around CLBs.(10) 5. Give the basic logic cell architecture of ACT1,ACT2 and ACT3 FPGA families and describe their functional behaviour.(10) 6. Consider an Alter a MAX 5000 logic array macro cell with three product-term lines. Implement the function Z=A.B.C+A.B`.C`+A`.B.C`+A`.B`.C since Z has four product terms show how to use shared logic expanders that feed terms back into the product term array.(10) 7. With neat diagrams showing the timing mod el with values for a Xilinx XC 4005-6 and Discuss the functional a view of clock distribution, explain the terms set up time, clock skew and latency.(6) 8. With an example explain how to use the expander logic and programmable inversion in Altera FLEX architecture.(8) 9. With simplified block diagram explain the Altera Max interconnect scheme.(6) 10. Briefly explain practical issues of FPGA technology.(16) 11. Explain Actel Act logic module architecture with an example.(16) 12. Discuss the functional behaviour of the Actel ACT 1 logic module and its circuit level implementation.(8) 13. Explain the Altera FLEX architecture with the details of its logic elements.(8) 14. Explain how programmable inversion is used to simplify logic.(8) 15. Write short note on FPGA synthesis.(8) 16. Draw the Xilinx XC4000 family CLB and discuss the Xilinx LCA timing model.(8)

17. Describe the interconnect schemes used in Altera MAX 5000 and FLEX family with necessary diagrams. How do the above schemes differ from that used in Xilinx EPLD?(8)

UNIT- 5
1. Write Short notes on. i) Techniques for SOC Testing. (8) ii) Hardware / Software codesign in SOC. (8) 2. Explain the different components in Digital Camera in SOC perspective. (16) 3. Explain the different components in Bluetooth Radio/Modem in SOC perspective. (16) 4. Write short notes about: i) USB (8) ii)SDRAM (8) 5. What are the different design methodology followed in SoC.(16) 6. What is configurable SoC ? Explain it with suitable example.(16) 7. What are design issues in emebedded software design for SoC? (16)

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