1116

Power Electronics-059

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006

Boost Current Multilevel Inverter and Its Application on Single-Phase Grid-Connected Photovoltaic Systems
Pedro Gomes Barbosa, Member, IEEE, Henrique Antonio Carvalho Braga, Senior Member, IEEE, Mrcio do Carmo Barbosa Rodrigues, Student Member, IEEE, and Estevo Coelho Teixeira, Member, IEEE

AbstractThis work presents a novel current multilevel (CML) inverter topology, named boost CML inverter, and its application on energy processing of single-phase grid-connected photovoltaic (PV) systems. The structure allows a high power factor operation of a PV system, injecting a quasi-sinusoidal current into the grid, with virtually no displacement in relation to the line voltage at the point of common coupling among the PV system and the loads. The major appeals of using the CML technique are the balanced current sharing among semiconductor switches and the decrease of the current slope in the circuit devices, with a consequent reduction of conducted and radiated electromagnetic interference (EMI). The CML technique also allows adapting or minimizing current waveforms harmonic content. System description, mathematical approach, and design guidelines are presented, providing an overview of the new topology. In order to validate the proposed concepts, experimental measurements, made in a small-scale laboratory prototype, are also presented. The obtained results evidence the feasibility of the application of this new topology on singlephase grid-connected PV systems. Index TermsCurrent multilevel (CML) inverter topology, electromagnetic interference (EMI), photovoltaic (PV) systems.

I. INTRODUCTION

UE TO the growing energy consumption around the world and the eminent exhaustion of fossil-fuel reserves, a great interest on alternative energy sources can be noticed nowadays. The threat of electrical energy rationing, blackouts, and overtaxes, in addition to the great environmental awareness, increases the requirement of research on alternative renewable energy systems. Among the clean and green power sources, the photovoltaic (PV) solar energy comes up as being a very interesting alternative to supplement the generation of electricity. Due to the persistent cost reduction of PV modulesaccording to some studies, a PV module will cost around US$ 1.00/Wp by 2007 [1]this kind of solar energy exploitation, once attractive in the past only in remote regions or rural zones, started to become an economically-interesting alternative even in urban applications, such as small-rated single-phase residential generation units connected to the utility grid.

Manuscript received October 5, 2004; revised July 29, 2005. This work was supported by CAPES, FAPEMIG, FINEP, and CNPQ/CTEnerg under Grant 552371/01-7. Recommended by Associate Editor K. Ngo. P. G. Barbosa and H. A. C. Braga are with the Electrical Engineering Department, Federal University of Juiz de Fora, Juiz deFora 36001970, Brazil (e-mail: h.braga@ieee.org). M. C. B. Rodrigues is with CEFET-MG, Leopoldina 36700-00, Brazil. E. C. Texeira is with COPPE-UFRJ, Rio de Janeiro 21941-972, Brazil. Digital Object Identier 10.1109/TPEL.2006.876784

There are grid-connected PV systems ranging from 100 W to several megawatts [2]. Most residential photovoltaic arrays range from 15 kW, depending on the available area, since they are usually located on the roof of houses and buildings. All the power generated by this kind of system is injected into the point of common coupling (PCC) among the loads and the grid, supplying or helping to supply the local power demand. If the generated power is greater than the demanded by the local loads, the generation excess will be injected into the utility grid. During periods when the PV generation is insufciente.g., at nightthe local loads are entirely fed by the utility. In these PV systems, a bidirectional power meter is required in order to register the power drawn by and generated on the building. As the PV cells generate dc power, a power conditioning system is also required, in order to suit the frequency and voltage level to the utility grid and allow the parallel connection. In addition, a PV system must present some features related to the safety, efciency, and power quality. There are some international standards, such as IEEE Std. 9292000 and UL 1741, that cover the connection of PV systems to the utility grid [3], [4]. An optional, but very interesting, feature of a PV system is the ability to track the maximum-power point (MPP) of the PV array. Several congurations of single-phase PV power conditioning systems, employing various static converter topologies, can be found in technical literature [5][7]. This paper introduces the application of the current-multilevel (CML) technique [8] on PV systems, in addition to the proposition of a novel CML single-phase inverter topology. CML converters have the advantage of reducing the current rating needs for the semiconductor devices, since the main current is shared by a number of paralleled cells. This benet is worthier for high power applications, although low power CML systems could be employed using small-rated (and often cheaper, as well as easily available) devices. Additionally, with intermediary levels (or steps) in the current waveform, in the circuit devices a decrease of current slope is achieved, with a consequent reduction of conducted and radiated electromagnetic interference (EMI). The CML technique has been applied to dc-to-dc converters, rectiers and current-source inverters [9][11]. A single-phase CML current-source inverter has been proposed some years ago, and is shown in Fig. 1 [10]. This topology employs two CML cells [8] and can synthesize an output current waveform with up to ve levelsemploying line-frequency switching [Fig. 2(a)]or up to three levelsemploying sinusoidal pulsewidth modulation (PWM) switching [Fig. 2(b)].

0885-8993/$20.00 2006 IEEE

BARBOSA et al.: BOOST CURRENT MULTILEVEL INVERTER

Power Electronics-059

1117

Fig. 3. Boost CML Inverter.

Fig. 1. CML currentsource inverter.

Fig. 4. Application of the two-cell Boost CML Inverter on a PV system.

frequency switching case, there is a considerable reduction of the switching strategy and logic complexities [12]. II. TWO-CELL BOOST CML INVERTER APPLIED TO PV SYSTEMS The application of the Boost CML Inverter to a PV system is shown in Fig. 4. This structure comprises a two-cell CML dc-to-dc Boost converter [9], cascaded by a current-source inverter. The modulation of the output current is performed by the dc-to-dc converter. The switches of the current-source inverter, operating in the line frequency, , are responsible only to set the direction the modulated current is injected into the grid. Each switch of the inverter bridge has been represented as a series connection of an idealized switch and a diode, since it must be an unidirectional current device. The current source, in the input of the dc-to-dc converter, is composed by the PV array connected to an inductive lter, the input inductor . Additionally, a capacitor ( ) is inserted between the PV array and the input inductor, thus reducing the voltage and current ripple in the PV array. It is important to consider that the proposed topology can also work without this capacitor. However, its utilization provides an optimization of the PV energy conversion system. A diode is placed between the input capacitor and the PV array in order to avoid a reverse energy ow. It is a setup found on various PV systems topologies [7]. and (dc-to-dc converter The gate signals of switches switches) are generated by comparing a rectied sinusoidal waveform (low frequency, ) with two 180 out of phase triangular carriers (with frequency ). This strategy is able to perform the PWM [12][15], as depicted in Fig. 5. An inverted logic on the gate signals can be noticed, since the current is or are blocked. The injected into the grid when either inverter bridge gate signals are also shown in this gure. With this switching strategy, the output current, before ltering, presents up to ve levels and the harmonics appear as sidebands

Fig. 2. CML current-source inverter output current waveform employing: (a) line-frequency switching and (b) sinusoidal PWM switching.

A new CML inverter topology, named Boost CML Inverter [12], whose electrical circuit is shown in Fig. 3, is presented in this work. It has some advantages, when compared with the previously referenced current-source CML inverter (Fig. 1), which employs eight self-commutated switches. Two balance inducand ) are required there, in order to achieve intertors ( mediary current levels and the balanced current sharing among the semiconductor devices. On the other hand, the topology proposed here needs only two self-commutated switches, since thyristors (spontaneous blocking) could be used to implement and . Moreover, only one balthe switches ance inductor is necessary. Up to ve-level can be synthesized in the output current waveform with this topology, employing either low frequency or sinusoidal PWM switching. For the low-

1118

Power Electronics-059

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006

Fig. 7. Cell 1 current modulation.

Additionally, the proposed switching strategy allows a balanced current sharing between the switches of the dc-to-dc converter, preserving an inherit characteristic of CML converters. A. Mathematical Analysis
Fig. 5. Theoretical representation of the sinusoidal PWM gating strategy (three upper traces) including inverter bridge pulses (two bottom traces).

Fig. 6. Typical representation of the ve-level sinusoidal PWM waveform and its harmonic spectrum.

around even multiples of the switching frequency. Fig. 6 shows this waveform and its harmonic spectrum for an idealized is the fundamental frequency of the output case, where current, equals to the line frequency. The switching harmonics can be practically eliminated by means of a simple and light second-order LC lter. Thus, it is possible to suit the system to international standards, such as the IEEE Std. 929-200, which recommends, for the general case, that the total harmonic distortion (THD) of the current injected by a PV system into the utility grid shall be inferior to 5 % at rated inverter output.

The main goal of the proposed topology is to process the PV power and inject a sinusoidal current into the utility grid. Such a low-distorted current is obtained by ltering the ve-level current waveform depicted in Fig. 6. Hence, a mathematical description of the ve-level waveform is of huge interest. To accomplish the mathematical task, as mentioned in the previous paragraph, one must rst consider the circuit shown in Fig. 4. It can be observed, according to Kirchhoff s currents law, that the boost CML dc-to-dc converter output current, which is the inversion stage input currentis the sum of the diodes currents, and . In other words, the current is composed by the sum of the current synthesized by each CML cell of the dc-to-dc converter. The same can be stated for the in. Thus, the analysis of verter output current, before ltering, this current will be done superimposing the contribution of each CML cell [8] of the proposed topology. Initially, consider the contribution of the CML cell that contains and . Here, it will be named cell 1. Under ordinary circuit operation, the switching frequency, , is much greater than the line frequency, . Hence, it is possible to assume that the reference signal is constant during a switching time period, the current waveform syntheas shown in Fig. 7, where sized by cell 1is also shown. The electrical angles are dened assuming that one switching period is equal to 2 rad, i.e., 2 , with 2 . The idealized mathematical expression of the current synthesized by cell 1 can be obtained by its Fourier series expansion, which, assuming ideal elements and no ripple in the inductors currents, leads to (1) where is the average current in the input inductor, is the (see Fig. 7). order of the th harmonic, and

BARBOSA et al.: BOOST CURRENT MULTILEVEL INVERTER

Power Electronics-059

1119

In practice, the reference (modulation) signal is not constant, as was supposed. It varies according to (2) as Since , the amplitude modulation ratio, referred in (1), can be replaced, without considerable errors, by [12], [14]. In this case, is dened by (3), according to the upper plot of Fig. 5

(3) Thus, (1) will be written as

(4) 1. which is valid to 0 , regarding The inverter output current, before ltering, and the switching strategy adopted to switches , shown in Fig. 5, can be written, as function of the dc-to-dc CML converter output current, , by

to verify that the switching harmonics appear as sidebands, centered around 2 4 6 , and so on [12], [14]. By this way, although boost devices are switched at , the output current lower harmonic is related to 2 . By analogy, this result can be extended to CML cells, employing triangular carriers of frequency with phase lag of 2 among them. In this case, the switching harmonics will also appear as sidebands, but centered (with 1,2,3, ). With a simple second-order around lter it is possible to practically eliminate the switching harmonics, what justies the use of this kind of modulation in the proposed topology. From (8) it is possible to derive the active power injected into the grid. Let us assume that a lter with unitary gain at in the fundamental line frequency, which leads a phase shift frequency current, is connected in the output of the inverter. Moreover, consider that the line voltage can be expressed by 2 , where is the rms line voltage. Therefore, the active power effectively delivered to the utility grid, , would be

(9) Other important relationships can be obtained from the analysis of the circuit operation, in a similar way to the approach described above. A detailed derivation of them can be found in [12], and the most important design relationships are presented here. The peak voltage across equals the peak of the line voltage, and the average value of the current through this switch is given by (10). Due to the symmetric operation of the two switches, these considerations also apply to switch

(5) Still regarding only the contribution of cell 1, and combining (4) and (5), the inverter output current could be expressed as

(10) (6) which proves that the proposed switching strategy implements a sinusoidal PWM for the boost CML inverter. Since the triangular carrier employed in the generation of the is 180 (i.e., rad) out of phase of gate pulse of the switch the triangular carrier associated to , the contribution of cell 2 (the CML cell that contains and ) could be written as The maximum reverse voltage across diodes and is also the peak of the line voltage and their average current can be calculated by (11) Regarding the switches and diodes of the inverter bridge, the maximum blocking voltage and average current can be assumed and . as the same dened for diodes The input and balance inductors are dened by (12) and (13), respectively (12) (13) where and are the acceptable current ripple (in %) in the input and balance inductors, respectively. From (13), it is possible to observe that the inductance of the balance inductor is dependent of the switching frequency. So, the inductance value can be reduced as the switching frequency increases, with a consequent inductor physical volume reducing.

(7) The effective inverter output current is given by the sum of the contribution of each CML cell. Adding (6) and (7), the odd 1,3,5, ) are canceled, resulting in switching harmonics (

(8) 1, shows that Expression (8), which is also valid to 0 amplitude of the fundamental-frequency component of the in. It is also possible verter output current varies linearly with

1120

Power Electronics-059

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006

Fig. 8. Simulation results: (a) ve-level waveform, (b) mains voltage (25% scaled) and current injected into the grid, and (c) and (d) currents through active switches.

On the other hand, as stated by (12), the input inductor inductance value does not depend on the switching frequency. It is only related to the line frequency. However, at higher currents, both inductance values could be considerably reduced. B. Medium-Power Simulation Results In order to check the main theoretical suppositions regarding the new structure, as well as the sinusoidal PWM strategy employed here, it would be interesting to verify the system behavior and performance by means of digital simulation. Pspice tool is used to provide simulation results considering a 3600-Wp PV array, which is inside the input power range of the most residential PV systems [2]. This arrangement is composed by the model of thirty BP SX-120 PV modules, which has these Pspice modeling described in [12]. It has been considered an insolation condition of 1000 W/m and the modules temperature of 25 C. Regarding this kind of photovoltaic module physical dimensions, in a real situation, this array would ll around 30 m of a house roof. The input and balance inductors have been designed by (12) and (13) and were chosen as 60 mH and 9.3 mH, respectively. Output lter elements were selected as 15 F 800 H and 2.2 . The other simu127 V, 60 Hz, 3 kHz, lation parameters were: 1000 F and 0.9. Diodes and active switches were modeled by means of conventional PSpice models. Fig. 8 shows the most important simulation results. A practically sinusoidal current, with a very small phase displacement in relation to the line voltage, is injected into the grid, as shown in Fig. 8(b). The total harmonic distortion of this current was 4.79 %, with a phase displacement of 5.7 in respect to the line voltage, resulting in a high power factor operation of the system (0.9939 in this case). Moreover, the simulation results comply with IEEE Std. 929-2000, regarding current harmonic distortion. Fig. 8(c) and (d) also show that the input current (which is close to 40 A) is well distributed among semiconductor devices, which is an expected feature of the current multilevel concept. It can be observed that the current synthesized at inverter output (before ltering) agrees with the theory: it is a ve-level waveformFig. 8(a)and its harmonic spectrum presents the

Fig. 9. Harmonic spectrum of the ve-level current waveform.

switching harmonics around 6 kHz, i.e., twice the switching frequencyas depicted in Fig. 9. These results provide strong evidences about the practical feasibility of the proposed system. Further proofs come from experimental results obtained by means of a small-scale system prototype, which is described in Section II-C. C. Small-Scale Prototype A 360-Wp prototype concerning the two-cell boost CML inverter has been developed in laboratory. Specication of the main components of the system is shown in Table I. It is important to comment that the input and balance inductors, MOSFETs and diodes are oversized due to the laboratory components availability. The dc-to-dc converter switching frequency, , has been chosen as 3 kHz in order to achieve low switching losses, while the switches of the inverter bridge are commutated at line frequency, i.e., 60 Hz. It is interesting to observe that, for higher power levels, the LC output lter should be redesigned in order to reduce the inductor physical volume and resistive losses. A lter like the

BARBOSA et al.: BOOST CURRENT MULTILEVEL INVERTER

Power Electronics-059

1121

Fig. 10. Modulation and gating circuitry.

TABLE I POWER CONDITIONER COMPONENTS

one employed in the simulation case study of Section II-B could be employed. A complete schematic diagram regarding the modulation and and were gating circuitry is shown in Fig. 10. Switches driven by means of IR2104 IC using its inverting output (LO), what is referenced to the logic circuit ground. On the other and ) hand, the inverter bridge switches ( were driven by means of a magnetic-coupled driver. The commutation of these switches occurs at line voltage zero-crossing, when the current synthesized by the dc-to-dc converter is null. So, it is not necessary to avoid a simultaneous blocking of the switches of a same inverter leg, as required for conventional current-source inverters. This feature considerably simplies the pulse logic. As can be noticed, the system operates in open-loop, since no control strategy has been adopted at this time. However, the laboratory prototype is still useful to provide practical concerns about the new converter and the employed PWM strategy. A closed-loop control system, e.g., to track the point of maximum power of the PV source, will be object of future publications. A picture of the laboratory prototype is presented in Fig. 11. The most important waveforms measured in the prototype are shown in Figs. 1216. These measurements have been acquired in a variable insolation day, what can imply in a slight divergence among some waveforms, since they have not been stored

Fig. 11. Laboratory prototype picture (input and balance inductors are oversized due to previous lab availability).

with rigorous simultaneity. However, it does not result in inconsistence, and neither does it invalidate the main conclusions. A balanced current distribution between CML boost active switches can be observed in Fig. 12. The current equilibrium regarding main inductive elements can be also evidenced by means of Fig. 13 (measurements have shown that experimental inductor currents do not differ more than 3% from theoretical ones). As can be noticed from the upper trace of Fig. 13, the current ripple of input inductor is higher than the balance inductor one. Due to a natural characteristic of the CML cell, this and diode (see Fig. 12). ripple is transferred to switch Fig. 16 highlights the low displacement between the synthesized currenteffectively injected into the gridand the line voltage. Actually, a lag of 3.9 has been registered between the fundamental output current and line voltage. A current THD equal to 4.62% around the rated inverter output has also been achieved. It implies a high power factor operation (PF 0.9966). Moreover, the proposed system has been able to meet IEEE Std. 929-2000 requirements, regarding current harmonic distortion. An evaluation of output current THD, for different output power levels, is shown in Fig. 17. It is possible to observe a THD

1122

Power Electronics-059

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006

Fig. 13. Input and balance inductors currents (1 A/div; 5 ms/div).

Fig. 12. CML boost dc-to-dc converter switches and diodes currents (1 A/div; 2 ms/div).

Fig. 14. Five-level current waveform (inverter output current, before ltering): 2 A/div; 5 ms/div.

lower than 10% around one third of the nominal inverter rating, i.e., 120 W. A THD lower than 5% can be attained at nominal power. Fig. 18 depicts the measured efciency of the structure for several points of operation. As shown, at maximum output power, the efciency reached a mark close to 93.2%, what agrees with theoretical calculations and is not so far from conventional photovoltaic power processing systems. As stated before, negligible switching losses occur for this system, due to the low switching frequency employed. It is important to notice that more efcient transformerless PV converterswith efciencies above 96%have been reported in recent literature [16]. In the present case, the main causes of system losses are related to parasitic elements of inductors, line-lter damping resistor and semiconductor conduction losses. In order to achieve

a higher system efciency, those sources of losses could be minimized by means of lter and inductors design optimization and better semiconductor devices selection. However, at higher power levels, it is not expected a system efciency greater than losses of inductors increase signicantly. A 90%, since higher efciency (and even compact solution) is theoretically possible and could be achieved by using high temperature superconducting (HTS) coils [17]. Of course, economic issues may arise, since HTS inductors need additional cryo-refrigerator systems. III. CONCLUSION This paper presented the application of the current multilevel technique to grid-connected PV systems, which was made by

BARBOSA et al.: BOOST CURRENT MULTILEVEL INVERTER

Power Electronics-059

1123

Fig. 17. Evaluation of output current THD.

Fig. 15. Five-level waveformzoomed view: 2 A/div; 2 ms/div.

Fig. 18. Measured system efciency.

Fig. 16. Line voltage (50 V/div; 5 ms/div) and current injected into the grid (2 A/div; 5 ms/div).

means of a novel CML single-phase inverter topology. Some mathematical expressions for this topology have been presented in order to provide design guidelines for the circuit components. Experimental waveforms and measured parameters, obtained from a small-scale lab prototype, have been used to validate the proposed theoretical concepts and the feasibility of the application of the CML technique on grid-connected PV systems. The proposed system presented a good performance concerning efciency and power quality. The latter is evidenced by the compliance with IEEE Std. 929-2000, regarding current harmonic distortion. In addition to these features, a natural short-circuit protection and a balanced current sharing among the switches of the dc-to-dc converter has been also achieved, which is an inherit characteristic of a CML converter. The results presented here constitute a very important step in the study of the CML converter and its applications, because it

provides evidence of the robustness and reliability of the proposed system. The authors believe that such advantages may be of interest to PV system designers, although a reduced efciency in very high power levels has been predicted. This drawback is mainly related to the present technological limitations regarding practical high-power inductors, which could be solved in the near future by means of economic lossless inductors. Future works include the development of a DSP-based maximum power point tracking (MPPT) system and the application of the CML boost inverter to reactive power compensation and other energy source setups, such as fuel cell systems. REFERENCES
[1] P. Fairley, BP solar ditches thin-lm photovoltaics, IEEE Spectrum, vol. 40, no. 1, pp. 1819, Jan. 2003. [2] B. Kroposki and R. de Blasio, Technologies for the new millenium: Photovoltaics as a distributed resource, in Proc. IEEE Power Eng. Soc. Summer Meeting, 2000, pp. 17981801. [3] Recommended Practices for Utility Interface of Photovoltaic Systems, IEEE Std. 929-2000, 2000. [4] Static Inverters and Charge Controllers for Use in Photovoltaic Power Systems, Std. UL Subject 1741, 2005. [5] M. Calais, J. Myrzik, T. Spooner, and V. G. Agelides, Inverters for single-phase grid connected photovoltaic systemsAn overview, in Proc. IEEE 33rd Power Electron. Spec. Conf. (PESC02), 2002, vol. 4, pp. 19952000.

1124

Power Electronics-059

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 21, NO. 4, JULY 2006

[6] S. B. Kjaer, J. K. Pedersen, and F. Blaabjerg, power inverter topologies for photovoltaic modulesA review, in Proc. 37th IEEE Ind. Appl. Soc. Conf. (IAS02), 2002, pp. 782788. [7] M. C. B. Rodrigues, E. C. Teixeira, and H. A. C. Braga, Uma viso topolgica sobre sistemas fotovoltaicos monofsicos conectados rede de energia eltrica, in Proc. 5th Latin-Amer. Congress: Eletr. Gen. Transm. (5th CLAGTEE), Nov. 2003, [CD ROM]. [8] H. A. C. Braga and I. Barbi, A new technique for parallel connection of commutation cellsAnalysis, design and experimentation, in Proc. IEEE PESC95, 1995, pp. 8186. [9] H. A. C. Braga and I. Barbi, Current multilevel DC-DC converters, in Proc. III Brazilian Power Electron. Conf. (COBEP95), So Paulo, Brazil, 1995, pp. 417422. [10] H. A. C. Braga, F. M. Antunes, and I. Barbi, Application of a generalized current multilevel cell to current-source inverters, IEEE Trans. Ind. Electron., vol. 46, no. 1, pp. 3138, Feb. 1999. [11] E. C. Teixeira and H. A. C. Braga, A high power factor single-phase rectier based on a current multilevel buck converter, in Proc. 6th Brazilian Power Electron. Conf. (COBEP01), Florianpolis, Brazil, Nov. 2001, pp. 180185. [12] M. C. B. Rodrigues, Inversor Boost Multinvel em Corrente e sua Aplicao no Processamento de Energia em Sistemas Fotovoltaicos Monofsicos Conectados Rede Eltrica, M.E.E. thesis, Federal Univ. Juiz de Fora (UFJF), Juiz de Fora, MG, Brazil, 2004. [13] P. G. Barbosa, Compensador Srie Sncrono Esttico Baseado em Conversores VSI Multipulso, D.Sc. dissertation, Federal Univ. Rio de Janeiro (COPPE-UFRJ), Rio de Janeiro, Brazil, 2000. [14] N. Mohan, T. M. Undeland, and W. P. Robbins, Power Electronics: Converters, Applications, and Design, 2nd ed. New York: Wiley, 1995. [15] R. Redl and L. Balogh, Power-factor correction with interleaved boost converters in continuous-inductor-current mode, in Proc. IEEE APEC93, 1993, pp. 168174. [16] K. Ogura, T. Nishida, E. Hiraki, M. Nakaoka, and S. Nagai, Time-sharing boost chopper cascaded dual mode single-phase sinewave inverter for solar photovoltaic power generation system, in Proc. 35th IEEE Power Electron. Spec. Conf. (PESC04), Aachen, Germany, 2004, pp. 47634767. [17] E. Schempp and C. Russo, Application of high-temperature superconducting coils as inductors in switching power supplies, IEEE Trans. Appl. Supercond., vol. 3, no. 1, pp. 563565, Mar. 1993.

newable energy sources, active power lters, and static power compensators for FACTS applications.

Henrique Antonio Carvalho Braga (S83M88 SM01) was born in Aimores, Brazil, in 1959. He received the B.S. degree in electrical engineering from the Universidade Federal de Juiz de Fora (UFJF), Juiz de Fora, Brazil, in 1982, the M.Sc. degree in electrical engineering from Coordenacao de Programas de Pos-Graduacao (COPPE), Federal University of Rio de Janeiro, Rio de Janeiro, Brazil, in 1988, and the Dr.Eng. degree from the Universidade Federal de Santa Catarina, Florianopolis, Brazil, in 1996. Since 1985, he has been teaching basic electronics and power electronics at UFJF in undergraduate and graduate levels (Masters program was installed in 1999). He has also served as the head of the Electrical Circuits Department, Electrical Engineering Undergraduate Program Coordinator, and Electrical Engineering Master Program Coordinator, UFJF. He has been a Reviewer of technical papers for several conferences and scientic journals, and has authored or coauthored of more than 50 publications, during the past 10 years. From 20052006, he will be on leave for a post-doctoral stage at Universidad de Oviedo, Gijon, Spain. His research interests are mainly related to the power electronics eld, including multilevel converters, Pspice modeling of power electronics circuits and devices, active power lters, high power factor rectiers, photovoltaic conversion systems, energy-efcient lighting.

Mrcio do Carmo Barbosa Rodrigues (S98) was born in Cataguases, Brazil, in 1978. He received the B.S. and M.S. degrees in electrical engineering from the Federal University of Juiz de Fora (UFJF), Juiz de Fora, Brazil, in 2002 and 2004, respectively. In 2005, he joined the Department of Electrical Engineering, UFJF, where he taught analog and digital electronics for undergraduate courses. He is now with CEFET-MG, Leopoldina, Brazil. His main research interests includes renewable energy systems, power converter control, active power lters, and power quality.

Pedro Gomes Barbosa (S94M00) was born in Juiz de Fora, Brazil, in 1962. He received the B.S. degree in electrical engineering from the Federal University of Juiz de Fora (UFJF), Juiz de Fora, Brazil, in 1986, and the M.Sc. and the D.Sc. degrees in electrical engineering from Coordenacao de Programas de Pos-Graduacao (COPPE), Federal University of Rio de Janeiro, Rio de Janeiro, Brazil, in 1994 and 2000, respectively. From 1987 to 1992, he was a Commissioning Engineer with the Brazilian Navy. Since 1999, he has been teaching power electronics and electric machine and drives at the Federal UFJF. His main research interests are multilevel and multipulse converters, re-

Estvo Coelho Teixeira (S01M03) was born in So Paulo, Brazil, in 1974. He received the B.S. and M.S. degrees in electrical engineering from the Federal University of Juiz de Fora (UFJF), Juiz de Fora, Brazil, in 1998 and 2002, respectively, and is currently pursuing the Ph.D. degree in electrical engineering at Coordenacao de Programas de Pos-Graduacao (COPPE), Federal University of Rio de Janeiro, Rio de Janeiro, Brazil. From 2003 to 2004, he lectured on digital and analog electronics at UFJF. He is now with is with COPPE-UFRJ, Rio de Janeiro, Brazil. His research interests are power converters, microprocessors, and eld programmable gate arrays.