ISSCC 2001 / SESSION 13 / Wireless LAN / 13.

13.1

A Fully-Integrated Single-Chip SOC for Bluetooth

Frank Opt Eynde1, Jean-Jacques Schmit1, Vincent Charlier1, Rudolph Alexandre1, Charles Sturman2, Kevin Coffin1, Bruno Mollekens1, Jan Craninckx1, Steven Terrijn1, Andrea Monterastelli1, Sofie Beerens1, Paul Goetschalckx1, Mark Ingels1, Dieter Joos1, Selim Guncer3, Ared Pontioglu3 Alcatel Microelectronics, Zaventem, Belgium TTP Communications, Melbourne, UK 3 Alcatel Microelectronics Teletas, Istanbul, Turkey
2 1

13.1.2) which also manages the Bluetooth clock offset application and re-synchronization. Synchronization and recognition of a valid access code (which initiates the receive function in the baseband controller) is by the RX-correlator block. The Audio Subsystem has a link to the Dual-Port buffer memory and a link to the microprocessor interface. This allows Bluetooth-specific speech over Host Controller Interface as well as a standard PCM-dedicated speech interface. The latter is more optimum for low-latency applications such as in a cellular terminal. In general, the Dual-Port RAM contains just enough information for the Baseband Core to operate during the next timeslot pair Rx-Tx or Tx-Rx. It is the responsibility of the LC state machine software to download just enough control information at the appropriate point to sustain the system. This is achieved by programming the next packet header and control information during transmission of the current packet. The analog radio front-end block schematic is shown in Figure 13.1.3. Since the Bluetooth specification [1] requires a receiver image rejection of only about 20dB, this image rejection is obtained fairly easily with a classical image-reject mixer, followed by a polyphase filter. The receiver intermediate frequency is 1MHz. With 15dB overall receiver noise figure, the sensitivity is 80dBm. This is 10dB better than the specification requirement. The differential LNA is realized with a common-gate architecture, as shown in Figure 13.1.4. Transistor M1 and resistor R1 form an amplifier stage, with a gain equal to gm1R1, and with an input impedance 1/gm1. The transconductance of transistor M1 is boosted by a second gain stage, formed by M2 and resistor R2. In this way, total LNA gain and input impedance are: A = gm1 R1 (1+ gm2 R2) and Zin = 2 gm (1+ gm R ) 1 2 2 For the transmitter, direct conversion is used. Image rejection and carrier feedthrough are improved by on-chip digital calibration. The calibration words are determined during factory testing, and stored in the Flash memory. The Transmitter Power Amplifier is integrated on-chip, and delivers up to +2dBm into a symmetrical antenna of 75W. The synthesizer is also fully integrated. The PLL is built around an integrated VCO, running at double the Local Oscillator frequency (4.8 to 5.0GHz). In this way, the parasitic coupling between PA and VCO is reduced. Furthermore, the VCO frequency divider (/2 in Figure 13.1.3) immediately provides the two quadrature LO signals. To compensate for process variations, a coarse digital VCO frequency autocalibration is integrated, in the same way as in Reference 2. The circuit is realized in a 0.25m CMOS technology and occupies a 40 mm2 die. A die micrograph is shown in Figure 13.1.5. About 50% of the chip area is occupied by the 48kB of Data RAM. The process features standard digital nMOS and pMOS transistors and an analog extention to realize resistors and metal-insulator-metal capacitors. Furthermore, additional process layers are included, to realize the Flash memory. A summary of the circuit specifications in given in Table 13.1.1. In normal operation, the Flash is seen by the processor as a ROM, without write access. The memory content is programmed by the foundry during device production test. Device-specific data such as the device serial number or calibration data for the radio are also pre-programmed. The Flash memory can also be re-programmed in the field: at power-up, a boot routine from a BootROM is executed by the microprocessor. Two dedicated pins are used to select the loading of a new program, either from the UART or from the SPI interface. An on-chip crystal oscillator provides the 13MHz reference clock for the RF frontend (Figure 13.1.6). By means of a bank of integrated capacitors, the crystal frequency can be slightly tuned. The tuning control word is stored in the Flash memory. The required frequency precision of 20ppm can be obtained with a low-precision quartz.

Market price targets for Bluetooth call for a low-cost integration of the full Bluetooth modem function. This single-chip Bluetooth implementation contains all necessary analog and digital functions for a fullfledged implementation of the V.0.1.b. Bluetooth specification [1], including point-to-multipoint communications, seven simultaneous links, multislot packets, encryption, master-slave switch, scatternet, etc. The circuit is built around four basic building blocks, as shown in Figure 13.1.1: a) The heart of the circuit is formed by an embedded microprocessor system (Processor, 48kB of RAM, 256kB Flash, BootROM in Figure 13.1.1). Parts of the physical layer protocol are executed by software on this microprocessor. All software layers up to the Host Control Interface are implemented. Since the software is stored in an on-chip Flash memory, it can be easily adapted towards future modifications of the Bluetooth standard, or towards specific customer needs. b) Dedicated Digital Baseband Processor hardware is foreseen for the time-critical parts of the Bluetooth physical layer protocol. c) An RF analog frontend is integrated on the chip. d) Several digital audio and data interfaces (Voice, UART and SPI in Figure 13.1.1) are included in the circuit. These interfaces are highly reprogrammable. In this way, the integration of the IC in an overall system is facilitated. Furthermore, theer are 12 general-purpose IO pins (GPIO in Figure 13.1.1). This allows interfacing the IC to external devices such as a display or a keyboard. The IC is primarily intended to serve as a Bluetooth modem for data and/or voice. However, spare Flash memory space is available for customer applications. Hence, complete Bluetooth applications (such as a Bluetooth mouse, for instance) can be realised as true single-chip systems. The Digital Baseband Core, as depicted in Figure 13.1.2, forms the lowest layer of the Link Controller function within the Bluetooth system. The hardware Baseband Core is complemented by a C-coded Bluetooth protocol stack. The lowest layer of this software is the Link Control state machine, which directly controls the hardware baseband processor. Together, the Link Control (LC) state machine software and the baseband processor device form the LC part of the Bluetooth protocol stack. The internal architecture of the Baseband processor is centered around a dual-port RAM buffer memory of 8kB, serving as data interface between the hardware Baseband Core and the microprocessor. For each active communication, the data stream is stored in this RAM. Also stored in this RAM are the encryption keys for each active link and all the context information such as active member address, packet type and encryption key selection ID. The bitstream Data Path performs all the required data processing such as Forward Error Correction, CRC calculation and Data Whitening. It is controlled directly by the Baseband State Controller. In this State Controller, the packet header is assembled from the link context information. This header is appended to the appropriate payload data stream from the Dual-Port RAM. The resulting packet is applied to the Data Path for bit-level data processing. The State controller interfaces with the software Link Control Interrupt Service Routine via the link context information in RAM. Sequencing of all baseband operations, such as header and payload assembly and radio interface timing, is by a Timing engine (Figure

2001 IEEE International Solid-State Circuits Conference

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ISSCC 2001 / February 6, 2001 / Salon 7 / 1:30 PM

The digital baseband processor and microprocessor operate using a 26MHz clock obtained from an on-chip PLL. An optional 32kHz crystal can be connected to the IC. This allows turning off the 13MHz clock while still maintaining the Bluetooth clock with the benefit of lower power consumption. The presence of the optional 32kHz crystal is detected automatically. The overall circuit development cycle was shorter than 18 months, achieved using concurrent engineering wherever possible. When the project started, neither the silicon technology nor the package were available. Furthermore, the Bluetooth specification was still in evolution. Parallel teams worked on technology development, silicon parameter extraction, package engineering, digital design, software design and analog front-end design.
References: [1] The Bluetooth Special Interest group, The Bluetooth specification V.1.0.b. [2] J. Craninckx et al., A Fully-Integrated Zero-IF DECT Transceiver, ISSCC Digest of Technical Papers, pp. 138-139, Feb. 2000.

Table 13.1.1: Major circuit specifications.

Figure 13.1.2: Baseband processor block diagram.

Figure 13.1.1: Bluetooth SOC block diagram.

Figure 13.1.3: RF frontend block schematic.

2001 IEEE International Solid-State Circuits Conference

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Figure 13.1.4: Low-noise amplifier schematic.

Figure 13.1.5: Die micrograph.

Figure 13.1.6: Tunable crystal oscillator.

2001 IEEE International Solid-State Circuits Conference

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