International Journal of Advanced Computer Science, Vol. 2, No. 9, Pp. 343-347, Sep., 2012.

Manuscript
Received:
20,Sep., 2011
Revised:
21,Mar.,2012
Accepted:
27,Apr.,2012
Published:
15,Oct., 2012

Keywords
Common
mode voltage,
Four-level
inverter,
PWM,
SVM

Abstract It is well known that pulse
width modulated (PWM) inverters generate
common-mode voltages. Common mode
voltages may cause motor shaft voltages and
bearing currents and conducted
electromagnetic interference (EMI). It is
shown that inverters which have an odd
number of levels can generate zero common
mode voltage by switching among certain
states. But inverters which have an even
number of levels have no switching states
with zero common mode voltages. So in these
inverters achieving elimination of common
mode voltages is impossible. This paper
proposed a new modulation strategy to
reduce common mode voltage in modular
multilevel inverters. The main idea of the
proposed method is based on the restriction
of space vectors to vectors with minimum
common mode voltage. This scheme almost
has a good linear relationship and can be
easily extended to a 2n level inverter.

1. Introduction
Nowadays, multilevel voltage source inverters offer
several advantages compared to their conventional
two-level inverters. In these inverters, by synthesizing
several levels of dc voltages, the staircase output waveform
is produced. The structure of this waveform will have lower
total harmonic distortion which leads to an approach to a
desired sinusoidal waveform. Achieving higher output
voltage and lower stress on power switches are other
advantages of these inverters. But in multilevel inverters the
problem of common mode voltage generation which had
been found in conventional two level inverters can still be
considered as a major issue. [1-3].
This voltage enables motor shaft voltage to build up
through electrostatic couplings between the rotor and the
stator windings and between the rotor and the frame,
resulting in excessive bearing currents when the shaft
voltage exceeds the dielectric capability of the bearing
grease. It has been found that bearing currents may cause
premature motor bearing failures. This problem in
inverter-fed ac machines has been studied in the last number
of years [1, 2].
Some solutions are based on additional hardware, like
lters and other methods are based on more advanced
modulation strategies which avoid the generation of
common-mode voltages [4-6]. So far various pulse-width
modulation (PWM) techniques to control multilevel
inverters have been studied. Among these, SVM is the most
popular one due to its simplicity both in hardware and
software, and its relatively good Performance at low
modulation ratio [7].
Using SVM in multilevel inverters that have an odd
number of levels, because of switching states with zero
common mode voltage, results in elimination of common
mode voltages [4].
2. Power Circuit Topology
Figure 1 shows a four level diode-clamped inverter. An
n-level inverter uses 2(n-1) power switches per leg, and the
blocking voltage of each switch is equal to the DC-link
voltage divided by (n-1).


Fig. 1. Four-level inverter circuit design
So in figure 1 each arm of the four-level inverter
consists of six switching devices and the blocking voltage
of each switching device is one-third the DC voltage
(
3
d
E
). Each arm of the inverter can be clamped to the DC
terminals P, A, B, N as shown in Table 1.
In an n-level inverter only (n-1) switches can
simultaneously be on, so in this inverter the number of these
switches is 3. The combinations of the three-phase output
Reduction of Common-Mode Voltage in an Even
Level Inverter by a New SVM Method
Nasim Rashidi-rad, Abdolreza Rahmati, Adib Abrishamifar, & Mohammad Arasteh
International Journal of Advanced Computer Science, Vol. 2, No. 9, Pp. 343-347, Sep., 2012.
International Journal Publishers Group (IJPG)

344
voltages result in 64 switching states ( )
3
4 . Considering Fig.
1, where
UO
V ,
VO
V and
WO
V are the voltages of
terminals U, V and W with respect to the neutral point (O),
common mode voltage is defined as:
( ) 3 /
WO VO UO com
V V V V + + = (Equ. 1)

Since the common-mode voltage is defined as Equ. 1,
it cannot be zero for none of its switching states as shown in
Table 1 [4, 8-10].
Therefore in inverters which have an even number of
levels, modulation strategies which are based on switching
states with zero common mode voltages cannot be applied.
TABLE 1
SWITCHING STATES OF EACH ARM
DC
Terminals
SX1 SX2 SX3 SX4 SX5 SX6 Arm
Voltage
P On On On Off Off Off
d
E
A Off On On On Off Off
d
E 3 2
B Off Off On On On Off
d
E 3 1
N Off Off Off On On On
0

3. Proposed Modulation
Algorithm
One simple strategy to eliminate or reduce common
mode voltage in multilevel inverters has been introduced in
[1, 11]. The main idea of these strategies is to deliver the
nearest voltage vector with respect to the reference
vectorVref .
In the case of even levels, due to absence of switching
states with zero common mode voltages, this strategy can be
applied with switching states which have minimum
common mode voltages. This strategy is named reference
method.
This restriction of vectors increases the distance
between reference vector and the vectors of space vector
diagram. In other words the error of the generated voltage
with respect to the reference will increase. Considering
figure 3, it can be easily observed that this strategy doesnot
have a linear relationship between fundamental voltage
and modulation index, which is unfavorable. Furthemore, as
shown in figure 3, another disadvantage of the reference
method is related to its nonzero fundamental voltage at low
modulation indexes that is the result of zero state absence.
This paper proposed a new modulation scheme for a
2n level inverter. In the proposed scheme only vectors with
minimum common mode voltage which are shown in figure
2 are used. Based on the voltage vectors arrangement shown
in figure 2, Sectors can be divided into two sets. As shown
in figure 4, the categories are: odd sectors which are 40
degree, and even sectors which are 20 degree. Considering
figures 2 and 4, all vectors in space vector diagram of the
four level inverter are active vectors, and there is no zero
vector. Similar to 60 degree coordinate systems, in 20 or 40
degree systems, containing zero voltage vector is a
prerequisite for synthesized voltage vectors to be a good
approximation of the reference voltage vector.
-3 -2 -1 0 1 2 3
-3
-2
-1
0
1
2
3
211
221 121
122
112
031
032
023
013
103 203
302
301
310
320
230 130
212

Fig. 2. representation of voltage vectors that are used in the proposed
scheme
In this paper, the main idea to create an effective zero
state, is based on utilizing two, four or six opposing active
voltage vectors. It should be noted that to create this state,
dwell times of these opposing active voltage vectors should
be equal.
For example by utilizing only two opposing active
vectors in sector 1, V1 and V4 provide effective zero state.
Also two opposing active voltage vectors for sector 2 (even
sectors) are similar sector 1 ( adjacent odd sectors).
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.5
1
1.5
2
2.5
3
Index Modulation
a
1


using nearest vectors
ideal

Fig. 3. Fundamental voltage (a1) versus modulation index (m) in a
four-level inverter (
v
E
pu
d
200
3
1 = =
)
Employing the effective zero state and depending on
the number of sector,

40 or

20 coordinate system similar
to

60 coordinate system [7, 12] will be utilized.

Equations for odd sectors:
Nasim Rashidi-rad et al.: Reducing Common-Mode Voltage in an Even Level Inverter by a Novel Modulation Method.
International Journal Publishers Group (IJPG)

345
)
40 tan
) 40 sin(
) 40 (cos(
)
40 tan
sin
(cos

u
u
u
u
|
o

=
=
V V
V V
(Equ. 2)
And equations for even sectors:
)
20 tan
) 20 sin(
) 20 (cos(
)
20 tan
sin
(cos

u
u
u
u
|
o

=
=
V V
V V
(Equ. 3)
-3 -2 -1 0 1 2 3
-3
-2
-1
0
1
2
3
sector 7
sector 5 sector 3
v1
v3 v2
v4
v5
v6
sector 1
sector 2
sector 4
sector 6
sector 8
sector 9 sector 11
sector 12
sector 10

Fig. 4. Representation of sectors in space vector diagram
Two vectors composing each sector will also be as the
axes which are known as o and | . So
o
V and
|
V are
the coordinates of a space vector in the

20 or

40
coordinate system.
To achieve simpler calculations, all of odd and even
sectors should be mapped respectively to regions
) 40 0 (

and ( ) 20 0

. So o axis is always the
horizontal axis. V and u are respectively the amplitude of
reference vector and phase angle between reference vector
and o axis in each sector.
To calculate dwell times of vectors, volt-second
balancing principle is used. So according to this principle:
s vector active
T
V
T =
3
1
o
(Equ. 4)
s vector active
T
V
T =
3
2
|
(Equ. 5)
2 1 vector active vector active s vectors zero
T T T T = (Equ. 6)

Calculation of dwell times for each of opposing active
vectors depends on the number of these vectors. Therefore
the equation for two opposing active vectors is:
2
2 sin 1 sin
vectors zero
vector active g oppo vector active g oppo
T
T T = = (Equ. 7)

And also the equation for dwell times of six opposing
vectors is:
6
sin
vectors zero
vector active g oppo
T
T = (Equ. 8)
When we consider a power switch as an ideal switch,
that means the switch can handle unlimited current and
blocks unlimited voltage. The voltage drop across the
switch and the leakage current through the switch are
considered zero with no rise and fall times as shown in Fig.
5.
But in real case, ideal switches do not exist and during
switching transients, there are significant losses associated
with dv/dt and di/dt [13, 14].
As we know a modern power electronic system is a power
processing system based on a Modulation technique.
Therefore a comparative study (about these issues) among
the proposed and reference methods needs to be necessary.
It should be noted that these issues lead to more problems in
the proposed method compared to the reference method.
The first problem is related to switching losses that will be
more in the proposed method with respect to the reference
method, and the second problem is related to restriction of
proposed method to high modulation indexes. These
problems will be considered in the next sections.


Fig. 5. Voltages and current waveforms in an ideal switch

A. High Switching Losses
When a switch is turned on or off, energy is lost during
the switching transients. This type of energy loss is called
switching loss of the power switch and it depends on
voltage across the switch, current through the switch and the
switching time.
In the reference method maximum number of
switching per PWM cycle will be limited to the total
number of voltage vectors in the space vector diagram.
International Journal of Advanced Computer Science, Vol. 2, No. 9, Pp. 343-347, Sep., 2012.
International Journal Publishers Group (IJPG)

346
While in the case of the proposed method, because of
estimation using four active vectors (utilizing only two
active vectors to create zero state) at each sampling instance,
this value will be much higher. Therefore it can be
concluded that during one PWM cycle, switching and
consequently switching times of the proposed method will
be more than the reference method, which will lead to more
switching losses.
Therefore utilizing more than two opposing active
vectors to create a zero effective state (in spite of better
simulation results) is not recommended.
B. Recommended Modulation Indexes
In the calculations of proposed method, power
switches have been considered as ideal switches. But as we
know in real case, power switches have rise and fall times in
the scale of microseconds.
Furthermore at low modulation indexes, specified
dwell time of the zero state will increase and therefore lead
to decrease dwell times of active vectors. So it can be
concluded that at very low modulation indexes the dwell
times of active vectors will be very short and even may be
in the scale of rise and fall times of switches. Therefore this
modulation method is not recommended at low modulation
indexes.
Similarly, due to possibility of short dwell time of the
effective zero state, using six active opposing vectors can
lead to decrease dwell times of each opposing vector in the
scale of rise and fall times of switches. Therefore utilizing
more than two opposing vector to create a zero state is not
recommended.
4. Simulation Results
The waveforms of figure 6 have been measured with
m=.68 and an output frequency of 50 Hz. Switching
frequency is 5 kHz.
Relationships between fundamental voltage and
modulation index in the reference and proposed methods
have been shown in figure 7. It can be concluded that
linearity in the new modulation method is much better than
the reference method. Furthermore using more active
vectors to create a zero state leads to have a more linear
relationship. Figure 8 shows the comparison of total
harmonic distortion among proposed and reference methods.
By considering figure 8 it can be concluded that total
harmonic distortion of the reference method will be lower
than the proposed methods. Furthemore as shown in figure
8, utilizing more active vectors to create a zero state leads to
lower total harmonic distortions with respect to utilizing
less active vectors.

(a)


(b)

(c)

(d)
Fig. 6. (a) phase voltages, (b) line to line voltage, (c) common mode
voltage and (d) spectrum of line to line voltage
|
.
|

\
|
= = v
E
pu
d
200
3
1


Fig. 7. Comparsion of fundamental voltage (a1 ) versus modulation index
(m) in a four-level inverter among proposed methods and the reference
method (
v
E
pu
d
200
3
1 = =
)
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
0.5
1
1.5
2
2.5
3
Index Modulation
a1


Using nearest vectors
Using 2 active vectors
Using 6 active vectors
Ideal
Nasim Rashidi-rad et al.: Reducing Common-Mode Voltage in an Even Level Inverter by a Novel Modulation Method.
International Journal Publishers Group (IJPG)

347

Fig. 8. Comparsion of THD versus modulation index (m) in a four-level
inverter among proposed methods and the reference method
(
v
E
pu
d
200
3
1 = =
)
Considering figures 7 and 8 show that the proposed
method based on more active vectors (to create zero state)
will have better simulation results. But it should be noted
that beacause of the mentioned shortcomings (such as more
switching losses and also nonzero fundamental voltage at
low indexes), the best choice to create zero state is based on
utilizing only two opposing active vectors.
5. Conclusion
This paper proposed a new SVM scheme to reduce
common-mode voltage for inverters which have even
number of levels. This scheme will restrict the space vectors
to vectors with minimum common mode voltage. But due to
absence of a zero voltage vector, two opposing active
voltage vectors with equal dwell times will be utilized. Then
all of calculations for switching between two active and one
zero state (which is composed of two opposing active
vectors) will be done in 20 or 40 coordinate systems. This
scheme almost has a good linearity relationship between
fundamental voltage and modulation index. By modifying
this scheme it can be extended to higher even levels.

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0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
0
20
40
60
80
100
120
140
160
180
200
Index Modulation
% THD


Using nearest vectors
Using 2 active vectors
Using 6 active vectors