( (EE EE6205 6205) VLSI Design ) VLSI Design

IC fabrication process &

Layout Design Techniques
By Dr. Yaseer A. Durrani
Dept. of Electronics Engineering
University of Engineering & Technology, Taxila
Outline
IC Manufacturing Sequence
Overview of Silicon Process
Photolithography Process
Die Assembly & Testing
Layout Design Methodology
Design Rules
2
Stick Diagram
Layout Example
Wafer Manufacturing from Sand to Si
3
Si Starting material
Silicon prepared by the reaction of high-purity silica with wood,
charcoal, & coal, in electric arc furnace using carbon electrodes
at more than 1900, carbon reduces silica to silicon
SiO2 + C Si + CO2
SiO2 + 2C Si + 2CO (~1800C)
Form of metallurgical grade Si (MGS)
Si has impurities like Al, Fe & heavy metal at 100s to 1000s parts/million
MGS is further refined with electronic-grade Si (EGS): Levels of impurities are
reduced to parts pet billion or ppb 5x10
13
cm
-3
Si +3HCl SiHCl3 + H2 Si +3HCl SiHCl3 + H2
2SiHCl3+2H2 2Si+6HCl
4
Growth of Single-Crystal Ingots
Growth process of purifying silicon: It converts high purity but still polysilicon
EGS to single crystal Si ingots or boules
Heating to produce 95% ~ 98% pure polycrystalline Si
Czochralski (CZ) Growth: Main stream growth technology for large diameter
wafer
Float Zone (FZ) Growth: For small & medium diameter wafer less
contaminations than CZ method
5
Seed Crystal
A seed crystal is a small piece of single crystal/polycrystal material from which
a large crystal of same material typically is to be grown. The large crystal can
be grown by dipping the seed into a supersaturated solution, into molten
material that is then cooled, or by growth on the seed face by passing vapor of
the material to be grown over it
6
Czochralski Si Growth
To grow single-crystal material, it is necessary to have a seed which can provide
a template for growth
To melt EGS in a quartz-lined graphite crucible by resistively heating it to
melting point of Si (1412C)
Seed crystal is lowered into molten material and then is raised slowly, allowing
crystal to grows to provide a slight stirring of melt & to average out any
temperature variations that would cause in homogenous solidification of
compound semiconductors
7
Growth Control:
Pulling Speed
Rotation Speed
Final Control:
Pulling Speed
Rotation Speed
Critical Control:
Seed Crystal
First Pull
Pulling Speed
Rotation Speed
Cylindrical Ingot
Cylindrical ingot of high purity monocrystalline semiconductor, such as Si or
Ge, is formed by pulling a seed crystal from a 'melt
Donor impurity atoms, such as boron or phosphorus in case of Si, can be
added to molten intrinsic material in precise amounts in order to dope the
crystal, thus changing it into n-type or p-type extrinsic semiconductor
8
Wafer
Si IC is created on larger circular sheets of Si called Wafers
Typically 100-300mm in diameter, Thickness 0.4-0.7mm
Large Si circuit is about 1-cm on a side so that many individual circuits can be
made on a single wafer
To construct Wafer thousands of steps in manufacturing processes
Not every wafer turns out to be functional
Diameter
Wafer
Die
9
Die
Die
Die is a small piece of Si wafer upon which a given circuit is fabricated
Die cutting, or dicing, is the process of separating a wafer of multiple identical
integrated circuits into dies
10
Defective IC
IC Package
IC Package is a plastic, ceramic, laminate or metal seal that encloses the chip or
die inside. It can protect the chip from contamination or damage by foreign
material in environment
Packages are classified into two types:
Pin-through-hole packages: Pins are inserted into through-holes in board &
soldered in place from opposite side of board
Surface-mount technology: Packages have leads that are soldered directly
to metal leads on surface of circuit board
IC packaging process step:
Die attaching: Die is mounted and fixed to package or support structure
11
Die attaching: Die is mounted and fixed to package or support structure
Bonding: Creating interconnections b/w die and outside world
Encapsulated: Die being encapsulated with ceramic, plastic, metal or epoxy
to prevent physical damage
IC Package
Two types of mounting devices to Printed Wiring Boards (PWB):
Through-hole (TH) mounting:
Dual-in-line packages (DIP)
Pin-grid-array (PGA)
(Available in hermetic plastic & ceramic) (pitches: 2.54, 1.78, 1.27mm)
Surface mounting (SM)
Up to 48 terminals:
Small outline (SO) (available in plastic only)
Small Outline Package (SOP)
Shrinked Small Outline Package (SSOP)
Quad types: Chip carriers (CC) & flatpacks (available in ceramic & plastic)
12
Quad types: Chip carriers (CC) & flatpacks (available in ceramic & plastic)
Above 48 terminals: Quad types only
Leaded Plastic (PLCC), Leaded Ceramic (LDCC), Leadless Ceramic (LLCC)
(pitches: 1.37 or 0.635 mm)
IC Package
13
Wire-bonded package
IC Package
14
CAD template for positioning bonding pads
CAD template for checking adherence to wire-span
CAD template for checking the maximum
distance that wire spans over silicon. Here:
violation of the guidelines. The circle must be at
minimum tangent to the step-and-repeat
centerline (case of maximum distance) or cross it
Interconnects in high-density IC chips are formed by multilevel networks
For 90 nm CMOS process, 7/8 levels of metals. Between any two adjacent
metal levels dedicated layer called Vertical Interconnect Access (VIA) that is
used to make the necessary connection between the two metals
Through-silicon via (TSV) is VIA passing completely through silicon wafer or die
TSVs pass through silicon substrate(s) b/w active layers and/or b/w an
active layer & external bond pad
IC Package
15
IC Package
Good chips are
attached to a lead
frame package
Good chips are
attached to a lead
frame package
16
Lead frame
Gold wire
Bonding pad
Connecting pin
IC Package
17
IC Package
Dual in-line package (DIP) Quad flat package (QFP) Small outline (SQIC)
18
Small outline J-leaded (SOJ)
Plastic leadless chip carrier (PLCC)
Thin small outline package (TSOP)
Pin grid array (PGA)
Ball grid array (BGA)
IC Package
19
Multi-chip module (MCM) is a specialized electronic package where multiple ICs,
semiconductor dies or other discrete components are packaged onto unifying
substrate, facilitating their use as single component (as though larger IC)
MCM packaging is an important facet of modern electronic miniaturization &
micro-electronic systems. MCMs are classified according to the technology used
to create the HDI (High Density Interconnection) substrate
Laminated MCM (MCM-L): Substrate is a multi-layer laminated PCB
Deposited MCM (MCM-D): Modules are deposited on base substrate using
thin film technology
Multi-Chip Module
20
thin film technology
Ceramic substrate MCM (MCM-C): Such as LTCC
Oxidation
Etching
Ion
Implantation
Diffusion
Chemical
Layout Mask
IC Processing Flow
21
Chemical
Vapor Deposition
Wafers
Fabrication
Processed
wafer
Chips
IC Processing Flow
Materials IC Fab
Test
Packaging
Thermal
Etch
Metallization
Dielectric
deposition
Wafers
Chemical
Mechanical
Polishing
22
IC Design
Masks
Final Test
Thermal
Processes
Photo-
lithography
Etch
PR strip
Implant PR
strip
Implant PR
strip
Front-end processing refers to formation of transistors directly on silicon
Back-end processing is the creation of metal interconnecting wires, which are
isolated by insulating materials, to connect the transistor formations
Silicon Crystal Growth
Wet Cleaning
Photolithography
Ion Implantation
Dry, Wet Plasma Etching
Thermal Treatments (Rapid Thermal
Front End
Device
Fabrication
Front End
interconnection
Metallization
Front End/Back End Fabrication
23
Thermal Treatments (Rapid Thermal
Annealing, Furnace Annealing, &
oxidation)
Chemical Vapor Deposition
Physical Vapor Deposition
Molecular Beam Epitaxy
Electrochemical Deposition
Metallization
Chemical Mechanical Planarization
Wafer Testing
Wafer Back Grinding
Wafer Mounting
Die Cutting
Si Thermal
Oxidation
Lithography
Etching
Doping
Gate Oxide
Formation
Metallization
Inter-level
Dielectrics
Deposition
Gate Oxide
Formation
IC Processing Flow
Electronic circuits are fabricated with sequence of multiple photographic &
chemical processing steps
Semiconductor fabrication processes are grouped into four general categories:
Deposition:
Deposition is any process that grows, coats, or transfers a material onto the
wafer. Available deposition technologies are:
Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD),
Electrochemical Deposition (ECD), Molecular Beam Epitaxy (MBE),
Atomic Layer Deposition (ALD)
Removal:
24
Removal:
Removal processes are techniques for removing material from wafer either
in bulk or selectively
Primary removal methods are wet & dry etching, ChemicalMechanical
Planarization (CMP)
Patterning: Series of processes that pattern or alter existing shape of deposited
materials is called lithography
IC Processing Flow
Si-substrate
(a) Silicon base material
Photoresist
SiO
2
SiO
2
Si-substrate
Si-substrate
Hardened resist
Chemical or plasma
etch
25
Si-substrate Si-substrate
(b) After oxidation and deposition
of negative photoresist
(c) Stepper exposure
UV-light
Patterned
optical mask
Exposed resist
Si-substrate
SiO
2
SiO
2
(d) After development and etching of resist,
chemical or plasma etch of SiO
2
(e) After etching
(f) Final result after removal of resist
Hardened resist
Total Light
Intensity
Total Light
Intensity
Phase shift
coating
Normal Mask
Phase Shift Mask
Destructive
Interference
Constructive
Interference
IC Processing Flow
26
Substrate
PR
Substrate
PR
Final Pattern
Designed Pattern
Substrate
PR
Designed Pattern
Substrate
PR
Final Pattern
Interference
Modifying Electrical Properties:
Consists of doping a transistors source & drain in diffusion furnaces or by
implanting it with ions
Doping processes are followed by furnace annealing or Rapid Thermal
Annealing (RTA), which activates the implanted dopants
Modification of electrical properties includes the reduction of dielectric
materials via ultraviolet light
IC Processing Flow
27
Rapid Thermal Annealing
IC Processing Flow
Oxidation: High-temperature exposure of Si to O2 to form SiO2
Etching: Removal of undesired material to create geometric patterns
28
Diffusion: Doping process to form n-type or p-type material by high-
temperature exposure to donor or acceptor impurities
Dry Etching
Wet Etching
Ion implantation: High-energy bombardment of Si with donor or acceptor ions
from particle accelerators followed by an anealing step to activate implants and
repair any damage
IC Processing Flow
Chemical Vapor Deposition: Materials such as metal or oxide are deposited out
of a gaseous mixture. Metals can also be deposited using
29
Lithography
Process through which we make (microfluidic) chips is called lithography
There are two types
Photolithography
Making a mold on a silicon wafer using UV light to etch a design
Soft lithography
Using mold to make a chip from polydimethyl siloxane (PDMS) polymer
Ion Implant
Etch
Mask or Mask or
E-Beam or
Photo
30
EDA
Mask or
Reticle
Photoresist
Mask or
Reticle
Photolithography is the technique to create a pattern on each layer with
submicron features to material layer
Optically projected the shadow of pattern onto the surface chip, then employ
photolightographic-type techniques to transfer the pattern to surface
Photolithography
31
Oxidation Oxidation
Optical
Mask
Optical
Mask
Photoresist Coating Photoresist Coating Photoresist Photoresist
Photolithographic Process
Photolithography Steps:
Photoresist
Wafer priming
Spincoating
Prebaking
Exposure
Development
Post-Baking
32
Process
\Steps
Photoresist Coating Photoresist Coating Photoresist
Removal (ashing)
Photoresist
Removal (ashing)
Spin, Rinse, Dry Spin, Rinse, Dry
Acid Etch Acid Etch
Photoresist
Development
Stepper Exposure Stepper Exposure
Typical operations in a single Typical operations in a single
Photolithographic Cycle Photolithographic Cycle
Photolithography
Light
Source
Reticle
Projection
Lens
Alignment
Laser
Reticle
Stage
Reference
Mark
Light
Source
Reticle
33
Wafer Stage
Projection
Lens
Wafer
Wafer Stage
Interferometer
Mirror Set
Projection
Lens
Wafer
Interferometer
Laser
X
Y
Light Diffraction Without Lens
Diffracted light
Mask
Intensity of
projected light
Short wavelength waves have less diffraction
Optical lens can collect diffracted light & enhance the image
Name Wavelength (nm) Application feature
size ( m)
G-line 436 0.50
Mercury Lamp H-line 405
I-line 365 0.35 to 0.25
XeF 351
XeCl 308
Excimer Laser KrF (DUV) 248 0.25 to 0.15
34
Diffracted light
collected by lens
Strayed
refracted light
Lens
Ideal light
Intensity pattern
Less diffraction after
focused by lens
Mask
r
o
D
Excimer Laser KrF (DUV) 248 0.25 to 0.15
ArF 193 0.18 to 0.13
Fluorine Laser F2 157 0.13 to 0.1
Future Trends
Even shorter wavelength
193 nm, 157 nm
Silicate glass absorbs UV light when <
180 nm
CaF
2
optical system
Next generation lithography (NGL)
Extreme UV (EUV), Electron Beam, X-ray (?)
Applications of Photolithography
IC patterning, Printed electronic board, nameplate, printer plate e.g.
35
Photoresist
To transfer the reticle pattern to surface of Si region, we first coat wafer with
light-sensitive liquid plastic material called photoresist
To create small structures or features on silicon wafer, made out of
photoresist by etching with UV light
Two types of photoresist:
Positive: Exposure to UV light removes resist
Negative: Exposure to UV light maintains resist
Substrate
Photoresist
36
Mask Positive
Resist
Negative
Resist
P-Well
USG
STI
Polysilicon
Photoresist
Primer
Photoresist coating Photoresist coating
Mask/reticle
Exposure
After
Development
Negative
Photoresist
UV light
Positive
Photoresist
Substrate
Substrate
Substrate
Photoresist
Substrate
Fabrication Equipment
Molecular Beam Epitaxy (MBE)
Photoresist Spinner
Bake-out Ovens
Mask Aligner
37
Fabrication Equipment
Reactive Ion Etching
(RIE)
Chemical Vapor Deposition (CVD)
Plasma Sputter
Perkin-Elmer MBE
38
Fabrication Equipment
Probe Station
Scanning Electron Microscope (SEM)
39
IC Layouts
40
CMOS Layers
41
Metal 2
M1/M2 Via
Metal 1
Polysilicon
Diffusion
MOSFET (under polysilicon gate)
MOSFET Schematics
42
CMOS Schematics
Metal1: 1
st
level of interconnect
Metal2: 2
nd
level of interconnect
43
Metal2: 2 level of interconnect
Metal3: 3
rd
level of interconnect
Metal4: 4
th
level of interconnect
Metal5: 5
th
level of interconnect
Metal6: 6
th
level of interconnect
Metal7: 7
th
level of interconnect
Via1: Connect the metal1 & metal2
Via2: Connect the metal2 & metal3
Via3: Connect the metal3 & metal4
Via4: Connect the metal4 & metal5
Via5: Connect the metal5 & metal6
Via6: Connect the metal6 & metal7
n-well
p-channel transistor
p-well
n-channel transistor
p+ substrate
bonding pad
nitride
Metal 2
n+
psubstrate
p+
nwell
A
Y
GND
V
DD
n+ p+
SiO
2
n+diffusion
p+diffusion
polysilicon
metal1
nMOStransistor pMOStransistor
Cross-Sectional CMOS View
44 44
GND V
DD
Y
A
substrate tap well tap
nMOS transistor pMOS transistor
M e t a l
P o l y s i l i c o n
C o n t a c t
n + D i f f u s i o n
p + D i f f u s i o n
n w e l l
Six masks
n-well
Polysilicon
n+ diffusion
p+ diffusion
Contact
Metal
Cross Sectional CMOS
45
Physical Layers
46
CMOS Process Flow
47
Latch-Up Effect
If base-emitter junction of pnp transistor becomes forward biased, transistor is
ON. The collector current of the npn transistor forces the pnp transistor to
conduct more current. This feedback leads to latch-up & circuit will be destroyed
by heat
Circuit can be prevented from latch-up by placing heavily doped guard ring
around MOSFETs. This reduces the effectiveness of base-emitter regions in
both transistors
48
IC Layout
IC layout, IC mask layout, or mask design, is the representation of IC in terms of
planar geometric shapes which correspond to patterns of metal, oxide, or
semiconductor layers that make up components of IC
Chips are specified with set of masks & guidelines for constructing process
masks
Required for resolution/tolerances of masks
Minimum dimensions of masks determine transistor size (Speed, Cost, Power)
Feature size F = Distance b/w Source & Drain
Set minimum width of polysilicon
Feature size improves 30% every 3 years or normalize for feature size when
49
Feature size improves 30% every 3 years or normalize for feature size when
describing design rules
Rules in terms of Interface b/w designer & process engineer
Fabrication processes defined by minimum channel width
Layout can be very time consuming
Design gates to fit together nicely
Build a library of standard cells
IC Layout
Generated layout must pass a series of checks in a process known as physical
verification. The most common checks in this verification process are
:
Design Rule Checking (DRC)
Layout Versus Schematic (LVS)
Parasitic Extraction
Antenna Rule Checking
Electrical Rule Checking (ERC)
50
Design objective in which Wp & Wn are separated may take into account such
parameters as power dissipation, propagation delay, noise immunity, & area
Basic steps are as follows:
Identification of gates (i.e., Inverter, NAND, NOR) and compute an average
delay time
Calculation of worst-case propagation time to ration of Wp/Wn
Calculation of noise immunity to Wp/Wn
Selection of ratio that balances the functions
IC Layout
51
Cell I/O should be available, at same relative horizontal distance, on top &
bottom of cell
Horizontal metal are used to supply power & ground to cell. Well & substrate
tie downs should be under these busses
Layout Design Rules
Design rules are an abstraction of the fabrication process that specify various
geometric constraints on how different masks can be drawn
Design rules can be absolute measurements (e.g. in nm) or scaled to an
abstract unit, lambda (). Lambda-based designs are scaled to appropriate
absolute units depending on manufacturing process finally used
Design rules do not represent some hard boundary b/w correct & incorrect
fabrication. Rather, they represent a tolerance that ensures very high probability
of correct fabrication & subsequent operation
Rules provide necessary communication link b/w circuit designer & process
52
Rules provide necessary communication link b/w circuit designer & process
engineer during manufacturing phase
Design rules are used to obtain circuit with optimum yield in as small geometry
as possible without compromising reliability of circuit
Layout Design Rules
Design rules define ranges for features
Min. wire widths to avoid breaks
Min. spacing to avoid shorts
Min. overlaps to ensure complete overlaps
Minimum line width
Scalable design rules:
lambda parameter = f/2, E.g. = 0.3 m in 0.6 m process (which is
half of the minimum channel length)
Classes of MOSIS SCMOS rules:
Submicron, Deep Submicron
Absolute dimensions measured in microns (micron rules) Absolute dimensions measured in microns (micron rules)
53
Extension
rules
Width
rules
Exclusion rule
Surround rule
Spacing rules
Layout Design Rules
Uniform cell & well height, when standard cells are placed, power & ground
busses line up
Cell width should be as narrow as layout will allow
NMOS at bottom & PMOS at top
V
dd
& V
ss
in metal at top & bottom of the cell with standard height
Metal-1 V
dd
& V
ss
rails
Metal-2 access to I/Os
Well/substrate taps
Vertical polysilicon lines for each gate input Vertical polysilicon lines for each gate input
Adjacent gates should satisfy design rules
All gates include well & substrate contacts
Layout should be labeled to indicate power, ground, input, & output
connections. Cell outline is useful in alignment, should be added to cell layout
Ordering polysilicon gate signals to allow maximal connection b/w transistors
via abutting source-drain connections
54
Lambda-based Design Rules
One lambda ()= one half of the minimum mask dimension
Typically the length of a transistor channel is 2. Usually all edges must be on
grid, e.g., in the MOSIS scalable rules, all edges must be on a lambda grid
.
z
,
z z
z
z.z
, , z
Length of the
transistor channel
is usually the
feature that sets
the process
technology name
(e.g., 0.18m has
0.18m transistor
length)
Layer
Polysilicon
Metal1
Metal2
Contact To Poly
Contact To Diffusion
Via
Well (p,n)
Active Area (n+,p+)
Color Representation
Yellow
Green
Red
Blue
Magenta
Black
Black
Black
Select (p+,n+) Green
.
,
, , z
.
z.z
,
.|,
.-..|.
a........ ,.....-,
.......
length)
Metal2
4
3
10
9
0
Well
Active
3
3
Polysilicon
2
2
Different Potential
Same Potential
Metal1
3
3
2
Contact
or Via
Select
2
or
6
2
Hole
55
1
2
5
3
Transistor
1
2
1
Via
Metal to
Poly Contact
Metal to
Active Contact
1
2
5
4
3 2
2
Vias & Contacts
56
1
3 3
2
2
2
Well
Substrate
Select
3
5
Layout Design Rules
Transistor dimensions are in W/L ratio
NFETs are usually twice the width
PFETs are usually twice the width of NFETs
Holes move more slowly than electrons (must be wider for same current)
57
Layout Design Rules
3-input NAND
58
Wiring Tracks
Wiring track is space required for a wire
4 width, 4 spacing from neighbor = 8 pitch
Transistors also consume one wiring track
59
Wells must surround transistors by 6
Implies 12 between opposite transistor flavors
Leaves room for one wire track
Area Estimation & Guard Rings
Estimate area by counting wiring tracks
Multiply by 8 to express in
60
Latch-up risk greatest when diffusion-to-substrate diodes could become
forward-biased
Surround sensitive region with guard ring to collect injected charge
VDD & VSS Connections
Section shown
61
Metal
Poly
A
B
C
D
E
C
D
A
E
B
Stick diagrams are capturing topography & layer information using simple diagrams
Stick diagrams convey layer information through colour codes or monochrome
encoding
Acts as an interface between symbolic circuit & actual layout
Stick diagrams help plan layout quickly
Need not be to scale
Draw with color pencils or dry-erase markers
Does show:
All components/vias
Stick Diagrams
3
V
DD
62
All components/vias
It shows relative placement of components
Goes one step closer to the layout
Helps plan the layout and routing
Does not show:
Exact placement of components
Transistor sizes
Wire lengths, wire widths, tub boundaries.
Any other low level details such as parasitics..
1
3
In
Out
GND
Stick Diagrams
Metal 1
Poly
N-Diff
P-Diff
Can also draw
in shades of
gray/line style
Similarly for contacts, via, tub etc..
Rule 1: When two or more sticks of the same type cross or touch each other that
represents electrical contact
Rule 2: When two or more sticks of different type cross or touch each other there
63
is no electrical contact
(If electrical contact is needed we have to show the connection explicitly)
Rule 3: When a poly crosses diffusion it represents a transistor
Rule 4: In CMOS a demarcation line is drawn to avoid touching of p-diff with n-diff.
All pMOS must lie on one side of line & all nMOS will have to be on other side
Stick Diagrams
N+ N+
V
DD
x
x
X
X
V
DD
x
x
64
V
DD
V
SS
Well
signals
Routing Channel
metal1
polysilicon
Gnd
x
X
X
Gnd
Stick Diagrams
Power
Ground
B
C
Out A
a c b a b c
x
x
GND
V
DD
V
DD
GND
(a) Input order {a c b}
(b) Input order {a b c}
Two Versions of (a+b).c
65
V
DD
C
i
A
B B A
B
A
A B
Kill
Generate
"1"-Propagate
"0"-Propagate
V
DD
C
i
A B C
i
C
i
B
A
C
i
A
B B
A
V
DD
S
C
o
C
i
A B
V
DD
GND
B
C
o
A Ci Co Ci A B
S
Stick Diagrams
66
Mirror Adder
B
24 transistors
G
2

C
3
G
3
C
i,0
P
0
G
1
V
DD

G
0
P
1
P
2
P
3
C
3
C
2
C
1
C
0
P
i + 1
G
i + 1

C
i
Inverter/Sum Row
Propagate/Generate Row
P
i
G
i

C
i - 1
C
i + 1
V
DD
GND
Manchester Carry Chain
Example
Sketch a stick diagram & estimate area of
( ) Y A B C D = + +
67
CMOS Inverter
Polysilicon
In
Out
V
DD
GND
PMOS
Metal 1
NMOS
Contacts
N Well
Out In
V
DD
PMOS
NMOS
A A
In
Out
GND V
DD
Layout
n
p-substrate Field
A A
68
GND
V
DD
V
DD
V
in
V
out
M1
M2
M3
M4
V
out2
Polysilicon
In
Out
Metal1
V
DD
GND
PMOS
NMOS
n
p-substrate Field
Oxide p+ n+
Cross-Section along A-A
CMOS Inverter Symbolic Layouts
a) Shows symbolic layout of inverter
corresponding to symbolic
schematic
b) Alternate inverter layout showing
horizontal active areas with vertical
poly stripe for gates & vertical metal
drain connections
c) Uses M2 metal to connect transistor
drains in order to allow passing
horizontal M1 metal wires
69
horizontal M1 metal wires
d) Uses diffused N & P source region
extensions (active mask) to Vss and
Vdd, respectively, in order to allow
passing M1 metal wires at top &
bottom of cell
Alternate Methods for Creating Inverter Layouts
Option (a): Increase Wn & Wp beyond
the min values
Option (b): Use parallel sections to obtain
increased Wn & Wp
Stitch Vdd & Vss in such a way as to
share drain regions b/w parallel
device sections
Option (c): Use of circular transistors
effectively quadruples the available
channel width of each device channel width of each device
Since drain regions are in center,
drain capacitance terms are minimum
70
NAND Gate Layout
Single polysilicon lines (for inputs) are vertically across both N & P active regions
Single active shapes used for building both NMOS & PMOS devices
Power bussing is running horizontal across top & bottom of layout
Output wire runs horizontal for easy connection to neighboring circuit
In
3
In
1
In
2
In
4
In
1
In
2
In
3
In
4
V
DD
Out
In1 In2In3 In4
Vdd
GND
Oul
Pseudo-NMOS NAND Gate

Vss
71
NOR Gate Layout
Features of the layout are similar to the 2-input NAND
Single vertical poly lines for each input
Single active shapes for N & P devices
Metal busing running horizontal
72
Examples
73
4-input NAND in CPL
Examples
74
A
M
2
M
1
B
S
S
S
F
V
DD
GND
V
DD
In
1
In
2
5
5
5 5
4-input NAND in CPL
Pass-Transistor based MUX
Examples
GND
VDD
word
buffer inverter NANDgate
A0 A0 A1 A2 A3 A2 A3 A1
75
buffer inverter NANDgate
Row Decoder
SRAM Layout
Cell size is critical: 26 x 45 (even smaller in industry)
Tile cells sharing V
DD
, GND, bitline contacts
V D D
G N D G N D B I T B I T _ B

2
More
Cells
Bitline Conditioning
76
W O R D
C e ll b ou nd ar y
SRAM Cell
word_q1
b
i
t
_
v
1
f
b
i
t
_
b
_
v
1
f
data_s1
write_q1
10T CAM Cell
Add four match transistors to 6T SRAM
56 x 43 unit cell
bit bit_b
word
match
c
e
l
l
c
e
l
l
_
b
77
match
RAM Layout
V
DD
GND
Q
Q
WL
M1 M3
M4 M2
M5 M6
V
DD
Q
Q
M1 M3
M4 M2
M5
BL
WL
BL
M6
6T-SRAM
78
BL BL
BL2 BL1 GND
RWL
WWL
M3
M2
M1
6T-SRAM
M2
M1
BL1
WWL
BL2
M3
RWL
C
S
X
3T-DRAM
ROM-Layout
Read-Only Memories are nonvolatile
Retain their contents when power is removed
Mask-programmed ROMs use one transistor per bit
Presence or absence determines 1 or 0
4-word x 6-bit ROM
Represented with dot diagram
Dots indicate 1s in ROM
A0 A1
weak
pseudo-nMOS
pullups
79
ROM Array
2:4
DEC
Y0 Y1 Y2 Y3 Y4 Y5
Looks like 6 4-input pseudo-nMOS NORs
Unit
Cell
Unit cell is 12 x 8 l (about 1/10 size of SRAM)
ROM
PLA-Layout
A N D P l a n e O R P l a n e
a b c
a b c
a b c
a b c
a b
b c
a c
s
a b c
o u t
c

80
V
DD
GND
And-Plane Or-Plane
f
0
f
1
x
0
x
0
x
1
x
1
x
2
x
2
Pull-up devices Pull-up devices
f
0
f
1 GND
V
DD

OR
x
0
x
0
x
1
x
1
x
2
x
2
GND
V
DD
AND-PLANE OR-PLANE

AND

OR

AND
Dynamic PLA
Sh3 Sh2 Sh1 Sh0
Sh3
Sh2
Sh1
A
3
A
2
A
1
A
0
B
3
B
2
B
1
B
0
: Control Wire
: Data Wire
Area Dominated by Wiring Sh3 Sh2 Sh1 Sh0
A
3
A
2
A
1
A
0
Shifter-Layout
81
4x4 Barrel Shifter 4x4 Barrel Shifter
Sh3 Sh2 Sh1 Sh0
Area Dominated by Wiring
Buffer
Sh1 Sh0
Widlh
laiieI
~ 2 p
n
M
A
3
A
2
A
1
A
0
Out3
Out2
Out1
Out0
Sh1 Sh1 Sh2 Sh2 Sh4 Sh4
A
3
A
2
A
1
A
0
B
1
B
0
B
2
B
3
0-7 bit Logarithmic Shifter
Automatic Layout Cell Generation
Standard Cells
82
Manually Designed Cell Layout
NMOS
PMOS
Oxide-isolation
PMOS
NMOS
NMOS
Using oxide-isolation Using gate-isolation
Standard Cells
Floorplan: Defines overall topology of design, relative placement of modules,
and global routes of busses, supplies & clocks
Routing channel requirements are reduced by presence of more interconnect
layers
Logic Cell Feedthrough Cell
Macrocell
Interconnect Bus
Routing
Channel
83
Functional
Module
(RAM,
multiplier, )
3-input NAND gate
Standard Cells
rows of
cells
routing
channel
uncommitted
V
D D
GND
polysilicon
metal
possible
contact
In 1 In 2 In 3 In4
Uncommited Cell
Committed Cell
(4-input NOR)
84
Out
(4-input NOR)
Gate Array
SRAM
SRAM
Data
paths
Standard Cells based Chip
85
Video-Encoder Chip
Standard
Cells
Layout Technique using Euler Graph Method
Euler Graph Technique can be used to determine if any complex CMOS gate can
be physically laid out in an optimum fashion
Start with either NMOS or PMOS tree & connect lines for transistor
segments, labeling devices, with vertex points as circuit nodes
Next place a new vertex within each confined area on pull-down graph &
connect neighboring vertices with new lines, making sure to cross each edge
of pull-down tree only once
New graph represents the pull-up tree & is dual of pull-down tree
Stick diagram is done with arbitrary gate ordering that gives non-optimum layout Stick diagram is done with arbitrary gate ordering that gives non-optimum layout
86
Layout with Optimum Gate Ordering
By using Euler path approach to re-order the polysilicon lines of previous chart,
we can obtain an optimum layout
Find a Euler path in both pull-down tree graph & pull-up tree graph with identical
ordering of inputs
Euler path: Traverses each branch of the graph exactly once!
By reordering input gates as E-D-A-B-C, we obtain an optimum layout of given
CMOS gate with single actives for both NMOS & PMOS devices
87
Automated Method to Design Gate Layouts
Place inputs as vertical poly stripes
Place Vdd & Vss as horizontal stripes
Group transistors within stripes to allow
maximum source/drain connection
Allow poly columns to interchange in
necessary to improve stripe wireability
Place device groups in rows
Wire up circuit by using vertical diffusions
for connections & manhattan metal routing
(both horizontal & vertical) (both horizontal & vertical)
88
CMOS XNOR Gate Layouts
Separate sections & stack transistors for
each section over identical gate inputs
XNOR implementation in (b) shows
separate sections with X = (AB) & Z = ((A
+ B) X) = XNOR (A,B)
Uses single row of N & P transistors
with a break b/w active regions
Alternate layout in (c) uses vertical device
regions making it a bit more compact
89
Euler Method for OAI Circuit Schematic
Layout at is an optimum layout of (OR AND Inverter) OAI circuit
Single poly vertical inputs
Unbroken single active regions for both N & P transistors
Problem: Find an equivalent inverter circuit for layout assuming:
W/L)
P
= 15 for all PMOS transistors
W/L)
N
= 10 for all NMOS transistors
90
CMOS 1-Bit Full Adder Circuit
1-Bit Full Adder logic function:
Sum=A XOR B XOR C
=ABC+ABC+ABC+ABC
Carry_out = AB+AC+BC
Alternate representation of sum function allows the 1-bit full adder to be
implemented in complex CMOS with 28 transistors
Carry_out internal node is used as an input to adder complex CMOS gate
91
CMOS Full Adder Layout
Use Euler method
Carry_out inverter requires separate active shapes, but all other N & P
transistors were laid out in single active region
Layout is non-optimized for performance
All transistors are seen to be minimum W/L
Design of n-bit full adder:
Carry ripple adder design uses carry_out of stage k as carry_in for stage
k+1
Typically layout is modified in order to use larger transistors for carry_out
CMOS gate in order to improve the performance of ripple bit adder CMOS gate in order to improve the performance of ripple bit adder
92
PLL Design: Layout
Area 1.4 mm x 1.7 mm
PLL-Layout
94
PLL-Layout
95