MOS Transistor Theory

VLSI Design VLSI Design

MOS Transistor Theory
By Dr. Yaseer A. Durrani
Dept. of Electronics Engineering
University of Engineering & Technology, Taxila
Outline
Semiconductor IC Chip
pn-Junction
Transistor I-V Characteristics
RC Delay Model
Transistor Families
2
Silicon Chip
A pattern of interconnected switches & gates on surface of crystal of
semiconductor (typically Si)
Silicon is a Group IV semiconducting material
Crystal lattice: covalent bonds hold each atom to four neighbours
These switches & gates are made of:
Areas of n-type silicon
Areas of p-type silicon
Areas of insulator
Lines of conductor (interconnects) joining areas together
Aluminium, Copper, Titanium, Molybdenum, polysilicon, tungsten Aluminium, Copper, Titanium, Molybdenum, polysilicon, tungsten
Geometry of these areas is known as layout of the chip
Connections from chip to outside world are made around the edge of the chip to
facilitate connections to other devices
3
Semiconductor is a solid material that has electrical conductivity in between
conductor & insulator
Similar to insulators
Less Larger energy band gaps
Doping is the process of intentionally introducing impurities into extremely
pure/intrinsic semiconductor in order to change its electrical properties
Number of dopant atoms needed to create a difference in ability of a
semiconductor to conduct is very small
Small number of dopant atoms are added (order of 1 every 100,000,000
atoms) then doping is said to be low, or light
Semiconductor
atoms) then doping is said to be low, or light
More dopant atoms are added (order of 1 in 10,000) then doping is said to
be heavy, or high. This is often shown as n+ for n-type dopant or p+ for p-
type doping
4
Significance of Semiconductors
Computers, palm pilots, laptops: Silicon (Si) MOSFETs, ICs, CMOS
Cell phones, pagers: Si ICs, GaAs FETs, BJTs
CD players: AlGaAs, InGaP laser diodes, Si photodiodes
TV remotes, mobile terminals: Light emitting diodes
Satellite dishes: InGaAs MMICs
Fiber networks: InGaAsP laser diodes, pin photodiodes
Traffic signals, car: GaN LEDs (green, blue)
Taillights: InGaAsP LEDs (red, amber)
5
n & p type
Crystal lattice: covalent bonds hold each atom to four neighbors
Adding trace amounts of certain materials to semiconductors alters the crystal
structure & can change their electrical properties
In particular it can change the number of free electrons or holes
n-type
Semiconductor has free electrons
Dopant is (typically) phosphorus, arsenic, antimony
p-type
Semiconductor has free holes
Dopant is (typically) boron, indium, gallium Dopant is (typically) boron, indium, gallium
Dopants are usually implanted into the semiconductor using Implant
Technology, followed by thermal process to diffuse the dopants
As Si Si
Si Si Si
Si Si Si
B Si Si
Si Si Si
Si Si Si
-
+
+
-
6
p-n Junction
A p-n junction is a boundary or interface b/w two types of semiconductor
material, p-type & n-type, inside a single crystal of semiconductor
pn junctions are elementary "building blocks" of most semiconductor
electronic devices such as diodes, transistors, solar cells, LEDs, ICs
Common type of transistor, bipolar junction transistor, consists of two pn
junctions in series, in the form npn or pnp
Its main electrical property is that it rectifies (allow current to flow easily in one
direction only)
7
p-type n-type
anode cathode
Type of junctions
Homojunction: is a semiconductor interface that occurs b/w layers of similar
semiconductor material, these materials have equal band gaps but typically
have different doping
Heterojunction: is interface that occurs b/w two layers or regions of dissimilar
crystalline semiconductors. These semiconducting materials have unequal band
gaps as opposed to a homojunction
8
Image of nanoscale heterojunction
b/w iron oxide & cadmium sulfide
p-n Junction
Si Si As Si
-
Si Si Si Ga Si Si Si Ga
+
Si
Si
Si
As
Si
Si
Si
Si
-
As Si
Si Si
Si Si
Si
Si
Ga
Si
Si
+
Si
Si
Si
Si Ga
N Type P Type Depleted
Si
Si
Si
As
Si
Si
Si
Si
-
Si Si As Si
Si
Si
Si
As
Si
Si
Si
Si
-
-
As Si
Si
Si
Si
As
As Si
Si Si
Si
Si
Si
Si
Si
Ga
Si
Si
+
Si Ga Si Si
Si Si
Si
Si
Ga
Si
Si
+
Si
Si
Si
Si
Si Ga
Si
Si
Si
Si
+
Ga
9
p-n junction Electrostatics
When p & n-type regions are contacted, electrons & holes move by diffusion
until an electric field is generated that oppose their movement. So a dynamic
equilibrium is established, where drift & diffusion component are equal for both
holes & electrons
10
Holes diffused to metalurgical junction & combine with electrons. They leave
behind -vely charged acceptor, while electrons diffused & leave behind +vely
charged donor
Diffusion process can not go on forever, because, increasing amount of fixed
charge wants to electrostatically attract the carriers that are trying to diffuse
away & equlibrium is reached
Fixed charge produce an electric field which slows down the diffusion process
Fixed charge region is called depletion/space charge region
Idealized p-n Junction
11
Contact Potential
When p & n-type materials are joined, electrons & holes diffuse due to their
large carrier concentration gradients at junction where holes diffuse from p-
side into n-side, & electron diffuse from n to p. Thus, concentration gradients
creates a diffusion component of current from p to n region
+
+
+
+
-
-
-
-
-
-
-
+
+
12
+
+
+
-
-
-
-
-
+
+
+
+
Transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed
13
NMOS Capacitor
Gate & body form MOS capacitor
Operating modes
Accumulation
Depletion
Inversion
polysilicon gate
(a)
silicon dioxide insulator
p-type body
+
-
V
g
< 0
+
-
0 < V
g
< V
t
depletion region
(b)
-
(c)
+
-
V
g
> V
t
depletion region
inversion region
14
Terminal Voltages
Mode of operation depends on V
g
, V
d
, V
s
V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
- V
gd
Source & drain are symmetric diffusion terminals
However, V
ds
0
Three- regions of operation
Cutoff, Linear, & Saturation
V
g
V
s
V
d
V
g d
V
g s
V
ds
+ -
+
-
+
-
NMOS Saturation Region
Channel pinches off if V
ds
> V
gs
V
t
.
I
ds
independent of V
ds
, i.e., current saturates
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
< V
t
V
ds
> V
gs
-V
t
p-type body
b
g
s d
I
ds
+
-
V
gs
= 0
n+ n+
+
-
V
gd
p-type body
b
g
s d
NMOS Cutoff Region
Assume V
s
= V
b
No channel, if V
gs
= 0
I
ds
= 0
+
-
V
gs
> V
t
n+ n+
+
-
V
gd
= V
gs
+
-
V
gs
> V
t
n+ n+
+
-
V
gs
> V
gd
> V
t
V
ds
= 0
0 < V
ds
< V
gs
-V
t
p-type body
p-type body
b
g
s d
b
g
s d
I
ds
NMOS Linear Region
Channel forms if V
gs
> V
t
No Currernt if V
ds
= 0
Linear Region:
If Vds > 0, Current flows
from d to s ( e
-
from s to d)
I
ds
increases linearly
with V
ds
if V
ds
> V
gs
V
t
.
Similar to linear resistor
I
ds
independent of V
ds
, i.e., current saturates
Similar to current source
15
I-V Characteristics
In Linear region, I
ds
depends on
How much charge is in the channel
How fast is the charge moving
Channel Charge: MOS structure looks like parallel plate capacitor while
operating in inversion
Gate oxide (dielectric) channel
Q
channel
= CV
C = C
g
=
ox
WL/t
ox
= C
ox
WL
V = V
gc
V
t
= (V
gs
V
ds
/2) V
t
C
ox
=
ox
/ t
ox
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9)
polysilicon
gate
16
Carrier Velocity
Carrier Velocity
Charge is carried by e-
Carrier velocity v proportional to lateral E-field b/w source & drain
v = E, is mobility, E = V
ds
/L
Time for carrier to cross channel: t=L/v
NMOS Linear I-V
How much charge Q
channel
is in the channel
How much time t each carrier takes to cross
NMOS Saturation I-V
If V
gd
< V
t
, channel pinches off near drain
channel
ox
2
2
ds
ds
gs t ds
ds
gs t ds
Q
I
t
W V
C V V V
L
V
V V V

=
| |
=
|
\
| |
=
|
\
ox
=
W
C
L

If V
gd
< V
t
, channel pinches off near drain
When V
ds
> V
dsat
= V
gs
V
t
Now drain voltage no longer increases current
NMOS IV Summary
Shockley 1
st
order transistor models (valid for Large channel devices only
( )
2
2
2
dsat
ds gs t dsat
gs t
V
I V V V
V V

| |
=
|
\
=
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V

<

| |
= <
|
\

>

17
Example
For a 0.6 m process
From AMI Semiconductor
t
ox
= 100
= 350 cm
2
/V*s
V
t
= 0.7 V
Plot I
ds
vs. V
ds
V
gs
= 0, 1, 2, 3, 4, 5
Use W/L = 4/2
( )
14
2
3.9 8.85 10
350 120 /
W W W
C A V

| | | |
= = =
| |
0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
= 5
V
gs
= 4
V
gs
= 3
V
gs
= 2
V
gs
= 1
( )
2
8
350 120 /
100 10
ox
W W W
C A V
L L L

| |
= = =
| |

\
\
V
ds
18
PMOS I-V
All dopings & voltages are inverted for PMOS
Mobility
p
is determined by holes
Typically 2-3x lower than that of electrons
n
120 cm
2
/V*s in AMI 0.6 m process
Thus PMOS must be wider to provide same current
In this class, assume
n
/
p
= 2
19
Gate Capacitance
Any two conductors separated by an insulator have capacitance
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source & drain have capacitance to body
Across reverse-biased diodes
Called diffusion capacitance because it is associated with source/drain
diffusion
Approximate channel as connected to source
C
gs
=
ox
WL/t
ox
= C
ox
WL = C
permicron
W
C is typically about 2 fF/m
W
polysilicon
gate
C
permicron
is typically about 2 fF/m
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
= 3.9
0
)
20
Dynamic Behavior of the Transistor
Propagation Delay, Tp: defines how quickly output is affected by input
Measured between 50% transition from input to output
t
pLH
defines delay for output going from low to high
t
pHL
defines delay for output going from high to low
Overall delay, t
p
, defined as the average of t
pLH
and t
pHL
Rise and fall time, Tr & Tf: Defines slope of the signal
Defined b/w 10% and 90% of the signal swing
Propagation delay and rise and fall times affected by the fan-out due to
larger capacitance loads
Standard method to measure gate delay is based on ring oscillator:
2Ntp >> tf + tr for proper operation
t
pHL
t
pLH
t
t
V
in
V
out
50%
50%
t
r
10%
90%
t f
t
pHL
t
pLH
t
t
V
in
V
out
50%
50%
t
r
10%
90%
t f
v
0
v 1 v
2
v
3
v
4
v
5
v 0
v
1
v
5
T = 2 t
p
N
Ring Oscillator
21
Switch Model of Dynamic Behavior
V
DD
R
p
V
out
C
L
V
DD
R
n
V
out
C
L
Gate response time is determined by the time to charge C
L
through R
p
(discharge C
L
through R
n
)
V
DD
V
out
V = V
CL I
av
t
pHL
= C
L
V
swing
/2
I
av
C
L
k
n
V
DD
~
Technique-1
V
in
= 0
R
n
V
in
= V
DD
V
in
= V
DD
V
DD
V
out
V
in
= V
DD
R
on
CL
t
pHL
= f(R
on
.C
L
)
= 0.69 R
on
C
L
t
V
out
V
DD
R
on
C
L
1
0.5
ln(0.5)
0.36
) /(
L on
C R t
OH out
e V V

=
Technique-2 22
How can the designer build a fast gate?
tpHL = f(Ron*CL)
Keep output capacitance, CL, small
low fan-out
Keep interconnections short (floor-plan your layout!)
Decrease on-resistance of transiston
Increase W/L ratio
Make good contacts (slight effect)
3
23
0 0. 5 1 1. 5 2 2. 5
x 10
- 10
-0. 5
0
0. 5
1
1. 5
2
2. 5
t (sec)
V
o
u
t
(
V
)
t
p
= 0.69 C
L
(R
eqn
+R
eqp
)/2
t
pHL
t
pLH
Transient Response
Inverter Transient Response

V
in
t
f
t
r
t
pHL
t
pLH
V
DD
=2.5V
0.25m
W/L
n
= 1.5
W/L
p
= 4.5
R
eqn
= 13 k ( 1.5)
R
eqp
= 31 k ( 4.5)
t
pHL
= 36 psec
t
pLH
= 29 psec
so
t
p
= 32.5 psec

t (sec)
x 10
-10
From simulation: t
pHL
= 39.9 psec & t
pLH
= 31.7 psec
24
Propagation Delay Analysis - Switch Model
VDD
V
DD
Propagation delay depends on input patterns
Example: Two input NAND gate
Two PMOS transistors are ON
Delay: 0.69x(Rp/2)xCL
Only one PMOS transistor ON then
Delay: 0.69xRpxCL
Large number of transistors (2N) increases overall capacitance of gate
Series connection of transistors in PUN/PDN of gate causes additional slow down
25
VDD
VDD
V
DD
C
L
F
CL
CL
F
F
Rp
Rp Rp
R
p
Rp
Rn
Rn
Rn
Rn Rn
A
A A
A
A
A
B
B
B
B
Inverter Inverter 2 input NAND 2 input NAND
2-input NOR 2-input NOR
t
p
= 0.69 R
on C
L
(assuming that C
L
dominates!)
=
RON
Analysis of Propagation Delay
V
DD
C
L
F
R
p
R
p
R
n
R
n
A
A
B
B
1. Assume R
n
=R
p
= resistance of minimum
sized NMOS inverter
2. Determine Worst Case Input transition
(Delay depends on input values)
3. Example: t
pLH
for 2input NAND
- Worst case when only ONE PMOS Pulls
up the output node
- For 2 PMOS devices in parallel, the
resistance is lower
V
DD
C
L
F
A
B
B
2
2
1 1
V
DD
A
B
C
D
A
1
2
2
2
4
4
F
26
A
2-input NAND
resistance is lower
4. Example: t
pHL
for 2input NAND
- Worst case : TWO NMOS in series
t
pLH
= 0.69R
p
C
L
t
pHL
= 0.69(2R
n
)C
L
A
2
D
B C
1
2 2
Here it is assumed that
R
p
= R
n
Design for worse case
Elmore Delay
R
1
C
1
R
2
C
2
R
i-1
C
i-1
R
i
C
i
R
N
C
N
V
in
N
1 2 i -1
i
Elmore delay is equivalent to first-order time constant of n/w
Time constant represents simple approx. of actual delay b/w source
node and node i
27
1 2 i-1 i N
Delay Optimization
Approx RC model of digital cir circuits

= = =
= =
N
i
i
j
N
i
ii i j i DN
R C R C
1 1 1

RC Delay Model
Use equivalent circuits for MOS transistors
Ideal switch + capacitance and ON resistance
NMOS has resistance R, capacitance C
PMOS has resistance 2R, capacitance C
Capacitance proportional to width
Resistance inversely proportional to width
k g
d
g
d
kC
R/k
k g
d
g
s
kC
kC
2R/k
s
s
kC
kC
k g
s
g
d
kC
k1
Capacitance
C = C
g
= C
s
= C
d
= 2 fF/m of gate width
Values similar across many processes
Resistance
R 6 K*m in 0.6um process
Improves with shorter channel lengths
Unit transistors
May refer to minimum contacted device (4/2 )
Or maybe 1 m wide device
Doesnt matter as long as you are consistent
28
Inverter Delay Estimate
Estimate the delay of a fanout-of-1 inverter
C
R
2C
2C
R
2
1
A
Y
C
2C
C
2C
C
2C
R
Y
2
1
C
R
C C
d = 6RC
29
Transistor Families
CMOS: Displace bipolar technology in digital applications are as follows:
CMOS logic circuits dissipate much less power than bipolar logic circuits
High input impedance of MOS transistor allows designer to use charge
storage for temporary storage of information in both logic & memory circuits
Feature size (i.e., minimum channel length) of MOS transistor has
decreased which permits very tight circuit packing & integration
Bipolar: Two logic-circuit families based on bipolar junction transistor are in
some use at present: TTL & ECL
BiCMOS: Combines the high operating speeds possible with BJTs with low
power dissipation & other excellent characteristics of CMOS
Gallium Arsenide (GaAs): High carrier mobility results in very high speeds Gallium Arsenide (GaAs): High carrier mobility results in very high speeds
30
Transistor Families
Resistortransistor logic (RTL)
Direct-coupled transistor logic (DCTL)
Resistortransistor logic (RCTL)
Diodetransistor logic (DTL)
Complemented transistor diode logic (CTDL)
High-threshold logic (HTL)
Emitter-coupled logic (ECL)
Positive emitter-coupled logic (PECL)
Low-voltage positive emitter-coupled logic(LVPECL)
Gunning transceiver logic (GTL)
31
Gunning transceiver logic (GTL)
Transistortransistor logic (TTL)
P-type metaloxidesemiconductor logic (PMOS)
N-type metaloxidesemiconductor logic (NMOS)
Depletion-load NMOS logic
Complementary metaloxidesemiconductor logic (CMOS)
Bipolar complementary metaloxidesemiconductor logic (BiCMOS)
Integrated injection logic (I
2
L)
Transistor Families
Family Description
Propagation
delay (ns)
Toggle
speed
(MHz)
Power/gate@
1MHz (mW)
Typical supply
voltage V (range) Year Remarks
RTL Resistor
transistor logic
__ 4 10 3.3 1963 First CPU built from used RTL.
DTL Diode
transistor logic
__ __ 10 5 1962 Introduced by Signetics, Fairchild 930
line became industry standard in 1964
CMOS AC/ACT 3 125 0.5 3.3 or 5 (2-6 or 4.5-
5.5)
1985 ACT has TTL Compatible levels
CMOS HC/HCT 9 30 0.5 5 (2-6 or 4.5-5.5) 1982 HCT has TTL compatible levels
CMOS 4000B/74C 30 5 1.2 10V (3-18) 1970 Approximately half speed & power at 5V
TTL Original series 10 25 10 5 ) 4.75 - 5.25 ( 1964 Several manufacturers
32
TTL Original series 10 25 10 5 ) 4.75 - 5.25 ( 1964 Several manufacturers
TTL L 33 3 1 5 ) 4.75 - 5.25 ( 1964 Low power
TTL H 6 43 22 5 ) 4.75 - 5.25 ( 1964 High speed
TTL S 3 110 19 5 ) 4.75 - 5.25 ( 1969 Schottky high speed
TTL LS 10 33 2 5 ) 4.75 - 5.25 ( 1976 Low power Schottky high speed
TTL ALS 4 34 1.3 5 ) 4.5 - 5.5 ( 1976 Advanced Low power Schottky
TTL F 3.5 100 5.4 5 ) 4.75 - 5.25 ( 1979 Fast
TTL AS 2 105 8 5 ) 4.5 - 5.5 ( 1980 Advanced Schottky
TTL G 1.5 1125
(1.125
GHz)
1.65 - 3.6 2004 First GHz 7400 series logic
ECL ECL III 1 500 60 - 5.2 ) - 5.19 - - 5.21 ( 1968 Improved ECL
ECL MECL I 8 31 - 5.2 1962 first IC commercially produced
ECL ECL 10K 2 125 25 - 5.2 ) - 5.19 - - 5.21 ( 1971 Motorola
ECL ECL 100K . 75 350 40 - 4.5 ) - 4.2 - - 5.2 ( 1981
ECL ECL 100KH 1 250 25 - 5.2 ) - 4.9 - - 5.5 ( 1981
Field Effect Transistors (FET)
Field effect devices are voltage controlled by action of electric field, rather than
carrier injection
FETs have weak electrical signal coming in through one electrode creates an
electrical field through the rest of transistor
FET transistor uses an electric field to control the shape & conductivity of a
channel of one type of charge carrier in a semiconductor material
FETs are unipolar, as they involve single-carrier-type operation
FET behaves like bipolar transistor with important difference that gate has a very
high input impedance and therefore draws no current high input impedance and therefore draws no current
33
FET Types
N Channel (as NPN transistor)
P Channel (as PNP transistor)
N & P channel each come as:
Enhancement mode (just IGFET)
Depletion mode (IGFET or JFET)
34
Basic Operation of JFET
JFET operation can be compared to a water spigot:
Source of water pressure: Accumulated electrons at ve pole of applied voltage
from Drain to Source
Drain of water: Electron deficiency (or holes) at +ve pole of applied voltage from
Drain to Source
Control of flow of water: Gate voltage that controls the width of n-channel, which
in turn controls the flow of electrons in n-channel from Source to Drain
35
JFET
If channel is doped with donor impurity, n-type material is formed & channel
current will consist of electrons
If channel is doped with acceptor impurity, p-type material will be formed &
channel current will consist of holes
N-channel devices have greater conductivity than p-channel types, since
electrons have higher mobility than do holes; thus n-channel JFETs are
approximately twice as efficient conductors compared to their p-channel
counterparts
Magnitude of current is controlled by voltage applied to gate, which is reverse-
36
Magnitude of current is controlled by voltage applied to gate, which is reverse-
biased
An Insulated Gate FET
Source Gate Drai n
Substrate
N Type
P Type
Insul ator
Metal
Source Gate Drai n
Substrate
N Type
P Type
Insul ator
Metal
Insulated Gate FET
n-Channel Enhancement mode
Source Gate + Drai n
Substrate
N Type
P Type
Insul ator
Metal
Channel
n-Channel enhancement
IGFET turned on
JFET
n-Channel Enhancement mode IGFET turned on
Source Gate + Drai n +
Substrate
N Type
P Type
Insul ator
Metal
Channel
N enhance FET at
Pinchoff
N enhance FET
beyond Pinchoff
N enhance FET
beyond Pinchoff
Source Gate + Drai n++
Substrate
N Type
P Type
Insul ator
Metal
Channel
n-Channel Depletion mode
FET ON No gate bias
Source Gate Drai n
Substrate
N Type
P Type
Insul ator
Metal
Channel
n-Channel Depletion
mode FET off
Source Gate - Drai n
Substrate
N Type
P Type
Insul ator
Metal
No Channel
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MOSFET
MOSFETMetalOxideSemiconductor Field-Effect Transistor is a transistor
used for amplifying or switching electronic signals
Source & Drain terminals are specified by operation voltage
MOSFET has four-terminals: Source (S), Gate (G), Drain (D), Body (B)
Body (or substrate) of MOSFET often is connected to source terminal, making it
three-terminal
MOSFET is by far the most common transistor in both digital and analog circuits,
though the bipolar junction transistor was at one time much more common
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BJTBipolar Junction Transistors is current controlled device consists of two pn-
junctions
Three region: Base, Collector , Emitter
Operational modes are Base-Emitter & Base-Collector voltages
When there is no base current, almost no collector current flows
When base current flow, collector current can flow
BJT consists of N-type material with P-type on either side, or visa-versa
PNP P-type N-type P-type
NPN N-type P-type N-type
BJTs
39
VMOS
VMOS Vertical MOSFET increases the surface area of the device
Advantage:
This allows the device to handle higher currents by providing it more
surface area to dissipate the heat
VMOSs also have faster switching times
40
CMOS
CMOS Complementary Metal Oxide Semiconductor employs both PMOS &
NMOS devices
CMOS Complementary MOSFET p & n-channel MOSFET on same substrate
If substrate is p-type, PMOS transistors are formed in n-well (n-type body need)
If substrate is n-type, NMOS transistors are formed in p-well (p-type body need)
Substrate & well are connected to voltages which reverse bias the junctions for
device isolation
Advantage:
Lower power consumption
Useful in logic circuit designs Useful in logic circuit designs
Higher input impedance
Faster switching speeds
41
BJT Vs. CMOS
Advantages of Bipolar over CMOS
Switching speed
Currents drive per unit area
Noise performance
Analog capability
Input/output speed
Advantages of CMOS over Bipolar
Power dissipation
Noise margin
Packing density
Ability to integrate large complex functions with high yields
42
BiCMOS
BiCMOS technology combines Bipolar & CMOS transistors onto a single IC
where the advantages of both can be utilized
BiCMOS technologies have tended to evolve from CMOS processes in order to
obtain the highest CMOS performance possible
Bipolar processing steps have been added to core CMOS flow to realize the
desired device characteristics
BiCMOS gates can be an efficient way of speeding up VLSI circuits
Advantages:
Improved speed over CMOS Improved speed over CMOS
Lower power dissipation than Bipolar
Flexible input/outputs
High performance analog
Latch up immunity
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BiCMOS Structure
NMOS device, built on top of P+substrate
PMOS transistor, built in an N-well approximately 5um deep
P+substrate is used to reduce latch up susceptibility by providing low impedance
patch through a vertical pnp device
Polysilicon gates are used for both the PMOS & NMOS transistors
Simplest way to add npn bipolar transistor to CMOS structure is by using PMOS
N-well as collector of Bipolar device & introducing an additional mask level for P-
base region
P-base is approx 1-um deep with doping level of about 1e17 atoms/cm^3
N+source/drain ion implantation step is used for emitter & collector contact of
bipolar structure
P+source/drain ion implantation step is used to create a P+ base contact to
minimize the base series resistance
44
CMOS Nanoelectronics
Key of success of CMOS nanoelectronics: additive technology features
Ultra-thin body FET
Double- (or Multi-) gate FET
Strained Si (bulk, on insulator)
Ge (bulk, on insulator)
High-k gate dielectrics
Metal gates
Crystal orientation
45
Emerging Devices
New technologies based on something other than electronic charge
thatextend the scaling of information processing technologies through
multiple generations beyond 2019
Provide a path to scale CMOS to the end of Roadmap using new transistor
structural designs & new materials
Transport-Enhanced FETs: Enhance the velocity of carriers
Ultra-thin Body SOI FETs: Thin transistor body is employed
Source/Drain Engineered FETs: Engineering the source/drain
Multiple Gate FETs:
N-Gate (N>2) FETs: Use more than two gates to improve electrostatic control
Double-gate FETs: Use two isolated gates for low-power & mixed-signal
processing
46
Emerging Devices
Single-electron transistors
Resonant tunnel devices
Molecular devices
Single-electron transistors
Spin transistors 47