Fabrication and Layout

Kenneth Yun UC San Diego

Adapted from EE271 notes, Stanford University

Overview
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Semiconductor properties How chips are made Design rules for layout Reading
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Fabrication: W&E 3.1, 3.2.1, 3.3.1 Design Rules: W&E 3.4-3.4.3

What To Build
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Transistors
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nMOS and pMOS Many levels of (real) metal wires (aluminum and copper)
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Wires
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Need low resistance (high conductivity)

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Oxide insulators between metal layers Contacts (hole in the oxide) between adjacent layers

Silicon
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Semiconductor
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Conductivity changed by adding impurities Impurities, called dopants, create either ntype or p-type regions SiO2 (quarz or glass) Great for sealing things from impurities Can be selectively patterned Etching can remove SiO2 without harming Si

Oxide is stable
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Doping
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Adding arsenic or phosphorous to intrinsic silicon increases conductivity

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By adding free electrons n-type since current is carried by negatively charged particles (electrons)

Adding boron to intrinsic silicon increases conductivity

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By adding free holes p-type since current is carried by positively charged particles

Diode
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Junction between n-type and p-type regions form a diode

I
n+ p+ p+

n V

How To Build Transistor

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Diffusion made by adding (diffusing) impurities into silicon

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n+ (p+) diffusion has lots of impurities (dopants), so higher conductivity p (n) regions lightly doped p region formed first; n+ doped over parts of p region n+ dopant added after poly is down so that poly blocks dopant
poly p n+ n+

Two Transistor Types

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CMOS requires two types of substrates for isolation of transistors

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n-type for pMOS p-type for nMOS

cross section

n+

n+

p+

p+

Substrate = p

Substrate = n

Well: Local Substrate

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Base wafer type may be

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n-type: add pwell / p-type: add nwell Some have twin well

n+ p n

p+

pwell process

n substrate

Well Requirement
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Well must be tied to a power supply to keep isolation diode reversed biased
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Using well contacts (ohmic connection to the well)

n+ p+ p+

n+

Tied to GND

Tied to Vdd

Well Contacts
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Formed by placing p+ doped region in pwell (n+ region in nwell) These regions make good electrical contact to the well (ohmic, not diode)
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Well potential equal to the diffusion potential

Need to have at least one well contact in each well

Whats On A Chip: Review

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Transistors
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Require silicon substrate, wells, two types of diffusion, poly Many levels of (real) metal wires Oxide insulator between metal layers Contacts between adjacent layers

Wires
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Fabrication
Masks

Chips Wafers Processing Processed Wafer

Basic Fabrication Steps

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Transfer image of the design to wafer (photolithography) Create layers (diffusion/oxide/metal)

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Ion implant for diffusion; shoot impurities at silicon Deposition for oxide/metal; usually chemical vapor deposition (CVD) Grow for oxide; place silicon in oxidizing ambient

Basic Processing
Start with wafer at current step Spin on a photoresist Pattern photoresist with mask Step specific processing etch, implant, etc... Wash off resist

IC Fabrication
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Repeat
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Create layer on wafer Put photo-sensitive material (resist) on top of wafer Optically project image of pattern on water Develop resist Use resist as mask to prevent etch from reaching layer below, when transferring pattern to layer Remove resist

All die on wafer processed in parallel; for some chemical steps, many wafers processed in parallel

Photolithography
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To transfer pattern onto wafer, first need an image to project

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Glass plate (mask) with image of pattern etched in chrome generated from design database
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Mask = negative in photography

Image optically projected onto wafer using projection aligner

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projection aligner = enlarger in photography

Mask allows printing on large number of wafers

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Cost per wafer low, assuming lots of wafers

Making Transistors
1. Implant N-Well

2. Define thin oxide; grow field oxide

3. Etch poly

Making Transistors
4. Implant threshold adjust

5. Implant source and drain

Making Wires
1. Deposit insulator; may be polished to make it fit

2. Etch contacts to Si; fill with conductor

3. Pattern metal wires

Foundry Interface

Designer

Layout (Mask Set)

Foundry

Design Rules Process Parameters

MAGIC MOSIS SCMOS Layers

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4 types of diffusion
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Normal (forms transistor)

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ndiff pdiff nohmic pohmic

Diffusion for well contacts

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Poly Metal
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M1 M2

Physical and MAGIC Layers

Physical Masks (simplified) Magic Layers nwell nwell active area (thin ox) ndiff (active & nselect & ~nwell) poly pdiff (active & pselect & nwell) threshold adjust (n & p) nnd (active & nselect & nwell) implant select (n & p) ppd (active & pselect & ~nwell) contact poly metal 1 metal1 via metal2 metal 2 contacts glass

Layer Example

MAGIC Contacts
+ + =

ndc - ndiff to metal1 pdc - pdiff to metal1 ppc - ppd to metal1 nnc - nnd to metal1 pc - poly to metal1 via - metal1 to metal2

Contact Example

Fabrication Constraints On Layout

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Resolution constraints
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Smallest printable feature / smallest spacing that guarantees no short Depends on lithography and processing steps Resolution often depends on smoothness of surface Need to align layers (like printing color picture)

Alignment/overlap constraints
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Geometric Design Rules

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Resolution
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width and spacing of lines on one layer to make sure interacting layers overlap (or dont) contact surround poly overlap of diff well surround of diff contact spacing to unrelated geometry

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Alignment
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MOSIS SCMOS Design Rules

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Allow you to send designs to different fabs Rules are based on - half the drawn gate length (poly width) All other design rules expressed in multiples of
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Poly width = 2, space = 3 metal width = space = 3 Manhattan layout (only 90 degree angles)

Conservative
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SCMOS Design Rule Highlights

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Resolution rules
Layer poly diff m1 m2 nwell cut via Width 2 3 3 3 10 2 2 Space 3 3 3 4 9 2 3

Alignment rules
cut/via surround poly overlap diff poly space to diff 1 2 1

Notes: Cut plus surround is 4 Layout falls on 8 grid

Pitch
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Repeat distance between objects

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8
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contacted transistor pitch

cut + poly width + 2 x cut-to-poly

6.5
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semi-contacted m1 pitch semi-contacted m2 pitch fully contacted m1 pitch

(contact + width)/2 + spacing (contact + width)/2 + spacing contact + spacing

7.5
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7
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8
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fully contacted m2 pitch

contact + spacing

Contact Rules
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Spacing from contacts is slightly larger than from base material

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Poly contact to poly spacing = 3 Diffusion contact (ndc, pdc, nwc, pwc) to diffusion = 4

So that the fab can make surround of contact cut slightly larger than 1 if necessary

Magic Number 8
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Most of the important rules for estimating the size of stick diagram can (diff width =4) be approximated by 8
diff w/c = 8 M2 w/c = 8 M1 w/c = 7 poly w/c = 7 8

poly w/dc = 8

Stick Diagrams
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Like a layout
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Basic topology of the circuit Relative positions of objects roughly correct Wires have no width Size of objects not to scale Missing wires can be squeezed in between two wires

But
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Layout Issues
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Two types of diffusion

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ndiff
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poly crossing ndiff makes nMOS transistor poly crossing pdiff makes pMOS transistor must connect ndiff to metal and metal to pdiff large spacing rule between ndiff and pdiff need to group nMOS transistors together and pMOS transistors together

pdiff
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Cannot directly connect ndiff and pdiff

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Cannot get ndiff too close to pdiff because of wells

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Basic Layout Planning

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Need to route power and ground (in metal) Keep nMOS devices near nMOS devices and pMOS devices near pMOS devices
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nMOS near ground and pMOS near Vdd

Run poly vertically and diffusion horizontally with m1 horizontally Keep diffusion wires as short as possible
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just enough to make transistors

All long wires in m1 and m2

Typical Cell Layout Plan

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Parity

Inverter
Vdd Gnd