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Passivation Metal 3 ILD: Inter layer dielectric Metal 2 ILD: Inter layer dielectric Metal 1 ILD: Inter layer dielectric Xtor gate High-k Gate oxide Silicon base Transistor (Xtor) Other active devices
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Passivation Metal 3 ILD: Inter layer dielectric Metal 2 ILD: Inter layer dielectric Metal 1 ILD: Inter layer dielectric Xtor gate High-k Gate oxide Silicon base Via
n+
n+
p+
p+
Silicon Substrate (P) Diode NWELL (n-doping) Can also make BJTs, standalone diodes, ..
DIGITAL
Universal gate: Can implement any Boolean function with This gate.
Boolean functions
x 0 0 1 1 y 0 1 0 1 f(x,y) 0 1 1 0
f ( x, y) = x ' y + xy '
Full Adder
Subtracter
One/Zero detector
Sequencing
!! Sequencing operations ! Synchronous ! Asynchronous
Synchronous counter
Course Goals
! Understand
! Transistors, wires, deep submicron issues ! delay, power and energy for digital circuits ! digital circuit design concepts, basic digital cells, sequencing elements ! Clocking, clock distribution techniques, timing constraints ! Memory structures ! Low power techniques like power gating, multithreshold, sizing, parallelism, minimum energy operation ! IO and packaging
Logistics
Class Timings: M-W-F 11:15am to 12:30pm Lab Timings: Anytime you can get access to a machine with opensource tools: Electric and LTI-SPICE Grading: 1st Quiz (Jan end), Midterm (Feb end), Mini-project (Mar end), Final (first week of December)
Text:
CMOS VLSI Design. 4th Edition. Weste/Harris