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Pin
+ + (1 + in ) = = V1 + V1 V1
Zin VS Zin + ZS
+ Solve for V1
+ (1 + in ) = V1
VS 1 S 2 1 in S
V2
The operating power gain can be written in terms of the two-port s-parameters and the load reection coefcient |S21 |2 (1 |L |2 ) PL = Gp = Pin |1 S22 L |2 (1 |in |2 )
+ 2 V1a 2Z0
2 (1 | S| )
+ V1 a
+ V1
in = S
VS 1 S = 2 1 |S |2
Pavs
|VS |2 |1 S |2 = 8Z0 1 |S |2
Transducer Gain
The transducer gain can be easily derived PL |S21 |2 (1 |L |2 )(1 |S |2 ) = = Pavs |1 in S |2 |1 S22 L |2
GT
Note that as expected, GT is a function of the two-port s-parameters and the load and source impedance. If the two port is connected to a source and load with impedance Z0 , then we have L = S = 0 and GT = |S21 |2
Unilateral Gain
M2
Z0
GS
|S21 |
GL
If S12 0, we can simplify the expression by just assuming S12 = 0. This is the unilateral assumption 1 |S |2
2
GT U =
|1 S11 S |
|S21 |
|1 S22 L |
1 |L |2
= GS |S21 |2 GL
The gain partitions into three terms, which can be interpreted as the gain from the source matching network, the gain of the two port, and the gain of the load. In reality the source/load matching network are passive and hopefully lossless, so the power gain is 1 or less, but by virtue of the matching network we can change the gain of the two-port.
University of California, Berkeley EECS 242 p. 6/20
We know that the maximum gain occurs for the biconjugate match
S = S11 L = S22
GS,max =
GL,max =
GT U,max =
Note that if |S11 | = 1 of |S22 | = 1, the maximum gain is innity. This is the unstable case since |Sii | > 1 is potentially unstable.
Ideal MOSFET
Cgs
+ vin
gm vin
ro
Cds
The AC equivalent circuit for a MOSFET at low to moderate frequencies is shown above. Since |S11 | = 1, this circuit has innite power gain. This is a trivial fact since the gate capacitance cannot dissipate power whereas the output can deliver real power to the load.
Real MOSFET
Ri + vs Ri + vin
Cgs
gm vin
R ds
Cds
R ds
A more realistic equivalent circuit is shown above. If we make the unilateral assumption, then the input and output power can be easily calculated. Assume we conjugate match the input/output |VS |2 = 8Ri
1 2
Pavs
1 )= IL VL PL = ( 2
GT U,max
2 V 1 2 = gm Rds Ri VS
gm V1 2 2 Rds
At the center resonant frequency, the voltage at the input of the FET is given by V1 = 1 VS jCgs 2Ri
GT U,max
This can be written in terms of the device unity gain frequency fT GT U,max 1 Rds = 4 Ri fT f 2
The above expression is very insightful. To maximum power gain we should maximize the device fT and minimize the input resistance while maximizing the output resistance.
So far we have only discussed power gain using bi-conjugate matching. This is possible when the device is unconditionally stable. In many case, though, wed like to design with a potentially unstable device. Moreover, we would like to introduce more exibility in the design. We can trade off gain for
We can make this tradeoff by identifying a range of source/load impedances that can realize a given value of power gain. While maximum gain is acheived for a single point on the Smith Chart, we will nd that a lot more exibility if we back-off from the peak gain.
Unilateral Design
No real transistor is unilateral. But most are predominantly unilateral, or else we use cascades of devices (such as the cascode) to realize such a device. The unilateral gure of merit can be used to test the validity of the unilateral assumption Um = |S12 |2 |S21 |2 |S11 |2 |S22 |2 (1 |S11 |2 )(1 |S22 |2 )
It can be shown that the transducer gain satises the following inequality GT 1 1 < < (1 + U )2 GT U (1 U )2
Where the actual power gain GT is compared to the power gain under the unilateral assumption GT U . If the inequality is tight, say on the order of 0.1 dB, then the amplier can be assumed to be unilateral with negligible error.
Gain Circles
We now can plot gain circles for the source and load. Let gS = GS GS,max GL GL,max
gL =
By denition, 0 gS 1 and 0 gL 1. One can show that a xed value of gS represents a circle on the S plane 2 1 gS (1 |S11 | ) S11 gS S = |S11 |2 (gS 1) + 1 |S11 |2 (gS 1) + 1
More simply, |S CS | = RS . A similar equation can be derived for the load. corresponding to the maximum gain. Note that for gS = 1, RS = 0, and CS = S11
0.14 0.36
0.1
0 .09 0.4 1
55
0.39
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OM PO NE NT (+ jX /Z o
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CT AN C
EC
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IND UCT IV E
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1.8
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1.2
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5 -4
. We can select any desired All gain circles lie on the line given by the angle of Sii value of source/load reection coefcient to acheive the desired gain. To minimize the impedance mismatch, and thus maximize the bandwidth, we should select a point closest to the origin.
University of California, Berkeley EECS 242 p. 14/20
0.3
0.1
-25
3 0.3
0.1
-30
0.3
0.1
-35
0.35
0.15
0.36
0.14
-4
0.37
0.13
0.4
0.2
0.12
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0.11
0.39
0.1
0.4
CAP AC
ITIV
0.0
0.4
RE AC TA NC EC O M PO NE NT (
.08
0.4
0.4
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4.0
gS = 3 dB
0.8
-10
gS = 2 dB
0.8
10
gS = 1 dB
0.4
50
20
5.0
-20
3.0
1.0
0.6
0.2
S11
0.8
0.6
0.4
0.0
0.4
0.4
0.2
20
0.3
0.6
3.0
1 0.2 9 0.2
0.3
0.8
4.0
15
0.22
gS = 0 dB
1.0
0.28
5.0
10
0.2
0.23
0.27
OF ANGLE
10 0.1
20
50
0.25 0.24 0.26 C OF REFLECTION OEFFICIENT IN DEGREES ANGLE TRANSMISSION COEFFICIENT IN DEGRE ES
0.23 0.27
0.24
0.25
0.26
0.22
0.2 1 0.2 9
0.28
0.2 0.3
0.1 9 0.3 1
For || > 1, we can still employ the Smith Chart if we make the following mapping. The reection coefcient for a negative resistance is given by (R + jX ) = (R + Z0 ) jX R + jX Z0 = R + jX + Z0 (R Z0 ) jX
1 (R Z0 ) + jX = (R + Z0 ) + jX
We see that can be mapped to the unit circle by taking 1/ and reading the resistance value (and noting that its actually negative).
For a unilateral two-port with |S11 | > 1, we note that the input impedance has a negative real part. Thus we can still design a stable amplier as long as the source resistance is larger than (Zin ) (ZS ) > |(Zin )|
The same is true of the load impedance if |S22 | > 1. Thus the design procedure is identical to before as long as we avoid source or load reection coefcients with real part less than the critical value.
Consider a transistor with the following S -Parameters S11 = 2.02 130.4 S22 = 0.50 70
0.11
0.12 0.38
0.13
0.37
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0.1
0.39
0.15
50
45
0
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0.4
0.35
1.0
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6
0.1 0.3 3 7
0.8
1.2
40
55
0.6 60
2 0.4
0.7
1.4
35
1.6
0.0
7 0.4 3
0.0
REA 75 CT AN CE CO MP ON EN T( +j X/ Zo
R ), O
o) jB/Y E (+ NC TA EP SC U ES TIV CI PA CA
65
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30
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0.1 0.3
2.0
0.2
2
9 0.1
0.0 6
0.4 4
25
0.4
1 0.3
0.4 6
s
RS CS
0.0 4
le tab
region
0.6
0.4
20
3.0
1 0.2 9 0.2
> WAVEL ENGTH S TOW ARD 0.49 GEN ERA 0.48 TOR
GS = 5 dB
1.0 1.0
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0.8
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10
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0.3
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1.2
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3.0
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IVE CT DU IN
-75
R ,O o) /Z jX
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1.4
0.8
0.9
1.0
1.2
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0 -5
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0.3
0.1
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0.1
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0.3
0.1
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0.35
0.15
0.36
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0.1
0.4
CAP AC ITIV E
0.0
0.4
RE AC TA NC E CO M PO NE NT (-
0.4
-10
5.0
1 S11
0.6
0.8
50
20
-15
4.0
-20
3.0
1.0
0.8
0.6
0.4
S
0.2
10
20
50
Since |S11 | > 1, the amplier is potentially unstable. We to nd begin by plotting 1/S11 the negative real input resistance. Now any source inside this circle is stable, since (ZS ) > (Zin ). We also draw the source gain circle for GS = 5 dB.
0.47
85
90
0.8
0.6
0.0
0.4 2
0.0
0.4
0.4
70
0.2 0.3
0.3
0.28
0.2
0.23
0.27
0.25 0.24 0.26 CO OF REFLECTION EFFICIENT IN DEGREES ANGLE ISSION COEFFICIENT IN D EGREES OF TRANSM ANGLE
0.1
0.24
0.25
0.26
0.23
0.27
0.22
0.2 1 0.2 9
0.28
0.2 0.3
0.1 9 0.3 1
. Note the real part is The input impedance is read off the Smith Chart from 1/S11 interpreted as negative Zin = 50(0.4 0.4j )
1 |S11 | (1 gS )
= 0.236
CS =
1 |S11 |2 (1 gS )
= .3 + 0.35j
We can select any point on this circle and obtain a stable gain of 5 dB. In particular, we can pick a point near the origin (to maximize the BW) but with as large of a real impedance as possible: ZS = 50(0.75 + 0.4j )
In the bilateral case, we will work with the power gain Gp . The transducer gain is not used since the source impedance is a function of the load impedaance. Gp , on the other hand, is only a function of the load. |S21 |2 (1 |L |2 ) Gp = = |S21 |2 gp 2 11 L 2 1 S | 1 S | 22 L 1S
22 L
It can be shown that gp is a circle on the L plane. The radius and center are given by q 2 1 2K |S12 S21 |gp + |S12 S21 |2 gp RL = 2 2 2 1 |S22 | gp + || gp CL = 1 + gp (|S22 |2 ||2 )
S ) gp (S22 11
We can also use this formula to nd the maximum gain. We know that this occurs when RL = 0, or
2 =0 1 2K |S12 S21 |gp,max + |S12 S21 |2 gp,max
The design procedure is as follows 1. Specify gp 2. Draw operating gain circle. 3. Draw load stability circle. Select L that is in the stable region and not too close to the stability circle. 4. Draw source stability circle. 5. To maximize gain, calculate in and check to see if S = in is in the stable region. If not, iterate on L or compromise.