EEE 433/591 Fall 2013 - Final Project

Final Lab Report Grade: Last Name: Venepally First Name: Jashwanth ID: 1206445964

(10) Objectives / Requirements (50) Opamp (30) Buffer / second stage (30) Load Drive Stage (80) Overall system uncompensated & compensated (50) Comparison / Conclusion Total Grade : _______________ / 250

Venepally Jashwanth

EEE 433/591 Fall 2013 - Final Project 1. Lab Objective:

The objective of this lab is to design a Low Drop-Out voltage regulator with a regulated voltage of 2.25V. A voltage regulator is needed to maintain a stable voltage for varying load conditions. It is especially important in portable/mobile devices where the battery is continuously discharging, it is essential to provide a regulated voltage. Else the electronic circuitry may get damaged. A LDO finds application in portable electronics, medical equipment, telecommunications etc. Absence of a LDO in electronic circuitry may prove to be catastrophic because of varying voltages. Hence a LDO is very important. It's importance is only growing with the growth of portable mobile devices.

Requirements:
Voltage supply 2.5 V, 0.35 Micron CMOS Process Delivers 50 mA current Output Regulated Voltage of 2.25 V VRipple <5%

Overall System:

LDO regulator: symbol view The first stage is a Differential amplifier, followed by buffer and driver stages. It is a closed loop system with the feedback implemented by a resistor divider circuit. The load has a capacitance of 100nF and an associated ESR of 0.5m Ohms. The LDO is expected to maintain a regulated voltage of 2.25V for various load currents. These load currents is implemented using a current source drawing different currents in the specified range. The choice of the individual stages and their design is explained in the following sections. Venepally Jashwanth 2

EEE 433/591 Fall 2013 - Final Project 2. Amplifier Design

Objective: The objective is to design a differential amplifier which serves as the first stage of LDO. The gain of this amplifier is expected to be high. The requirement is 50-60 dB. Therefore I have chosen a cascode differential amplifier with 9 transistors to achieve the required gain because the normal differential amplifier with 5 transistors can provide a maximum speed of 30dB. Specifications: Amplifier : Cascode Differential Amplifier Gain : 50-60dB Common mode i/p : 1.125V Output voltage : vdd/2=1.25 The schematic for the Differential Amplifier is

Differential Amplifier

The transistors are marked p0,p1,p2,p3,no,n1,n2,n3,n4 in the schematic.

2.1 DC
2.1.1 Analysis: The current through the tail transistor is 10uA. Therefore a current of 5uA flows through each of the two branches of the diff amp. Let veff=0.1V The output has to be biased at vdd/2=1.25V. For PMOS: Venepally Jashwanth 3

EEE 433/591 Fall 2013 - Final Project

w= 3.133u since the PMOS are diode connected vsd=vsg=veff+vth= 0.1+0.54=0.64 (vsd,vsg are the same for all the PMOS transistors here) the output is at vout= vdd-(vsd1+vsd2)=2.5-2*0.64= 1.22 For NMOS: Let veff=0.1V L=300n Kn= 274u w comes out to be w= 1.094u vgs= veff+vth = 0.1+0.5= 0.6V vds=vdSat= 0.1v For the tail transistor: I=10uA w/l= 450/300n 2.1.2 DC Simulations: The simulated diff amp is shown below

From these values and the current equ veff= 0.22V vgs= veff+vth = 0.22+0.5= 0.72V

Differential Amplifier: DC simulations

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EEE 433/591 Fall 2013 - Final Project

VGS (mv) -705.1 -705.1 -578.4 -578.4 629.9 629.9 718.4 718.4 757.8 IDS (uA) -5.143 -5.143 -5.143 -5.143 5.143 5.143 5.143 5.143 10.27 VDS (mv) -705.1 -705.1 -578.4 -578.4 220.6 220.6 563.6 563.6 432.1 W(uM)/L(nM) 3.133/300=10.443 3.133/300 =10.443 3.133/300 =10.443 3.133/300 =10.443 1.094/300 = 3.649 1.094/300= 3.649 1.094/300= 3.649 1.094/300= 3.649 450n/300n=1.5

P0 P1 P2 P3 N0 N1 N2 N3 N4

2.1.3. DC Comparisons: For NMOS: vgs= veff+vth = 0.1+0.5= 0.6V vds=vdSat= 0.1v For Tail transistor: vgs=0.22V vgs= veff+vth = 0.22+0.5= 0.72V

For PMOS: since the PMOS are diode connected vsd=vsg=veff+vth= 0.1+0.54=0.64 (vsd,vsg are the same for all the PMOS transistors here) VGS (mV) Analysis/ Simulations -640/ -705.1 -640/ -705.1 -640/ -578.4 -640/ -578.4 600/629.9 600/629.9 600/718.4 600/718.4 720/757.8 IDS (UA) Analysis/ Simulations -5/-5.143 -5/-5.143 -5/-5.143 -5/-5.143 5/5.143 5/5.143 5/5.143 5/5.143 10/10.27 VDS Analysis/ Simulations -640/ -705.1 -640/ -705.1 -640/ -578.4 -640/ -578.4 100/220.6 100/220.6 100/563.6 100/563.6 220/432.1

P0 P1 P2 P3 N0 N1 N2 N3 N4

The values are close. The error is possibly due to the current equation is an approximation and further it neglects the channel-length modulation effect. 2.2 AC 2.2.1 Analysis: Output Impedance: The output impedance can be approximated to be rout= (gmp1*rds3*rds1) * (gmn3*rds3*rds1) From cadence: gmp1=68.22u gdsp1=1.103u gdsp3= 1.176u gmn3= 74.14u gds3=2.293u gds1= 3.40u Therefore rout= 499.4MOhms. Input Impedance: The current flowing in to the gate is almost zero. Therefore rin= infnity Transconductance: Gm= The transconductance for a cascoded diff amp is given by Venepally Jashwanth 5

EEE 433/591 Fall 2013 - Final Project

Gm= -gmp1. gmn1. (r0p||gmn1rrds1|| Gain: Gain: Gm* Rout= 74.14u*499M= 80dB 2.2.2 Simulations: Gain: ) = -gmn1=74.14u

gain: 55dB Input Impedance:

input impedance= 1/1.55E-11=64G Ohms

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EEE 433/591 Fall 2013 - Final Project

Output Impedance:

output impedance= 1/9.22E-8=10.8M Ohms Transconductance: Gm=

transconductance: 1.37E-6 gm 1.37E-6 Ro 10.8M Rin 64G gain 55dB 7

Simulations Venepally Jashwanth

EEE 433/591 Fall 2013 - Final Project

2.2.3 Comparison: gm 74.4E-6 1.37E-6 Ro 500M 10.8M Rin infinity 64G gain 80dB 55dB

Analysis Simulations

2.3 Frequency Response:

2.3.1 Analysis: The dominant pole is given by Rout( from as calculated in the AC analysis above)= 500M Ohms cout= cdbp1+cdsn3+cgdn3+cgdp1+cgdn3(1+1/A)= 0.93f( values taken from cadence) f= 0.34M Hz 2.3.2 Simulations:

Pole freq is around 1M Hz 2.3.3 Comparison:

Diff Amp 3-dB pole analysis 0.3 MHz simulations 1MHz

Venepally Jashwanth

EEE 433/591 Fall 2013 - Final Project 3. Buffer Stage: Objective:

The objective is to design a buffer stage. Here I implement it using a PMOS buffer. The buffer is used to avoid the impedance mismatch that exists between a diff amp and PMOS pass transistor. The output impedance of a cascoded differential amplifier is very high. Connecting it directly to a driver PMOS transistor would lead to impedance mismatch. Therefore a voltage buffer is introduced between the two. The buffer stage has high input impedance and relatively low output impedance. Thus it takes care of impedance matching. Buffer stage can be implemented by both PMOS or NMOS buffer. The choice of PMOS buffer is because it operates at relatively low AC voltages at its gate terminal. Since we are using a cascode Diff Amp in the previous stage, its output AC swing is severely restricted because of the cascode implementation. So a PMOS buffer would be more beneficial here. Specifications: Voltage gain: 1V/V Input Impedance: High Output impedance: Low The schematic for buffer is shown below

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EEE 433/591 Fall 2013 - Final Project

3.1 DC: 3.1.1 Analysis: The top PMOS is for current mirror. We chose a current of 10uA to be flowing through the PMOS's. therefore its W/L is same as the one used in the current mirroring circuit i.e W/L= 450/300n. for the bottom PMOS Let veff= 0.1V and Current through the PMOS's be 10uA then using w= 6.266u. also, vsg= veff+vth=0.64V 3.2.2 DC Simulations: vsd> veff

P1 P0

VGS (mA) -938.8 -752.4

IDS (uA) -9.65 -9.65

VDS (mA) W/L -747.6m 450n/300n 1752 6.266u/300n=20.88

3.2.3 Comparision: For PMOS P0: w= 6.266u. also, vsg= veff+vth=0.64V Venepally Jashwanth

vsd> veff 10

EEE 433/591 Fall 2013 - Final Project

P0 Simulation Analysis

VGS (mA) -752.4 -640m

IDS (uA) -9.65 -10u

VDS (mA) 1752 -

W/L 6.266u/300n=20.88 6.266u/300n=20.88

3.2 AC 3.2.1 Analysis: Input Impedance: The current flowing in to the gate is 0 therefore rin= infinity

Output Impedance: rds0||rds1 from cadence gds1= 1.853u gds2=1.902u rout= 0.265M Transconductance: Gm The transconductance is equal to transconductnce of P0= gm from Cadence gm=134.5u AC Voltage Gain: The AC voltage gain of an amplifier is 1V/V. that is 0dB 3.2.2 AC SIMULATIONS: Input Impedance:

Input Impedance: 36G

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Output Impedance:

output Impedance: 0.84M Transconductance: gm

gm= 916u

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AC gain:

Parameter Values

gm 916u

gain=-2.3dB Ro 0.84M

Rin 36G

Gain dB -2.3

3.2.3 Comparison: gm Analysis 134.5u Simulations 916u

Ro 0.26M 0.84M

Rin infinity 36G

Gain dB 0 -2.3

3.3 Frequency Response: 3.3.1 Analysis: Pole of the buffer as calculated in part 2 of this lab was taking values from cadence this values turns out to be fp= 41.9M Hz 3.3.2 simulations:

frequency response of buffer: 3-dB pole 515MHz Venepally Jashwanth 13

EEE 433/591 Fall 2013 - Final Project

3.3.3 Comparisons:
Buffer 3-dB pole analysis 41.9M Hz simulations 515MHz

4. Driver Circuit: Objective: The objective is to design a driver transistor which drives the load. It should be able to drive a range of currents like 1mA-50mA. Also, the voltage drop across its source-drain should be less i.e 250mv since we are implementing a low drop-out voltage regulator. The choice for driver circuit is PMOS source follower. The PMOS source follower is chosen over NMOS source follower because of the Diff Amp type we have chosen to implement. The cascode Diff Amp with 9 transistor implementation does not have a large voltage swing /headroom at its output. This small AC voltage cannot drive a NMOS gate to ON state. Whereas for a PMOS no such problem exists because it takes the difference of Source and Drain voltages. Requirements: Current drive: 1mA-50mA Voltage drop: 250mV Regulated Voltage: 2.25V 4.1 DC 4.1.1 Analysis: The output regulated voltage is 2.25V i.e Vdrain=Vd=2.25 Vsource= Vs=2.5V Vds= 0.25=250m Vsd> Vsg- |Vtp| ==> Vg > Vd- |Vtp| ==> Vg > 1.71V Vsg=Vs-Vg< 2.5-1.71= 1.79V ; L=300nM, Kp= 95.75u

for I=1mA upon calculation w turns out to be w= 0.1m for I=25mA upon calculation w turns out to be w= 2.5m for I=25mA upon calculation w turns out to be w= 5m For all the cases Vsg and Vsd are shown above

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4.2.2 Simulations:

The figures show the DC biasing points of the pass transistor for i=1m,50m,25mA. The values are tabulated as below.

PASS For i=1mA For i=25mA For i=50mA

VGS mV -474.9 -701.6 -792

IDS mA -1 -25 -50

VDS mV -249.5 -250.3 -250.6

W/L 0.1m/300n 2.5m/300n 5m/300n

4.1.3 Comparisons: VGS Analysis/ Simulations For i=1mA For i=25mA For i=50mA <-1.79V/-474.9 <-1.79V/-701.6 <-1.79V/-792

IDS Analysis/ Simulations -1/-1 -25/-25 -50/-50

VDS (mA) Analysis/ Simulations -250/-249.5 -250/-250.3 -250/-250.6

4.2 AC 4.2.1 Analysis: Input impedance: The current flowing in to the gate is 0. Therefore rin= infinity Output impedance: without any load. just for the Pass transistor output impedance = rds1= 1/gds= 1/41.43m= 24.1 Ohms Transconductance: The transconcutance is gm= 311.9m A/V Gain: The gain is gm. rds = 7.4V/V= 17.5dB

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4.2.2 Simulations: Input impedance:

Input impedance: 1.1M Output impedance:

Output impedance:158 Ohms

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EEE 433/591 Fall 2013 - Final Project

AC gain:

AC gain at low frequency: 34.9dB Transconductane:

Transconductane= 176m gm Pass 311.9u ro 158 Ohms gain dB 34.9 rin 1.1M Ohms

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EEE 433/591 Fall 2013 - Final Project

4.2.3 Comparisons: gm 311.9u 176m Ro 24.1 Ohms 158 Ohms Rin infinity 1.1M Ohms Gain dB 17 34.9

Analysis Simulations

4,3 Frequency response: 4.3.1 Analysis: The significant pole at the output can be approximated as( as explained in part-2 of the lab report) : Taking values from cadence Ro= 1/gds=24 Ohms: Cload= 1uF Therefore fp turns out to be 6.6KHz 4.3.2 Simulations:

Frequency response of pass transistor: pole occurs at 34.5kHz 4.3.3 Comparison:

Pass Transistor 3-dB pole analysis 6.6kHz simulation 34.5kHz

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EEE 433/591 Fall 2013 - Final Project 5. Complete System Analysis:

5.1 DC: For 1mA:

For 25mA:

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For 50mA:

For i=1mA P2 Vgs(mv) -610.8 Vds(mv) -610.8 Id(uA) -5.135

P3 -610.8 -610.8 -5.135

P0 -742 -742 -5.13

P1 -742.7 -691.9 -5.135

N2 720 496.2 5.135

N3 718.8 545.7 5.135

N0 692.9 218 5.135

N1 692.8 220.1 5.135

Ntail 757 432 10.2

Pbuff -720 -1.919 -1.924

Pdriver -581.3 -2.499 -1mA

For i=25mA P2 Vgs(mv) -610.8 Vds(mv) -610.8 Id(uA) -5.135 For i=50mA P2 Vgs(mv) -610.8 Vds(mv) -610.8 Id(uA) -5.132

P3 -610.8 -610.8 -5.135

P0 -742 -742 -5.13

P1 -740.8 -826.8 -5.135

N2 720 496.2 5.135

N3 722.2 412 5.135

N0 692.9 219 5.135

N1 693 216.8 5.135

Ntail 757 432 10.2

Pbuff -745.7 -1.807 -1.974

Pdriver -693.1 -250 -25mA

P3 -610.8 -610.8 -5.132

P0 -741 -742 -5.13

P1 -739.4 -930.9 -5.132

N2 720 496.2 5.132

N3 723.1 310 5.132

N0 692.8 219.1 5.132

N1 693.1 214.1 5.132

Ntail 757 431 10.2

Pbuff -764.5 -1.72 -2.011

Pdriver -779.5 -250 -50mA

For all the currents the voltage at the output is regulated at 2.25V. The figures for DC are shown above the tables.

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5.2 AC:

Magnitude and phase plots of the overall system: for i=1mA

Gain= 91.76dB Gain crossover: wgx= 2.087MHz Phase Crossover: wpx =1.119MHz wgx> wpx==> Overall system is unstable Poles: one pole at95.5Hz, 108.7kHz, 1MHz Zeros: Zero at 949.9Hz

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EEE 433/591 Fall 2013 - Final Project

for i=25mA

Gain= 82.55dB Gain crossover: wgx= 4.659MHz Phase Crossover: wpx =1.018MHz wgx> wpx==> Overall system is unstable Poles: one pole at 8.598KHz, 637.5kHz,2MHz Zeros: Zero at 91.56kHz Phase margin: -248+180=-68 for i=50mA

Gain= 71.61dB Venepally Jashwanth 22

EEE 433/591 Fall 2013 - Final Project

Gain crossover: wgx= 5.156MHz Phase Crossover: wpx =1.105MHz wgx> wpx==> Overall system is unstable Poles: one pole at 9.12KHz, two poles 978.9kHz,5MHz Zeros: Zero at 95.33KHz
gain dB gain crossover Hz phase crossover Hz phase margin deg poles Hz zeros Hz for 1mA 91.76 2.087M 1.119MM 95.5, 108.7k,1Mhz 949.9k for 25mA 82.5 4.659M 1.028M 8.59k, 637.5k, 2MHz 9.15k for 50mA 71.6 5.156M 1.105M 912k, 2 978.9k,5MHz 95.33k

The magnitude and phase plots for the individual blocks: The plots are drawn for a current of 25mA. at the output of diff amp:

The poles, gain and zeros are marked in the graph. Their values and analysis is given in the tables below. at the output of buffer:

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Frequency response of buffer for 25mA

gain dB 3dB pole gain crossover phase crossover Diff Amp 56.87 484.4k 294.9M Buffer 55.1 589.4k 23.7M -

Overall open loop System gain is without compensation: 71.6dB Bandwidth: 5.16M Hz 5.3 Transient uncompensated:

vripple= (2.37-2.1)/2.5= 0.108% Settling time: the system was found to be unstable. In fact it was found to be marginally stable. So it keeps oscillating.

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5.5 Compensated system: The system above was found to be unstable. Therefore I compensated it with a capacitor. A capacitor at the output adds an extra pole. Therefore the gain falls faster than in the previous case. By the time it reaches wpx, it would have fallen adequately so that at phase crossover its gain is less than 1. hence the system stabilizes. The capacitance value that i chose to compensate is 50uF 5.5.1 AC The magnitude and phase plots of the overall system: for 1mA:

for 25mA:

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EEE 433/591 Fall 2013 - Final Project

for 50mA:

gain dB gain crossover Hz phase crossover Hz phase margin deg poles Hz zeros Hz

for 1mA 83.3 18.6k 1.17M 89 1.98,1.047M,10M 28.08

for 25mA 82.34 203.6K 996.9K 68.8 1100.4,55.88K,9.7M 304K

for 50mA 71.6 243K 1.057m 67 102, 243.9K,1.69M 1.479K

The magnitude and phase plots for the individual blocks: at the differential amplifier:

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EEE 433/591 Fall 2013 - Final Project

at buffer:

gain dB 3dB pole gain crossover phase crossover

Diff Amp 55.8 456.8k 294.6M -

Buffer 54 56.1k 23.7M -

5.5.2 Transient response: the transient response after compensation is given by

Upon zooming in, the same graph looks like Venepally Jashwanth 27

EEE 433/591 Fall 2013 - Final Project

ripple: (2.2495-2.2493)/2.5=0.008% settling time: 100uSec

Compensated 0.108% 100uSec Uncompensated 0.008% system doesn't settle

Ripple Settling time

6. Comparison/ Conclusion:
Op-Amp: we set out design an op-amp with a very high gain so that it acts as a good error amplifier. 50-60 dB gain was sufficient. I have designed a op-amp with a gain of 62dB. Since such a high gain is not possible with 5 transistor differential amplifier, I chose a cascodeddifferential amplifier. The output of the op-amp is biased at vdd/2. Buffer Stage: The buffer stage is used to avoid impedance missmatch between the op-amp and pass transistor. The buffer has a very high input impedance and moderaltely output impedance. The voltage gain of the buffer was designed to be 0dB. The buffer was implemented using a PMOS transistor. Load Stage: The load/ driver transistor is used to regulate the output voltage at 2.25V irrespective of the Load currents. For all the varying currents in the load, the output was regulated at 2.25V. Since a Low drop out is required it cannot be implemented using a NMOS transistor. So I designed the driver stage with PMOS of width 6m. Over-all Feedback System: Venepally Jashwanth 28

EEE 433/591 Fall 2013 - Final Project

The feedback is used to sample a part of the output voltage to the op-amp so that it can do corrections necessary so as to maintain the voltage at 2.25V. The feedback circuitry was implemented using resistor voltage divider circuit. Since we chose to implement it using resistors, not much variations occur in their values. Hence although variations occur in the active devices, the passive resistors are not prone to changes. hence the output gain can be maintained constant. 6.1 DC Parameters: For the various currents, all the transistors have to be maintained in saturation under all conditions. also, the output has to be regulated at 2.25V. The DC operating points of the transistors at various currents in the feedback is shown in the tables below. For i=1mA P2 Vgs(mv) -610.8 Vds(mv) -610.8 Id(uA) -5.135

P3 -610.8 -610.8 -5.135

P0 -742 -742 -5.13

P1 -742.7 -691.9 -5.135

N2 720 496.2 5.135

N3 718.8 545.7 5.135

N0 692.9 218 5.135

N1 692.8 220.1 5.135

Ntail 757 432 10.2

Pbuff -720 -1.919 -1.924

Pdriver -581.3 -2.499 -1mA

For i=25mA P2 Vgs(mv) -610.8 Vds(mv) -610.8 Id(uA) -5.135 For i=50mA P2 Vgs(mv) -610.8 Vds(mv) -610.8 Id(uA) -5.132

P3 -610.8 -610.8 -5.135

P0 -742 -742 -5.13

P1 -740.8 -826.8 -5.135

N2 720 496.2 5.135

N3 722.2 412 5.135

N0 692.9 219 5.135

N1 693 216.8 5.135

Ntail 757 432 10.2

Pbuff -745.7 -1.807 -1.974

Pdriver -693.1 -250 -25mA

P3 -610.8 -610.8 -5.132

P0 -741 -742 -5.13

P1 -739.4 -930.9 -5.132

N2 720 496.2 5.132

N3 723.1 310 5.132

N0 692.8 219.1 5.132

N1 693.1 214.1 5.132

Ntail 757 431 10.2

Pbuff -764.5 -1.72 -2.011

Pdriver -779.5 -250 -50mA

6.2 AC Parameters: The various AC parameters are summarized in the tables below: Differential Amp Buffer Pass Gain (dB) f3dB (MHz) P2 P3 Unity BW Analysis 80 0.3M 41.9M 6.6K Simulation 55 1M 515M 34.5K 5.16M 70 80 Error % 31 91

Final Discussion: An LDO is designed with a regulated voltage of 2.25V. The transient analysis is plotted and the ripple time is found to be 0.18%. Settling time is 100usec.

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Output Regulated Voltage: 2.25V Ripple: 0.18% Settling time: 100usec Issues: Initially an LDO was designed but it was found to be unstable. We Did not have enough phase margin. Then I used compensation techniques to adjust the poles so that the overall feedback system was stable. I did the compensation using a capacitor of 60uF at the load. The uncompensated and compensated phase margins was found to be For uncompensated:
gain dB gain crossover Hz phase crossover Hz phase margin deg for 1mA 91.76 2.087M 1.119MM for 25mA 82.5 4.659M 1.028M for 50mA 71.6 5.156M 1.105M -

For compensated:
gain dB gain crossover Hz phase crossover Hz phase margin deg for 1mA 83.3 18.6k 1.17M 89 for 25mA 82.34 203.6K 996.9K 68.8 for 50mA 71.6 243K 1.057m 67

Improvements: Since the compensation was done using a capacitor at the output, slew rate at the output decreases. Instead by using lead compensation technique this can be avoided. To make the system insusceptible to changes in the output load, a high gain error amplifier may be used. The settling time was found to be 100usec. In application where this amount of settling time is not acceptable, I can decrease it by using higher current drive in the LDO and by chooisng a Q-factor that is optimal. Result: I have designed an LDO with the required specifications.

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