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com

circuits on a sin le chip first occurre' in

PAPER ON

the 1()0s as part of the semicon'uctor an' communication technolo ies that were *ein 'evelope'. #he first semicon'uctor chips hel' one transistor each. !u*se+uent a'vances a''e' more an' more transistors, an' as a conse+uence more in'ivi'ual functions or systems were inte rate' over time. #he microprocessor is a VL!" 'evice.VL!" involves 'esi nin an' implementation of circuits to provi'e more computational spee' with less power 'issipation an' less circuit *oar' area. #he electronics in'ustry has achieve' a phenomenal rowth over the last two 'eca'es 'ue to the rapi' a'vances in inte ration technolo ies an' lar e$scale systems 'esi n. As the nee' for more comple- an' faster processin 'evices on a smaller chip is increasin , there has *een a stea'y rise an' a'vance in the inte ration technolo y. .or e-ample, the "N#EL Pentium$/

VERY LARGE SCALE INTEGRATION DESIGN AND ITS APPLICATIONS

Very Lar e !cale "nte ration

Abstract
#he concept of Very$lar e$scale inte ration %VL!"& into inte rate' www.1000projects.com www.fullinterview.com www.chetanasprojects.com

processor has more than 00 million on$ chip transistors. "n this paper we have covere' the evolution of VL!", 'esi n

www.1000projects.com www.fullinterview.com www.chetanasprojects.com concepts an' metho'olo ies use', fa*rication process, limitations, future challen es an' some applications.

*oore. #hese projections he ma'e *ase' on this pattern have *ecome 1nown as the *oore+s la,)

Introduction
Historical perspecti e! #he num*er of applications of inte rate' circuits in hi h$performance computin , telecommunications, an' consumer electronics has *een risin stea'ily, an' at a very fast pace. #his tren' is e-pecte' to continue, with very important implications on VL!" an' systems 'esi n .#a*le 1 shows the evolution of lo ic comple-ity in inte rate' circuits over the last three 'eca'es, an' mar1s the milestones of each era.

De$inition!
Very Lar e !cale "nte ration is term 'escri*in a*out semicon'uctor inte rate' circuits compose' of hun're's of thousan's of lo ic elements or memory cells. VL!" is the techni+ue of circuit 'esi nin an' implementation to provi'e more computational spee' with less power 'issipation an' less circuit *oar' area.

-i%) # " E olution o$ inte%ration densit( and &ini&u& $eature si.e/ as seen in t0e earl( Table "#! E olution o$ lo%ic co&ple'it( in inte%rated circuits) E-ample for 2L!" chips is the "N#EL Pentium$/ processor, which has more than 00 million transistors.#his e-ponential rowth pattern in the inte rate' circuit function was earlier envisa e' in the late 1(30s *y Gordon www.1000projects.com www.fullinterview.com www.chetanasprojects.com #123s) #hus the VL!" techni+ue provi'es less area4volume an' therefore, compactness,less power consumption,less testin re+uirements at system level,hi her relia*ility, mainly 'ue to improve' on$chip

www.1000projects.com www.fullinterview.com www.chetanasprojects.com interconnects,hi her spee', 'ue to si nificantly re'uce' interconnection len th,si nificant cost savin s.

Desi%n
VLSI Desi%n -lo,! #he 'esi n process, at various levels, is usually evolutionary in nature. "t starts with a iven set of re+uirements. "nitial 'esi n is 'evelope' an' teste' a ainst the re+uirements. 5hen re+uirements are not met, the 'esi n has to *e improve'. "f such improvement is either not possi*le or too costly, then the revision of re+uirements an' its impact analysis must *e consi'ere'. #he 6$ chart %first intro'uce' *y 7. 8ajs1i& shown in the followin fi ure illustrates a 'esi n flow for most lo ic chips, usin 'esi n activities on three 'ifferent a-es %'omains&, which resem*le the letter 6. #he 6$chart consists of three major 'omains, namely9 : *ehavioral 'omain, : structural 'omain, : eometrical layout 'omain. -i%) 4 " T(pical VLSI desi%n $lo, in t0ree do&ains 5Y"c0art representation6) #he 'esi n flow starts from the al orithm that 'escri*es the *ehavior of the tar et chip. #he correspon'in architecture of the processor is first 'efine'. "t is mappe' onto the chip surface *y floor plannin . #he ne-t 'esi n evolution in the *ehavioral 'omain 'efines .inite !tate ;achines %.!;s&, which are structurally implemente' with functional mo'ules. #hese mo'ules are then eometrically place' onto the chip surface usin <A7 tools for automatic mo'ule placement followe' *y routin , with a oal of minimi=in interconnects area an' si nal 'elays. At thir' sta e the chip is 'escri*e' in terms of lo ic ates %leaf cells&, which can *e place' an' www.1000projects.com www.fullinterview.com www.chetanasprojects.com

www.1000projects.com www.fullinterview.com www.chetanasprojects.com interconnecte' *y usin a cell placement > routin pro ram. #he last evolution involves a 'etaile' ?oolean 'escription of leaf cells followe' *y a transistor level implementation of leaf cells an' mas1 eneration. #he eri$ication of 'esi n plays a very important role in every step 'urin this process. #he failure to properly verify a 'esi n in its early phases typically causes si nificant an' e-pensive re$ 'esi n at a later sta e, which ultimately increases the time$to$mar1et.

verifie', at all levels of a*straction. ;o'ularity in 'esi n means that the various functional *loc1s, which ma1e up the lar er system must have well$ 'efine' functions an' interfaces. ;o'ularity allows that each *loc1 or mo'ule can *e 'esi ne' relatively in'epen'ently from each other All of the *loc1s can *e com*ine' with ease at the en' of the 'esi n process, to form the lar e system. #he concept of mo'ularity ena*les the parallelisation of the 'esi n process?y 'efinin well$characteri=e' interfaces for each mo'ule in the system, we effectively ensure that the internals of each mo'ule *ecome unimportant to the e-terior mo'ules. "nternal 'etails remain at the local level. #he concept of localit( also ensures that connections are mostly *etween nei h*orin mo'ules, avoi'in lon $'istance connections as much as possi*le.

Desi%n Hierarc0(!
#he use of hierarchy, techni+ue involves 'ivi'in a mo'ule into su*$ mo'ules an' then repeatin this operation on the su*$ mo'ules until the comple-ity of the smaller parts *ecomes mana ea*le. Concepts o$ Re%ularit(/ *odularit( and Localit(! Re%ularit( means that the hierarchical 'ecomposition of a lar e system shoul' result in not only simple, *ut also similar *loc1s, as much as possi*le. A oo' e-ample of re ularity is the 'esi n of array structures consistin of i'entical cells $ such as a parallel multiplication array. Re ularity usually re'uces the num*er of 'ifferent mo'ules that nee' to *e 'esi ne' an' www.1000projects.com www.fullinterview.com www.chetanasprojects.com

VLSI Desi%n St(les

Various 'esi n styles use' for VL!" chip fa*rication are as follows9 #)-ield Pro%ra&&able Gate Arra( 5-PGA6! .ully fa*ricate' .P8A chips containin thousan's of lo ic ates or even more, with pro ramma*le interconnects, are availa*le to users for

www.1000projects.com www.fullinterview.com www.chetanasprojects.com their custom har'ware pro rammin to reali=e 'esire' functionality. A typical .iel' Pro ramma*le 8ate Array %.P8A& chip consists of "4O *uffers, an array of <onfi ura*le Lo ic ?loc1s %<L?s&, an' pro ramma*le interconnect structures. #he pro rammin of the interconnects is implemente' *y pro rammin of RA; cells whose output terminals are connecte' to the ates of ;O! pass transistors.#he a'vanta es of .P8A are very short turn aroun' time an' no physical manufacturin re+uire' for customi=in it.#he 'isa'vanta e is typical price of .P8A chips are usually hi her than other reali=ation alternatives.

the ate array is 'one with metal mas1 'esi n an' processin .8ate array implementation re+uires a two$step manufacturin process9 #he first phase, which is*ase' on eneric %stan'ar'& mas1s, results in an array of uncommitte' transistors on each 8A chip. #hese uncommitte' chips can *e store' for later customi=ation, which is complete' *y 'efinin the metal interconnects *etween the transistors of the array.!ince the patternin of metallic interconnects is 'one at the en' of the chip fa*rication, the turn$ aroun' time can *e still short, a few 'ays to a few wee1s. #he a'vanta es of 8A are *etter chip utili=ation factor,more chip spee' an' more customi=e' 'esi n.

-i% 7 8 General arc0itecture o$ 9ilin' -PGAs) 4)Gate Arra( Desi%n! "n view of the fast prototypin capa*ility, the ate array %8A& comes after the .P8A. 5hile the 'esi n implementation of the .P8A chip is 'one with user pro rammin , that of www.1000projects.com www.fullinterview.com www.chetanasprojects.com -i%) : " ;asic processin% steps re<uired $or %ate arra( i&ple&entation =) Standard"Cells ;ased Desi%n9 #he stan'ar'$cells *ase' 'esi n is one of the most prevalent full custom 'esi n styles

www.1000projects.com www.fullinterview.com www.chetanasprojects.com which re+uire 'evelopment of a full custom mas1 set. #he stan'ar' cell is also calle' the polycell. "n this 'esi n style, all of the commonly use' lo ic cells are 'evelope', characteri=e', an' store' in a stan'ar' cell li*rary. #he characteri=ation of each cell is 'one for several 'ifferent cate ories li1e 'elay time vs. loa' capacitance, circuit, timin an' fault simulation mo'els, cell 'ata for place$an'$route, mas1 'ata.

pins are locate' on the upper an' lower *oun'aries of the cell. #he fi ure that follows shows the layout of a typical stan'ar' cell. @ere the n;O! transistors are locate' closer to the roun' rail while the p;O! transistors are place' closer to the power rail. 7) -ull Custo& Desi%n! "n a full custom 'esi n, the entire mas1 'esi n is 'one anew without use of any li*rary. @owever, the 'evelopment cost of such a 'esi n style is *ecomin prohi*itively hi h. #hus, the concept of 'esi n reuse is *ecomin popular in or'er to re'uce 'esi n cycle time an' 'evelopment cost. "n real full$custom layout in which the eometry, orientation an' placement of every transistor is 'one in'ivi'ually *y the 'esi ner, 'esi n pro'uctivity is

-i%) > " A standard cell la(out e'a&ple) #o ena*le automate' placement of the cells an' routin of inter$cell connections, each cell layout is 'esi ne' with a fi-e' hei ht, so that a num*er of cells can *e a*utte' si'e$*ysi'e to form rows. #he power an' roun' rails typically run parallel to the upper an' lower *oun'aries of the cell, thus, nei h*orin cells share a common power an' roun' *us. #he input an' output www.1000projects.com www.fullinterview.com www.chetanasprojects.com

usually very low $ typically 10 to A0 transistors per 'ay, per 'esi ner. "n 'i ital <;O! VL!", full$custom 'esi n is rarely use' 'ue to the hi h la*or cost. E-ceptions to this inclu'e the 'esi n of hi h$volume pro'ucts such as memory chips, hi h$ performance microprocessors an' .P8A masters.

Li&itin% $actors in VLSI desi%n!

#here are a certain physical factors of real VL!" 'esi ns, which limit the

www.1000projects.com www.fullinterview.com www.chetanasprojects.com performance of 'i ital VL!" circuits. #he switchin characteristics of 'i ital inte rate' circuits essentially 'ictate the overall operatin spee' of 'i ital systems. #he 'ynamic performance re+uirements of a 'i ital system are usually amon the most important 'esi n specifications. #herefore, the switchin spee' of the circuits must *e estimate' an' optimi=e' very early in the 'esi n. "t is o*serve' that %1& #he interconnection 'elay is *ecomin the 'ominatin factor which 'etermines the 'ynamic performance of lar e$scale systems, an' %A& #he interconnect parasitics are 'ifficult to mo'el an' to simulate. Various parasitics that affect the 'esi n of a chip are ;O!.E# an' interconnect capacitance an' interconnect resistance

systems an' the nee' to limit power consumption %an' hence, heat 'issipation& in very$hi h 'ensity 2L!" chips have le' to rapi' an' innovative 'evelopments in low$power 'esi n 'urin the recent years. the re+uirements of low power consumption must *e met alon with e+ually 'eman'in oals of hi h chip 'ensity an' hi h throu hput. @ence, low$power 'esi n of 'i ital inte rate' circuits has emer e' as a very active an' rapi'ly 'evelopin fiel' of <;O! 'esi n. 5ays to re'uce power 'issipation at 'ifferent levels of 'esi nin areas follows9

?a(s and *et0ods $or Lo, Po,er VLSI Desi%n!

#he avera e power consumption in conventional <;O! 'i ital circuits can *e e-presse' as the sum of three main components, namely, %1& the 'ynamic %switchin & power consumption, %A& the short$circuit power consumption, an' %B& the lea1a e power consumption. #he increasin prominence of porta*le www.1000projects.com www.fullinterview.com www.chetanasprojects.com -i%) 1 8 Lo, Po,er Desi%n

Applications!
VL!" has since 1(C0s inva'e' all fiel's an' applications *rin in a revolution in Everythin $ from small 'i ital watches to comple- 7!P applications. #he fastest

www.1000projects.com www.fullinterview.com www.chetanasprojects.com of microprocessor "N#EL$Pentium /, em*e''e' systems, smart 'evices etc are all possi*le an' via*le to'ay only *ecause of VL!" an' 2L!". !ome of the Applications are 'iscusse' *elow9 #)*ulti&edia!#o'ay there is a race to 'esi n interopera*le vi'eo systems for *asic 'i ital computer functions, involvin multime'ia applications in areas such as me'ia information, e'ucation, me'icine an' entertainment, to name *ut a few are Di%iti.ation o$ @TV -unctionsA! "n to'ayDs state$of$the$art solution one can reco ni=e all the *asic functions of the analo #V set with, however, a mo'ularity in the concept, permittin a''itional features *ecomes possi*le, some special 'i ital possi*ilities aree-ploite', e. . stora e an' filterin techni+ues to improve si nal repro'uction %a'aptive filterin , 100 @= technolo y&, to inte rate special functions %picture$in$picture, =oom, still picture& or to receive 'i ital *roa'castin stan'ar's %;A<, N"<A;&. -i%) ## 8 C0ip P0oto%rap0 4) VLSI in Co&&unication -i%) #3 " T0e DIGIT4333 TV recei er blocB dia%ra& #owar's stan'ar'i=ation, namely, the inte ration of 13 i'entical hi h$spee' processors with communication an' pro ramma*ility concepts comprise' in the architecture. #he hoto raph of which is shown *elow

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www.1000projects.com www.fullinterview.com www.chetanasprojects.com scalin of the *ul1 ;O!.E# structure. One major pro*lem is the controllin of short channel effects manifeste' as V# roll$off an' 7rain "n'uce' ?arrier -i%) #4 " T0e Nordic VLSI nR-37== #he features of #he Nor'ic VL!" nR.0/BB are it is a true sin le chip .!E transceiver ,on chip 2@. synthesiser, /;@= crystal reference,/BB;@= "!; *an' operation,few e-ternal components re+uire', up to 10m5 transmit power an' no setup4confi uration. #he applications of Nor'ic VL!" nR.0/BB are Alarm an' !ecurity !ystems, @ome Automation, Remote <ontrol, !urveillance, Automotive, #elemetry, #oys an' 5ireless <ommunication. .uture challen es for further inte ration9 As was pre'icte' *y ;oore in 1(30, the num*er of 'evices on a chip 'ou*le' every 1A months till in1(C0Ds. #his slowe' 'own in 1()0Ds an' num*er of 'evices on a chip 'ou*le' every A/ months. #his tren' is e-pecte' to <ontinue for another couple of 'eca'es without any major pro*lems. ?ut after that further inte ration may pose several pro*lems. !ome of these further challen es are as follows9 #) Transistor scalin%! 7evice physics poses several challen es to further www.1000projects.com www.fullinterview.com www.chetanasprojects.com Lowerin effects. #o minimi=e these short channel effects, the transistor lateral$to$vertical aspect ratio must *e preserve' from one technolo y eneration to the ne-t. .or this, ate o-i'e thic1ness, the junction 'epth, an' the 'epletion 'epth all nee' to scale 'own *y B0F per eneration. Lea1a e throu h the ate o-i'e *y 'irect *an'$to$ *an' tunnelin limits physical o-i'e thic1ness scalin . Re'ucin the source4 'rain junction e-tensions is limite' *y the increase in the parasitic resistances. Re'ucin junction 'epths *elow B0nm 'e ra'es 'rive current, even thou h short channel effect is improve'. 4) Subt0res0old leaBa%e! !upply volta es will continue to re'uce with each technolo y eneration an' continue to contri*ute to lower the power 'issipation. @owever transistor threshol' volta e %V#& must re'uce at the same rate to maintain enou h ate over'rive an' ena*le circuit performance to improve B0 F each eneration. Lower V# causes the transistor su*threshol'

www.1000projects.com www.fullinterview.com www.chetanasprojects.com lea1a e current to increase e-ponentially. =) Interconnect scalin%! <hip performance is increasin ly limite' *y the inter connect R< 'elay as the transistor 'elays 'ecrease pro ressively, while the narrower metal lines an' space actually increase the 'elay associate' with the interconnects. @ence, interconnect scalin couple' with hi her operatin fre+uencies re+uires careful capacitive an' in'uctive noise mo'elin . 7) Po,er dissipation! Power 'issipation is increasin 'ue to hi her operatin fre+uencies an' transistor counts. !upply volta es will continue, *ut its contri*ution to power re'uction is 'efinitely not enou h. @ence power efficient micro$architectures are re+uire' an' the 'ie si=e an' the fre+uency rowth may nee' to *e containe'. :) Plat$or& inte%ration! At the platform level, e-ternal *us fre+uencies have not 1ept pace with processor fre+uencies. Also, the ap *etween "4O volta es of a'vance' microprocessors an' other mother*oar' components is increasin . #his re+uires new hi h$ volta e tolerant circuits or process options. "nspite of these challen es, there is no fun'amental *arrier for www.1000projects.com www.fullinterview.com www.chetanasprojects.com

;ooreDs law to e-ten' for another couple of 'eca'es.

<onclusion9
: VL!" provi'es circuit 'esi ns with more computational spee' with less power 'issipation an' less circuit *oar' area alon with hi her spee's an' hi her relia*ility at lower costs. : #here are very stron lin1s *etween the fa*rication process, the circuit 'esi n process an' the performance of the resultin chip. @ence, circuit 'esi ners must have a wor1in 1nowle' e of chip fa*rication to create effective 'esi ns an' in or'er to optimi=e the circuits with respect to various manufacturin parameters. : VL!" has revolutioni=e' the electronic in'ustry an' has a wi'e ran e of applications li1e microprocessors, memory 'evices, 7!P chips, in communication, multime'ia, sensors, em*e''e' systems etc. : #here are certain factors that pose as future challen es for further inte ration. #hou h the tren' in inte ration may continue for another couple of 'eca'es, *ut may*e after that there may *e a nee' to invent new materials for further

www.1000projects.com www.fullinterview.com www.chetanasprojects.com inte rationG as of to'ay no such other material is 1nown.

References9
1. Principles of <;O! VL!" 'esi n H Eamran Eshra hian A 7i ital 'esi n principles > practices H Iohn .. 5a1erly. B.http944www.nationmaster.com4encyclo pe'ia

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