POWERENG 2009

Lisbon, Portugal, March 18-20, 2009

Control of AC-DC Matrix Converter using digital PLL

I. Barbieri, P. Lambruschini, M. Raggio
barbieri@dibe.unige.it, lambruschini@dibe.unige.it, raggio@dibe.unige.it Department of Biophysical and Electronic Engineering, University of Genova, Via Opera Pia 11 A, 16146 Genova, Italy
Abstract- In this paper, the implementation of a DSP controlled acdc matrix converter is presented. A Phase Locked Loop is used to synchronize the high frequency ac voltage synthesized by the matrix converter with the three phase input line. This solution allows obtaining a stable output dc voltage even in case of non ideal input phases, which is the typical actual input in an industrial environment. Experimental results, obtained with a 5kW prototype and compared with computer simulated model results, are shown. Functional issues are discussed and design solutions proposed and implemented.

In the following section: the PLL implementation based on the Clarke transformation, the control strategy, the system implementation and experimental results compared with computer simulation.

II.

PLL

The Phase Locked Loop must synchronize the high frequency (20 kHz) voltage synthesized by the matrix converter at the primary of the transformer with the three input phase voltages [15, 16]:

I.

INTRODUCTION

The matrix converter structure [3, 5] is a typical approach for direct power conversion. Main advantages are a reduced number of components, reactive elements size, capability of power regeneration and sinusoidal input current. Main issues are bidirectional switches employment and a quite complex modulation algorithm, respect to traditional conversion structures. In the past, implementations of matrix power structures have been considered hardly achievable due to the lack of efficient bidirectional switches and digital signal processor cost. Thanks to power switching technology advancement these issues are nowadays resolved; therefore matrix converter based devices are now suitable. In this paper a low complex implementation for an efficient matrix ac-dc converter have been studied. The converter consists of an input filter, a power bidirectional switches bridge [3], a compact high frequency transformer producing the isolation, a rectifier module and an output filter to achieve the desired output dc voltage. In the following figure a schema of the described converter structure is presented:

V A = V m cos(t + ) 2 VB = Vm cos(t + + ) 3 2 VC = Vm cos(t + ) 3

(1)

In order to simplify the problem [14], the Clarke transform has been used. This transform allows representing the three phase input voltage in a two dimensional space:

V = V A V = 1 3 VA 2 3 VB
(2)

The following figure represents the Clarke transform:

Fig. 1. ac-dc converter schema.

Fig. 2. Clarke transform.

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The three phase reference voltage, VA, VB, VC in figure 2, can be represented by a vector V rotating in the (, ) plain at the angular velocity . The rotating angle of the space vector V at each instant can be calculated as:

= arctg (

V V

(3)

PLL output

Reference input Reference input

A PLL schema is presented in figure 3. Starting from the three phase line voltages, V, V components and phase of voltage vector V in figure 2 are calculated using (2) and (3). The angle is compared with the internal reference and a proportional integrative regulator provides to null the error. The PLL control is implemented by a proportional integrative regulator with transfer function given by (4).

PLL output (b) Fig. 4. PLL with ideal(a) and distorted(b) input line.

T (s) = k p +

ki s

(4)

The proportional gain kp and the integrative one ki must be calculated considering a band-width allowing not to suppress the control signal at 50Hz frequency, but, at the same time, significantly narrow to suppress harmonics of distorted three phase input line voltages [19, 20]. The challenge is to obtain a good compromise between stability and dynamic performance [15]. In the figure 4 the simulation results for , components in case of ideal and distorted input lines.
Theta Increment

In purple the , components obtained from Clarke transform (2) and in yellow the component reconstructed by the PLL. In Figure 5 the experimental result obtained with a DSP implementation of the exposed PLL algorithm is shown, for a non ideal input case. No important differences between simulation end empirical tests have been evidenced. It is worth noting that the PLL output is not affected from distortion of , input. This means a voltage DC output free from harmonic components due to distorted input line or noise on the AD acquisition.

III. MODULATION STRATEGY In order to achieve the unitary power factor [17], the input phase currents must be sinusoidal and in phase with the input line voltages. Input currents can be represented, similarly to the input voltage in figure 2, in the (, ) plain. The current space vector can be obtained switching between two adjacent switching state vectors [17, 18], and the zero vector represented in figure 6:

Theta Grid

Kp.s+Ki s Regulator

Internal Theta

Fig. 3. PLL.

PLL output Reference input

Reference input PLL output

(a)

Fig. 5. PLL experimental result.

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Fig. 6. Switching State Vectors hexagon.

b) Fig. 7. Six Step PWM. a)Sectors in a period. b) pi/2-5pi/6 sector.

Following this approach the ac-dc converter modulation strategy can be considered analogous to that one of an inverter [6]. The switching state vector can be composed by several combinations of the switches in figure 1. The combination choice is based on the minimization of switches losses and on the requirement to avoid short circuit between input lines. Considering that each switch of figure 1 is constituted by two switches [9], named n and p, our choice for the initial pi/6 of the first sector is presented in table 1. The last column of the table shows the instants of the voltage synthesized from the matrix converter at the primary of the transformer Vp (figure 9), in each conversion time. The input voltage period is divided in six sectors of pi/3 rad [1]. Within each interval, phases do not change their signs. In figure 7 a), the division in sector of one three phase voltage period is represented, while figure 7 b) illustrates one sector. Its worth noting in figure 7 b), that VC is the biggest voltage and |VB|>|VA| at the beginning of the sector pi/2-5pi/6.
S11n 1 1 1 1 1 S11p 1 0 1 0 1 S21n 0 1 0 1 1 S21p 1 1 1 1 1 S12n 0 1 0 0 0 S12p 1 1 1 0 1 S22n 1 1 0 1 1 S22p 1 0 0 0 0 S13n 0 0 0 1 0 S13p 1 0 1 1 1 S23n 0 1 1 1 1 S23p 0 0 1 0 0 Vp I II III IV
zero

Referencing to the previous sector, the individual duty cycles of the matrix converter switches result: d11= 0, d12= 0, d13= 1 d21= -m*VA/Vm, d22= -m*VB/Vm, d23= 1-(d21+d22)

(5)

where m is the modulation index, varying between 0 and 1 and allowing achieving the desired output voltage level. The duty d21 and d22 are respectively the sum of the instant I, II and III, IV present in table 1. In a similar way, the duty can be calculated for all others sectors [1,2].

IV.

SYSTEM IMPLEMENTATION

Table 1

a)

The implementation of the previously described PLL and modulation strategy has been developed using a close interaction between simulation and prototype testing. A model of the converter has been developed in order to test the designed algorithm. During this process the model structure has been modified due to problems evidenced during physical prototype tests. The converter in figure 1 has been controlled with a board equipped with a DSP Freescale 56F8345 and a CPLD Xilinx XC95144XL, providing the PWM control signals to drive the IGBTs. In figure 8 a diagram of the control system is represented. In an open loop configuration, the control [22] process within each sampling period starts with the measuring of the three phase voltage acquired by the DSP integrated AD converter. The firmware running on DSP implements the above described PLL calculating the Clarke transform and synchronizing an internal counter with the rotating angle of the external input voltages vector. The counter is implemented as a pointer to a look up table containing the duty cycles previously calculated according to (5). In this way the high frequency voltage at the primary of the transformer is synchronized with the external three phase voltages, with reduced computational weigh.

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Control Board
DSP Freescale 56F8345 CPLD Xilinx XC95144XL Three pahse input

7 Vp instants

12 control signals

Output filter

Recti fier

HF transfor mer

Power switch bridge

Input filter

Power Block

Fig. 10. An IGBT control signal. Fig. 8. Converter block diagram.

Duty cycles are function of the sampled three phase voltage, therefore their duration and their position in the control period varies [6]. This can be better cleared with an example. If we want to synthesize at the primary of the transformer the voltage represented in figure 9, we need to open and close the IGBTs at the correct instant for the correct duration, in each sampling period. The DSP loads from the look up table the duty cycles, calculates the t1t7 instants shown in figure 9 and generates seven PWM signals that are processed from the CPLD to obtain the 12 control signals for the IGBTs constituting the matrix converter [9], like shown in figure 8. The control signals of each switch in the first sector are in table 1. The DSP cant be used to directly drive the bidirectional switches, due to the complexity of the control signals. Figure 10 shows the evolution of one of these signals in a conversion period. With the DSP we can only provide PWM signals. This problem has been resolved using the CPLD [6].

The CPLD provides dead times [7] in order to avoid short circuits between the input phases due to a IGBT turn off time largest of a IGBT turn on time. To minimize the switching losses [12] an efficient Zero Voltage Switching (ZVS) algorithm [4, 10] has been implemented in the CPLD code. The introduced dead times have been modified in order to obtain switches commutations at zero voltage, using the resonance between the leakage inductance and the parasitic capacitance of node K and M [4] shown in figure 1. Introducing the ZVS, not all duty cycles of (5) are physically achievable. We have chosen to keep a peak of 3us every time there is a duty cycle shorter than 3us and to reduce the others peaks in order to maintain the same average output voltage. For example, considering the figure 9 if t5-t4 is shorter then 3us, t1-t0 is rescaled according to (6). This solution is a good trade off between ripple behaviour and distortion of input currents.

(t1 t 0 ) =

(t1 t 0 )(VC V B ) + (t 5 t 4 3us )(VC V A ) (6) (VC V B )

In the closed loop configuration, the load dc voltage is sampled from the DSP and using a proportional integrative control [8] the modulation index m (5) is regulated. In order to simulate the above described controlled system, a Matlab-Simulink model has been developed [11, 21]. The control board model has been implemented using an ad hoc block that simulates the DSP behaviour. The CPLD have been tested simulating all events that could produce damage to the prototype converter in case of software failure.

V.
Tc Fig. 9. Primary voltage.

SIMULATION AND EXPERIMENTAL RESULTS

The main features of the prototype produced to test our work are listed in table 2 and a photo is in figure 11.

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Input Voltage Output Voltage Ripple Output Current Output Power Conversion Freq. PF Efficiency

3x400Vac-50Hz 50Vdc ~1% 100A 5kW 20kHz ~1 ~98%

Table 2 Converter features.

a)

100V

20 s b) Fig. 12. Primary Voltage. a) Oscilloscope acquisition. b) Simulation result.

Fig. 11. ac-dc converter.

Figure 12 a) shows the synthesized primary voltage in an experimental test on the prototype. This acquisition can be compared with the simulated one of figure 11 b) and with the theoretical one of figure 9. The three wave forms are very similar. In order to verify the PLL, the converter has been tested and simulated at different frequency of the input line and with phase disturbances. Same test with distorted three phases input voltages, similarly at that present in industrial area, has been performed and the results can be considered not significantly different from the above shown.

VI.

CONCLUSION

Obtained results demonstrate that matrix converters are cost effective structures for power conversion. The versatility of the digital control and flexibility of a power bidirectional switches bridge are sure an efficient strategy to implement in general power converter, not only ac-dc. This structure can be considered affordable even for an industrial environment usage thanks to the PLL-driven capability

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to adapt internal parameters to power line conditions, without decrease significantly the performance.

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