Unit 5 VHDL Programming VHDL 1.

VHDL stands for VHSIC (Very High Speed Integrated Circuits) Hardware Description Language. 2. It is a hardware description language that can be used to model a digital system. In other words it is a language to describe the digital electronics system. 3. The complexity of the digital system being modelled could vary from that of a simple gate to a complete digital electronic system, or anything in between. 4. The digital system can also be described hierarchically. 5. Timing can also be explicitly modelled in the same description. CAPABILITIES The following are the major capabilities that the language provides along with the features that differentiate it from other hardware description languages. The language can be used as an exchange medium between chip vendors and CAD tool users. Different chip vendors can provide VHDL descriptions of their components to system designers. CAD tool users can use it to capture the behaviour of the design at a high level of abstraction for functional simulation. The language supports hierarchy; that is, a digital system can be modelled as a set of interconnected components; each component, in turn, can be modelled as a set of interconnected subcomponents. 1

 The language supports flexible design methodologies: top-down, bottom-up, or mixed. It supports both synchronous and asynchronous timing models. The language is publicly available, human-readable, machinereadable, and, above all, it is not proprietary. Arbitrarily large designs can be modelled using the language, and there are no limitations imposed by the language on the size of a design. The language has elements that make large-scale design modelling easier; for example, components, functions, procedures, and packages. Test benches can be written using the same language to test other VHDL models. Generics and attributes are also useful in describing parameterized designs. A model can not only describe the functionality of a design, but can also contain information about the design itself in terms of userdefined attributes, such as total area and speed. Behavioral models that conform to a certain synthesis description style are capable of being synthesized to gate-level descriptions. BUILDING BLOCKS The entity describes the interface of the block and a separate party associated with the entity describes how that block operates. This interface description is like a pin description in the data blocks, specifying inputs and outputs of the block.

The description of operation of the part is like a scheme for the block. The complete design may be a collection of many blocks using their connectors. In the entity declaration, the line in-between is called the port map, which describes the interface to the design, contains a list of interface declarations. Each interface declaration defines one or more signals that are input or outputs to the design. Each interface declaration contains a list of names of mode type. The architecture declaration describes how the design operates in the data flow model and describes the operation of the signal. CONNECTING BLOCKS Once we have defined the basic building blocks for our design using entity and architecture, we can combine them together to form structural description of a schematic. A list of components and their connection is called net list. The net list is done by synthesis function. CODE STRUCTURE The fundamental sections that comprise a piece of VHDL Code are given below: 1. Library Declarations 2. Entity 3. Architecture. 1. Library Declarations Contains a list of all libraries to be used in the design. For example IEEE, Work, STD etc.... 3

Syntax: LIBRARY library_name; USE library_name.package_name.package_parts; A library is a collection of commonly used pieces of code, Placing such a piece inside library allows them to be reused or shared by other designs. 2. Entity An entity is a List with specifications of all inputs and output pins (Ports) of the circuit. Syntax: ENTITY entity_name IS PORT{ Port_name : signal_mode signal_type; Port _name : signal_mode signal_type; .....}; END entity_name; There are three different modes of signals. They are as follows: 1. In 2. Out 3. In out 4. Buffer : unidirectional input pin : unidirectional output pin : Bi_directional Pin : employed when output is used (Read) Internally 4

3. Architecture Architecture is a description of how a circuit should behave (function). Syntax: ARCHITECTURE architecture_name of entity_name IS [declarations] BEGIN (code) END architecture_name; The architecture has two parts: Declarative part (Optional), where signals and constants are declared, and the code part (from begin down). Likewise entity, the name of architecture should be same name used in entity. Architecture is further classified into three types. 1. Dataflow 2. Behavioral 3. Structural LEVELS OF MODELLING 1. Dataflow eeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeeee In the data flow approach, circuits are described by indicating how the inputs and outputs of built-in primitive components are connected together. In other words we describe how signals (data) flow through the circuit.

Syntax: Architecture dataflow of <filename> is <Declarations> Begin <Code> <Concurrent statements> End 2. Behavioral In the Behavioral description, we are concerned with the circuit or the modules in it, but we are only concerned with the behaviour of that particular circuit. In other words we are mainly concerned with the functionality of that particular circuit. Syntax: Architecture behavioral of <filename> is <Declarations> Begin Process (inputs, or only clock in sequential circuits) Begin <Code> 6

<Sequential statements> End process; End; 3. Structural In structural description, we consider all the modules in the circuit individually and their interconnections. Here we are not much bothered about behaviour. Syntax: Architecture Structural of <filename> is <Declarations> Component <name> is Port(.............) End component; . . <signals declaration> Begin Name: <component name> port map (original entity pin names) . . 7

End;

COMMANDS USED 1. IF Statement Syntax: If <Condition> then <Sequence of Statements>; End if; 2. IF, ELSEIF, ELSE Statement Syntax: If <Condition> then <Sequence of statements>; Elsif <Sequence of statements>; Else <Sequence of statements>; End if;

3. CASE Statement Case is another fragment of sequential code along with If, Wait, Loop etc.... Syntax: Case <Expression/Identifier> is When <Choice/Value> => sequence of statements; When <Choice/Value> => sequence of statements; When <Choice/Value> => sequence of statements; ......................... .......................... When others => <Sequence of statements>; End case; 4. LOOP Statement As the name says, Loop is useful when a piece of code must be instantiated several times. Like If, Wait and case, Loop is intended exclusively for Sequential Code. So it too can only be used inside a process, Function or procedure. There are several ways of using Loop. For Loop Syntax: [Loop_Label] : For <Identifier> in <Discrete range> loop 9

<Sequential Statements>; End Loop [Label];

While Loop Syntax: [Loop_Label] : While <Condition> Loop <Sequential Statements>; End Loop [Label]; 5. Variable Declarations Variables are used for local storage in process statements and subprograms. Variable declaration looks like this: VARIABLE variable_name {,variable_name} : variable_type [:=value]; 6. Signal Declarations Signal objects are used to connect entities together to form models. Signals are the means for communication of dynamic data between entities. A signal declaration looks like this: SIGNAL signal_name : signal_type [:=initial_value];

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DataFlow Modelling:
Half Adder:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HalfAdder is port(a,b: in std_logic; sum,carry: out std_logic); end HalfAdder; architecture Dataflow of HalfAdder is begin sum<= a xor b; carry<= a and b; end Dataflow;

Full Adder:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdder is

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port(a,b,cin: in std_logic; sum,carry: out std_logic); end FullAdder; architecture Dataflow of FullAdder is begin sum<= a xor b xor cin; carry<= (a and b) or (b and cin) or (cin and a); end Dataflow;

Half Subtractor:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HalfSubtractor is port(x,y: in std_logic; diff,borrow: out std_logic); end HalfSubtractor; architecture Dataflow of HalfSubtractor is begin diff<= x xor y; borrow<= (not x) and y; end Dataflow;

Full Subtractor:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity FullSubtractor is port(x,y,bin: in std_logic; diff,borrow: out std_logic); end FullSubtractor; architecture Dataflow of FullSubtractor is begin diff<= x xor y xor bin; borrow<= ((not x) and y) or (y and bin) or (bin and (not x)); end Dataflow;

4 to 1 MUX:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity MUX is port(d0,d1,d2,d3,s1,s0: in std_logic; y: out std_logic); end MUX; architecture Dataflow of MUX is begin y<= (d0 and (not s1) and (not s0)) or (d1 and (not s1) and s0) or (d2 and s1 and (not s0)) or (d3 and s1 and s0); end Dataflow;

1 to 4 Demux:
library IEEE;

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use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Demux is port(d,s1,s0: in std_logic; d0,d1,d2,d3: out std_logic); end Demux; architecture Dataflow of Demux is begin d0<= d and (not s1) and (not s0); d1<= d and (not s1) and s0; d2<= d and s1 and (not s0); d3<= d and s1 and s0; end Dataflow;

Octal to Binary Encoder:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity OCTtoBINARYencoder is port(d1,d2,d3,d4,d5,d6,d7,d8: in std_logic; y0,y1,y2: out std_logic); end OCTtoBINARYencoder; architecture Dataflow of OCTtoBINARYencoder is begin y0<= d1 or d3 or d5 or d7; y1<= d2 or d3 or d6 or d7; y2<= d4 or d5 or d6 or d7;

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end Dataflow;

Binary to Octal Decoder:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity BINARYtoOCTdecoder is port(a,b,c: in std_logic; d1,d2,d3,d4,d5,d6,d7,d8: out std_logic); end BINARYtoOCTdecoder; architecture dataflow of BINARYtoOCTdecoder is begin d1<= ((not a) and (not b) and (not c)); d2<= ((not a) and (not b) and c); d3<= ((not a) and b and (not c)); d4<= ((not a) and b and c); d5<= (a and (not b) and (not c)); d6<= (a and (not b) and c); d7<= (a and b and (not c)); d8<= (a and b and c); end dataflow;

Behavioral Modelling:
Half Adder:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity HalfAdderBEHAVE is port(a,b: in std_logic; sum,carry: out std_logic); end HalfAdderBEHAVE; architecture Behavioral of HalfAdderBEHAVE is begin process(a,b) begin if a='0' and b='0' then sum<= '0'; carry<= '0'; elsif a='0' and b='1' then sum<= '1'; carry<= '0'; elsif a='1' and b='0' then sum<= '1'; carry<= '0'; else sum<= '1'; carry<= '1'; end if; end process; end Behavioral;

Full Adder:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullAdderBEHAVE is port(a,b,cin: in std_logic; sum,carry: out std_logic); end FullAdderBEHAVE; architecture Behavioral of FullAdderBEHAVE is

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begin process(a,b,cin) begin if a='0' and b='0' and cin='0' then sum<= '0'; carry<= '0'; elsif a='0' and b='0' and cin='1' then sum<= '1'; carry<= '0'; elsif a='0' and b='1' and cin='0' then sum<= '1'; carry<= '0'; elsif a='0' and b='1' and cin='1' then sum<= '0'; carry<= '1'; elsif a='1' and b='0' and cin='0' then sum<= '1'; carry<= '0'; elsif a='1' and b='0' and cin='1' then sum<= '0'; carry<= '1'; elsif a='1' and b='1' and cin='0' then sum<= '0'; carry<= '1'; else sum<= '1';carry<= '1'; end if; end process; end Behavioral;

Half Subtractor:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity HalfSubtractorBEHAVE is port(x,y: in std_logic; diff,borrow: out std_logic); end HalfSubtractorBEHAVE;

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architecture Behavioral of HalfSubtractorBEHAVE is begin process(x,y) begin if x='0' and y='0' then diff<= '0'; borrow<= '0'; elsif x='0' and y='1' then diff<= '1'; borrow<= '1'; elsif x='1' and y='0' then diff<= '1'; borrow<= '0'; else diff<= '0'; borrow<= '0'; end if; end process; end Behavioral;

Full Subtractor:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity FullSubtractorBEHAVE is port(x,y,bin: in std_logic; diff,borrow: out std_logic); end FullSubtractorBEHAVE; architecture Behavioral of FullSubtractorBEHAVE is begin process(x,y,bin) begin if x='0' and y='0' and bin='0' then

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diff<= '0'; borrow<= '0'; elsif x='0' and y='0' and bin='1' then diff<= '1'; borrow<= '1'; elsif x='0' and y='1' and bin='0' then diff<= '1'; borrow<= '1'; elsif x='0' and y='1' and bin='1' then diff<= '0'; borrow<= '1'; elsif x='1' and y='0' and bin='0' then diff<= '1'; borrow<= '0'; elsif x='1' and y='0' and bin='1' then diff<= '0'; borrow<= '0'; elsif x='1' and y='1' and bin='0' then diff<= '0'; borrow<= '0'; else diff<= '1';borrow<= '1'; end if; end process; end behavioral;

4 to 1 MUX:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity MuxBEHAVE is port(d0,d1,d2,d3,s1,s0: in std_logic; y: out std_logic); end MuxBEHAVE; architecture Behavioral of MuxBEHAVE is begin

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process(d0,d1,d2,d3,s1,s0) begin if s1= '0' and s0= '0' then y<= d0; elsif s1= '0' and s0= '1' then y<= d1; elsif s1= '1' and s0= '0' then y<= d2; else y<= d3; end if; end process; end Behavioral;

1 to 4 Demux:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DemuxBEHAVE is port(d,s1,s0: in std_logic; d0,d1,d2,d3: out std_logic); end DemuxBEHAVE; architecture Behavioral of DemuxBEHAVE is begin process(d,s1,s0) begin if s1= '0' and s0= '0' then

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d0<= d; elsif s1= '0' and s0= '1' then d1<= d; elsif s1= '1' and s0= '0' then d2<= d; else d3<= d; end if; end process; end Behavioral;

Octal to Binary Encoder:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity EncoderBEHAVE is port(d1,d2,d3,d4,d5,d6,d7,d8: in std_logic; y0,y1,y2: out std_logic); end EncoderBEHAVE; architecture Behavioral of EncoderBEHAVE is begin process(d1,d2,d3,d4,d5,d6,d7,d8) begin if d1='1' and d2='0' and d3='0' and d4='0' and d5='0' and d6='0' and d7='0' and d8='0' then y2<='0'; y1<='0'; y0<='0'; elsif d1='0' and d2='1' and d3='0' and d4='0' and d5='0' and d6='0' and d7='0' and d8='0' then y2<='0'; y1<='0'; y0<='1';

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elsif d1='0' and d2='0' and d3='1' and d4='0' and d5='0' and d6='0' and d7='0' and d8='0' then y2<='0'; y1<='1'; y0<='0'; elsif d1='0' and d2='0' and d3='0' and d4='1' and d5='0' and d6='0' and d7='0' and d8='0' then y2<='0'; y1<='1'; y0<='1'; elsif d1='0' and d2='0' and d3='0' and d4='0' and d5='1' and d6='0' and d7='0' and d8='0' then y2<='1'; y1<='0'; y0<='0'; elsif d1='0' and d2='0' and d3='0' and d4='0' and d5='0' and d6='1' and d7='0' and d8='0' then y2<='1'; y1<='0'; y0<='1'; elsif d1='0' and d2='0' and d3='0' and d4='0' and d5='0' and d6='0' and d7='1' and d8='0' then y2<='1'; y1<='1'; y0<='0'; elsif d1='0' and d2='0' and d3='0' and d4='0' and d5='0' and d6='0' and d7='0' and d8='1' then y2<='1'; y1<='1'; y0<='1'; end if; end process; end Behavioral;

Binary to Octal Decoder:

library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity DecoderBEHAVE is port(a,b,c: in std_logic; d1,d2,d3,d4,d5,d6,d7,d8: out std_logic); end DecoderBEHAVE; architecture Behavioral of DecoderBEHAVE is

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begin process(a,b,c) begin if a='0' and b='0' and c='0' then d1<='1'; d2<='0'; d3<='0'; d4<='0'; d5<='0'; d6<='0'; d7<='0'; d8<='0'; elsif a='0' and b='0' and c='1' then d1<='0'; d2<='1'; d3<='0'; d4<='0'; d5<='0'; d6<='0'; d7<='0'; d8<='0'; elsif a='0' and b='1' and c='0' then d1<='0'; d2<='0'; d3<='1'; d4<='0'; d5<='0'; d6<='0'; d7<='0'; d8<='0'; elsif a='0' and b='1' and c='1' then d1<='0'; d2<='1'; d3<='0'; d4<='1'; d5<='0'; d6<='0'; d7<='0'; d8<='0'; elsif a='1' and b='0' and c='0' then d1<='0'; d2<='0'; d3<='0'; d4<='0'; d5<='1'; d6<='0'; d7<='0'; d8<='0'; elsif a='1' and b='0' and c='1' then d1<='0'; d2<='0'; d3<='0'; d4<='0'; d5<='0'; d6<='1'; d7<='0'; d8<='0'; elsif a='1' and b='1' and c='0' then d1<='0'; d2<='0'; d3<='0'; d4<='0'; d5<='0'; d6<='0'; d7<='1'; d8<='0'; else d1<='0'; d2<='0'; d3<='0'; d4<='0'; d5<='0'; d6<='0'; d7<='0'; d8<='1'; end if; end process; end Behavioral;

RS Flip Flop:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity RSFlipFlop is

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port(s,r,reset,clk: in std_logic; q,qinv: inout std_logic); end RSFlipFlop; architecture Behavioral of RSFlipFlop is begin process(s,r,clk) begin if reset='1' then q<='0'; qinv<='1'; else if clk<='1' and clk'event then if s='0' and r<='0' then q<= q; qinv<= qinv; elsif s='0' and r='1' then q<='0'; qinv<='0'; elsif s='1' and r='0' then q<='1'; qinv<='0'; else q<='X'; qinv<='X'; end if; end if; end if; end process; end Behavioral;

JK Flip Flop:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

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entity jkflipflop is port(j,k,reset,clk: in std_logic; q,qinv: inout std_logic); end jkflipflop; architecture Behavioral of jkflipflop is begin process(j,k,clk) begin if reset='1' then q<='0'; qinv<='1'; else if clk<='1' and clk'event then if j='0' and k<='0' then q<= q; qinv<= qinv; elsif j='0' and k='1' then q<='0'; qinv<='1'; elsif j='1' and k='0' then q<='1'; qinv<='0'; else q<= not q; qinv<= not qinv; end if; end if; end if; end process; end Behavioral;

D Flip Flop:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

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use IEEE.STD_LOGIC_UNSIGNED.ALL; entity dflipflop is port(d,reset,clk: in std_logic; q,qinv: inout std_logic); end dflipflop; architecture Behavioral of dflipflop is begin process(d,clk) begin if reset='1' then q<='0'; qinv<='1'; else if clk<='1' and clk'event then if d='0' then q<= '0'; qinv<= 1; else q<= '1'; qinv<= '0'; end if; end if; end if; end process; end Behavioral;

T Flip Flop:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity tflipflop is

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port(t,reset,clk: in std_logic; q,qinv: inout std_logic); end tflipflop; architecture Behavioral of tflipflop is begin process(d,clk) begin if reset='1' then q<='0'; qinv<='1'; else if clk<='1' and clk'event then if t='0' then q<= q; qinv<= qinv; else q<= not q; qinv<= not qinv; end if; end if; end if; end process; end Behavioral;

SISO:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SISO is port(din,reset,clk: in std_logic; dout: out std_logic); end SISO; architecture Behavioral of SISO is

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signal d0,d1,d2,d3,q0,q1,q2,q3: std_logic:='0'; begin process(din,reset,clk) begin if reset='1' then q0<='0'; q1<='0'; q2<='0'; q3<='0'; else if clk<='1' and clk'event then dout<=q3; q3<=d3; d3<=q2; q2<=d2; d2<=q1; q1<=d1; d1<=q0; q0<=d0; d0<=din; end if; end if; end process; end Behavioral;

SIPO:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity SIPO is port(din,reset,clk: in std_logic; q0,q1,q2,q3: inout std_logic); end SIPO; architecture Behavioral of SIPO is signal d0,d1,d2,d3: std_logic:='0';

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begin process(din,reset,clk) begin if reset='1' then q0<='0'; q1<='0'; q2<='0'; q3<='0'; else if clk<='1' and clk'event then q3<=d3; d3<=q2; q2<=d2; d2<=q1; q1<=d1; d1<=q0; q0<=d0; d0<=din; end if; end if; end process; end Behavioral;

PIPO:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity PIPO is port(d0,d1,d2,d3,reset,clk: in std_logic; q0,q1,q2,q3: inout std_logic); end PIPO; architecture Behavioral of PIPO is begin process(d0,d1,d2,d3,reset,clk) begin

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if reset='1' then q0<='0'; q1<='0'; q2<='0'; q3<='0'; else if clk<='1' and clk'event then q0<= d0; q1<= d1; q2<= d2; q3<= d3; end if; end if; end process; end Behavioral;

PISO:
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity PISO is port(a,b,c,d:inout std_logic; reset,clk,S_L: in std_logic; q3: inout std_logic); end PISO; architecture Behavioral of PISO is signal d0,d1,d2,d3,q0,q1,q1:std_logic :='0' begin process(d0,d1,d2,d3,reset,clk) begin if reset='1' then q0<='0'; q1<='0'; q2<='0'; q3<='0'; else if clk<='1' and clk'event then

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if S_L='0' then d0<= a; d1<= b; d2<=c; d3<=d; else q3<=d3; d3<=q2; q2<=d2; d2<=q1; q1<=d1; d1<=q0; q0<=d0; d0<=a; end if; end if; end Behavioral;

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