CpE 690: Introduction to VLSI Design

Fall 2013
Lecture 7
CMOS Transistor Theory and DC Response
1
Bryan Ackland
Department of Electrical and Computer Engineering
Stevens Institute of Technology
Hoboken, NJ 07030

Adapted from Lecture Notes, David Mahoney Harris CMOS VLSI Design
2

So far, we have treated transistors as ideal switches
An ON transistor passes a finite amount of current
Depends on terminal voltages
Derive current-voltage (I-V) relationships
Transistor gate, source, drain all have capacitance
I = C (V/t) -> t = (C/I) V
Capacitance and current determine speed
Also revisit what a degraded level means

Introduction
nMOS pMOS
3

Gate and body form
MOS capacitor:

Accumulation:
V
g
< 0


Depletion:
0 < V
g
< V
t


Inversion:
V
g
> V
t


MOS Capacitor
4
Mode of operation depends on V
g
, V
d
, V
s
V
gs
= V
g
V
s
V
gd
= V
g
V
d
V
ds
= V
d
V
s
= V
gs
V
gd
Source and drain are (physically)
symmetric terminals
By convention, nMOS source is terminal at
lower voltage
Hence V
ds
0
nMOS body is grounded (0 volts).
For now, assume source is grounded too.
Three regions of operation
Cutoff
Linear
Saturation



nMOS Terminal Voltages
V
g
V
s
V
d
V
gs
V
gd
V
ds
5
V
gs
< V
t
: No channel
Source-body and drain-body junctions are reverse biased
I
ds
0



nMOS Cutoff
+
-
V
gs
=0
n+ n+
+
-
V
gd
p-type body
b
g
s
d
6
V
gs
< V
t
: Channel forms
Current flows from drain
to source
electrons go from source
to drain

I
ds
increases with V
ds
Similar to linear resistor
Also called:
resistive
triode
non-saturated



nMOS Linear
7
If V
ds
> V
gs
V
t
then V
gd
< V
t
: channel pinches off
Conduction due to drift induced by positive drain voltage
I
ds
independent of V
ds
We say channel current saturates
Similar to current source



nMOS Saturation
+
-
V
gs
>V
t
n+ n+
+
-
V
gd
<V
t
V
ds
>V
gs
-V
t
p-type body
b
g
s
d
I
ds
8
In linear region, I
ds
depends on
How much charge is in the channel?
How fast is the charge moving?



Linear I/V Characteristics
9
MOS structure looks like parallel plate capacitor while
operating in inversion
Gate : oxide : channel
Q
channel
=
C =
V =




Channel Charge
C.V
C
g
=
ox
.W.L/t
ox
= C
ox
.W.L where C
ox
=
ox
/ t
ox
C
ox
is gate capacitance per
unit area
V
gc
V
t
= (V
gs
V
ds
/2) V
t
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
=3.9)
polysilicon
gate
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
10
Charge is carried by e-
Electrons are propelled by the lateral electric field
between source and drain
E = V
ds
/L
Carrier velocity v proportional to lateral E-field
v = .E called (electron) mobility
(~ 500-600 cm
2
/V.s in heavily doped channel)
Time for carrier to cross channel:
= L / v



Carrier Velocity
= L
2
/(.V
ds
)
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
v
11
Now we know
How much charge Q
channel
is in the channel
How much time each carrier takes to cross
I
ds
= Q
channel
/
= (C
ox
.W.L) . (V
gs
V
t
V
ds
/2) / (L
2
/(.V
ds
))
= . C
ox
.(W/L). (V
gs
V
t
V
ds
/2). V
ds

= . (V
gs
V
t
V
ds
/2). V
ds




nMOS Linear I/V
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
v
where = . C
ox
.(W/L)

nMOS IV Linear Region

12
For small

increases linearly behaves as a resistor

As

increases, charge in channel decreases

as a result:

decreases
What happens when

reaches it maximum ?

= .

2
.

()

()

= 2

= 1.5

= 1
13
Suppose we increase V
ds
until V
ds
= V
gs
- V
t

Then V
gd
= V
gs
V
ds
= V
t

The channel pinches off near drain
We call this value of V
ds
the saturation voltage:
V
dsat
= V
gs
V
t
At the point of saturation:
I
dsat
= . (V
gs
V
t
V
dsat
/2). V
dsat
= (/2). (V
gs
- V
t
)
2

nMOS Saturation
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
14
What happens if V
ds
> V
dsat

Pinch off extends from the drain towards the source
Now, length of inverted channel is L = L.(V
dsat
/V
ds
)
Gate to channel capacitance is now
C = C
ox
.W.L = C
ox
.W.L.(V
dsat
/V
ds
)

Average voltage across capacitor is (V
gs
-V
t
)/2 = V
dsat
/2
So Q
channel
= C
ox
.W.L.(V
dsat
)
2
/(2.V
ds
)


nMOS Saturation Channel Charge
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
L
15
As before: I
ds
= Q
channel
/
= (C
ox
.W.L.(V
dsat
)
2
/(2

.V
ds
)) ((.V
ds
)/L
2
)
= (. C
ox
.(W/L)/2) . (V
dsat
)
2
= (/2). (V
gs
- V
t
)
2
Note that I
ds
= I
dsat
and is now independent of V
ds
MOS transistor in saturation behaves like a constant current
source (with respect to V
ds
)
Square law dependence on V
gs

nMOS Saturation I/V
n+ n+
p-type body
+
V
gd
gate
+ +
source
-
V
gs
-
drain
V
ds
channel
-
V
g
V
s
V
d
C
g
nMOS IV Linear Region

16

For

>

, channel saturates
Transistor behaves as a constant current source
I
ds
independent of V
ds

= ( 2) .

()

()

= 2

= 1.5

= 1
17
Shockley first-order model:
also known as ideal, long-channel model

nMOS I/V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V

<

| |
= <
|
\ .

>

0 1 2 3 4 5
0
0.5
1
1.5
2
2.5
V
ds
I
d
s

(
m
A
)
V
gs
=5
V
gs
=4
V
gs
=3
V
gs
=2
V
gs
=1 V
gs
=1
V
gs
=2
V
gs
=3
V
gs
=4
V
gs
=5
18
t
ox
= 100
= 350 cm
2
/V.s
V
t
= 0.7 V
Use W/L = 4/2

Example: 0.6m process
( )
14
2
8
3.9 8.85 10
350 120 /
100 10
ox
W W W
C A V
L L L

| |
| |
= = =
| |

\ .
\ .
19
t
ox
= 10.5
= 80 cm
2
/V.s
V
t
= 0.3 V
Use W/L = 4/2

Example: 65 nm process
= 262 . (W/L) A/V
2
20
Shockley first-order model:
also known as ideal, long-channel model

pMOS I/V Summary
( )
2
cutoff
linear
saturatio
0
2
2
n
gs t
ds
ds gs t ds ds dsat
gs t ds dsat
V V
V
I V V V V V
V V V V

<

| |
= <
|
\ .

>

>

>

<

21
All dopings and voltages are inverted for pMOS
Source is the more positive terminal
Mobility
p
is determined by holes
Typically 2-3x lower than that of electrons
n
120 cm
2
/V.s in 0.6 m process
Thus pMOS must be wider to
provide same current
In this class:
assume
n
/
p
= 2
pMOS I/V
-5 -4 -3 -2 -1 0
-0.8
-0.6
-0.4
-0.2
0
I
d
s
(
m
A
)
V
gs
=-5
V
gs
=-4
V
gs
=-3
V
gs
=-2
V
gs
=-1
V
ds
65nm
pMOS
22
Input to CMOS gate presents effectively infinite input
resistance
The dominant load in CMOS circuits is capacitance
Capacitance exists wherever there are two conductors
separated by a thin insulator
Gate to channel capacitor is very important
Creates channel charge necessary for operation
Source and drain have capacitance to body
Parasitic capacitance across reverse-biased diodes
Depletion region (insulator) separates N & P type conductors
Called diffusion capacitance because it is associated with
source/drain diffusion
Capacitance
23
Gate is top plate of capacitor
Assume bottom plate is source
In cut-off, bottom plate is actually the body
In linear mode, bottom plate is channel which is connected to
source and drain
In saturation, bottom plate is channel connected to source
C
gs
=
ox
.W.L/t
ox
= C
ox
.W.L = C
permicron
.W
C
permicron
is typically about 1-2 fF/m of width
Gate Capacitance
n+ n+
p-type body
W
L
t
ox
SiO
2
gate oxide
(good insulator,
ox
=3.9
0
)
polysilicon
gate
24
C
sb
, C
db
Diffusion region is
resistive and capacitive
(to body)
Capacitance depends on
area and perimeter
Use small as possible
diffusion nodes
Comparable to C
g
for
contacted diffusion
Use C
g
/2 for merged
Varies with process
Diffusion Capacitance
Isolated
Diffusion
G
g

C
node
=2.C
g
Shared
Diffusion
G
g

C
node
=C
g

Merged
Diffusion
G
g
/2

C
node
=C
g
/2


25
We have assumed source is grounded
or at least close to ground, pulling drain down
What if source >> 0?
e.g. nMOS pass transistor passing V
DD
V
g
= V
DD
If V
s
> V
DD
-V
t
, V
gs
< V
t
Hence transistor would turn itself off
nMOS pass transistors pull no higher than V
DD
-V
tn
Produces a degraded 1
Approach degraded value slowly (low I
ds
)
pMOS pass transistors pull no lower than |V
tp
|
Transmission gates are needed to pass both good 0 and good 1
Pass Transistors
V
DD
V
DD
26
Degraded Time Constant
V
DD
V
DD
C

I
ds
((V
DD
V
t
) - V
s
)
2
I
ds

pull-up device
is in saturation:
V
DD
C

I
ds
V
s

I
ds

pull-down device is
in linear (mostly):
V
DD
GND
V
DD
- V
t
t/

Pull-up time constant (to
90% final value) can be 6x
pull-down time constant!
27
Cascaded Pass Transistors
V
DD
V
DD
V
DD
- V
tn
| V
tp
|
V
DD
V
DD
V
DD
V
DD
V
DD
- V
tn
V
DD
- V
tn
V
DD
- V
tn
V
DD
V
DD
V
DD
- V
tn
V
DD
2.V
tn
28
Digital circuits are merely analog circuits used over a
constrained portion of their range
Derive DC transfer function for static CMOS inverter
When V
in
= 0 V
out
= V
DD
When V
in
= V
DD
V
out
= 0
In between, V
out
depends on
transistor size and current
By KCL, must settle such that
I
dsn
= | I
dsp
|

We could solve equations, but
Graphical solution gives more insight
DC Response: Inverter
I
dsn
I
dsp
V
out
V
DD
V
in
29
Current (I
dsn
, I
dsp
) depends on region of transistor behavior
For what V
in
and V
out
are nMOS and pMOS in
Cutoff?
Linear?
Saturation?
Transistor Operation
I
dsn
I
dsp
V
out
V
DD
V
in
30
Inverter: nMOS Operation
Cutoff Linear Saturated
V
gsn


V
gsn

V
dsn

V
gsn

V
dsn

I
dsn
I
dsp
V
out
V
DD
V
in
< V
tn
> V
tn
> V
tn
< V
gsn
- V
tn
> V
gsn
- V
tn
V
gsn
= V
in
V
dsn
= V
out
V
in
< V
tn
V
in
> V
tn
V
in
> V
tn
V
out
< V
in
- V
tn
V
out
> V
in
- V
tn
31
Inverter: pMOS Operation
Cutoff Linear Saturated
V
gsp
> V
tp
V
in
> V
DD
+ V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
> V
gsp
V
tp
V
out
> V
in
- V
tp
V
gsp
< V
tp
V
in
< V
DD
+ V
tp
V
dsp
< V
gsp
V
tp
V
out
< V
in
- V
tp
I
dsn
I
dsp
V
out
V
DD
V
in
V
gsp
= V
in
- V
DD
V
dsp
= V
out
- V
DD
(remember: V
dsp
and V
tp
< 0)

32
Mobility of holes is 2-3x less than mobility of electrons
Usually make pMOS 2x wider than nMOS
so that

I-V Characteristics
I
dsn
I
dsp
V
DD
V
DD
V
dsn
V
dsp
V
gsn0
V
gsn1
V
gsn2
V
gsn3
V
gsn4
V
gsn5
V
gsp0
V
gsp1
V
gsp2
V
gsp3
V
gsp4
V
gsp5
33
Replot I-V as function of V
out
& V
in
I
dsn
I
dsp
V
out
V
DD
V
in
V
out
is where I
dn
= -I
dp
V
inC
I
dsn
,

V
out
V
DD
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
V
inC
V
in5
V
in4
V
in3
V
in2
V
in1
V
in0
|I
dsp
|

34
Load Line Analysis

I
dsn
I
dsp
V
out
V
DD
V
in
V
in
= 0
V
in0
V
in0
I
dsn
,
|I
dsp
|

V
out
V
DD
35
Load Line Analysis

I
dsn
I
dsp
V
out
V
DD
V
in
V
in
= 0.2V
DD
V
in1
V
in1
I
dsn
,
|I
dsp
|

V
out
V
DD
36
Load Line Analysis

I
dsn
I
dsp
V
out
V
DD
V
in
V
in
= 0.4V
DD
V
in2
V
in2
I
dsn
,
|I
dsp
|

V
out
V
DD
37
Load Line Analysis

I
dsn
I
dsp
V
out
V
DD
V
in
V
in
= 0.5V
DD
V
inC
V
inC
I
dsn
,
|I
dsp
|

V
out
V
DD
38
Load Line Analysis

I
dsn
I
dsp
V
out
V
DD
V
in
V
in
= 0.6V
DD
V
in3
V
in3
I
dsn
,
|I
dsp
|

V
out
V
DD
39
Load Line Analysis

I
dsn
I
dsp
V
out
V
DD
V
in
V
in
= 0.8V
DD
V
in4
V
in4
I
dsn
,
|I
dsp
|

V
out
V
DD
40
Load Line Analysis

I
dsn
I
dsp
V
out
V
DD
V
in
V
in
= V
DD
V
in5
V
in5
I
dsn
,
|I
dsp
|

V
out
V
DD
41
Load Line Analysis

I
dsn
I
dsp
V
out
V
DD
V
in
V
inC
V
inC
I
dsn
,
|I
dsp
|

V
out
V
DD
V
in5
V
in5
V
in4
V
in4
V
in3
V
in3
V
in2
V
in2
V
in1
V
in1
V
in0
V
in0
42
DC Transfer Curve

C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
V
in0
V
in1
V
in2
V
in3
V
in4
V
in5
Trans-scribe points onto V
in
vs. V
out
plot
43
Supply Current

I
DD
= I
dsn
= -I
dsp






Zero current when in normal logic range
Transient current pulse drawn from V
DD
supply on each
switching event
I
DD
V
in
V
DD
0

44
Operating Regions

C
V
out
0
V
in
V
DD
V
DD
A B
D
E
V
tn
V
DD
/2 V
DD
+V
tp
V
in0
V
in1
V
in2
V
in3
V
in4
V
in5
Re-visit operating regions
Region nMOS pMOS
A
B
C
D
E
Cutoff
Saturation
Saturation
Linear
Linear
Cutoff
Saturation
Saturation
Linear
Linear
V
out
V
DD
V
in
45

Simulated 65nm DC Characteristic
46
If
p
/
n
1, switching point will move from V
DD
/2
Called skewed gate
Other gates: collapse into equivalent inverter
Beta Ratio

Restoring Logic
Reason that we can build digital circuits with millions
of gates and always get same answer is:
Most CMOS logic gates are restoring
output logic level is better than input logic level
47
input 0
input 1
output 1
output 0
48
How much noise can a gate input see before it does not
recognize the input?
Noise Margins
Indeterminate
Region
NM
L
NM
H
Input Characteristics Output Characteristics
V
OH
V
DD
V
OL
GND
V
IH
V
IL
Logical High
Input Range
Logical Low
Input Range
Logical High
Output Range
Logical Low
Output Range
49
To maximize noise margins, select worst case logic levels at
unity gain point of DC transfer characteristic
Nominal Logic Levels
V
out
V
in
V
DD
V
DD
0

V
out
V
DD
V
in

p
/
n
> 1
V
OH
V
OL
V
IL
V
IH
Unity Gain Points
Slope =-1

50
Example: MOS IV Formula
Suppose we connect two identical nMOS devices in series between VDD
and GND and connect the gates of each to VDD:










Assuming V
DD
> V
T
,
1.In which region is the upper transistor operating? Why?
2.In which region is the lower transistor operating? Why?
3.Derive an expression for the voltage V
x
at the intermediate node