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Electronic Circuits I

2007 Spring
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Chapter 3-1

Circuit Analysis and Design

Microelectronics

Chapter 3 The Field Effect Transistor

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Chapter 3-2

In this chapter, we will:

Study and understand the operation and characteristics of the various types of MOSFETs. Understand and become familiar with the dc analysis and design techniques of MOSFET circuits. Examine three applications of MOSFET circuits. (Switch, Digital Logic Gate, Amplifier) Investigate current source biasing of MOSFET circuits, such as those used in integrated circuits. Analyze the dc biasing of multistage or multitransistor circuits. Understand the operation and characteristics of the junction field-effect transistor, and analyze the dc response of JFET circuits.
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Chapter 3-3

Basic Structure of MOS Capacitor

Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) Two-terminal MOS Structure
Al or other metal polycrystalline Si polysilicon

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Chapter 3-4

MOS Capacitor Under Bias: Electric Field and Charge

Parallel plate capacitor

Negative gate bias:

Positively charged holes accumulated at the oxide-semiconductor interface

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Chapter 3-5

MOS Capacitor with p-type Substrate

Positive gate bias:

Electrons attracted to gate

Positive gate bias:

As the holes are pushed away from the oxide-semiconductor interface, a negative space-charge region is crated. When a larger positive voltage is applied to the gate, minority carrier electrons are attracted to the oxide-semiconductor interface. This region of minority carrier electrons is called an electron inversion layer.
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Chapter 3-6

MOS Capacitor with n-type Substrate

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Chapter 3-7

Schematic of n-Channel Enhancement-Mode MOSFET

The term enhancement mode means that a voltage must be applied to the gate to create an inversion layer.
The channel length L is less than 1m. 0.18m, 0.13m, 90nm, 51nm ... The oxide thickness tox is on the order of 400A or less.

MOS capacitor
Chapter 3-8

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Basic Transistor Operation

Zero bias to the gate Large positive gate voltage

Before electron inversion layer is formed

After electron inversion layer is formed

Enhancement-mode MOSFET

N-channel MOSFET(NMOS)
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Chapter 3-9

Basic Transistor Operation

The threshold voltage of the n-channel MOSFET, VTN, is defined as the applied gate voltage needed to create an inversion charge in which the density is equal to the concentration of majority carriers in the semiconductor substrate.

VTN is the gate voltage required to turn on the transistor

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Chapter 3-10

Current Versus Voltage Characteristics: Enhancement-Mode NMOSFET at nonsaturation vGS > VTN vGD = vGS vDS > VTN at saturation inversion vGS vDS (sat ) = VTN vDS (sat ) = vGS VTN
conduction parameter :
' W n Cox k n W Kn = = 2L 2 L

nonsaturation region : vDS < vDS (sat )

2 iD = K n 2(vGS VTN )vDS vDS

Cox =

ox
tox

saturation region : vDS > vDS (sat ) iD = K n (vGS VTN ) 2

EIEN307 I Chapter 3-11

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Cross section and iD Versus vDS for Enhancement-Mode NMOSFET

vGD > VTN

linear ohmic

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Chapter 3-12

Cross section and iD Versus vDS for Enhancement-Mode NMOSFET

vGD =VTN vGD < VTN

vGD = VTN vGS VDS (sat ) = VTN VDS (sat ) = vGS VTN
saturation

g o = 0 ro =
Independent of vDS

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Chapter 3-13

Family of iD Versus vDS Curves: Enhancement-Mode NMOSFET

nonsaturation region : vDS < vDS (sat )
2 iD = K n 2(vGS VTN )vDS vDS

saturation region : vDS > vDS (sat ) iD = K n (vGS VTN ) 2

triode region

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Chapter 3-14

p-Channel Enhancement-Mode MOSFET

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Chapter 3-15

Symbols for n-Channel Enhancement-Mode MOSFET

n-channel p-substrate

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Chapter 3-16

Symbols for p-Channel Enhancement-Mode MOSFET

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Chapter 3-17

n-Channel Depletion-Mode MOSFET

Normally-on device

A negative gate voltage must be applied to the n-channel depletion-mode MOSFET to turn the device off.

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Chapter 3-18

Family of iD Versus vDS Curves: Depletion-Mode nMOSFET

enhancement

depletion

Symbols
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Chapter 3-19

p-Channel DepletionMode MOSFET

skip

Symbols
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Chapter 3-20

Cross-Section of nMOSFET and pMOSFET

PMOS NMOS

Both transistors are used in the fabrication of CMOS circuitry.

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Chapter 3-21

Summary of I-V Relationships

Region NMOS PMOS vSD < vSD(sat)

Nonsaturation vDS < vDS(sat)

2 iD = Kn 2(vGS VTN)vDS vDS

2 iD = Kp 2(vSG +VTP)vSD vSD

Saturation

vDS > vDS (sat)

vSD > vSD (sat)

2

iD = K n (vGS VTN )
Transition Pt. Enhancement Mode Depletion Mode

iD = K p (vSG + VTP )
vSD(sat) = vSG + VTP VTP < 0V VTP > 0V

vDS(sat) = vGS - VTN VTN > 0V VTN < 0V

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Chapter 3-22

Conduction Parameters
' W n Cox k n W = Kn = 2L 2 L ' = nCox kn

NMOSFET

PMOSFET
where:

2L ' = p Cox kp Cox =

Kp =

W p Cox

' kp W = 2 L

ox
tox

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Chapter 3-23

Channel Length Modulation: Early Voltage

L is on the order of 0.2m or less for modern devices. Short-Channel Effects Finite Output Resistance Body Effect Subthreshold Conduction Breakdown Effects Tempertaure Effects

Channel-length modulation

I D = K n (vGS VTN ) 2 (1 + vDS )

is the channel - length modulation parameter.

iD ro = v DS ro I DQ
1

IDQ

= [K (v
n vGS = const

GSQ

VTN )

2 1

1 VA = = I DQ I DQ

VA+VDQ
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VDQ

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Chapter 3-24

Body Effect
Vo 0 VS2B 0

VTN = VTNO +

2 f + vSB 2 f

where VTNO is the threshold voltage for vSB = 0

is called body - effect parameter , and

is typically on the order of 0.5V1 2 ;

f is a function of semiconductor doping, on the order of 0.35V

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Chapter 3-25

Subthreshold Conduction

iD = K n (vGS VTN ) 2
linear
GS =VTN iD = K n (vGS VTN ) v iD = 0

vGS < VTN

Subthreshold current

Subthreshold current

Experimental results show that when vGS is slightly less than VTN, the drain current is not zero. DRAM
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Chapter 3-26

NMOS Common-Source Circuit

dc equivalent circuit

C-S Circuit
If VDS > VDS (sat ) = VG S VTN saturation If VDS < VDS (sat ) = VG S VTN nonsaturation
Total power dissipated in the transistor, since I G = 0 PT = I DVDS
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R2 VG = VGS = R +R VDD 2 1 I D = K n (VGS VTN ) 2 VDS = VDD I D RD

Chapter 3-27

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Example 3.3
Calculate ID and VDS of a common-source circuit with n-channel enhancement-mode MOSFET. Find the power dissipated in the transistor. Assume that R1=30k, R2=20k, RD=20k, VDD=5V, VTN=1V, and Kn=0.1mA/V2.

VDS = 3V VDS (sat ) = VGS VTN = 2 1 = 1V VDS > VDS (sat )

R2 20 VG = VGS = V = R + R DD 20 + 30 (5) = 2V 2 1 I D = K n (VGS VTN ) 2 = (0.1)(2 1) 2 = 0.1mA VDS = VDD I D RD = 5 (0.1)(20) = 3V PT = I DVDS = (0.1)(3) = 0.3mW
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Chapter 3-28

PMOS Common-Source Circuit

skip

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Chapter 3-29

Load Line and Modes of Operation: NMOS Common-Source Circuit

The transition point is the boundary between the saturation and nonsaturation region and is defined as the point where VDS = VDS(sat)=VGS - VTN

VDS = VDD I D RD = 5 I D (20) ID = 5 VDS (mA) 20 20

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Chapter 3-30

Problem-Solving Technique: NMOSFET DC Analysis

1. Assume the transistor is in saturation. a. VGS > VTN, ID > 0, & VDS VDS(sat) 2. Analyze circuit using saturation I-V relations. 3. Evaluate resulting bias condition of transistor. a. If VGS < VTN, transistor is likely in cutoff b. If VDS < VDS(sat), transistor is likely in nonsaturation region 4. If initial assumption is proven incorrect, make new assumption and repeat Steps 2 and 3.

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Chapter 3-31

Enhancement Load Device

VTN > 0 vDS = vGS > (vGS VTN ) = vDS (sat ) The transistor is always biased in the saturation.

2 ( ) iD = K n vGS VTN

enhancement - mode NMOS enhancement load device

Kn = 1mA/V2 VTN = 1V
VTN = 1V
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Chapter 3-32

Circuit with Enhancement Load Device and NMOS Driver

VDD R VI

ML is always in saturation.

MD can be biased either in saturation or nonsaturation region. amplifier or inverter

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Chapter 3-33

NMOS Inverter with Enhancement Load Device Example 3.11

vI < VTN vI > VTN

Voltage Transfer Characteristics:

For VI < 1V VO = VDD VTNL = 5 1 = 4V

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Chapter 3-34

Depletion-mode NMOS

>0

vGS = 0 VTN < 0

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Chapter 3-35

NMOS Inverter with Depletion Load Device

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Chapter 3-36

CMOS Inverter

on

PMOS off

off

NMOS on

very little power dissipation

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Chapter 3-37

Homework #5

Chapter 3 1, 9, 17, 19, 23, 29, 33, 39, 45, 49

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Chapter 3-38

Basic MOSFET Applications: Switch, Digital Logic gate, and Amplifier NMOS Inverter

vI < VTN iD = 0 vO = VDD vI > VTN vI > VDD saturation nonsaturation iD = K n 2(vI VTN )vO v vO = vDD I D RD

2 O

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Chapter 3-39

2-Input NMOS NOR Logic Gate

V1 (V) 0 5 0 5

V2 (V) VO (V) 0 0 5 5 High Low Low Low

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Chapter 3-40

MOS Small-Signal Amplifier

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Chapter 3-41

Constant-Current Biasing

IQ3

IQ2

VGS3 = VGS2 IQ3 = IQ2 Current mirror

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Chapter 3-42

Analyze the circuit shown in Fig. 3.53(a). Determine the bias current IQ1, the gate-to-source voltages of the transistors, and the drain-to-source voltage of M1.

Example 3.17

I REF 1 = 200 A, V + = 2.5V, V = 2.5V, VTN = 0.4V, = 0,

Solution : I D 3 = I REF 1 = 200 A I D 3 = K n 3 (VGS 3 VTN ) 2 since M 3 is in saturation. VGS 3 = I D3 0.2 + VTN = + 0.4 = 1.555V = VGS 2 K n3 0.15

K n1 = 0.25mA/V 2 , K n 2 = K n 3 = 0.15mA/V 2

I D 2 = I Q1 = K n 2(VGS 2 -VTN )2 = 0.15(1.555 - 0.4) 2 = 200 A VGS1 = I Q1 K n1 + VTN 0.2 = + 0.4 = 1.29V 0.25

VDS1 = V + -I Q1 RD -(-VGS 1 ) = 2.5 - (0.2)(8) - (-1.29) = 2.19V VDS (sat ) = VGS1-VTN = 1.29 0.4 = 0.89V
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VDS1 > VDS (sat) M 1 is biased in the saturation.

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Chapter 3-43

2-Stage Cascade Amplifier

Source follower

Common-source

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Chapter 3-44

NMOS Cascode Circuit

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Chapter 3-45

Cross Section of n-Channel Junction Field Effect Transistor (JFET)

pn junction

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Chapter 3-46

Cross Section of n-Channel MESFET

Metal-Semiconductor Field-Effect Transistor MESFET Schottky barrier junction Si MESFET GaAs MESFET

Metal

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Chapter 3-47