Int ro d u c t i o n t o H y p e r v i s o r Te c h n o l o gy Par t 1

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Introduction to Hyper visor Technology - Par t 1

History of the Hypervisor With the emergence in recent years of multi-core processors, a breakthrough computing innovation that promises to deliver higher performance without drastically increasing power, the embedded military industry finds itself in a new era of great potential, rife with system design choices never before available to software designers. In the early days of multicore, which originated in dual core architectures, operating system (OS) designers didnt know yet how to optimally leverage the processing potential of this promising new chip architecture. Whats more, software architects often struggled to understand why their applications, originally designed for a classic single core processor, would actually perform slower on the new multi-core technology. Today, operating systems are much more sophisticated: theyve evolved along with the multi-core technology which now frequently incorporates 4, 8 or 16 cores, and can now be leveraged by architects to harness the full processing power contained in contemporary multiple core offerings. The first efforts to exploit the potential of multi-core processors involved the use of Symmetrical Multi Processing (SMP). SMP emerged early as a popular way to evolve traditional single core applications to be able to take advantage of all available cores. With SMP all of the processors cores are controlled by a single OS. While this approach had advantages, the use of a single operating system was also found to be a serious limitation. For example, in the case where the application had hard real-time requirements as well as HMI (Human Machine Interface) and/ or control requirements, SMP resulted in a Real Time Operating System (RTOS) being overkill for the HM, while the standard operating system would be unable to manage the applications real-time requirements.
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In the previous example the ideal solution is to run two individual operating systems - one tailored for the real-time requirements and one designed for system management. Before the advent of multicore processors along with the operating systems designed to fully support them, the typical solution would have required an Asymmetrical Multiprocessor (AMP) architecture in which two individual physical processors are placed on a board, each with physically separated memory and hardware resources. In this AMP approach each processor would run a separate copy of its required operating systems. AMP continues to be appropriate for some system designs in High Performance Embedded Computing (HPEC) applications, but today they are both costly and too complex to use in classic Single Board Computer (SBC) applications. Today, with the quad-core Intel Core i7 and associated bridge, memory and hardware, its possible to design a SBC with multi-core processors and run multiple operating systems. The key element that makes it possible to move from older AMP designs to now fully leverage the potential of multi-core processors is Hypervisor.

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Introducing Hypervisor A Hypervisor provides a supervisory function and a framework that enables multiple operating systems commonly referred to as Guest Operating Systems to run on a single multi-core processor. A Hypervisor is fundamentally a small but highly refined operating system that resides on bare metal in other words, the Hypervisors instructions are the first executed by the BIOS after its POST is complete. A Hypervisor resides directly above and has full access to all of the SBCs hardware: memory, flash, NICs, etc. By using a Hypervisor running on a contemporary multi-core processor, it is now possible to support disparate applications running on separate operating systems across multiple cores all on a single, low-power processor. There are two types of Hypervisors. A Type 1 Hypervisor runs on bare metal as described above. A Type 2 Hypervisor runs on top of an existing operating system. For the embedded market space, the Type 1 Hypervisor has emerged as the ideal solution. Figure 1: Classic Type 1 Hypervisor architect supporting AMP

Hypervisor use cases are many, but tend toward three areas:

Disparate application requirements in a single

system (typically RTOS requirements coupled with an HMI) critical systems such as D0-178B applications security separation is the main concern

Separate operating systems for safety/non-safety MILS (Multiple Independent Levels of Security) where

RTOS + HMI An application that requires a hard real-time component RTOS and an HMI is the simplest Hypervisor use case. In this case, the Core i7 SBC would run the Hypervisor as a base and two Guest Operating Systems such as VxWorks for the RTOS, and Windows or Linux for the HMI. Safety Critical Systems In Safety Critical System applications, the key is certification which requires the ability to separate the non-safety from the safety critical application components during the certification process. Both Wind River and LynuxWorks provide Hypervisors as well as Guest Operating Systems that reside on the Intel Core i7 based SBC, and have been highly tested to stand up to the rigorous FAA requirements. Figure 2: Hypervisor example supporting Safety Critical separation

Operating System

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Operating System

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Hypervisor

Intel Core i7 CPU Core #1 CPU Core #2 CPU Core #3 CPU Core #4 Operating System Safety Critical Application Operating System Safety Critical Application Operating System Non-Safety Critical Operating System Non-Safety Critical

Several leading embedded operating system vendors, including Wind River and LynuxWorks, have introduced their unique versions of a Hypervisor. The common thread among the various Hypervisor offerings is their support for Intel Core i7 2nd and 3rd generation processors. Intels ground-breaking Core i7 architecture enables SBC designers to place four cores at 2.1GHz and 16 GB of memory on a single board, thus creating the ideal platform to run a Hypervisor and host several operating systems.
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MILS MILS has emerged as a highly critical requirement in the Aerospace and Defense market, particularly for Size, Weight, and Power (SWaP) sensitive architectures. MILS applications typically involve a RTOS + HMI architecture with the addition of a security component to the system. With MILS a single computer may be used to run several applications, some of which may be highly sensitive and so must be partitioned from the non-sensitive applications. Meeting the MILS requirement requires the use of a Hypervisor capable of running several Guest Operating Systems while ensuring that the individual data from the Guest Operating System is kept completely separated. One example of a MILS application is the U.S. Armys new Vehicular Integration for C4ISR/EW Interoperability (VICTORY) architecture. VICTORY defines a set of open standards in which current multiple stovepipe subsystems are replaced with a shared open architecture networked approach. VICTORY makes it possible to deploy a single system running multiple applications, to replace multiple systems each running a single application and maintain the high level of security required by a MILS application. Hypervisor fits perfectly with the goals and spirit of the US Armys VICTORY initiative. Figure 3: Hypervisor example supporting MILS application
Operating System RTOS Secure Operating System Router Secure Operating System RTOS Non-Secure Operating System HMI Application Non-Secure

Curtiss-Wright Controls Defense Solutions Support of Hypervisor Applications Curtiss-Wrights Intel Core i7-based family of SBCs is uniquely designed to support any application requiring a Hypervisor. With a rich selection of Core i7-based platforms, designed to meet the most demanding embedded processing requirements, these rugged SBCs include 6U VME and 3U and 6U VPX form factors, and support maximizing system resources such as SDRAM and Flash memory and high speed I/O. Currently, the extremely popular small form factor 3U OpenVPX VPX3-1257 is available with both Wind Rivers and LynuxWorks Hypervisor. For more intensive computing applications, our 6U OpenVPX VPX6-1957, and follow-on family members, also support leading Hypervisor technologies.

Contact Information To find your appropriate sales representative: Website: www.cwcdefense.com/sales Email: defensesales@curtisswright.com Technical Support For technical support: Website: www.cwcdefense.com/support Email: support@curtisswright.com The information in this document is subject to change without notice and should not be construed as a commitment by Curtiss-Wright Controls Defense Solutions. While reasonable precautions have been taken, Curtiss-Wright assumes no responsibility for any errors that may appear in this document. All products shown or mentioned are trademarks or registered trademarks of their respective owners. *Other names and brands may be claimed as the property of others.

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