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The ARM architecture (previously, the Advanced RISC Machine, and prior to that Acorn RISC Machine) is a 32-bit

RISC processor architecture developed by ARM Limited that is widely used in embedded designs. Because of their power saving features, ARM CPUs are dominant in the mobile electronics market, where low power consumption is a critical design goal[1]. Today, the ARM family accounts for approximately 75% of all embedded 32bit RISC CPUs,[2] making it one of the most widely used 32-bit architectures. ARM CPUs are found in most corners of consumer electronics, from portable devices (PDAs, mobile phones, media players, handheld gaming units, and calculators) to computer peripherals (hard drives, desktop routers); however it no longer has significant penetration as the main processor in the desktop computer market and has never been used in a supercomputer or cluster. Prominent branches in this family include Marvell's XScale and the Texas Instruments OMAP series. Design notes To keep the design clean, simple and fast, it was hardwired without microcode, like the much simpler 8-bit 6502 processor used in prior Acorn microcomputers. The ARM architecture includes the following RISC features: * Load/store architecture * No support for misaligned memory accesses (now supported in ARMv6 cores, with some exceptions related to load/store multiple word instructions) * Uniform 16 32-bit register file * Fixed instruction width of 32 bits to ease decoding and pipelining, at the cost of decreased code density. (Later, "Thumb mode" increased code density.) * Mostly single-cycle execution To compensate for the simpler design, compared with contemporary processors like the Intel 80286 and Motorola 68020, some unique design features were used: * Conditional execution of most instructions, reducing branch overhead and compensating for the lack of a branch predictor

* Arithmetic instructions alter condition codes only when desired * 32-bit barrel shifter which can be used without performance penalty with most arithmetic instructions and address calculations * Powerful indexed addressing modes * A link register for fast leaf function calls. * Simple, but fast, 2-priority-level interrupt subsystem with switched register banks An interesting addition to the ARM design is the use of a 4-bit condition code on the front of every instruction, meaning that execution of every instruction is optionally conditional. Other CPU architectures typically only have condition codes on branch instructions. This cuts down significantly on the encoding bits available for displacements in memory access instructions, but on the other hand it avoids branch instructions when generating code for small if statements. The standard example of this is the Euclidean algorithm:

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