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FINALTERM EXAMINATION Fall 2009 CS302- Digital Logic Design (Session - 1) Question No: 1 ( Marks: 1 ) - Please choose one
The output of an AND gate is one when _______
All of the inputs are one Any of the input is one Any of the input is zero All the inputs are zero Question No: 2 ( Marks: 1 ) - Please choose one
The OR Gate performs a Boolean _______ function
Addition Subtraction Multiplication Division Question No: 3 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value.
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True False Question No: 4
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( Marks: 1 ) - Please choose one
The binary numbers A = 1100 and B = 1001 are applied to the inputs of a comparator. What are the output levels?
A > B = 1, A < B = 0, A < B = 1 A > B = 0, A < B = 1, A = B = 0 A > B = 1, A < B = 0, A = B = 0 A > B = 0, A < B = 1, A = B = 1 Question No: 5 ( Marks: 1 ) - Please choose one
AND Gate level
NOT Gate level
OR Gate level
The diagram above shows the general implementation of _____ form boolean arbitrary POS SOP Question No: 6 ( Marks: 1 ) - Please choose one
The device shown here is most likely a
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Comparator Multiplexer Demultiplexer Parity generator Question No: 7 ( Marks: 1 ) - Please choose one
Demultiplexer converts _______ data to __________ data
Parallel data, serial data Serial data, parallel data Encoded data, decoded data All of the given options. Question No: 8 ( Marks: 1 ) - Please choose one Flip flops are also called _____________ Bi-stable dualvibrators Bi-stable transformer Bi-stable multivibrators Bi-stable singlevibrators Question No: 9 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 10 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop 0 1 Invalid Input is invalid

Question No: 11 ( Marks: 1 )
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- Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
Doesnt have an invalid state Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 12 ( Marks: 1 ) - Please choose one
The minimum time for which the input signal has to be maintained at the input of flip-flop is called ______ of the flip-flop.
Set-up time Hold time Pulse Interval time Pulse Stability time (PST)
Question No: 13
( Marks: 1 )
- Please choose one
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by ___________
Using S-R Flop-Flop D-flipflop J-K flip-flop T-Flip-Flop Question No: 14 True False Question No: 15 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________ Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set
( Marks: 1 )
- Please choose one

In
asynchronous digital systems all the circuits change their state with respect to a common clock
Question No: 16
( Marks: 1 )
- Please choose one
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negative edge-triggered flip-flop changes its state when ________________ Enable input (EN) is set Preset input (PRE) is set Low-to-high transition of clock High-to-low transition of clock
Question No: 17
( Marks: 1 )
- Please choose one
A flip-flop is connected to +5 volts and it draws 5 mA of current during its operation, the power dissipation of the flip-flop is
10 mW 25 mW 64 mW 1024 Question No: 18 ( Marks: 1 ) - Please choose one
__________occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options
Question No: 19
( Marks: 1 )
- Please choose one A
counter is implemented using three (3) flip-flops, possibly it will have ________ maximum output status. 3 7 8 15
Question No: 20
( Marks: 1 )
- Please choose one

A
divide-by-50 counter divides the input ______ signal to a 1 Hz signal. 10 Hz 50 Hz
100 Hz

500 Hz Question No: 21 ( Marks: 1 )
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The
- Please choose one
design and implementation of synchronous counters start from _________ Truth table k-map state table state diagram Question No: 22 ( Marks: 1 ) - Please choose one A synchronous decade counter will have _______ flip-flops 3 4 7 10
Question No: 23
( Marks: 1 )
- Please choose one

The
output of this circuit is always ________.
1 0 A Question No: 24 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? 2 4 6 8 Question No: 25 ( Marks: 1 ) - Please choose one
In
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_______ the output of the last flip-flop of the shift register is connected to the data input of the first flip-flop. Moore machine Meally machine Johnson counter Ring counter
Question No: 26
( Marks: 1 )
- Please choose one
In ________ Q output of the last flip-flop of the shift register is connected to the data input of the first flipflop of the shift register.
Moore machine Meally machine Johnson counter Ring counter Question No: 27 ( Marks: 1 ) - Please choose one
Which is not characteristic of a shift register?
Serial in/parallel in Serial in/parallel out Parallel in/serial out Parallel in/parallel out Question No: 28 ( Marks: 1 ) - Please choose one
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.)
1100 0011 0000 1111 Question No: 29 ( Marks: 1 ) - Please choose one
The _________ of a ROM is the time it takes for the data to appear at the Data Output of the ROM chip after an address is applied at the address input lines
Write Time Recycle Time Refresh Time Access Time

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The
- Please choose one
sequence of states that are implemented by a n-bit Johnson counter is
n+2 (n plus 2) 2n (n multiplied by 2) 2n (2 raise to power n) n2 (n raise to power 2) Question No: 31 ( Marks: 1 )
In the statement "X PIN 22 ISTYPE reg.buffer" What is the meaning of the keyword reg.buffer
Question No: 32
( Marks: 1 )
What are the two basic operations which are performed on memory?
Reading of information from the memory and Writing of data on the memory.
Question No: 33
( Marks: 2 )
Explain state assignment process. Question No: 34 ( Marks: 2 )
What is RAM Stack, which register stores the address of the top of the stack?
Question No: 35
( Marks: 3 )
How can we calculate the frequency of an unknown signal? Question No: 36 ( Marks: 3 )
Explain dynamic RAM in your own words.
Question No: 37
( Marks: 3 )
Suppose a 2 bit up-down counter having states A, B, C, D. the counter counts upward when X=1 and downward when X=0. Write down IF-THEN-ELSE statements to show how present states change to next states and previous states.

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Explain memory read operation with the help of an example.
Question No: 39
( Marks: 5 )
Draw the next-state table of any sequential counter with the help of J-K flip flop transition Question No: 40 ( Marks: 10 ) You are given the diagram of up-down counter; explain how it works as an up and down counter.
Question No: 41
( Marks: 10 )
Consider a state sequence a, b, c, f, d, d, c, f, d, c, a, f, d, c. Starting from initial state a, draw a table for the inputs and outputs for the state diagram given below (up to first ten transitions).
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FINALTERM EXAMINATION Fall 2009 CS302- Digital Logic Design (Session - 2) Ref No: 1129616 Time: 120 min Marks: 75 Student Info StudentID: Center: ExamDate: BC080402322 OPKST 3/6/2010 12:00:00 AM
For Teacher's Use Only Q No. 1 2 Marks Q No. Marks Q No. Marks Q No. Marks Q No. 33 34 25 26 17 18 9 10
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Cav
- Please choose one
eman number system is Base ______ number system 2 5 10 16 Question No: 2 ( Marks: 1 ) - Please choose one
The output of an XOR gate is zero (0) when __________ I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one
I Only IV Only I and IV only II and III only Question No: 3 ( Marks: 1 ) - Please choose one
The decimal 17 in BCD will be represented as _________10001(right opt is not given) 11101 11011 10111 11110 Question No: 4 ( Marks: 1 ) - Please choose one A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value.
True False Question No: 5 ( Marks: 1 ) - Please choose one

The simplest and most commonly used Decoders are the ______ Decoders
n to 2n (n-1) to 2n

(n-1) to (2 -1) n to 2n-1 Question No: 6 ( Marks: 1 )
n
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- Please choose one

The
_______ Encoder is used as a keypad encoder.
2-to-8 encoder 4-to-16 encoder BCD-to-Decimal Decimal-to-BCD Priority Question No: 7 ( Marks: 1 ) - Please choose one
3-to8 decoder can be used to implement Standard SOP and POS Boolean expressions
True False Question No: 8 ( Marks: 1 ) - Please choose one If S=1 and R=0, then Q(t+1) = _________ for positive edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 9 ( Marks: 1 ) - Please choose one
If the S and R inputs of the gated S-R latch are connected together using a ______ gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated DLatch)
AND OR NOT XOR Question No: 10 True False Question No: 11 ( Marks: 1 ) - Please choose one ( Marks: 1 ) - Please choose one
In asynchronous digital systems all the circuits change their state with respect to a common clock
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The
low to high or high to low transition of the clock is considered to be a(n) ________ State Edge Trigger One-shot
Question No: 12
( Marks: 1 )
- Please choose one

A
positive edge-triggered flip-flop changes its state when ________________ Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set
Question No: 13
( Marks: 1 )
- Please choose one

RCO
Stands for _________
Reconfiguration Counter Output Reconfiguration Clock Output Ripple Counter Output Ripple Clock Output
Question No: 14
( Marks: 1 )
- Please choose one
Bistable devices remain in either of their _________ states unless the inputs force the device to switch its state
Ten Eight Three Two Question No: 15 ( Marks: 1 ) - Please choose one ____ _______ is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) Question No: 16 ( Marks: 1 ) - Please choose one
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____ ______occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. Race condition Clock Skew Ripple Effect None of given options
Question No: 17
( Marks: 1 )
transparent mode means _____________
The changes in the data at the inputs of the latch are seen at the output The changes in the data at the inputs of the latch are not seen at the output Propagation Delay is zero (Output is immediately changed when clock signal is applied) Input Hold time is zero (no need to maintain input after clock transition) Question No: 18 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the current state.
Mealy machine Moore Machine State Reduction table State Assignment table Question No: 19 ( Marks: 1 ) - Please choose one
The alternate solution for a multiplexer and a register circuit is _________
Parallel in / Serial out shift register Serial in / Parallel out shift register Parallel in / Parallel out shift register Serial in / Serial Out shift register Question No: 20 ( Marks: 1 ) - Please choose one
The alternate solution for a demultiplexer-register combination circuit is _________
Parallel in / Serial out shift register Serial in / Parallel out shift register Parallel in / Parallel out shift register

Serial in / Serial Out shift register Question No: 21 ( Marks: 1 )
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In
- Please choose one
asynchronous transmission when the transmission line is idle, _________
It is set to logic low It is set to logic high Remains in previous state State of transmission line is not used to start transmission Question No: 22 ( Marks: 1 ) - Please choose one
Smal lest unit of binary data is a ________
Bit Nibble Byte Word Question No: 23 ( Marks: 1 ) - Please choose one
A Nibble consists of _____ bits

A GAL is essentially a ________.
Non-reprogrammable PAL PAL that is programmed only by the manufacturer Very large PAL Reprogrammable PAL Question No: 25 ( Marks: 1 ) - Please choose one A 8bit serial in / parallel out shift register contains the value 8, _____ clock signal(s) will be required to shift the value completely out of the register. 1 2

4 8 Question No: 26 ( Marks: 1 )
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- Please choose one DRA
M stands for __________
Dynamic RAM Data RAM Demoduler RAM None of given options Question No: 27 ( Marks: 1 ) - Please choose one
FIFO is an acronym for __________
First In, First Out Fly in, Fly Out Fast in, Fast Out None of given options Question No: 28 ( Marks: 1 ) - Please choose one
In the circuit diagram of 3-bit synchronous counter shown above, The red rectangle would be replaced by which gate?
AND OR NAND XNOR

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The
- Please choose one
sequence of states that are implemented by a n-bit Johnson counter is
n+2 (n plus 2) 2n (n multiplied by 2) 2n (2 raise to power n) n2 (n raise to power 2) Question No: 30 ( Marks: 1 ) - Please choose one
Stac k is an acronym for _________
FIFO memory LIFO memory Flash Memory Bust Flash Memory Question No: 31 ( Marks: 1 )
Gen erally two types of D/A Converters are used. Name at least one.
One type of D/A converter is electromechanical-also called shaft- or position-to-digitaland electronic.
Question No: 32
( Marks: 1 )
Nam
e at least one device that converts signals form analog to digital or from digital to analogue.
A codec (coder/decoder) is a device that converts an analog signal into a digital signal. Mobile phone converts signals from digital to analogue and from analogue to digital.
Question No: 33
( Marks: 2 )
How
glitches due to race condition can be avoided?
A new clocking scheme is developed to produce race-free, glitch-free outputs of synchronous digital systems. The maximum input clock frequency for race-free operation is calculated as a single-phase system. Output signals are sampled at twice the input clock frequency, at time instants when the glitches are not there. Using the scheme, glitches generated anywhere within a quarter (T/4) of the input clock period (T) can be eliminated. The margin T/4 is large enough for most practical systems. Hence the scheme is of universal application as verified by the simulation of two 3 m CMOS gate array ASICs, designed using VINYAS CAD tools.

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For a four bit serial in/serial out shift register is initially set to 0000. We want to enter the value 1111. How many clock pulses will be required to enter the data and then again bring the contents of register to 0000.
After 8 clock pulses the 4-bit data is completely shifted out of the shift register. The register is first cleared, forcing all four outputs to zero. The input data is then applied sequentially to the D input of the first flip-flop on the left (FF0). During each clock pulse, one bit is transmitted from left to right Question No: 35 ne down counter. In digital logic and computing, a counter is a device which stores (and sometimes displays) the number of times a particular event or process has occurred, often in relationship to a clock signal. Down counters, are those which decrease (decrement) in value. Decrement the counter by one (if it's already zero, this leaves it unchanged) Question No: 36 ( Marks: 3 ) ( Marks: 3 ) Defi
Expl ain Rotate Left Operation with the help of diagram. The serial output of the register is connected to the serial input of the register. By applying clock pulses data is shifted left. The data shifted out of the serial out pin at the left hand side is re-circulated back into the shift register input at the right hand side. Thus the data is rotated left within the register.
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Question No: 37
( Marks: 3 )
Expl
ain dynamic RAM in your own words.
DRAM
Dynamic RAM (DRAM) is a type of RAM that contains a single transistor and a capacitor. DRAM is smaller than SRAM, and therefore can store more data in a smaller area. Because of the charge and discharge times of the capacitor, however, DRAM tends to be slower than SRAM. Many modern types of Main Memory are based on DRAM design because of the high memory densities. Because DRAM is simpler than SRAM, it is typically cheaper to produce. A popular type of RAM, SDRAM, is a variant of DRAM and is not related to SRAM. As digital circuits continue to grow smaller and faster as per Moore's Law, the speed of DRAM is not increasing as rapidly. This means that as time goes on, the speed difference between the processor and the RAM units (so long as the RAM is based on DRAM or variants) will continue to increase, and communications between the two units becomes more inefficient.
Question No: 38
( Marks: 5 ) Expl
ain memory write operation with the help of an example. Memory write operation:
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The method employs a two-step technique which allows the out-of-order completion of read and write operations. When a write operation requires a resource needed for the completion of a read operation, the data being written is stored in a write data buffer in the memory device. The write data is stored in the buffer until a datapath is available to communicate the data to the memory device's memory core. Once the resource is free (or the memory device, or its controller force the write to complete) the data is written to the memory core of the memory device using the now-free datapath. A diagnostic memory write operation uses the same CSRs as the read. The data is written to the CSR data register, and the address at which the data is to be stored is written to the CSR diagnostic address register.
Question No: 39
( Marks: 5 ) Conv
ert the following state diagram into state table
Present state Q2 0 0 0 0 1 1 1 1
Q1 0 0 1 1 0 0 1 1
Q0 0 1 0 1 0 1 0 1
Next stat Q2 0 0 0 1 1 1 1 0
Q1 0 1 1 0 0 1 1 0
Q0 1 0 1 0 1 0 1 0
Question No: 40
( Marks: 10 )
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Give
n below is the circuit diagram of parallel in / serial out shift register. Explain how this circuit works (serially shifts the data)
SHIFT / LOAD
Question No: 41
( Marks: 10 )
Brief
ly explain address multiplexing in DRAM.
. FINALTERM EXAMINATION Fall 2009 CS302- Digital Logic Design (Session - 4) Ref No: 1129612 Time: 120 min Marks: 75 For Teacher's Use Only Q 1 2 3 No. Marks Q No. Marks Q No. Marks Q No. Marks 25 26 27 28 29 30 31 32 17 18 19 20 21 22 23 24 9 10 11
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NOR Gate can be used to perform the operation of AND, OR and NOT Gate FALSE TRUE Question No: 2 ( Marks: 1 ) - Please choose one
The output of an XNOR gate is 1 when ____________ I) All the inputs are zero II) Any of the inputs is zero III) Any of the inputs is one IV) All the inputs are one
I Only IV Only I and IV only II and III only Question No: 3 ( Marks: 1 ) - Please choose one
NAND gate is formed by connecting _________ AND Gate and then NOT Gate NOT Gate and then AND Gate AND Gate and then OR Gate OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one
Consider A=1,B=0,C=1. A, B and C represent the input of three bit NAND gate the output of the NAND gate will be _____ Zero One Undefined No output as input is invalid Question No: 5 ( Marks: 1 ) - Please choose one
The capability that allows the PLDs to be programmed after they have been installed on a circuit board is called __________
Radiation-Erase programming method (REPM)
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In-System Programming (ISP) In-chip Programming (ICP) Electronically-Erase programming method(EEPM) Question No: 6 ( Marks: 1 ) - Please choose one
The ABEL symbol for OR operation is
! & # $ Question No: 7 ( Marks: 1 ) - Please choose one If S=1 and R=1, then Q(t+1) = _________ for negative edge triggered flip-flop 0 1 Invalid Input is invalid Question No: 8 ( Marks: 1 ) - Please choose one
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop ___________
Doesnt have an invalid state Sets to clear when both J = 0 and K = 0 It does not show transition on change in pulse It does not accept asynchronous inputs Question No: 9 ( Marks: 1 ) - Please choose one For a gated D-Latch if EN=1 and D=1 then Q(t+1) = _________ 0 1 Q(t) Invalid Question No: 10 True False Question No: 11 ( Marks: 1 ) - Please choose one
A positive edge-triggered flip-flop changes its state when ________________
( Marks: 1 )
- Please choose one
In asynchronous digital systems all the circuits change their state with respect to a common clock

Low-to-high transition of clock High-to-low transition of clock Enable input (EN) is set Preset input (PRE) is set Question No: 12 ( Marks: 1 )
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- Please choose one
___________ is one of the examples of asynchronous inputs. J-K input S-R input D input Clear Input (CLR) Question No: 13 ( Marks: 1 ) - Please choose one
The _____________ input overrides the ________ input Asynchronous, synchronous Synchronous, asynchronous Preset input (PRE), Clear input (CLR) Clear input (CLR), Preset input (PRE)
Question No: 14
( Marks: 1 )
- Please choose one
Following Is the circuit diagram of mono-stable device which gate will be replaced by the red colored rectangle in the circuit.
AND NAND NOR XNOR Question No: 15 ( Marks: 1 ) - Please choose one
In ________ outputs depend only on the combination of current state and inputs.
Mealy machine Moore Machine

State Reduction table State Assignment table Question No: 16 ( Marks: 1 )
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- Please choose one
________ is used to simplify the circuit that determines the next state. State diagram Next state table State reduction State assignment
Question No: 17
( Marks: 1 )
multiplexer with a register circuit converts _________ Serial data to parallel Parallel data to serial Serial data to serial Parallel data to parallel Question No: 18 ( Marks: 1 ) - Please choose one
In asynchronous transmission when the transmission line is idle, _________
It is set to logic low It is set to logic high Remains in previous state State of transmission line is not used to start transmission Question No: 19 ( Marks: 1 ) - Please choose one
In the following statement Z PIN 20 ISTYPE reg.invert; The keyword reg.invert indicates ________
An inverted register input An inverted register input at pin 20 Active-high Registered Mode output Active-low Registered Mode output Question No: 20 ( Marks: 1 ) - Please choose one
A Nibble consists of _____ bits

2 4 8 16 Question No: 21 ( Marks: 1 )
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- Please choose one

The
output of this circuit is always ________.
1 0 A Question No: 22 ( Marks: 1 ) - Please choose one At T0 the value stored in a 4-bit left shift was 1. What will be the value of register after three clock pulses? 2 4 6 8 Question No: 23 ( Marks: 1 ) - Please choose one
A input is LOW. The nibble bidirectional 4-bit shift register is storing the nibble 1110. Its 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing ________.
The high density FLASH memory cell is implemented using ______________
1 floating-gate MOS transistor

2 floating-gate MOS transistors 4 floating-gate MOS transistors 6 floating-gate MOS transistors Question No: 25 ( Marks: 1 )
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- Please choose one
In order to synchronize two devices that consume and produce data at different rates, we can use _________
Read Only Memory Fist In First Out Memory Flash Memory Fast Page Access Mode Memory Question No: 26 ( Marks: 1 ) - Please choose one
If the FIFO Memory output is already filled with data then ________
It is locked; no data is allowed to enter It is not locked; the new data overwrites the previous data. Previous data is swapped out of memory and new data enters None of given options Question No: 27 ( Marks: 1 ) - Please choose one
The process of converting the analogue signal into a digital representation (code) is known as ___________
Strobing Amplification Quantization Digitization Question No: 28 ( Marks: 1 ) - Please choose one

Above is the circuit diagram of _______. Asynchronous up-counter Asynchronous down-counter Synchronous up-counter Synchronous down-counter Question No: 29 ( Marks: 1 )
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- Please choose one
(A + B)(A + B + C)(A + C)
is an example of ______________
Product of sum form Sum of product form Demorgans law Associative law Question No: 30 ( Marks: 1 ) - Please choose one
Q2 :=Q1 OR X OR Q3 The above ABEL expression will be
Q2:= Q1 $ X $ Q3 Q2:= Q1 # X # Q3 Q2:= Q1 & X & Q3 Q2:= Q1 ! X ! Q3
Question No: 31
( Marks: 1 )
How the hour counter is implemented in a digital clock (i.e. how many counters are used and what is their configuration Mod)? Question No: 32 ( Marks: 1 )
The top of the stack contains the value 5 and bottom of the stack contains the value 6, a pop (read data from stack) operation was executed, which value would be read?
Question No: 33
( Marks: 2 )
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What kind of devices use the shift register based First In First Out (FIFO) memory?
Ans: FIFOs are used commonly in electronic circuits for buffering and flow control which is from hardware to software. In hardware form a FIFO primarily consists of a set of read and write pointers, storage and control logic. Storage may be SRAM, flip-flops, latches or any other suitable form of storage. For FIFOs of non-trivial size a dual-port SRAM is usually used where one port is used for writing and the other is used for reading. Question No: 34 ( Marks: 2 )
Differentiate between positive-edge triggered flip-flop and negative edge-triggered flipflop.
Ans: A negative edge triggered flip-flop generates an output pulse in response to a negative edge of a clock signal. A first set of nodes receives data input signals, and a second set of nodes receives select input signals for selecting one data input signal as a selected data input signal. The clock node receives the clock signal which has a positive edge and a negative edge. A header circuit connects to the second set of nodes and to the clock node, and integrates the clock signal with the select input signals to generate at least one control signal. A pulse generator circuit connects to the first set of nodes, the header circuit and the output node. The pulse generator circuit generates an output pulse on the output node in response to a control signal and the selected data input signal. The operation and truth table for a negative edge-triggered flip-flop are the same as those for a positive except that the falling edge of the clock pulse is the triggering edge.
Question No: 35
( Marks: 3 )
Name some of the important operating characteristics of flip-flops Ans; The operating characteristics mention here apply to all flip-flops regardless of the particular form of the circuit. They are typically found in data sheets for integrated circuits. They specify the performance, operating requirements, and operating limitations of the circuit.
Propagation Delay Time - is the interval of time required after an input signal has
been applied for the resulting output change to occur.
Set-Up Time - is the minimum interval required for the logic levels to be
maintained constantly on the inputs (J and K, or S and R, or D) prior to the triggering
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edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
Hold Time - is the minimum interval required for the logic levels to remain on the
inputs after the triggering edge of the clock pulse in order for the levels to be reliably clocked into the flip-flop.
Maximum Clock Frequency - is the highest rate that a flip-flop can be

reliably triggered.
Power Dissipation - is the total power consumption of the device. Pulse Widths - are the minimum pulse widths specified by the manufacturer for
the Clock, SET and CLEAR inputs. Question No: 36 ( Marks: 3 )
What is memory expansion process?
Computers ad digital system have the capability to to allow RAM memory to be extended as the needed arise by inserting extra memory in dedicated memory sockets on the computer motherboard.th e total amount of memory that is supported by any digital system depends upon the size of the address bus of micro processor or a micro controller.
Question No: 37
( Marks: 3 )
Write down at least three characteristics of serial in / serial out 4-bit right shift register. Ans: A serial-in/serial-out shift register has a clock input, a data input, and a data output from the last stage. In general, the other stage outputs are not available Otherwise, it would be a serial-in, parallel-out shift register.. The waveforms below are applicable to either one of the preceding two versions of the serial-in, serial-out shift register. The three pairs of arrows show that a three stage shift register temporarily stores 3-bits of data and delays it by three clock periods from input to output. Question No: 38 ( Marks: 5 )
Explain Flash Analogue-to Digital Converter. Flash Analogue-to Digital Converter:
A flash analogue to digital converter is the fastest type of converter we use. Like the successive approximation converter it works by comparing the input signal to a reference voltage, but a flash converter has as many comparators as there are steps in the comparison. An 8-bit converter, therefore, has 2 to the power 8, or 256, comparators. The resistor net and comparators provide an input to the combinational logic circuit, so
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the conversion time is just the propagation delay through the network - it is not limited by the clock rate or some convergence sequence. It is the fastest type of ADC available, but requires a comparator for each value of output (63 for 6-bit, 255 for 8-bit, etc.) Such ADCs are available in IC form up to 8-bit and 10-bit flash ADCs (1023 comparators) are planned. The encoder logic executes a truth table to convert the ladder of inputs to the binary number output. Question No: 39 ( Marks: 5 )
Explain the next-state table with the help of a table for any sequential circuit. Ans
State Table
The state table representation of a sequential circuit consists of three sections labelled present state, next state and output. The present state designates the state of flip-flops before the occurrence of a clock pulse. The next state shows the states of flip-flops after the clock pulse, and the output section lists the value of the output variables during the present state. Present state Q1Q2 00 01 10 11 Next state x=0 11 11 10 10 Next state x=1 01 00 11 10 Out put x=0 0 0 0 0 Out put x=1 0 0 1 1
Question No: 40
( Marks: 10 )
Why the inputs of S-R, J-K and D-flip-flops are called synchronous inputs. What are asynchronous inputs, explain effect of PRE and CLR inputs on flip-flops.
Ans: The normal data inputs to a flip flop (D, S and R, or J and K) are referred to as synchronous inputs because they have effect on the outputs (Q and not-Q) only in step, or in sync, with the clock signal transitions. These extra inputs that I now bring to your attention are called asynchronous because they can set or reset the flip-flop regardless of the status of the clock signal. Typically, they're called preset and clear:
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When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of the synchronous inputs or the clock. When the clear input is activated, the flipflop will be reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock. So, what happens if both preset and clear inputs are activated? Surprise, surprise: we get an invalid state on the output, where Q and not-Q go to the same state, the same as our old friend, the S-R latch! Preset and clear inputs find use when multiple flip-flops are ganged together to perform a function on a multi-bit binary word, and a single line is needed to set or reset them all at once. Asynchronous inputs, just like synchronous inputs, can be engineered to be active-high or active-low. If they're active-low, there will be an inverting bubble at that input lead on the block symbol, just like the negative edge-trigger clock inputs.
Sometimes the designations "PRE" and "CLR" will be shown with inversion bars above them, to further denote the negative logic of these inputs:
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Question No: 41
( Marks: 10 )
Explain the following in context of Memory: Address signals A memory circuit, in using address transition detection to equilibrate bit lines, generates a summation address transition signal for the row address as well as a summation address transition signal for the column address. There is a transition detector for each address signal. The outputs of the transition detectors for the row address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the row address. Similarly, the outputs of the transition detectors for the column address signals are summed in at least two logic stages using CMOS logic gates to generate the summation address signal for the column address.
Data signals Method of how information is transferred; usually it is transferred in binary code in signals or pulses. A phase lock oscillator includes a phase discriminator that develops an error signal by comparing a clock from a voltage controlled oscillator with incoming random data bits. In the absence of data, the phase lock oscillator is inactive. However, when data is sensed, a logic and delay network in the phase discriminator develops an error voltage of suitable polarity and amplitude, indicative of the lead or lag between the data and clock signals. The error voltage is applied to the voltage controlled oscillator to modify the frequency and phase of the clock. Furthermore, first and second integrations are provided by the phase discriminator and an integrator respectively so that the steady state phase error is held close to zero. It is known that spurious variations in the mechanical or electrical parameters of a storage system cause unwanted displacement and shift of the signal being processed,
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thus necessitating frequency and phase compensation. To this end, synchronizing systems, servosystems, phase lock oscillator circuits, separation circuits and the like are employed. Q1. THE
FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT __________ GATE
16-INPUT
AND OR NAND XOR Q2. FLIP FLOPS ARE ALSO CALLED _____________
BI-STABLE DUALVIBRATORS BI-STABLE TRANSFORMER BI-STABLE MULTIVIBRATORS Bi-stable singlevibrators
Q3. ___________ IS ONE OF THE EXAMPLES OF SYNCHRONOUS INPUTS. J-K INPUT EN INPUT Preset input (PRE) CLEAR INPUT (CLR)
Q4. GIVEN THE STATE DIAGRAM OF AN UP/DOWN COUNTER, WE CAN FIND __________
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THE NEXT STATE OF A GIVEN PRESENT STATE THE PREVIOUS STATE OF A GIVEN PRESENT STATE BOTH THE NEXT AND PREVIOUS STATES OF A GIVEN STATE The state diagram shows only the inputs/outputs of a given states
Q5. AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS 1. W HAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES?
2 4 6 8
Q6. A 8-BIT SERIAL IN / PARALLEL OUT SHIFT REGISTER CONTAINS THE VALUE 8, _____ CLOCK SIGNAL(S) WILL BE REQUIRED TO SHIFT THE VALUE COMPLETELY OUT OF THE REGISTER. 1 2 4 8
Q.7 WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO _________
THE FLOP-FLOP IS TRIGGERED

Q=0 AND Q=1 Q=1 AND Q=0
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THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED
Q.8 THE ___RCO_____ OF FIRST 74HC163 COUNTER IS CONNECTED TO ___ ENT____ AND ___ENP_____ INPUTS OF OTHER 74HC COUNTER TO FORM A SINGLE CASCADED COUNTER.
Q9 How many stats does a module 4 counter have? 1 2 4 16 Q10 How will a serial in and out shift register accept data serially One bit at a time 8 bit Only after a load plus Only after being clear Q11 Te invalid stat of SR latch occur when S=1, R=0 S=0, R=1 S=1,R=1 S=0,R=0 Q12 To serially shift a byte of data in to a shift register there must be 1 clock plus One load plus 8 clock plus One clock plus for each in the data Q13
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What is the decimal value of the terminal count of 4 bit binary count 10 12 15 16
AllaH HaFiZ
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