Altera DE0 Board

CONTENTS
Chapter 1 DE0 Package.....................................................................................................................1 1.1 1.2 Package Contents .................................................................................................................1 The DE0 Board Assembly....................................................................................................2 Getting Help.........................................................................................................................2

Chapter 2 Altera DE0 Board.............................................................................................................4 2.1 2.2 2.3 Layout and Components ......................................................................................................4 Block Diagram of the DE0 Board........................................................................................5 Power-up the DE0 Board .....................................................................................................8

Chapter 3 DE0 Control Panel .........................................................................................................10 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Control Panel Setup ...........................................................................................................10 Controlling the LEDs and 7-Segment Displays.................................................................12 Switches and Buttons .........................................................................................................14 SDRAM and Flash Controller and Programmer................................................................15 PS2 Device.........................................................................................................................16 SD CARD ..........................................................................................................................17 VGA ...................................................................................................................................18

Chapter 4 Using the DE0 Board .....................................................................................................20 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 Configuring the Cyclone III FPGA....................................................................................20 Using the LEDs and Switches............................................................................................23 Using the 7-segment Displays............................................................................................26 Clock Circuitry...................................................................................................................28 Using the LCD Module......................................................................................................29 Using the Expansion Header..............................................................................................31 Using VGA ........................................................................................................................34 RS-232 Serial Port .............................................................................................................37 PS/2 Serial Port ..................................................................................................................38 SD Card Socket..................................................................................................................39 Using SDRAM and Flash ..................................................................................................39

Chapter 5 Examples of Advanced Demonstrations ......................................................................44 5.1 5.2 5.3 DE0 Factory Configuration................................................................................................44 SD Card..............................................................................................................................45 VGA Color Pattern Demonstration....................................................................................49

Chapter 6 Appendix .........................................................................................................................53 6.1 Revision History ................................................................................................................53

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The DE0 package includes: The DE0 board USB Cable for FPGA programming and control DE0 System CD containing : o Alteras Quartus II Web Edition and the Nios II Embedded Design Suit Evaluation Edition software o the DE0 documentation and supporting materials, including the User Manual, the Control Panel utility, reference designs and demonstrations, device datasheets, tutorials, and a set of laboratory exercises Clear plastic cover for the board 7.5 DC wall-mount power supply

1.2 The DE0 Board Assembly

To assemble the included stands for the DE0 board: Assemble a rubber (silicon) cover, as shown in Figure 1-2, for each of the four copper stands on the DE0 board The clear plastic cover provides extra protection, and is mounted over the top of the board by using additional stands and screws

Figure 1-2 The feet for the DE0 board.

Getting Help Here are the addresses where you can get help if you encounter problems: Altera Corporation 101 Innovation Drive
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San Jose, California, 95134 USA Email: university@altera.com Terasic Technologies No. 356, Sec. 1, Fusing E. Rd. Jhubei City, HsinChu County, Taiwan, 302 Email: support@terasic.com Web: DE0.terasic.com

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Altera Cyclone III 3C16 FPGA device Altera Serial Configuration device EPCS4 USB Blaster (on board) for programming and user API control; both JTAG and Active Serial (AS) programming modes are supported 8-Mbyte SDRAM 4-Mbyte Flash memory SD Card socket 3 pushbutton switches 10 toggle switches 10 green user LEDs 50-MHz oscillator for clock sources VGA DAC (4-bit resistor network) with VGA-out connector RS-232 transceiver PS/2 mouse/keyboard connector Two 40-pin Expansion Headers

2.2 Block Diagram of the DE0 Board

Figure 2-2 gives the block diagram of the DE0 board. To provide maximum flexibility for the user, all connections are made through the Cyclone IIII FPGA device. Thus, the user can configure the FPGA to implement any system design.

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User LEDs (10)

SDRAM (8 Mbytes) 16X2 LCD Module Flash (4 Mbytes)

PushButton Switches (3)

Slide Switches (10) EP3C16F484 PS/2

SD Card Socket

Triple 4-bit VGA DAC

Expansion Headers (2)

7-Segment Display (4)

16X2 LCD Interface

RS-232 Transceiver

EPCS4 Config Device

USB Blaster

Figure 2-2 Block diagram of the DE0 board. Following is more detailed information about the blocks in Figure 2-2: Cyclone IIII 3C16 FPGA 15,408 LEs 56 M9K Embedded Memory Blocks 504K total RAM bits 56 embedded multipliers 4 PLLs 346 user I/O pins FineLine BGA 484-pin package Built-in USB Blaster circuit On-board USB Blaster for programming and user API (Application programming interface) control Using the Altera EPM240 CPLD SDRAM One 8-Mbyte Single Data Rate Synchronous Dynamic RAM memory chip Supports 16-bits data bus
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Flash memory 4-Mbyte NOR Flash memory Support Byte (8-bits)/Word (16-bits) mode SD card socket Provides both SPI and SD 1-bit mod SD Card access Pushbutton switches 3 pushbutton switches Normally high; generates one active-low pulse when the switch is pressed Slide switches 10 Slide switches A switch causes logic 0 when in the DOWN position and logic 1 when in the UP position General User Interfaces 10 Green color LEDs (Active high) 4 seven-segment displays (Active low) 16x2 LCD Interface (Not include LCD module) Clock inputs 50-MHz oscillator VGA output Uses a 4-bit resistor-network DAC With 15-pin high-density D-sub connector Supports up to 1280x1024 at 60-Hz refresh rate Serial ports One RS-232 port (Without DB-9 serial connector) One PS/2 port (Can be used through a PS/2 Y Cable to allow you to connect a keyboard and mouse to one port) Two 40-pin expansion headers 72 Cyclone III I/O pins, as well as 8 power and ground lines, are brought out to two 40-pin expansion connectors 40-pin header is designed to accept a standard 40-pin ribbon cable used for IDE hard drives
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2.3 Power-up the DE0 Board

The DE0 board comes with a preloaded configuration bit stream to demonstrate some features of the board. This bit stream also allows users to see quickly if the board is working properly. To power-up the board perform the following steps: 1. Connect the provided USB cable from the host computer to the USB Blaster connector on the DE0 board. For communication between the host and the DE0 board, it is necessary to install the Altera USB Blaster driver software. If this driver is not already installed on the host computer, it can be installed as explained in the tutorial Getting Started with Altera's DE0 Board. This tutorial is available in the directory DE0\DE0_user_manual on the DE0 System CD-ROM. Connect the 7.5V adapter to the DE0 board Connect a VGA monitor to the VGA port on the DE0 board Turn the RUN/PROG switch on the left edge of the DE0 board to RUN position; the PROG position is used only for the AS Mode programming Turn the power on by pressing the ON/OFF switch on the DE0 board

2. 3. 4. 5.

At this point you should observe the following: All user LEDs are flashing All 7-segment displays are cycling through the numbers 0 to F The VGA monitor displays the image shown in Figure 2-3.

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Figure 2-3 The default VGA output pattern.

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Chapter 3

DE0 Control Panel

The DE0 board comes with a Control Panel facility that allows users to access various components on the board from a host computer. The host computer communicates with the board through an USB connection. The facility can be used to verify the functionality of components on the board or be used as a debug tool while developing RTL code. This chapter first presents some basic functions of the Control Panel, then describes its structure in block diagram form, and finally describes its capabilities.

3.1 Control Panel Setup

The Control Panel Software Utility is located in the DE0_Control_panel folder in the DE0 System CD-ROM. To install it, just copy the whole folder to your host computer. To activate the Control Panel, perform the following steps: 1. Make sure Quartus II and USB-Blaster Driver are installed successfully on your PC. 2. Connect the supplied USB cable to the USB Blaster port, connect the 7.5V power supply, and turn the power switch ON 3. Set the RUN/PROG switch to the RUN position 4. Start the executable DE0_ControlPanel.exe on the host computer. The Control Panel user interface shown in Figure 3-1will appear. When the control panel window appears, it will automatically download the bit stream file .sof into the FPGA. If any error message shows up as shown in Figure 3-2, please check steps 1 to 3 has been performed. Then, click Download Code button to program FPGA again. Note, the Control Panel will occupy the USB port until you close that port; you cannot use Quartus II to download a configuration file into the FPGA until you close the USB port. 5. The Control Panel is now ready to be use; experiment by setting the value of the LEDs display and observe the result on the DE0 board.

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The Control Panel also supports loading files with a .hex extension. Files with a .hex extension are ASCII text files that specify memory values using ASCII characters to represent hexadecimal values. For example, a file containing the line 0123456789ABCDEF defines four 8-bit values: 01, 23, 45, 67, 89, AB, CD, EF. These values will be loaded consecutively into the memory. The Sequential Read function is used to read the contents of the SDRAM and place them into a file as follows: 1. Specify the starting address in the Address box. 2. Specify the number of bytes to be copied into the file in the Length box. If the entire contents of the SDRAM are to be copied (which involves all 8 Mbytes), then place a checkmark in the Entire Memory box. 3. Press Load Memory Content to a File button. 4. When the Control Panel responds with the standard Windows dialog box asking for the destination file, specify the desired file in the usual manner. Users can use the similar way to access the Flash. Please note that users need to erase the flash before writing data to it.

3.5 PS2 Device

The Control Panel provides users a tool to receive the inputs from a PS2 keyboard in real time. The received scan-codes are translated to ASCII code and displayed in the control window. Only visible ASCII codes are displayed. For control key, only Carriage Return/ENTER key is implemented. This function can be used to verify the functionality of the PS2 Interface. Please follow the steps below to exercise the PS2 device: 1. Choosing the PS2 tab leads to the window in Figure 3-8. 2. Plug a PS2 Keyboard to the FPGA board. Then, 3. Press the Start button to start PS2Keyboard input receiving process; Button caption is changed from Start to Stop. 4. In the receiving process, users can start to press the attached keyboard. The input data will be displayed in the control window in real time. Press Stop to terminate the monitoring process.

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Chapter 4

Using the DE0 Board

This chapter gives instructions for using the DE0 board and describes each of its I/O devices.

4.1 Configuring the Cyclone III FPGA

The procedure for downloading a circuit from a host computer to the DE0 board is described in the tutorial Getting Started with Altera's DE0 Board. This tutorial is found in the user_manaul folder on the DE0 System CD-ROM. The user is encouraged to read the tutorial first, and to treat the information below as a short reference. The DE0 board contains a serial EEPROM chip that stores configuration data for the Cyclone III FPGA. This configuration data is automatically loaded from the EEPROM chip into the FPGA each time power is applied to the board. Using the Quartus II software, it is possible to reprogram the FPGA at any time, and it is also possible to change the non-volatile data that is stored in the serial EEPROM chip. Both types of programming methods are described below. 1. JTAG programming: In this method of programming, named after the IEEE standards Joint Test Action Group, the configuration bit stream is downloaded directly into the Cyclone III FPGA. The FPGA will retain this configuration as long as power is applied to the board; the configuration is lost when the power is turned off. 2. AS programming: In this method, called Active Serial programming, the configuration bit stream is downloaded into the Altera EPCS4 serial EEPROM chip. It provides non-volatile storage of the bit stream, so that the information is retained even when the power supply to the DE0 board is turned off. When the board's power is turned on, the configuration data in the EPCS4 device is automatically loaded into the Cyclone III FPGA. The sections below describe the steps used to perform both JTAG and AS programming. For both methods the DE0 board is connected to a host computer via a USB cable. Using this connection, the board will be identified by the host computer as an Altera USB Blaster device. The process for installing on the host computer the necessary software device driver that communicates with the USB Blaster is described in the tutorial Getting Started with Altera's DE0 Board. This tutorial is available on the DE0 System CD-ROM.

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In addition to its use for JTAG and AS programming, the USB Blaster port on the DE0 board can also be used to control some of the board's features remotely from a host computer. Details that describe this method of using the USB Blaster port are given in Chapter 3.

4.2 Using the LEDs and Switches

The DE0 board provides three pushbutton switches. The three outputs called BUTTON0, BUTTON 1, and BUTTON2 are connected directly to the Cyclone III FPGA. Each switch provides a high logic level (3.3 volts) when it is not pressed, and provides a low logic level (0 volts) when depressed. There are also 10 slide switches (sliders) on the DE0 board. These switches are not debounced, and are intended for use as level-sensitive data inputs to a circuit. Each switch is connected directly to a pin on the Cyclone III FPGA. When a switch is in the DOWN position (closest to the edge of the board) it provides a low logic level (0 volts) to the FPGA, and when the switch is in the UP position it provides a high logic level (3.3 volts). There are 10 user-controllable LEDs on the DE0 board. Each LED is driven directly by a pin on the Cyclone III FPGA; driving its associated pin to a high logic level turns the LED on, and driving the pin low turns it off. Figure 4-5 and Figure 4-7show the connections between the push buttons, slide switches, and Cyclone III FPGA As indicated in Figure 4-6, each of these switches is debounced using a Schmitt Trigger circuit. The three outputs called BUTTON0, BUTTON1, and BUTTON2 of the Schmitt Trigger devices are connected directly to the Cyclone III FPGA (only PCB 10-0100730-A0 version contains the debounced circuit). A list of the pin names on the Cyclone III FPGA that are connected to the toggle switches is given in Table 4.1. Similarly, the pins used to connect to the pushbutton switches and LEDs are displayed in Table 4.2 and Table 4.3, respectively.

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Figure 4-5. Connections between the pushbutton and Cyclone III FPGA
Pushbutton depressed Before Debouncing Pushbutton released

Schmitt Trigger Debounced

Figure 4-6 Switch debouncing

D2

E4

E3

H7

J7

G5

G4

H6

H5

J6

Logic ``1``

SW9

SW8 SW7

SW6 SW5 SW4

SW3 SW2 SW1 SW0

Logic``0``

Figure 4-7 Connections between the toggle switches and Cyclone III FPGA

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J1 J2 J3 H1 F2 E1 C1 C2 B2 B1

LEDG0 LEDG1 LEDG2 LEDG3 LEDG4 LEDG5 LEDG6 LEDG7 LEDG8 LEDG9

LEDG0

LEDG1

LEDG2

LEDG3

LEDG4

LEDG5

LEDG6

LEDG7

LEDG8

LEDG9

Figure 4-8 Connections between the LEDs and Cyclone III FPGA Table 4.1. Pin assignments for the slide switches
Signal Name SW[0] SW[1] SW[2] SW[3] SW[4] SW[5] SW[6] SW[7] SW[8] SW[9] FPGA Pin No. PIN_J6 PIN_H5 PIN_H6 PIN_G4 PIN_G5 PIN_J7 PIN_H7 PIN_E3 PIN_E4 PIN_D2 Description Slide Switch[0] Slide Switch[1] Slide Switch[2] Slide Switch[3] Slide Switch[4] Slide Switch[5] Slide Switch[6] Slide Switch[7] Slide Switch[8] Slide Switch[9]

Table 4.2. Pin assignments for the pushbutton switches

Signal Name BUTTON [0] BUTTON [1] BUTTON [2] FPGA Pin No. PIN_ H2 PIN_ G3 PIN_ F1 Description Pushbutton[0] Pushbutton[1] Pushbutton[2]

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Table 4.3. Pin assignments for the LEDs

Signal Name LEDG[0] LEDG[1] LEDG[2] LEDG[3] LEDG[4] LEDG[5] LEDG[6] LEDG[7] LEDG[8] LEDG[9] FPGA Pin No. PIN_J1 PIN_J2 PIN_J3 PIN_H1 PIN_F2 PIN_E1 PIN_C1 PIN_C2 PIN_B2 PIN_B1 Description LED Green[0] LED Green[1] LED Green[2] LED Green[3] LED Green[4] LED Green[5] LED Green[6] LED Green[7] LED Green[8] LED Green[9]

4.3 Using the 7-segment Displays

The DE0 board has four 7-segment displays. These displays are arranged into two pairs and a group of four, with the intent of displaying numbers of various sizes. As indicated in Figure 4-9, the seven segments are connected to pins on the Cyclone III FPGA. Applying a low logic level to a segment causes it to light up, and applying a high logic level turns it off. Each segment in a display is identified by an index from 0 to 6, with the positions given in Figure 4-10. In addition, the decimal point is identified as DP. Table 4.4 shows the connections between the FPGA pins to the 7-segment displays.

HEX0
HEX0_D0 HEX0_D0 HEX0_D1 HEX0_D2 HEX0_D3 E11 F11 H12 H13

HEX0_D5 HEX0_D6

HEX0_D1

HEX0_D4

HEX0_D2

HEX0_D3

HEX0_DP

HEX0_D4 HEX0_D5 HEX0_D6 HEX0_DP

G12 F12 F13 D13

Figure 4-9 Connections between the 7-segment displays and Cyclone III FPGA

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0 5 6 4 3 1

2 DP

Figure 4-10 Position and index of each segment in a 7-segment display

Table 4.4. Pin assignments for the 7-segment displays.

Signal Name HEX0_D[0] HEX0_D[1] HEX0_D[2] HEX0_D[3] HEX0_D[4] HEX0_D[5] HEX0_D[6] HEX0_DP HEX1_D[0] HEX1_D[1] HEX1_D[2] HEX1_D[3] HEX1_D[4] HEX1_D[5] HEX1_D[6] HEX1_DP HEX2_D[0] HEX2_D[1] HEX2_D[2] HEX2_D[3] HEX2_D[4] HEX2_D[5] HEX2_D[6] HEX2_DP FPGA Pin No. PIN_E11 PIN_F11 PIN_H12 PIN_H13 PIN_G12 PIN_F12 PIN_F13 PIN_D13 PIN_A13 PIN_B13 PIN_C13 PIN_A14 PIN_B14 PIN_E14 PIN_A15 PIN_B15 PIN_D15 PIN_A16 PIN_B16 PIN_E15 PIN_A17 PIN_B17 PIN_F14 PIN_A18 Description Seven Segment Digit 0[0] Seven Segment Digit 0[1] Seven Segment Digit 0[2] Seven Segment Digit 0[3] Seven Segment Digit 0[4] Seven Segment Digit 0[5] Seven Segment Digit 0[6] Seven Segment Decimal Point 0 Seven Segment Digit 1[0] Seven Segment Digit 1[1] Seven Segment Digit 1[2] Seven Segment Digit 1[3] Seven Segment Digit 1[4] Seven Segment Digit 1[5] Seven Segment Digit 1[6] Seven Segment Decimal Point 1 Seven Segment Digit 2[0] Seven Segment Digit 2[1] Seven Segment Digit 2[2] Seven Segment Digit 2[3] Seven Segment Digit 2[4] Seven Segment Digit 2[5] Seven Segment Digit 2[6] Seven Segment Decimal Point 2

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HEX3_D[0] HEX3_D[1] HEX3_D[2] HEX3_D[3] HEX3_D[4] HEX3_D[5] HEX3_D[6] HEX3_DP

PIN_B18 PIN_F15 PIN_A19 PIN_B19 PIN_C19 PIN_D19 PIN_G15 PIN_G16

Seven Segment Digit 3[0] Seven Segment Digit 3[1] Seven Segment Digit 3[2] Seven Segment Digit 3[3] Seven Segment Digit 3[4] Seven Segment Digit 3[5] Seven Segment Digit 3[6] Seven Segment Decimal Point 3

4.4 Clock Circuitry

The DE0 board includes a 50 MHz clock signals. This clock signal is connected to the FPGA that are used for clocking the user logic. In addition, all these clock inputs are connected to the phase lock loops (PLL) clock input pin of the FPGA allowed users can use these clocks as a source clock for the PLL circuit. The clock distribution on the DE0 board is shown in Figure 4-11. The associated pin assignments for clock inputs to FPGA I/O pins are listed in Table 4.5.

Figure 4-11 Block diagram of the clock distribution.

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Table 4.5. Pin assignments for the clock inputs.

Signal Name CLOCK_50 CLOCK_50_2 FPGA Pin No. PIN_G21 PIN_B12 Description 50 MHz clock input 50 MHz clock input

4.5 Using the LCD Module

The DE0 board provides a 2x16 LCD interface. In order to use the LCD interface, users are required to solder a LCD module onto the DE0 board shown in Figure 4-12. The detailed component reference is listed in Table 4.6. Also, users can buy this module from Terasic website (http://de0.terasic.com). Table 4.6. The listed information on the LCD module
Board Description Reference J2 2x16 LCD Module

The LCD module has built-in fonts and can be used to display text by sending appropriate commands to the display controller, which is called HD44780. Detailed information for using the display is available in its datasheet, which can be found on the manufacturer's web site, and from the Datasheet/LCD folder on the DE0 System CD-ROM. A schematic diagram of the LCD module showing connections to the Cyclone III FPGA is given in Figure 4-13. The associated pin assignments appear in Table 4.7.

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Table 4.7. Pin assignments for the LCD module

Signal Name LCD_DATA[0] LCD_DATA[1] LCD_DATA[2] LCD_DATA[3] LCD_DATA[4] LCD_DATA[5] LCD_DATA[6] LCD_DATA[7] LCD_RW LCD_EN LCD_RS LCD_BLON FPGA Pin No. PIN_D22 PIN_D21 PIN_C22 PIN_C21 PIN_B22 PIN_B21 PIN_D20 PIN_C20 PIN_E22 PIN_E21 PIN_F22 PIN_F21 Description LCD Data[0] LCD Data[1] LCD Data[2] LCD Data[3] LCD Data[4] LCD Data[5] LCD Data[6] LCD Data[7] LCD Read/Write Select, 0 = Write, 1 = Read LCD Enable LCD Command/Data Select, 0 = Command, 1 = Data LCD Back Light ON/OFF

Note that some LCD modules do not have backlight. Therefore the LCD_BLON signal should not be used in users design projects.

4.6 Using the Expansion Header

The DE0 Board provides two 40-pin expansion headers. Each header connects directly to 36 pins of the Cyclone III FPGA, and also provides DC +5V (VCC5), DC +3.3V (VCC33), and two GND pins. Among these 36 I/O pins, 4 pins are connected to the PLL clock input and output pins of the FPGA allowing the expansion daughter cards to access the PLL blocks in the FPGA. Finally, Figure 4-14 shows the related schematics. The figure shows the protection circuitry for only two of the pins on each header, but this circuitry is included for all 72 data pins. Table 4.8 gives the pin assignments.

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(GPIO 0) J4
[AB12] GPIO0_CLKIN0 [AA12] GPIO0_CLKIN1 [AA15] GPIO0_D2 [AA14] GPIO0_D4 [AB13] GPIO0_D6 5V [AB10] GPIO0_D8 [AB8] GPIO0_D10 [AB5] GPIO0_D12 [AB3] GPIO0_CLKOUT0 [AA3] GPIO0_CLKOUT1 [V14] GPIO0_D16 [Y13] GPIO0_D18 [U13] GPIO0_D20 3.3V [R10] GPIO0_D22 [Y10] GPIO0_D24 [T8] GPIO0_D26 [W7] GPIO0_D28 [V5] GPIO0_D30 1 3 5 7 9 2 4 6 8 10 GPIO0_D0 [AB16] GPIO0_D1 [AA16] GPIO0_D3 [AB15] GPIO0_D5 [AB14] GPIO0_D7 [AA13] GND GPIO0_D9 [AA10] GPIO0_D11 [AA8] GPIO0_D13 [AA5] GPIO0_D14 [AB4] GPIO0_D15 [AA4] GPIO0_D17 [U14] GPIO0_D19 [W13] GPIO0_D21 [V12] GND GPIO0_D23 [V11] GPIO0_D25 [W10] GPIO0_D27 [V8] GPIO0_D29 [W6] GPIO0_D31 [U7] [AB11] GPIO1_CLKIN0 [AA11] GPIO1_CLKIN1 [AA19] GPIO1_D2 [AB18] GPIO1_D4 [AA17] GPIO1_D6 5V [Y17] GPIO1_D8 [U15] GPIO1_D10 [W15] GPIO1_D12 [R16] GPIO1_CLKOUT0 [T16] GPIO1_CLKOUT1 [AA7] GPIO1_D16 [T14] GPIO1_D18 [U12] GPIO1_D20 3.3V [R11] GPIO1_D22 [U10] GPIO1_D24 [U9] GPIO1_D26 [Y7] GPIO1_D28 [V6] GPIO1_D30

(GPIO 1) J5
1 3 5 7 9 2 4 6 8 10 GPIO1_D0 [AA20] GPIO1_D1 [AB20] GPIO1_D3 [AB19] GPIO1_D5 [AA18] GPIO1_D7 [AB17] GND GPIO1_D9 [W17] GPIO1_D11 [T15] GPIO1_D13 [V15] GPIO1_D14 [AB9] GPIO1_D15 [AA9] GPIO1_D17 [AB7] GPIO1_D19 [R14] GPIO1_D21 [T12] GND GPIO1_D23 [R12] GPIO1_D25 [T10] GPIO1_D27 [T9] GPIO1_D29 [U8] GPIO1_D31 [V7]

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40

Figure 4-14 I/O distribution of the expansion headers Table 4.8. Pin assignments for the expansion headers.
Signal Name GPIO0_D[0] GPIO0_D[1] GPIO0_D[2] GPIO0_D[3] GPIO0_D[4] GPIO0_D[5] GPIO0_D[6] GPIO0_D[7] GPIO0_D[8] GPIO0_D[9] GPIO0_D[10] GPIO0_D[11] GPIO0_D[12] GPIO0_D[13] GPIO0_D[14] GPIO0_D[15] FPGA Pin No. PIN_AB16 PIN_AA16 PIN_AA15 PIN_AB15 PIN_AA14 PIN_AB14 PIN_AB13 PIN_AA13 PIN_AB10 PIN_AA10 PIN_AB8 PIN_AA8 PIN_AB5 PIN_AA5 PIN_AB4 PIN_AA4 Description GPIO Connection 0 IO[0] GPIO Connection 0 IO[1] GPIO Connection 0 IO[2] GPIO Connection 0 IO[3] GPIO Connection 0 IO[4] GPIO Connection 0 IO[5] GPIO Connection 0 IO[6] GPIO Connection 0 IO[7] GPIO Connection 0 IO[8] GPIO Connection 0 IO[9] GPIO Connection 0 IO[10] GPIO Connection 0 IO[11] GPIO Connection 0 IO[12] GPIO Connection 0 IO[13] GPIO Connection 0 IO[14] GPIO Connection 0 IO[15]

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GPIO0_D[16] GPIO0_D[17] GPIO0_D[18] GPIO0_D[19] GPIO0_D[20] GPIO0_D[21] GPIO0_D[22] GPIO0_D[23] GPIO0_D[24] GPIO0_D[25] GPIO0_D[26] GPIO0_D[27] GPIO0_D[28] GPIO0_D[29] GPIO0_D[30] GPIO0_D[31] GPIO0_CLKIN[0] GPIO0_CLKIN[1] GPIO0_CLKOUT[0] GPIO0_CLKOUT[1] GPIO1_D[0] GPIO1_D[1] GPIO1_D[2] GPIO1_D[3] GPIO1_D[4] GPIO1_D[5] GPIO1_D[6] GPIO1_D[7] GPIO1_D[8] GPIO1_D[9] GPIO1_D[10] GPIO1_D[11] GPIO1_D[12] GPIO1_D[13] GPIO1_D[14] GPIO1_D[15] GPIO1_D[16]

PIN_V14 PIN_U14 PIN_Y13 PIN_W13 PIN_U13 PIN_V12 PIN_R10 PIN_V11 PIN_Y10 PIN_W10 PIN_T8 PIN_V8 PIN_W7 PIN_W6 PIN_V5 PIN_U7 PIN_AB12 PIN_AA12 PIN_AB3 PIN_AA3 PIN_AA20 PIN_AB20 PIN_AA19 PIN_AB19 PIN_AB18 PIN_AA18 PIN_AA17 PIN_AB17 PIN_Y17 PIN_W17 PIN_U15 PIN_T15 PIN_W15 PIN_V15 PIN_AB9 PIN_AA9 PIN_AA7

GPIO Connection 0 IO[16] GPIO Connection 0 IO[17] GPIO Connection 0 IO[18] GPIO Connection 0 IO[19] GPIO Connection 0 IO[20] GPIO Connection 0 IO[21] GPIO Connection 0 IO[22] GPIO Connection 0 IO[23] GPIO Connection 0 IO[24] GPIO Connection 0 IO[25] GPIO Connection 0 IO[26] GPIO Connection 0 IO[27] GPIO Connection 0 IO[28] GPIO Connection 0 IO[29] GPIO Connection 0 IO[30] GPIO Connection 0 IO[31] GPIO Connection 0 PLL In GPIO Connection 0 PLL In GPIO Connection 0 PLL Out GPIO Connection 0 PLL Out GPIO Connection 1 IO[0] GPIO Connection 1 IO[1] GPIO Connection 1 IO[2] GPIO Connection 1 IO[3] GPIO Connection 1 IO[4] GPIO Connection 1 IO[5] GPIO Connection 1 IO[6] GPIO Connection 1 IO[7] GPIO Connection 1 IO[8] GPIO Connection 1 IO[9] GPIO Connection 1 IO[10] GPIO Connection 1 IO[11] GPIO Connection 1 IO[12] GPIO Connection 1 IO[13] GPIO Connection 1 IO[14] GPIO Connection 1 IO[15] GPIO Connection 1 IO[16]

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GPIO1_D[17] GPIO1_D[18] GPIO1_D[19] GPIO1_D[20] GPIO1_D[21] GPIO1_D[22] GPIO1_D[23] GPIO1_D[24] GPIO1_D[25] GPIO1_D[26] GPIO1_D[27] GPIO1_D[28] GPIO1_D[29] GPIO1_D[30] GPIO1_D[31] GPIO1_CLKIN[0] GPIO1_CLKIN[1] GPIO1_CLKOUT[0] GPIO1_CLKOUT[1]

PIN_AB7 PIN_T14 PIN_R14 PIN_U12 PIN_T12 PIN_R11 PIN_R12 PIN_U10 PIN_T10 PIN_U9 PIN_T9 PIN_Y7 PIN_U8 PIN_V6 PIN_V7 PIN_AB11 PIN_AA11 PIN_R16 PIN_T16

GPIO Connection 1 IO[17] GPIO Connection 1 IO[18] GPIO Connection 1 IO[19] GPIO Connection 1 IO[20] GPIO Connection 1 IO[21] GPIO Connection 1 IO[22] GPIO Connection 1 IO[23] GPIO Connection 1 IO[24] GPIO Connection 1 IO[25] GPIO Connection 1 IO[26] GPIO Connection 1 IO[27] GPIO Connection 1 IO[28] GPIO Connection 1 IO[29] GPIO Connection 1 IO[30] GPIO Connection 1 IO[31] GPIO Connection 1 PLL In GPIO Connection 1 PLL In GPIO Connection 1 PLL Out GPIO Connection 1 PLL Out

4.7 Using VGA

The DE0 board includes a 16-pin D-SUB connector for VGA output. The VGA synchronization signals are provided directly from the Cyclone III FPGA, and a 4-bit DAC using resistor network is used to produce the analog data signals (red, green, and blue). The associated schematic is given in Figure 4-15 and can support standard VGA resolution (640x480 pixels, at 25 MHz).

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H19 H17 H20 H21

VGA_R0 VGA_R1 VGA_R2 VGA_R3

6 1 11

VGA_R

H22 J17 K17 J21

VGA_G0 VGA_G1 VGA_G2 VGA_G3

VGA_G VGA_B

VGA_B0 K22 K21 J22 K18 VGA_B1 VGA_B2 VGA_B3

10 5 15

L22 L21

VGA_VS VGA_HS

Figure 4-15 Connections between VGA circuit and Cyclone III FPGA The timing specification for VGA synchronization and RGB (red, green, blue) data can be found on various educational web sites (for example, search for VGA signal timing). Figure 4-16 illustrates the basic timing requirements for each row (horizontal) that is displayed on a VGA monitor. An active-low pulse of specific duration (time a in the figure) is applied to the horizontal synchronization (hsync) input of the monitor, which signifies the end of one row of data and the start of the next. The data (RGB) inputs on the monitor must be off (driven to 0 V) for a time period called the back porch (b) after the hsync pulse occurs, which is followed by the display interval (c). During the data display interval the RGB data drives each pixel in turn across the row being displayed. Finally, there is a time period called the front porch (d) where the RGB signals must again be off before the next hsync pulse can occur. The timing of the vertical synchronization (vsync) is the same as shown in Figure 4-16, except that a vsync pulse signifies the end of one frame and the start of the next, and the data refers to the set of rows in the frame (horizontal timing). Table 4.9 and Table 4.10 show different resolutions of the durations of time periods a, b, c, and d for both horizontal and vertical timing. Detailed information for using the ADV7123 video DAC is available in its datasheet, which can be found on the manufacturer's web site, or in the Datasheet/VGA DAC folder on the DE0 System CD-ROM. The pin assignments between the Cyclone III FPGA and the VGA connector are listed in Table 4.11. An example of code that drives a VGA display is described in Sections 5.3.
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Figure 4-16 VGA horizontal timing specification Table 4.9. VGA horizontal timing specification
VGA mode Configuration VGA(60Hz) Resolution(HxV) 640x480 a(us) 3.8 Horizontal Timing Spec b(us) 1.9 c(us) 25.4 d(us) 0.6 Pixel clock(Mhz) 25 (640/c)

Table 4.10. VGA vertical timing specification

VGA mode Configuration VGA(60Hz) Resolution (HxV) a(lines) 2 Vertical Timing Spec b(lines) 33 c(lines) 480 d(lines) 10

640x480

Table 4.11. VGA pin assignments

Signal Name VGA_R[0] VGA_R[1] VGA_R[2] VGA_R[3] VGA_G[0] VGA_G[1] VGA_G[2] VGA_G[3] VGA_B[0] VGA_B[1] VGA_B[2] VGA_B[3] VGA_HS VGA_VS FPGA Pin No. PIN_H19 PIN_H17 PIN_H20 PIN_H21 PIN_H22 PIN_J17 PIN_K17 PIN_J21 PIN_K22 PIN_K21 PIN_J22 PIN_K18 PIN_L21 PIN_L22 Description VGA Red[0] VGA Red[1] VGA Red[2] VGA Red[3] VGA Green[0] VGA Green[1] VGA Green[2] VGA Green[3] VGA Blue[0] VGA Blue[1] VGA Blue[2] VGA Blue[3] VGA H_SYNC VGA V_SYNC

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Table 4.12. RS-232 pin assignments

Signal Name UART_RXD UART_TXD UART_CTS UART_RTS FPGA Pin No. PIN_U22 PIN_U21 PIN_V21 PIN_V22 Description UART Receiver UART Transmitter UART Clear to Send UART Request to Send

4.9 PS/2 Serial Port

The DE0 board includes a standard PS/2 interface and a connector for a PS/2 keyboard or mouse. In addition, users can use the PS/2 keyboard and mouse on the DE0 board simultaneously by plugging an extension PS/2 Y-Cable. Note that both the PS_MSDAT and PS_MSCLK signals can be used only when the PS/2 Y-cable is connected to the PS/2 connector. Figure 4-19 shows the connections between the PS/2 circuit and FPGA. Instructions for using a PS/2 mouse or keyboard can be found by performing an appropriate search on various educational web sites. The pin assignments for the associated interface are shown in Table 4.13.
P22 R21 PS2_KBCLK PS2_MSCLK

J3

8 5 2 1

6 3

R22 P21

PS2_MSDAT PS2_KBDAT

Figure 4-19 Connections between PS/2 and Cyclone III FPGA Table 4.13. PS/2 pin assignments
Signal Name PS2_KBCLK PS2_KBDAT PS2_MSCLK PS2_MSDAT FPGA Pin No. PIN_P22 PIN_P21 PIN_R21 PIN_R22 Description PS/2 Clock PS/2 Data PS/2 Clock (reserved for second PS/2 device) PS/2 Data(reserved for second PS/2 device)

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4.10 SD Card Socket

The DE0 board has a SD card socket and can be accessed as optional external memory in both SPI and 1-bit SD mode. Table 4.14 shows the pin assignments for the SD card socket with the Cyclone III FPGA.
3.3V

9 W21 Y22 SD_DATA3 SD_CMD 1 2 3

3.3V

DATA2 DATA3 CMD VSS VCC CLK VSS DATA0 DATA1 WP

4 5 6 7 8

Y21

SD_CLK

AA22

SD_DATA0

W20

SD_WPn

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Figure 4-20 Connections between SD Card and Cyclone III FPGA Table 4.14. SD Card pin assignments
Signal Name SD_CLK SD_CMD SD_DAT0 SD_DAT3 SD_WP_N FPGA Pin No. PIN_Y21 PIN_Y22 PIN_AA22 PIN_W21 PIN_W20 Description SD Clock SD Command bidirectional signal SD Data bidirectional signal SD Data bidirectional signal SD Card write protect signal (active low)

4.11 Using SDRAM and Flash

The DE0 board provides a 4-Mbyte Flash memory, and 8-Mbyte SDRAM chips. Figure 4-21 and Figure 4-22 show the connections between the memory chips and Cyclone III FPGA. The pin assignments for each device are listed in Tables 4.15 and 4.16. The datasheets for the memory chips are provided in the Datasheet/Memory folder on the DE0 System CD-ROM.

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SDRAM
See Table 4.15 See Table 4.15 B5 A4 E7 B8 D6 G8 F7 G7 E5 E6 DRAM_ADDR[12:0] DRAM_DQ[15:0] DRAM_BA_0 DRAM_BA_1 DRAM_LDQM DRAM_UDQM DRAM_WE_N DRAM_CAS_N DRAM_RAS_N DRAM_CS_N DRAM_CLK DRAM_CKE A[12:0] D[15:0] BA0 BA1 LDQM UDQM nWE nCAS nRAS nCS CLK CKE

U1

Figure 4-21 Connections between SDRAM and Cyclone III FPGA

FLASH
See Table 4.16 See Table 4.16 Y2 P4 R1 T3 M7 G8 R6 AA1 FL_ADDR[12:0] FL_DQ[15:0] FL_DQ15_AM1 FL_WE_N FL_RST_N FL_WP_N FL_RY FL_CE_N FL_OE_N FL_BYTE_N A[21:0] DQ[14:0] DQ15/A-1 WE# RESET# WP#ACC RY/BY# CE# OE# BYTE#

U2

Figure 4-22 Connections between Flash and Cyclone III FPGA

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Table 4.15. SDRAM pin assignments

Signal Name DRAM_ADDR[0] DRAM_ADDR[1] DRAM_ADDR[2] DRAM_ADDR[3] DRAM_ADDR[4] DRAM_ADDR[5] DRAM_ADDR[6] DRAM_ADDR[7] DRAM_ADDR[8] DRAM_ADDR[9] DRAM_ADDR[10] DRAM_ADDR[11] DRAM_ADDR[12] DRAM_DQ[0] DRAM_DQ[1] DRAM_DQ[2] DRAM_DQ[3] DRAM_DQ[4] DRAM_DQ[5] DRAM_DQ[6] DRAM_DQ[7] DRAM_DQ[8] DRAM_DQ[9] DRAM_DQ[10] DRAM_DQ[11] DRAM_DQ[12] DRAM_DQ[13] DRAM_DQ[14] DRAM_DQ[15] DRAM_BA_0 DRAM_BA_1 DRAM_LDQM DRAM_UDQM DRAM_RAS_N DRAM_CAS_N FPGA Pin No. PIN_C4 PIN_A3 PIN_B3 PIN_C3 PIN_A5 PIN_C6 PIN_B6 PIN_A6 PIN_C7 PIN_B7 PIN_B4 PIN_A7 PIN_C8 PIN_D10 PIN_G10 PIN_H10 PIN_E9 PIN_F9 PIN_G9 PIN_H9 PIN_F8 PIN_A8 PIN_B9 PIN_A9 PIN_C10 PIN_B10 PIN_A10 PIN_E10 PIN_F10 PIN_B5 PIN_A4 PIN_E7 PIN_B8 PIN_F7 PIN_G8 Description SDRAM Address[0] SDRAM Address[1] SDRAM Address[2] SDRAM Address[3] SDRAM Address[4] SDRAM Address[5] SDRAM Address[6] SDRAM Address[7] SDRAM Address[8] SDRAM Address[9] SDRAM Address[10] SDRAM Address[11] SDRAM Address[12] SDRAM Data[0] SDRAM Data[1] SDRAM Data[2] SDRAM Data[3] SDRAM Data[4] SDRAM Data[5] SDRAM Data[6] SDRAM Data[7] SDRAM Data[8] SDRAM Data[9] SDRAM Data[10] SDRAM Data[11] SDRAM Data[12] SDRAM Data[13] SDRAM Data[14] SDRAM Data[15] SDRAM Bank Address[0] SDRAM Bank Address[1] SDRAM Low-byte Data Mask SDRAM High-byte Data Mask SDRAM Row Address Strobe SDRAM Column Address Strobe

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DRAM_CKE DRAM_CLK DRAM_WE_N DRAM_CS_N

PIN_E6 PIN_E5 PIN_D6 PIN_G7

SDRAM Clock Enable SDRAM Clock SDRAM Write Enable SDRAM Chip Select

Table 4.16. Flash pin assignments

Signal Name FL_ADDR[0] FL_ADDR[1] FL_ADDR[2] FL_ADDR[3] FL_ADDR[4] FL_ADDR[5] FL_ADDR[6] FL_ADDR[7] FL_ADDR[8] FL_ADDR[9] FL_ADDR[10] FL_ADDR[11] FL_ADDR[12] FL_ADDR[13] FL_ADDR[14] FL_ADDR[15] FL_ADDR[16] FL_ADDR[17] FL_ADDR[18] FL_ADDR[19] FL_ADDR[20] FL_ADDR[21] FL_DQ[0] FL_DQ[1] FL_DQ[2] FL_DQ[3] FL_DQ[4] FL_DQ[5] FL_DQ[6] FPGA Pin No. PIN_P7 PIN_P5 PIN_P6 PIN_N7 PIN_N5 PIN_N6 PIN_M8 PIN_M4 PIN_P2 PIN_N2 PIN_N1 PIN_M3 PIN_M2 PIN_M1 PIN_L7 PIN_L6 PIN_AA2 PIN_M5 PIN_M6 PIN_P1 PIN_P3 PIN_R2 PIN_R7 PIN_P8 PIN_R8 PIN_U1 PIN_V2 PIN_V3 PIN_W1 Description FLASH Address[0] FLASH Address[1] FLASH Address[2] FLASH Address[3] FLASH Address[4] FLASH Address[5] FLASH Address[6] FLASH Address[7] FLASH Address[8] FLASH Address[9] FLASH Address[10] FLASH Address[11] FLASH Address[12] FLASH Address[13] FLASH Address[14] FLASH Address[15] FLASH Address[16] FLASH Address[17] FLASH Address[18] FLASH Address[19] FLASH Address[20] FLASH Address[21] FLASH Data[0] FLASH Data[1] FLASH Data[2] FLASH Data[3] FLASH Data[4] FLASH Data[5] FLASH Data[6]

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FL_DQ[7] FL_DQ[8] FL_DQ[9] FL_DQ[10] FL_DQ[11] FL_DQ[12] FL_DQ[13] FL_DQ[14] FL_DQ15_AM1 FL_BYTE_N FL_CE_N FL_OE_N FL_RST_N FL_RY FL_WE_N FL_WP_N

PIN_Y1 PIN_T5 PIN_T7 PIN_T4 PIN_U2 PIN_V1 PIN_V4 PIN_W2 PIN_Y2 PIN_AA1 PIN_N8 PIN_R6 PIN_R1 PIN_M7 PIN_P4 PIN_T3

FLASH Data[7] FLASH Data[8] FLASH Data[9] FLASH Data[10] FLASH Data[11] FLASH Data[12] FLASH Data[13] FLASH Data[14] FLASH Data[15] FLASH Byte/Word Mode Configuration FLASH Chip Enable FLASH Output Enable FLASH Reset LASH Ready/Busy output FLASH Write Enable FLASH Write Protect /Programming Acceleration

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Chapter 5

Examples of Advanced Demonstrations

This chapter provides a number of examples of advanced circuits implemented on the DE0 board. These circuits provide demonstrations of the major features on the board, such as its video capabilities and SD card storage. For each demonstration the Cyclone III FPGA (or EPCS4 serial EEPROM) configuration file is provided, as well as the full source code in Verilog HDL code. All of the associated files can be found in the DE0\demonstrations folder from the DE0 System CD-ROM. For each of demonstrations described in the following sections, we give the name of the project directory for its files, which are subdirectories of the DE0_demonstrations folder.

Installing the Demonstrations

To install the demonstrations on your computer, perform the following 1. Copy the directory DE0_demonstrations into a local directory of your choice. It is important to ensure that the path to your local directory contains no spaces otherwise, the Nios II software will not work.

5.1 DE0 Factory Configuration

The DE0 board is shipped from the factory with a default configuration that demonstrates some of the basic features of the board. The setup required for this demonstration, and the locations of its files are shown below.

Demonstration Setup, File Locations, and Instructions

Project directory: DE0_Default Bit stream used: DE0_Default.sof or DE0_Default.pof Power on the DE0 board, with the USB cable connected to the USB Blaster port. If necessary (that is, if the default factory configuration of the DE0 board is not currently stored in EPCS4 device), download the bit stream to the board by using either JTAG or AS programming You should now be able to observe that the 7-segment displays are displaying a sequence of characters, and green LEDs are flashing. Optionally connect a VGA display to the VGA D-SUB connector. When connected, the VGA display should show a pattern of colors
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The Verilog source code for this demonstration is provided in the DE0_Default folder, which also includes the necessary files for the corresponding Quartus II project. The top-level Verilog file, called DE0_Default.v, can be used as a template for other projects, because it defines ports that correspond to all of the user-accessible pins on the Cyclone III FPGA.

5.2 SD Card
Many applications use a large external storage device, such as a SD card or CF card, to store data. The DE0 board provides the hardware and software needed for SD card access. In this demonstration we will show how to browse files stored in the root directory of a SD card and how to read the file contents of a specific file. The size of the SD card should be less or equal to 2GB. Also, it is required to be formatted as FAT (FAT16 or FAT 32) File System in advance. Long file name is supported in this demonstration. Figure 5-1 shows the hardware system block diagram of this demonstration. The system requires a 50 MHz clock provided from the board. Four PIO pins are connected to the SD card socket. They are SD_CLK, SD_CMD, SD_DAT and SD_WP_N. The three pins SD_CLK, SD_CMD and SD_DAT are used to implement SD 1-bit Mode protocol for accessing the SD card content. The SD 1-bit protocol and FAT File System function are all implemented by NIOS II software. The software is stored in the on-board SDRAM memory.

Figure 5-1 Block Diagram of the SD Card Demonstration Figure 5-2 shows the software stack of this demonstration. The NIOS PIO block provides basic IO functions to access hardware directly. The functions are provided from NIOS II system and the
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function prototype is defined in the header file <io.h>. The SD-CARD block implements SD 1-bit mode protocol for communication with the SD card. The FAT File System block implements reading function for FAT16 and FAT 32 file system. Long filename is supported. By calling the exported FAT functions, users can browse files under the root directory of the SD card. Furthermore, users can open a specified file and read the contents of the file. The main block implements main control of this demonstration. When the program is executed, it detects whether a SD card is inserted. If a SD card is found, it will check whether the SD card is formatted as FAT file system. If a FAT file system is found, it searches all files in the root directory of the FAT file system and displays their names in the nios2-terminal. If a text file named test.txt is found, it will dump the file contents. If it successfully recognizes the FAT file system, it will turn on the all of green LED. On the other hand, it will turn off all of the green LED if it fails to parse the FAT file system. Half number of the green LED will be turn on if there is no SD card found in the SD Card socket. If users press BUTTON2 of the DE0 board, the program will perform above process again.

Main FAT File System SD-CARD NIOS II PIO

Figure 5-2. Clock Diagram of the SD Card Demonstration

Demonstration Source Code

Project directory: DE0_NIOS_SDCARD Bit stream used: DE0_TOP_SDCARD.sof NIOS II Workspace: DE0_NIOS_SDCARD\Software

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Demonstration Batch File

Demo Batch File Folder: DE0_NIOS_SDCARD \Demo_Batch The demo batch file includes following files: Batch File: test.bat, test_bashrc FPGA Configure File: DE0_TOP_SDCARD.sof NIOS II Program: DE0_SDCARD.elf

Demonstration Setup
Make sure Quartus II and NIOS II are installed on your PC. Change Switch to PROG Mode to RUN mode in DE0 board. Power on the DE0 board. Connect USB Blaster to the DE0 board and install USB Blaster driver if necessary. Execute the demo batch file test.bat under the batch file folder, DE0_NIOS_SDCARD\demo_batch. After NIOS II program is downloaded and executed successfully, a prompt message will be displayed in nios2-terminal Copy test files to the root directory of the SD Card. Insert the SD card into the SD Card socket of DE0, as shown in Figure 5-3. Press Button2 of the DE0 board to start reading SD Card. The program will display SD Card information, as shown in Figure 5-4.

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Figure 5-4. Display SD Card Information for the SD Card Demonstration

5.3 VGA Color Pattern Demonstration

The DE0 board provides a 4-bit resistor VGA circuit and D-SUB VGA connector that allow users to output VGA signals to LCD/CRT monitor using Cyclone III FPGA. This demonstration will implement a VGA color pattern generator in the FPGA. This color pattern generator can generate 2 color patterns using the resolution 640x480. In addition, using SW0 can switch the output color pattern to LCD/CRT monitor. Figure 5-5 shows the basic block diagram of this demonstration. There are two major blocks in the circuit, called VGA_Pattern and VGA_Ctr. The VGA_Pattern block controls every pixel value for each horizontal and vertical line; therefore the VGA_Pattern block can generate many color patterns. The VGA_Ctr block generate VGA control signals HS and VS that depend on the users resolution setting that are used to output onto the LCD/CRT monitor.
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Altera DE0 Board

Cyclone III FPGA

mVGA_R mVGA_G VGA_Pattern mVGA_B mVGA_X mVGA_Y VGA_Ctrl VGA_R VGA_G VGA_B VGA_HS VGA_VS 4-bit VGA Circuit & VGA Connector LCD/CRT Monitor

SW0

Figure 5-5. Block diagram of the VGA Color Pattern demonstration.

Demonstration Setup, File Locations, and Instructions

Project directory: DE0_VGA Bit stream used: DE0_VGA.sof or DE0_VGA.pof Connect the VGA output of the DE0 board to a VGA monitor (both LCD and CRT type of monitors should work) Load the bit stream into FPGA. The LCD/CRT monitor should display the color pattern as shown in Figure 5-6. Switch SW0 can change the color pattern (see Figure 5-7).

Figure 5-6 illustrates the setup for this demonstration.

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Pattern 1

Pattern 2

SW0

SW0

Figure 5-7. The output color pattern type for the demonstration

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Chapter 6

Appendix
6.1 Revision History
Version V1.0 V1.1 V1.2 V1.3 V1.4 V1.5 V1.6 Change Log Initial Version (Preliminary) GPIO Pin Assignments Corrected SDRAM pin description Corrected Figure 4.10 Clock Circuitry pin assignment Corrected SD card demonstration setup corrected Add debounced circuit description Modify section 4.2 PROG. SW description

6.2 Copyright Statement

Copyright 2011 Terasic Technologies. All rights reserved.

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