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Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary
Logical Effort
David Harris
Page 2 of 56
Introduction
Chip designers face a bewildering array of choices.
? ? ?
o o o o o o o o o
What is the best circuit topology for a function? How large should the transistors be? How many stages of logic give least delay?
Logical Effort is a method of answering these questions: Uses a very simple model of delay Back of the envelope calculations and tractable optimization Gives new names to old ideas to emphasize remarkable symmetries
Who cares about logical effort? Circuit designers waste too much time simulating and tweaking circuits High speed logic designers need to know where time is going in their logic CAD engineers need to understand circuits to build better tools
Logical Effort
David Harris
Page 3 of 56
Example
Ben Bitdiddle is the memory designer for the Motoroil 68W86, an embedded processor for automotive applications. Help Ben design the decoder for a register file: 32 bits a<3:0> a<3:0>
4:16 Decoder
Decoder specification:
o o o o o o o o
16
Register File
Each bit presents a load of 3 unit-sized transistors True and complementary inputs of address bits a<3:0> are available Each input may drive 10 unit-sized transistors
Ben needs to decide: How many stages to use? How large should each gate be? How fast can the decoder operate?
David Harris Page 4 of 56
Logical Effort
16 words
Outline o o o o o o o o
Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary
Logical Effort
David Harris
Page 5 of 56
d abs d = ---------
Delay of logic gate has two components: effort delay, a.k.a. stage effort parasitic delay
12 ps
in 0.18 m technology
d = f+p
Effort delay again has two components: logical effort electrical effort = Cout/Cin electrical effort is sometimes called fanout
f = gh
o o
Logical effort describes relative ability of gate topology to deliver current (defined to be 1 for an inverter) Electrical effort is the ratio of output to input capacitance
David Harris Page 6 of 56
Logical Effort
Delay Plots
6 Normalized delay: d 5 4 3 2 1 parasitic delay 1 2 3 4 5 Electrical effort: h = Cout / Cin
AN D
in ve rte r
2-
g= p= d=
effort delay
inp ut N
g= p= d=
o d = f + p = gh + p o Delay increases with electrical effort o More complex gates have greater logical effort and parasitic delay
Logical Effort David Harris Page 7 of 56
o o
Measured from delay vs. fanout plots of simulated or measured gates Or estimated, counting capacitance in units of transistor width:
a b 2 x a 1
4 4
x a b
1 1
Logical Effort
David Harris
Page 8 of 56
A Catalog of Gates
Table 1: Logical effort of static CMOS gates
Number of inputs Gate type 1 inverter NAND NOR multiplexer XOR, XNOR 1 4/3 5/3 2 4 5/3 7/3 2 12 6/3 9/3 2 32 7/3 11/3 2 (n+2)/3 (2n+1)/3 2 2 3 4 5
p inv 1
parasitic delays depend on diffusion capacitance
Logical Effort
David Harris
Page 9 of 56
Example
Estimate the frequency of an N-stage ring oscillator:
g = h = p = d =
Oscillator Frequency: F =
Logical Effort
David Harris
Page 10 of 56
Example
Estimate the delay of a fanout-of-4 (FO4) inverter:
g = h = p = d =
Logical Effort
David Harris
Page 11 of 56
Outline o o o o o o o o
Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary
Logical Effort
David Harris
Page 12 of 56
g1 = 1 h1 = x/10
g2 = 5/3 h2 = y/x
g3 = 4/3 h3 = z/y
g4 = 1 h4 = 20/z
o o o
G =
gi fi = g i h i
Dont define
H =
F =
hi
Can we write F = GH ?
Logical Effort David Harris Page 13 of 56
Branching Effort
No! Consider circuits that branch:
15 5 15 90 90
G = H = GH = h1 = h2 = F =
= GH?
Logical Effort
David Harris
Page 14 of 56
o o o
fi PF = pi DF = di = D F + P
DF =
1N f = gi hi = F
We can prove that delay is minimized when each stage bears the same effort:
NF
1N
+P
This is a key result of logical effort. Lowest possible path delay can be found without even calculating the sizes of each gate in the path.
Logical Effort
David Harris
Page 15 of 56
C in
C out g i i = --------------------- f
Check your work by verifying that the input capacitance specification is satisfied at the beginning of the path.
Logical Effort
David Harris
Page 16 of 56
Example
Select gate sizes y and z to minimize delay from A to B A Logical Effort: Electrical Effort: Branching Effort: Path Effort: Best Stage Effort: Delay: y z 9C z 9C z C
G = H = B = F =
f =
9C
D =
Logical Effort
David Harris
Page 17 of 56
Outline o o o o o o o o
Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary
Logical Effort
David Harris
Page 18 of 56
o o
Delay is not always minimized by using as few stages as possible Example: How to drive 64 bit datapath with unit-sized inverter 1 1 1 1 Initial driver 4 2.8 8 16 8 22.6 Datapath load 64 1 64 65 64 2 8 18 64 3 4 15 64 Fastest 4 2.8 15.3
N: f: D:
D = NF
Logical Effort
1N
+ P = N ( 64 )
1N
David Harris
How many stages should we use? Let N be the value of N for least delay. Logic Block: n1 stages Path effort F
n1 1N
D = NF
pi + ( N n1 )pinv
1
Define F
1N
p inv + ( 1 ln ) = 0
Logical Effort David Harris Page 20 of 56
o o
Neglecting parasitics (i.e. pinv = 0), we get the familiar result that = 2.718 (e)
D(N) / D(N)
1 .5 1 1 .2 6 1 .1 5
( = 2 .4 )
( = 6 )
I like to use =4
0 .0
0 .5
0 .7
1 .0
1 .4
2 .0
N /N
2.4 < < 6 gives delays within 15% of optimal -> we can be sloppy
David Harris Page 21 of 56
Logical Effort
Outline o o o o o o o o
Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary
Logical Effort
David Harris
Page 22 of 56
Example
Lets revisit Ben Bitdiddles decoder problem using logical effort: 32 bits a<3:0> a<3:0>
4:16 Decoder
Decoder specification:
o o o o o o o o
16
Register File
Each bit presents a load of 3 unit-sized transistors True and complementary inputs of address bits a<3:0> are available Each input may drive 10 unit-sized transistors
Ben needs to decide: How many stages to use? How large should each gate be? How fast can the decoder operate?
Logical Effort
David Harris
Page 23 of 56
16 words
o o o o o
Effort of decoders is dominated by electrical and branching portions Electrical Effort: Branching Effort:
H = B =
F =
Remember that the best stage effort is about = 4 Hence, the best number of stages is: N =
Logical Effort
David Harris
Page 24 of 56
y z
out15
o o o o
Actual path effort is: Therefore, stage effort should be: Gate sizes: Path delay:
F = f = z = D =
y =
Logical Effort
David Harris
Page 25 of 56
o o o
Logical effort facilitates comparing different designs before selecting sizes Using more stages also reduces G and P by using multiple 2-input gates Our design was about 10% slower than the best
Logical Effort
David Harris
Page 26 of 56
Outline o o o o o o o o
Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary
Logical Effort
David Harris
Page 27 of 56
Asymmetric Gates
Asymmetric logic gates favor one input over another. Example: suppose input A of a NAND gate is most critical.
o o
Select sizes so pullup and pulldown still match unit inverter Place critical input closest to output 2 2
x a
4/3 4
o o o
gA = gB = g tot = g A + g B
David Harris Page 28 of 56
Logical Effort
Symmetry Factor
In general, consider gates with arbitrary symmetry factor s:
o o
x a
1/(1-s) 1/s
gB
1 --+2 s = -----------3
o o
Critical input approaches logical effort of inverter = 1 for small s But total logical effort is higher for asymmetric gates
Logical Effort
David Harris
Page 29 of 56
Skewed Gates
Skewed gates favor one edge over the other. Example: suppose rising output of inverter is most critical.
x a
1/2
x a
1
x a
1/2
Unskewed w/ Unskewed w/ equal rise equal fall Compare with unskewed inverter of the same rise/fall time to compute effort.
HI-Skewed inverter
o o o
Logical Effort for rising (up) output: Logical Effort for falling (down) output: Average Logical Effort:
gu = gd = g avg = ( g u + g d ) 2
Logical Effort
David Harris
Page 30 of 56
o o o o
HI-Skewed gates favor rising outputs by downsizing NMOS transistors LO-Skewed gates favor falling outputs by downsizing PMOS transistors Logical effort is smaller for the favored input due to lower input capacitance Logical effort is larger for the other input
Logical Effort
David Harris
Page 31 of 56
2 2 2
4 4
HI-Skew
1 1
gu = 1 gd = 2 gavg = 3/2
1 1 1
2 2
gu = 2 gd = 1 gavg = 3/2
1
LO-Skew
1
2 2
gu = 2 gd = 1 gavg = 3/2
Logical Effort
David Harris
Page 32 of 56
Outline o o o o o o o o
Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary
Logical Effort
David Harris
Page 33 of 56
Pseudo-NMOS
Pseudo-NMOS gates replace fat PMOS pullups on inputs with a resistive pullup.
o o o o o
Resistive pullup must be much weaker than pulldown stack (e.g. 4x) Reduces logical effort because inputs must only drive the NMOS transistors However, NMOS current reduced by contention with pullup Unequal rising and falling efforts Quiescent power dissipation when output is low
2/3
o o o
Logical Effort for falling (down) output: Logical Effort for rising (up) output: Average Logical Effort:
gd = gu = g avg = ( g u + g d ) 2
x a
4/3
Logical Effort
David Harris
Page 34 of 56
Pseudo-NMOS Gates
Inverter 2/3
NAND2 2/3
NOR2 2/3
x a
4/3
x a b
8/3 8/3 gd = 8/9 gu = 8/3 gavg = 16/9 gd = 4/9 gu = 4/3 gavg = 8/9
x a
4/3 4/3
Logical Effort
David Harris
Page 35 of 56
Dynamic Logic
Dynamic logic replace fat PMOS pullups on inputs with a clocked precharge.
o o o o
Reduces logical effort because inputs must only drive the NMOS transistors Eliminates pseudo-NMOS contention current and power dissipation Only the falling (evaluation) delay is critical Downsize noncritical precharge transistors to reduce clock load and power
gd =
x a
1
Robust gates may require keepers and clocked pulldown transistors (feet).
o o
Feet prevent contention during precharge but increase logical effort Weak keepers prevent floating output at cost of slight contention during eval
David Harris Page 36 of 56
Logical Effort
Dynamic Gates
Inverter
Footless
NAND2 1
NOR2 1
x a
1 gd = 1/3
x a b
2 2 gd = 2/3
x a
1 1
b
gd = 1/3
Footed
x a
2 2 gd = 2/3
x a b
3 3 3 gd = 1
x a
2 2 2
b
gd = 2/3
Logical Effort
David Harris
Page 37 of 56
Domino Gates
Dynamic gates require monotonically rising inputs.
o o o o o o o o o o o
However, they generate monotonically falling outputs Alternate dynamic gates with HI-skew inverting static gates Dynamic / static pair is called a domino gate
Example: Domino Buffer Constraints: maximum input capacitance = 3, load = 54 Logical Effort: Electrical Effort: Path Effort: Stage Effort: G= H= F= f= 3 3 g1 p HI-Skew 54 n Branching Effort: B =
g2
Logical Effort
David Harris
Page 38 of 56
o o o
PMOS transistors have half the drive of NMOS transistors Skewed gates downsize noncritical transistors by factor of two Pseudo-NMOS gates have 1/4 strength pullups Table 4: Summary of Logical Efforts
Inverter g Circuit Style Static CMOS HI-Skew LO-Skew Pseudo-NMOS Footed Dynamic Footless Dynamic 5/6 4/3 4/3 2/3 1/3 gu 1 5/3 2/3 4/9 gd n-input NAND g gu (n+2)/3 (n/2+2)/3 2(n+1)/3 4n/3 (n+1)/3 n/3 (n+4)/3 (n+1)/3 4n/9 gd n-input NOR g gu (2n+1)/3 (2n+.5)/3 2(n+1)/3 4/3 2/3 1/3 (4n+1)/3 (n+1)/3 4/9 gd
Logical Effort
David Harris
Page 39 of 56
Outline o o o o o o o o
Introduction Delay in a Logic Gate Multi-stage Logic Networks Choosing the Best Number of Stages Example Asymmetric & Skewed Logic Gates Circuit Families Summary
Logical Effort
David Harris
Page 40 of 56
Summary
Table 5: Key Definitions of Logical Effort
Term Logical effort Electrical effort Stage expression Path expression
(seeTable 1)
G =
gi bi fi
C out h = --------C in
n/a
Branching effort
B =
Effort Effort delay
f = gh f 1 p
(seeTable 2)
F = GBH DF = N P =
pi
Page 41 of 56
d = f+p
David Harris
D = DF + P
Logical Effort
o o o o o o
Compute the path effort: Estimate the best number of stages: Estimate the minimum delay:
F = GBH log F N
4
1N D = NF +P
Sketch your path using the number of stages computed above Compute the stage effort:
1N f = F
C in
C out g i i = --------------------- f
Logical Effort
David Harris
Page 42 of 56
o o o o
Chicken & egg problem how to estimate G and best number of stages before the path is designed Simplistic delay model neglects effects of input slopes Interconnect iteration required in designs with branching and non-negligible wire C or RC same convergence difficulties as in synthesis / placement problem Maximum speed only optimizes circuits for speed, not area or power under a fixed speed constraint
Logical Effort
David Harris
Page 43 of 56
Conclusion
Logical effort is a useful concept for thinking about delay in circuits:
o o o o o o o
Facilitates comparison of different circuit topologies Easily select gate sizes for minimum delay Circuits are fastest when effort delays of each stage are equal and about 4 Path delay is insensitive to modest deviations from optimal sizes Logic gates can be skewed to favor one input or edge at the cost of another Logical effort can be applied to domino, pseudo-NMOS, and other logic families
Logical effort provides a language for engineers to discuss why circuits are fast. Like any language, requires practice to master
o http://www.mkp.com/Logical_Effort o Discusses P/N ratios, gate characterization, pass gate logic, forks, wires, etc.
Logical Effort David Harris Page 44 of 56
Delay Plots
6 Normalized delay: d 5 4 3 2 1 parasitic delay 1 2 3 4 5 Electrical effort: h = Cout / Cin
AN D inp ut N
in ve rte r
2-
o d = f + p = gh + p o Delay increases with electrical effort o More complex gates have greater logical effort and parasitic delay
Logical Effort David Harris Page 45 of 56
Example
Estimate the frequency of an N-stage ring oscillator:
g1
out h = --------= 1
C C in
Logical Effort
David Harris
Page 46 of 56
Example
Estimate the delay of a fanout-of-4 (FO4) inverter:
g1
out h = --------= 4
C C in
p = p inv 1 d = gh + p = 5
The FO4 inverter delay is a useful metric to characterize process performance. 1 FO4 delay = 5 This is about 60 ps in a 0.18 m process.
Logical Effort
David Harris
Page 47 of 56
Branching Effort
No! Consider circuits that branch:
15 5 15 90 90
o o o
B =
bi
Note:
hi = BH H
in circuits that branch
Page 48 of 56
F = GBH
David Harris
Logical Effort
Example
Select gate sizes y and z to minimize delay from A to B A C Logical Effort: Electrical Effort: Branching Effort: Path Effort: Best Stage Effort: Delay:
3
z 9C y z 9C z
G = (4 3)
9C
C out H = --------- = 9 C in
B = 23 = 6 F = GHB = 128
13 f = F 5
9C (4 3) z = ---------------------------= 2.4 C
3z ( 4 3 ) y = --------------------------- = 1.92 C
D = 3 5 + 3 2 = 21
Logical Effort
David Harris
Page 49 of 56
o o o
Effort of decoders is dominated by electrical and branching portions Electrical Effort: Branching Effort:
o o o
Path Effort:
Remember that the best stage effort is about = 4 Hence, the best number of stages is: N = log 476.8 = 3.1 Lets try a 3-stage design
Logical Effort
David Harris
Page 50 of 56
y z
F = 2 8 9.6 = 154
o Therefore, stage effort should be: f = ( 154 )1 3 = 5.36 o z = 96 1 5.36 = 18 y = 18 2 5.36 = 6.7 o D = 3f + P = 3 5.36 + 1 + 4 + 1 = 22.1
Logical Effort David Harris
Page 51 of 56
Asymmetric Gates
Asymmetric logic gates favor one input over another. Example: Suppose input A of a NAND gate is most critical:
o o
Select sizes so pullup and pulldown still match unit inverter Place critical input closest to output 2 2
x a
4/3 4
b
Effort on A goes down at expense of effort on B and total gate effort
o o o
g A = 10 9 gB = 2 g tot = g A + g B = 28 9
Logical Effort
David Harris
Page 52 of 56
Skewed Gates
Skewed gates favor one edge over the other. Example: suppose rising output of inverter is most important.
x a
1/2
x a
1
x a
1/2
Unskewed w/ Unskewed w/ equal rise equal fall Critical rising Compare with unskewed inverter of the same rise/fall time effort goes down o Logical Effort for rising (up) output: gu = 5 6 at expense of noncritical and o Logical Effort for falling (down) output: g d = 5 3 average effort
Skewed inverter
g avg = ( g u + g d ) 2 = 5 4
Logical Effort
David Harris
Page 53 of 56
Pseudo-NMOS
Pseudo-NMOS gates replace fat PMOS pullups on inputs with a resistive pullup.
o o o o o
Resistive pullup must be much weaker than pulldown stack (e.g. 4x) Reduces logical effort because inputs must only drive the NMOS transistors However, NMOS current reduced by contention with pullup Unequal rising and falling efforts Logical effort can be applied to domino, pseudo-NMOS, and other logic families
o o o
Logical Effort for falling (down) output: Logical Effort for rising (up) output: Average Logical Effort:
gd = 4 9 gu = 4 3
4/3
g avg = ( g u + g d ) 2 = 8 9
Logical Effort
David Harris
Page 54 of 56
Dynamic Logic
Dynamic logic replace fat PMOS pullups on inputs with a clocked precharge.
o o o
Reduces logical effort because inputs must only drive the NMOS transistors Eliminates pseudo-NMOS contention current and power dissipation Critical pulldown (evaluation) delay independent of precharge size
gd = 1 3
x a
1
Robust gates may require keepers and clocked pulldown transistors (feet).
o o
Feet prevent contention during precharge but increase logical effort Weak keepers prevent floating output at cost of slight contention during eval
Logical Effort
David Harris
Page 55 of 56
Domino Gates
Dynamic gates require monotonically rising inputs.
o o o o o o o o o o o
However, they generate monotonically falling outputs Alternate dynamic gates with HI-skew inverting static gates Dynamic / static pair is called a domino gate
Example: Domino Buffer Constraints: maximum input capacitance = 3, load = 54 Logical Effort: Electrical Effort: Path Effort: Stage Effort: G = (1/3) * (5/6) = 5/18 H = 54/3 = 18 F = (5/18) * 1 * 18 = 5 f= 3 3 g1 = 1/3 p HI-Skew 54 n g2 = 5/6 Branching Effort: B = 1
5 = 2.2
Logical Effort
Page 56 of 56