Design and Harmonic analysis of Multi Level step up inverter

Veeranki. Sabari Pradeep

Koneru Lakshmaiah University, Department of Electrical and Electronics Engineering, Guntur, India pradeep9220@hotmail.com
Abstract In this paper a multilevel inverter whose output voltage can be boosted to desired voltage is proposed. The output level depends on the value of the modulation factor used. The modulation factor is varied using digital modulation technique. This proposed technique uses capacitor switching as the key concept. This, like a normal inverter has the virtue of harmonic reduction and also reduces the number of switches required for operation compared to a traditional converter Index terms boosting, multilevel inverter, switch mode operation. Digital modulation

alternating, but always less than are equal to voltage applied. The variable input voltage required by the inverter is supplied by a STEPUP model SMPS to counter the use of multiple sources and multiple HBridges. This paper deals with the Hybrid Multi-Level STEP UP Inverter. SWITCHED CAPACITOR STEP UP CONVERTER (SCSUC) A switched capacitor step up inverter uses capacitor switching to boost output voltage to the required value. This is done by charging the capacitors in parallel and discharging them in series. The circuit of the switched capacitor step up converter is shown in the figure-1. When switches 1 and 2 are closed the capacitors is charged to a voltage of for time 1 . = (1) II.

I. INTRODUCTION The proposed inverter has two technologies blended in it. First of it is the Multi-Level Inverter (MLI) technology. The FOUR switch VSI is generally called as two level inverter due to the fact that it has only two of instantaneous phase voltages
2

and . In other
2

words phase voltages can take one of the two voltage levels. Multi-level inverter provides an alternative to these voltage levels. For example in a three level inverter the output voltage levels are instantaneously 0, , . The complicated issue in this topology is the
2 2

During this time switches 3 and 4 are open when these switches are closed the output voltage is + across the load for time2 . = + (2)

switching sequence. This problem can be addressed by use of modulating techniques. There are usually inverter topologies which use diodes and capacitors for obtaining the required number of level of voltages. But due to the use of large number of elements its size and weight increases and complexity in design of switching circuitry. Digital methods of modulation are the most suitable techniques to address the problem of switching. Another topology which provides the additional advantage of getting the required voltage by increasing number of simple H-bridges connected in cascade with the Cascaded Multilevel Inverter (CMLI). The cascaded MLI uses many H-Bridges each with a separate source. This yields us higher voltage values, but increases the circuit size. The output obtained is

Figure 1 Step UP Converter

Here we observe as the number of capacitors increases the output voltage also increases. This circuit can be modified to obtain a unipolar multilevel step up converter, which has different output levels. The output wave form obtained is similar to that of a cascaded inverter, but unipolar as shown in figure 3 the output of normal step up converter is shown in figure 2.

voltage. Hence there is only one H-Bridge for any number of output voltage levels B. Working The switching sequence of the proposed inverter is shown in Fig. 6 for the switch mode section. The procedure cited below explains the inverter working in positive half cycle when and are closed. First level of 0v is obtained by maintaining a delay of 1 in switching and . After 1 , Sa and Sd are closed. During 2 , switches 1 ,3 ,4 , and 6 are closed to charge each capacitor to a voltage ( ) equal to supply voltage and 7 , 9 are closed to supply the voltage of 1 to H-Bridge inverter. During this interval of time we get a voltage equal to supply voltage at the output. The interval between 2 and 3 is the period in which switches 7 ,2 ,4 , 6 and 8 are closed so that the capacitor now becomes in series with source and so the total voltage input to the H-Bridge inverter is 2 . From 3 to 4 the switches 7 ,2 , 3 , and 8 are closed
2

Figure 2 output of SUSC

Figure 3 output of modified SUSC

to supply an input of 3 . From

4 2

to 6 the voltage

CIRCUIT DESCRIPTION AND WORKING OF MULTI LEVEL STEP UP INVERTER A. Circuit description The circuit shown in Fig 4 & Fig 5 is the setup multilevel inverter which has two sections 1. 2. Switched mode section. H Bridge section

III.

levels start stepping down and finally reach to a voltage of 0v at 6 . The same procedure is repeated, in negative sequence but with switches and closed. Thus we obtain a multilevel boosted alternating output voltage as shown in Fig. 7 1 = = supply voltage, 2 = + (3) = 2 = 2 3 = 2 + (4) (5) (6)

Switched mode section: This section contains solid state devices that act as switches. They take the role of charging the capacitors and discharging the voltage to the next section. This section focuses on the charging of capacitors in parallel and discharging them in series. For a four level inverter there are totally 9 switches, two capacitors and a voltage source as shown in the Fig. 5 As the number of output voltage levels increase the number of elements also increases for a particular input. H Bridge section: The H-Bridge inverter section is used to make the unipolar output obtained in the first section to bipolar. It has four switches and is similar to that of a typical H-Bridge. The number of switches used in this section does not depend on the number of levels of output

Figure 4 Multilevel step up inverter

C. Mode of conduction of the proposed converter The circuit topology of the proposed converter is shown in Figure 4. This converter consists of dc input voltage , power switch S, coupled inductors and , one clamp diode 1 and, clamp capacitor 1 , two blocking capacitors 2 & 3 , two blocking diodes 2 and 3 , output diode 0 and, output capacitor 0 . The coupling inductor is modeled as magnetizing inductor and leakage inductor . To simplify the circuit analysis the following conditions are assumed. 1. Capacitors 2 , 3 and 0 are large enough that 2 , 3 and 0 are considered constant in one switching period. The power MOSFETS and diodes are considered as ideal, where as the parasitic effect of the power switched is considered. The coupling coefficient of the coupled inductor k is equal to
+

Mode 2: During this time interval, S is still turned on. Diodes 1 and 0 are turned off, and 2 and 3 are turned on. The current-flow path is shown in Fig.6. The magnetizing inductor stores energy from dc source . Some of the energy from DC source transfers to the secondary side of the coupled inductor to charge the capacitors 2 and 3 . Voltages 2 and 3 are approximately equal to . Output capacitor 0 provides the energy to load R. This operating mode ends when switch S is turned off at = 2.

2.

3.

and turns ratio of

the coupled inductor is equal to

Continuous conduction mode (CCM) operation During this time interval (0 1 ) S is turned on and the diodes 1 , 2 and 3 are turned off, and 0 is turned on. The motor current path is show in the fig 5. The primary side current of the coupling inductor is increased linearly, the magnetizing inductor stores its energy from the dc voltage . Due to leakage inductor , the secondary side current of the coupling inductor is decreased linearly. The voltage across the secondary side winding of the coupled inductor 2 and blocking voltages 2 and 3 are connected in series to charge the output capacitor 0 and to provide the energy to the load R. when the current has become zero, dc source begins to charge capacitors 2 and 3 via the coupled inductor. When is equal to at = 1 this operating ends.

Figure 6 conduction process of mode 2 in ccm Mode 3 During this time interval, S is turned off. Diodes 1 and 0 are turned off, and 2 and 3 are turned on. The current-flow path is shown in Fig. 7. The energies of leakage inductor and magnetizing inductor are released to the parasitic capacitor of switch S. The capacitors 2 and 3 are still charged by the DC source via the coupled inductor. The output capacitor 0 provides energy to load R. When the capacitor voltage + is equal to at = 3 , diode 3 conducts and this operating mode ends.

Figure 5 continuous conduction mode (mode1)

Figure 7 conduction process of mode 3 in ccm.

Mode 4: During this time interval, S is turned off. Diodes 1 , 2 , and 3 are turned on and 0 is turned off. The current-flow path is shown in Fig.8. The energies of leakage inductor and magnetizing inductor are released to the clamp capacitor 1 . Some of the energy stored in starts to release to capacitors 2 and 3 in parallel via the coupled inductor until secondary current is equals to zero. Meanwhile, current is decreased quickly. Thus, diodes 2 and 3 are cut off at = 4 , and this operating mode ends.

Mode 6: During this time interval, S is still turned off. Diodes 1 and 0 are turned on, and 2 and 3 are turned off. The current-flow path is shown in Fig.10. The primary-side and secondary-side windings of the coupled inductor, DC sources , and capacitors 1 , 2 , and 3 transfer their energies to the output capacitor 0 and load R. This mode ends at = 6 when S is turned on at the beginning of the next switching period.

Figure 8 conduction process in mode 4 of ccm. Mode 5:

Figure 10 conduction process in mode 6 of ccm. IV. STUDY STATE ANALYSIS OF PROPOSED INVERTER

During this time interval, S is turned off. Diodes 1 and 0 are turned on, and 2 and 3 are turned off. The current-flow path is shown in Fig.9. The energies of leakage inductor and magnetizing inductor are released to the clamp capacitor 1 . The primary and secondary windings of the coupled inductor, DC sources , and capacitors 2 and 3 are in series to transfer their energies to the output capacitor 0 and load R. This operating mode ends when capacitor 1 starts to discharge at = 5 .

At modes 4 and 5, the energy of the leakage inductor is released to the clamped capacitor 1 . According to previous work, the duty cycle of the released energy can be expressed as 1 =
1

2(1) +1

(7)

Where is the switching period, 1 is the duty ratio of the switch, and 1 is the time of modes 4 and 5. by applying the voltage second balance rule on , the voltage across the capacitor 1 can be represented by 1 =
1

(1+)+(1) 2

(8)

Since durations of modes 1, 3, and 5 are significantly short only modes 2, 4, and 6 are considered in CCM operation for the steady state analysis. In the time period of mode 3, the following equations can be written. Figure 9 conduction process in mode 5 of ccm. 1 =
+

(9)

2 = 1 =

(10)

Thus the voltage across the capacitors 2 and 3 can be written as 2 = 3 = 2 = (11)

During the duration of mode 5 and 6 the following equations can be formulated
5 6 2 = 2 = + 1 + 2 + 3 0 (12)

Thus the voltage across the magnetizing inductor is given by equation

5 6 1 = 1 = + 1 + 2 + 3 0

(13)

Using the voltage second balance equation on we get the following

1 + 1 = 0
0

Solving the above found equations we get =

1+ 1

+ +

(1)(1) 1 2

(14) Figure 11 Simulink model of the proposed inverter

The schematic of the voltage gain versus the duty ratio under various coupling coefficients of the coupled inductor is shown in Fig. 6 It is seen that the voltage gain is not very sensitive to the coupling coefficient. When k is equal to 1, the ideal voltage gain is written as =
1+ 1

(15)

If the proposed converter is operated in boundary condition mode, the voltage gain of CCM operation is equal to the voltage gain of DCM operation. From (15), the boundary normalized magnetizing inductor time constant can be derived as =
(1)2 2(1+)(1+2)

(16)

Figure 12 Gate pules to the switches of the proposed inverter

Figure 13 output voltage of the inverter with R load VI.

Figure 10 current output of the R L load HARMONIC STUDY OF MULTILEVEL STEP UP INVERTER WITH R L LOAD.

As the output wave for is symmetric it has no even harmonics. Total harmonic distortion (THD), odd harmonics components, percentage of fundamental component are the components of interest. FFT analysis of the proposed inverter voltage wave is shown in figure 11.

Figure 14 output of the inverter with RL load V. SIMULATION USING MATLAB

For an input of 230 V, if the switching sequence described above is followed for the proposed circuit then we obtain a voltage of 690V alternating at the output as shown in the Fig. 7 at no load. For a resistive load of R=100 and inductive load of R=100 , L= 0.001 H, the output waveforms are shown in Fig. 8, Fig. 9 & Fig. 10 respectively

Figure 9 voltage output of R-L load

Figure 11 FFT analysis of output voltage with R-L load

The above analysis gives information about the harmonics present in the output. It is observed that the output fundamental has a peak voltage of 628.1V. The third, fifth and seventh harmonic components are 9.05%, 5.16% and 9.54% respectively. VII. CONCLUSION Multi level inverters are known for their virtues. So the concept of multilevel inverters blended with switch mode converter technology yields a good outcome that can replace the cascaded converter. It has the added advantage of reduction in number of switches used compared to other inverters when the number of levels are increased as described in Table1. It however has the drawback of designing complexity for gating and capacitor design, but if deployed it can yield much better results than other inverters.
TABLE 1

VIII.

REFERENCES

[1] L .Tolbert and T. Habetler, ``Novel multilevel inverter carrier-based PWM method, in IEEE Trans. Industry Applications, 35(5), 1098 1107 (1999). [2] G. Walker and G. Ledwich, Bandwidth considerations for multilevel converters, IEEE Trans. Power Electronics 14(1), 7481 (1999). [3] Y. Liang and C. Nwankpa, A new type of STATCOM based on cascading voltage-source inverters with phaseshifted unipolar SPWM, IEEE Trans. Industry Applications 35(5), 11181123 (1999). [4] N.Schibli, T.Nguyen, and A.Rufer, A three-phase multi level converter for high-power induction motors IEEE Trans. Power Electronics 13(5), 978986 (1998). [5] J. Lai and F. Peng, Multi level convertersA new breed of power converters, IEEE Trans. Industry Applications 32 (3), 509517 (1997). [6] S. Halaacute; sz, A. Hassan, and B. Huu,Optimal control of three level PWM inverters, IEEE Trans. Industrial Electronics 44(1), 96106 (1997). 268 J. Espinoza [7] R. Menzies, P. Steiner, and J. Steinke, Five-level GTO inverters for large induction motor drives, in IEEE Trans. Industry Applications 30(4), 938944 (1994). [8] R. P. Severns and G. Bloom, Modern DC-to-DC Switchmode Power Converter Circuits, Van Nostrand Reinhold Company, New York, 1985.

Comparison of number of switches used in CMLI and MLSUI Switches Switches required required S.NO Level for for Step cascaded Up MLI MLI 1 4 12 13 2 5 16 16 3 6 20 19 4 7 24 22 5 8 28 25 6 9 32 28 7 10 36 31 8 11 40 34 9 12 44 37

IX.

BIBILOGRAPHY V. Sabari Pradeep pursued his Bachelor of Technology degree from Koneru Lakshmaiah University in Electrical and Electronics Engineering. His research interests include power electronic converter design, 3 D Space vector modulation, Artificial Intelligence, etc.

Graphical analysis of switch requirement

60 40 20 0 1 2 3 4 5 6 7 8 9

Switches required for cascaded MLI Switches required for Step Up MLI

Figure 12 graphical analysis of switches requirement for CMLI vs. MLSUI.