Reg. No.

Question Paper Code :

Third Semester

11252

B.E./B.Tech. DEGREE EXAMINATION, APRIL/MAY 2011 Computer Science and Engineering

CS 2202 DIGITAL PRINCIPLES AND SYSTEMS DESIGN (Common to Information Technology) (Regulation 2008) Time : Three hours

Answer ALL questions

PART A (10 2 = 20 marks) 1. form.

Represent the decimal numbers 200 and 200 using 2's complement binary

3. 4.

Draw the schematic of half-adder logic.

Write the HDL description of the following circuit

5. 6.

Determine the size and number of multiplexers required to implement a full adder. and for a 2 KB

7. 8.

Write the state transition table of J-K Flip-Flop. Draw the timing diagram showing the output of a 2 stage synchronous counter with respect to its clock signal. Express the next state characteristics of D and SR flip-flops.

9.

10.

Define static and dynamic hazards. PART B (5 16 = 80 marks)

21

Determine the number of address lines required for 512 bytes of memory memory.

21

2.

Write the truth tables of logical AND and XOR gates.

4 21
Maximum : 100 marks

11.

(a)

(i) (ii)

Convert (1947 )10 representations.

into its equivalent octal and hexadecimal (10) (6)

Perform (147 89 ) using 2's complement binary arithmetic. Or

(b)

(i)

Minimize the following expression using Karnaugh map.

Y = A B C D + A B C D + AB C D + A B C D + A B C D .

(ii) 12. (a) (i)

State and prove the De Morgan's theorems.

Design a combinational circuit that comprises only of NOR gates for the following expression giving the input output relation.
Y = AB C + AC + B C .

(ii) Draw the schematic of a full adder circuit and give its truth table. (6) Or (b) (i)

(ii)

Draw the schematic of a magnitude comparator and give its truth table. (6) Design a combinational logic using a suitable multiplexer to realize the following Boolean expression.
Y = A D + B C + B C D .

13.

(a)

(i)

21
Or 2

Design a BCD to Excess-3 code converter using truth table and K-Map simplification. (10)

(ii)

Compare and contrast between encoders and multiplexers.

(b)

(i)

Write short notes on the basic configuration of the three types of programmable Logic Devices. Draw the signals of a 32 8 RAM with control input. Show the external connections necessary to have a 128 8 RAM using a decoder and replication of this RAM. (10)

4 21
(10) (6) (10) (10) (6) (6)

14.

(a)

21
JA = K A = 1,

(ii)

A synchronous counter with four JK flip-flops has the following connections :

J B = QA Q D , K B = QA

11252

J C = KC = QA QB
J D = QA QB QC , and K D = QA

Determine the modulus n of the counter, and draw the output waveforms of the same. (16) Or (b) Design a synchronous counter using JK flip-flops to count the following sequence : 1-3-15-5-8-2-0-12-6-9. 15. (a) (i) (ii)

Explain the working principle of switch debounce logic.

Determine whether the circuit is stable or not whose excitation function is given by y = ( x 1 y ) x 2 . (10) Or Derive a circuit specified by the following flow table. xy 00 01 10 10 A A,0 A,0 B A,0 A,0 (10)

(b)

(i)

(ii)

Determine whether the following circuit has a static hazard or not. If yes, design a hazard-free logic for the same input and output relation. (6)

21

21
A,0 B,0 B,1 B,1 3

4 21
(16) (6)

11252