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Experiment No.

: 01

Date : 28.10.2013

Experiment Name: Simulate the drain and gate I-V characteristics of an nchannel MOS transistor using L=0.25 m and W=1 m. The drain and the gate voltages should be varied between 0 to 2.5V. Schematic Diagram:

Netlist Command:
********* Simulation Settings - General Section ********* .include "D:\anusree\TannerSupportDocuments\TannerModelFiles\tannermodels\hp05.md" *-------- Devices With SPICE.ORDER > 0.0 -------***** Top Level ***** MNMOS_1 Iprint N_1 Gnd Gnd NMOS W=1u L=1u AS=900f PS=3.8u AD=900f PD=3.8u $ $x=17200 $y=8800 $w=400 $h=600 Vvds Iprint Gnd DC 2.5 $ $x=19000 $y=-8100 $w=400 $h=600 Vvgs N_1 Gnd DC 2.5 $ $x=16500 $y=-9400 $w=400 $h=600 $m .PRINT DC I(mnmos_1,Iprint) $ $x=18525 $y=-7900 $w=2250 $h=400 ********* Simulation Settings - Analysis Section ********* .dc lin vvgs 0 2.5 100m lin vvds 0 2.5 100m ********* Simulation Settings - Additional SPICE Commands ********* .end

Graph :

Result Analysis : In case of NMOS transistor at first the o/p current id increases

linearly with o/p voltage vds . but with constant increasing of vds id saturates because of pinch off condition . After pinch off condition a constant current flows through the device.

Conclusion: expected.

The NMOS transistor shows an amplifying characteristics as

Experiment No.: 02

Date : 28.10.2013

Experiment Name: Simulate the drain and gate I-V characteristics of a pchannel MOS transistor using L=0.25 m and W=1 m. The drain and the gate voltages should be varied between 0 to 2.5V. Schematic Diagram:

Netlist Command:
********* Simulation Settings - General Section ********* .include "D:\anusree\TannerSupportDocuments\TannerModelFiles\tannermodels\45nm_PTM.md" *-------- Devices With SPICE.ORDER > 0.0 -------***** Top Level ***** MPMOS_1 gnd N_1 Vdd Vdd PMOS W=1u L=500n AS=900f PS=3.8u AD=900f PD=3.8u $ $x=700 $y=-100 $w=400 $h=600 Vvgs Vdd N_1 DC 2.5 $ $x=100 $y=-600 $w=400 $h=600 Vvds1 Vdd Gnd DC 2.5 $ $x=3300 $y=300 $w=400 $h=600 .dc vvgs 0 1 0.05 sweep vvds1 0 1 .05 .PRINT I(MPMOS_1) ********* Simulation Settings - Analysis Section ********* ********* Simulation Settings - Additional SPICE Commands ********* .end

Graph :

Result Analysis : The graph we get is IDS vs. (VDS) graph. IDS, VDS, VGS, VTH are all negative
for PMOS. The different operating modes of PMOS are Cut off Mode: Occurs when VGS VTH. In this mode ID = 0. Triode Mode: Occurs when VGS < VTH and VDS > VGS VTH. ID = W/L P COX (VGS VTH (VDS/2)) VDS Saturation Mode: Occurs when VGS < VTH and VDS VGS VTH. ID = W/L P COX/2 (VGS VTH)2(1 + P VDS) In the experiment VGS and VDS both are varied between 0 and 2.5volts.

Conclusion:

It is clearly seen from the graph that All of the voltages are negative. Carrier mobility is less than for n channels. The bulk is now connected to Vdd.

Experiment No.: 03

Date : 28.10.2013

Experiment Name: Study the variations of ON current, OFF current and Subthreshold slope of an n-channel MOS transistor and a p-channel MOS transistor with the channel length L, keeping the channel width constant and then with channel width, keeping the length constant.

n-channel MOS transistor

Schematic Diagram:

Netlist Command:
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 N_2 N_1 GndGnd NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u VVoltageSource_1 N_1 Gnd DC 2.5 VVoltageSource_2 N_2 Gnd DC 2.5 .dc VVoltageSource_1 0 2.5 0.1 .include "D:\CALCUTTA UNIVERSITY M.Tech VLSI\indra_vlsi\Tanner Support hp05\Tanner Support Documents\Tanner Model Files\tanner models\ami05.md" .print I(MNMOS_1) VVoltageSource_1 ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .end

Graph :

Keeping the width constant (W=2.5m)

Keeping the Length constant (L=2.5m)

Result Analysis :

The ON-current, OFF-current and Sub-threshold slope with the channel length

L, keeping the channel width constant.


W
250 n 250 n 250 n 250 n

L
3 2.5 2 1.5

ON CURRENT
800 A 620 A 430 A 250 A

OFF CURRENT
0.1 A 0.1 A 0.1 A 0.1 A

SUB THRESHOLD SLOPE 71 .01 10 6 =0.00034 mho 205 .26 10 3 29 .46 10 6 =0.00029 mho 100 .35 10 3 13 .81 10 6 =0.00011 mho 95 .79 10 3 10 .94 10 6 =0.00010 mho 100 .47 10 3

The ON-current, OFF-current and Sub-threshold slope with channel width,

keeping the length constant.


W
200 n 250 n 300 n 350 n

L
2.5 2.5 2.5 2.5

ON CURRENT
689 A 600 A 540 A 485 A

OFF CURRENT
0.1 A 0.1 A 0.1 A 0.1 A

SUB THRESHOLD SLOPE 40 .98 10 6 =0.00042 mho 96 .30 10 3 33 .48 10 6 =0.00036 mho 91 .92 10 3 10 .48 10 6 =0.00011 mho 90 .68 10 3 8.02 10 6 =0.00010 mho 75 .66 10 3

p-channel MOS transistor

Schematic Diagram:

Netlist Command:
*-------- Devices: SPICE.ORDER > 0 -------MPMOS_1 Gnd N_2 N_1 N_1 PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u VVoltageSource_1 N_1 N_2 DC 2.5 VVoltageSource_2 N_1 Gnd DC 2.5 .include "D:\CALCUTTA UNIVERSITY M.Tech VLSI\indra_vlsi\Tanner Support hp05\Tanner Support Documents\Tanner Model Files\tanner models\ami05.md" .dc VVoltageSource_1 0 2.5 0.1 .print i(MPMOS_1) ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .end

Graph :

Keeping the width constant (W=2.5m)

Keeping the Length constant (L=2.5m)

Result Analysis : The ON-current, OFF-current and Sub-threshold slope with the channel length

L, keeping the channel width constant


W
250n 250n 250n 250n

L
3 2.5 2 1.5

ON CURRENT
-670A -540 A -400 A -270 A

OFF CURRENT
-0.1 A -0.1 A -0.1 A -0.1 A

SUB THRESHOLD SLOPE 45 .01 10 6 =-0.00031 mho 141 .00 10 3 37 .92 10 6 =-0.00024 mho 155 .09 10 3 23 .32 10 6 =-0.00017 mho 132 .28 10 3 13 .08 10 6 =-0.00011 mho 109 .40 10 3

The ON-current, OFF-current and Sub-threshold slope with the channel length

L, keeping the channel width constant and then with channel width, keeping the length constant.
W
200n 250n 300n 350n

L
2.5 2.5 2.5 2.5

ON CURRENT
-710A -520 A -405 A -302 A

OFF CURRENT
-0.1 A -0.1 A -0.1 A -0.1 A

SUB THRESHOLD SLOPE 58 .98 10 6 =-0.0003 mho 173 .33 10 3 43 .92 10 6 =0.00022 mho 196 .14 10 3 12 .92 10 6 =0.00012 mho 104 .91 10 3 7.11 10 6 =0.00011 mho 63 .86 10 3

Conclusion: For both the n-channel and the p-channel MOS Transistor, when we are decreasing the channel length, keeping the channel width constant, then the On-current as well as the sub-threshold slope is decreasing. We may observe the same phenomenon for increasing the channel width, keeping the channel length constant.

Experiment No.: 04

Date : 28.10.2013

Experiment Name: What is the model files used for this simulation and what level of device models have been used :- Study the variations of ON current, OFF current and Sub-threshold slope of an n-channel MOS transistor and a pchannel MOS transistor with the channel length L, keeping the channel width constant and then with channel width, keeping the length constant Solution: We are using here the model file of ami05.md Its Specifications are :
* T17Z SPICE BSIM3 VERSION 3.1 PARAMETERS * SPICE 3f5 Level 8, Star-HSPICE Level 49, UTMOST Level 8 * DATE: Aug 31/01 * LOT: T17Z WAF: * Temperature_parameters=Default .MODEL NMOS NMOS ( +VERSION = 3.1 TNOM +XJ = 1.5E-7 NCH +K1 = 0.9240592 K2 +K3B = -8.2637067 W0 +DVT0W = 0 DVT1W +DVT0 = 4.8161252 DVT1 +U0 = 452.9910821 UA +UC = 1.36892E-11 VSAT +AGS = 0.1225814 B0 +KETA = -1.403277E-3 A1 +RDSW = 1.009265E3 PRWG +WR = 1 WINT +XL = 0 XW +DWB = 4.715123E-8 VOFF +CIT = 0 CDSC +CDSCB = 0 ETA0 +DSUB = 0.2324094 PCLM +PDIBLC2 = 2.133519E-3 PDIBLCB +PSCBE1 = 5.797645E8 PSCBE2 +DELTA = 0.01 RSH +PRT = 0 UTE +KT1L = 0 KT2 +UB1 = -7.61E-18 UC1 +WL = 0 WLN 0103 = = = = = = = = = = = = = = = = = = = = = = = = 27 1.7E17 -0.1101636 1E-8 0 0.4265149 3.401004E-13 1.7399E5 2.516928E-6 2.426912E-5 0.1116523 2.383504E-7 0 0 2.4E-4 0.0261471 2.5474877 -0.1084533 7.964838E-5 81.5 -1.5 0.022 -5.6E-11 1 LEVEL = 49 TOX = 1.4E-8 VTH0 = 0.6448329 K3 = 23.4235629 NLX = 1E-9 DVT2W = 0 DVT2 = -0.0651522 UB = 1.45035E-18 A0 = 0.5657309 B1 = 5E-6 A2 = 0.3485275 PRWB = 0.0602327 LINT = 2.246083E-8 DWG = -1.008049E-8 NFACTOR = 0.6052024 CDSCD = 0 ETAB = -8.677414E-4 PDIBLC1 = -0.0864243 DROUT = 0.4199209 PVAG = 0 MOBMOD = 1 KT1 = -0.11 UA1 = 4.31E-9 AT = 3.3E4 WW = 0

+WWN = 1 +LLN = 1 +LWL = 0 +CGDO = 1.95E-10 +CJ = 4.208739E-4 +CJSW = 3.317061E-10 +CJSWG = 1.64E-10 +CF = 0 +PK2 = -0.034841 ) * .MODEL PMOS PMOS ( +VERSION = 3.1 +XJ = 1.5E-7 +K1 = 0.5515497 +K3B = -0.9439827 +DVT0W = 0 +DVT0 = 3.3002797 +U0 = 211.9394213 +UC = -6.12612E-11 +AGS = 0.1204526 +KETA = -3.212498E-3 +RDSW = 2.603871E3 +WR = 1 +XL = 0 +DWB = 2.10355E-8 +CIT = 0 +CDSCB = 0 +DSUB = 0.748371 +PDIBLC2 = 4.277884E-3 +PSCBE1 = 1.442293E10 +DELTA = 0.01 +PRT = 0 +KT1L = 0 +UB1 = -7.61E-18 +WL = 0 +WWN = 1 +LLN = 1 +LWL = 0 +CGDO = 2.39E-10 +CJ = 7.262406E-4 +CJSW = 2.648299E-10 +CJSWG = 6.4E-11 +CF = 0 +PK2 = 3.73981E-3 )

WWL LW CAPMOD CGSO PB PBSW PBSWG PVTH0 WKETA

= = = = = = = = =

0 0 2 1.95E-10 0.9851971 0.1 0.1 0.1188748 -0.0285217

LL LWN XPART CGBO MJ MJSW MJSWG PRDSW LKETA

= = = = = = = = =

0 1 0.5 1E-9 0.4446146 0.1185468 0.1185468 110.5079044 2.587244E-3

TNOM NCH K2 W0 DVT1W DVT1 UA VSAT B0 A1 PRWG WINT XW VOFF CDSC ETA0 PCLM PDIBLCB PSCBE2 RSH UTE KT2 UC1 WLN WWL LW CAPMOD CGSO PB PBSW PBSWG PVTH0 WKETA

= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =

27 1.7E17 8.631204E-3 5.982533E-7 0 0.4883519 2.76766E-9 2E5 8.44442E-7 0 -0.039596 2.825671E-7 0 -0.0391051 2.4E-4 0.0985525 2.1286859 -0.0531967 1.405139E-9 101.9 -1.5 0.022 -5.6E-11 1 0 0 2 2.39E-10 0.9498263 0.99 0.99 5.98016E-3 6.938515E-3

LEVEL = 49 TOX = 1.4E-8 VTH0 = -0.916972 K3 = 10.5990451 NLX = 5.621262E-8 DVT2W = 0 DVT2 = -0.0704755 UB = 1E-21 A0 = 0.8252611 B1 = 5E-6 A2 = 0.3 PRWB = -0.0178692 LINT = 5.512505E-8 DWG = -1.099676E-8 NFACTOR = 1.0044304 CDSCD = 0 ETAB = -0.0256269 PDIBLC1 = 0.0808794 DROUT = 0.2733248 PVAG = 0.1122947 MOBMOD = 1 KT1 = -0.11 UA1 = 4.31E-9 AT = 3.3E4 WW = 0 LL = 0 LWN = 1 XPART = 0.5 CGBO = 1E-9 MJ = 0.4954421 MJSW = 0.292953 MJSWG = 0.292953 PRDSW = 14.8598424 LKETA = -1.22599E-3

Experiment No.: 05

Date : 28.10.2013

Experiment Name: Simulate a CMOS inverter with channel length of the transistors equal to 0.25 m. Assume the W/L ratio of the n-channel MOS transistor to be 2, find out through repeated simulation what should be the aspect ratio of the p-channel MOS transistor to get the switching voltage equal to half of the supply voltage.

Schematic Diagram:

Netlist Command:
------- Devices: SPICE.ORDER > 0 -------.include "D:\CALCUTTA UNIVERSITY M.Tech VLSI\indra_vlsi\Tanner Support hp05\Tanner Support Documents\Tanner Model Files\tanner models\ami05.md" MNMOS_1 Vout N_1 Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 Vout N_1 VddVdd PMOS W=2.6u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u VVddVddGnd DC 5 VVin N_1 Gnd DC 5 .dc linVVin 0 5 0.1 .print dc V(Vout) .print dc V(N_1) .end

Graph :

Result Analysis : At first we kept the width of PMOS transistor at 1um keeping the length fixed in 0.5 m and simultaneously we observe the graph. We saw

that the switching voltage is coming 2.25V instead of 2.5V {because here Vdd/2 is 2.5}. So after that we vary the width of the PMOS transistor upto 3 m starting from 1 m and when we kept the width at 3 m then the switching voltage is coming 2.499V. Conclusion: We have seen that by keeping the switching voltage of CMOS transistor at Vdd/2, the (W/L) ratio of PMOS transistor will be higher compare to the (W/L) ratio of nMOS transistor.

Experiment No.: 06

Date : 28.10.2013

Experiment Name: For the CMOS inverter circuit drawn previously, extract the various propagation delay times using a unit step function as the input. Assume the input rise time to be 1ns. Repeat the problem for rise time to be 2ns, 4ns and 8ns. Make a comparison graph between the various delay parameters and rise time of the input. Schematic Diagram:

Netlist Command:
*-------- Devices: SPICE.ORDER > 0 -------MNMOS_1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 Out A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u VVoltageSource_1 A Gnd BIT({0101}PW=50n on=1 off=0 rt=1n ft=0.1n delay=0 lt=50n ht=50n) Vdd Vdd GND 1 .tran .1n 200n .print V(A) V(Out) .include "D:\CALCUTTA UNIVERSITY M.Tech VLSI\indra_vlsi\Tanner Support hp05\Tanner Support Documents\Tanner Model Files\tanner models\ami05.md" .measure tran delay trig v(Out) val=1 rise=1 targ v(A) val=350m fall=1 ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .end

Graph :

For 1 ns Output

For 2 ns Output

For 4 ns Output

For 8 ns Output

Result Analysis : Here we got various propagation delay times for unit step
function as input. Input rise times are taken as 1ns, 2ns, 4 ns. 8 ns respectively. From the comparison graph below, we can see that propagation delay increases with increasing rise times.

Conclusion: Key design challenge is to keep the signal rise times <= the gate propagation delay, for speed and power consumption. Keeping the rise and fall times of signals small and approximately equal is one of the major challenges in high-performance design. Experiment No.: 07 Date : 28.10.2013

Experiment Name: Draw and implement a full adder circuit and show its functionality for both sum and carry through simulation results. Schematic Diagram:

Netlist Command:
*************** Subcircuits ***************** .subckt INV A Out Gnd Vdd *-------- Devices: SPICE.ORDER > 0 -------MN1 Out A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MP1 Out A Vdd Vdd PMOS W=2.5u L=250n M=2 AS=4.5p PS=13.6u AD=3.125p PD=7.5u .ends ********* Simulation Settings - Parameters and SPICE Options ********* *-------- Devices: SPICE.ORDER == 0 -------XINV_1 Cout_bar COut Gnd Vdd INV XINV_2 N_4 Sum Gnd Vdd INV *-------- Devices: SPICE.ORDER > 0 -------MNMOS_3 Cout_bar C N_8 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_4 N_8 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_5 N_8 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_6 N_4 Cout_bar N_9 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_7 N_9 A Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_8 N_9 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_9 N_9 C Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_10 N_4 A N_10 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_11 N_10 B N_11 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u

MNMOS_12 N_11 C Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_1 Cout_bar A N_7 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MNMOS_2 N_7 B Gnd 0 NMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_10 N_5 A N_3 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_11 N_6 B N_5 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_12 N_4 C N_6 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_1 N_1 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_2 N_1 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_3 Cout_bar C N_1 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_4 N_2 A N_1 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_5 Cout_bar B N_2 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_6 N_3 A Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_7 N_3 B Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_8 N_3 C Vdd Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u MPMOS_9 N_4 Cout_bar N_3 Vdd PMOS W=2.5u L=250n AS=2.25p PS=6.8u AD=2.25p PD=6.8u VVoltageSource_1 A Gnd BIT({00001111} PW=50n on=1 off=0 rt=0.1n ft=0.1n delay=0 lt=50n ht=50n) VVoltageSource_2 B Gnd BIT({00110011} PW=50n on=1 off=0 rt=0.1n ft=0.1n delay=0 lt=50n ht=50n) VVoltageSource_3 C Gnd BIT({01010101}PW=50n on=1 off=0 rt=0.1n ft=0.1n delay=0 lt=50n ht=50n ) vdd vdd gnd 1 .tran .1n 800n .include "D:\CALCUTTA UNIVERSITY M.Tech VLSI\indra_vlsi\Tanner Support hp05\Tanner Support Documents\Tanner Model Files\tanner models\ami05.md" .print C B A COut Sum ********* Simulation Settings - Analysis section ********* ********* Simulation Settings - Additional SPICE commands ********* .end

Graph :

Result Analysis :

Full Adder Expression:


S A B Ci ABCi ABCi ABCi ABCi C 0 AB BC i AC i

This conventional expression can be reduced to


C 0 AB BC i AC i

S ABCi C0 ( A B Ci )

Truth table of a Full-Adder should be theoretically like the following:


INPUT A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 INPUT C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

What we are getting the values of Sum and Carry experimentally for the given inputs are matching the theoretical values for the same inputs given in the previous truth table. The experimental Truth Table is following:
INPUT A 0 0 0 0 1 1 1 1 INPUT B 0 0 1 1 0 0 1 1 INPUT C 0 1 0 1 0 1 0 1 SUM 0 1 1 0 1 0 0 1 CARRY 0 0 0 1 0 1 1 1

Conclusion: It is seen that the truth table and the waveform gives the identical result. Hence, the truth table verification of the response is done and also the experiment is completed successfully.

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