ARP and QPP Interleavers for LTE Turbo Coding

Ajit Nimbalker, Yufei Blankenship, Brian Classon, T. Keith Blankenship

Wireless and Solutions Research
Motorola Labs
1301 E. Algonquin Road, MD 2928
Schaumburg, IL 60196 USA
Email: {A.Nimbalker, Yufei.Blankenship, Brian.Classon, Keith.Blankenship}@motorola.com


Abstract The Long Term Evolution (LTE) of the WCDMA
standard requires turbo decoding throughputs of up to 100
Mbps. Unfortunately, the existing WCDMA turbo interleaver
does not permit an efficient high throughput implementation.
The almost regular permutation (ARP) and quadratic polynomial
permutation (QPP) interleavers were proposed to rectify this
situation with QPP selected for LTE. In this paper, the
interleavers are compared and a full suite of LTE designs and
performance results for both are presented.
Keywords-Long term evolution (LTE); turbo code; interleaver;
quadratic permutation polynomial (QPP), almost regular
permutation (ARP)
I. INTRODUCTION
The Third Generation Partnership Project (3GPP) is
developing a long term evolution (LTE) for the WCDMA
based air interface [1]. Key requirements of LTE include
packet data support with peak data rates up to 100 Mbps on the
downlink and 50 Mbps on the uplink, a low latency of 10 ms
layer-2 round trip delay, flexible bandwidths (up to 20 MHz),
improved system capacity and coverage, and efficient VoIP
support. Advanced technologies were selected to meet these
requirements including OFDM for the downlink, DFT-SOFDM
for the uplink, MIMO, and turbo coding.
The selection of turbo coding was considered carefully
during the study item phase of LTE to meet the stringent
requirements. After comparing several high performance codes
(e.g., turbo codes, LDPC codes, etc) on the basis of complexity,
flexibility, and backward compatibility, it was decided to use
the existing WCDMA turbo code with a new contention free
(CF) turbo interleaver to allow efficient parallelization of the
turbo decoder for high data rates. Following deliberations
within the working group, the Almost Regular Permutation
(ARP) and Quadratic Permutation Polynomial (QPP)
interleavers emerged as the most promising solutions to the
LTE requirements with QPP selected for LTE [2]. This paper
studies and compares ARP and QPP interleaver designs for
LTE.
Section II gives a brief review of WCDMA turbo code.
High throughput turbo decoding with CF interleavers is the
topic of Section III. A comparison of ARP and QPP
interleavers and how to design them are covered in Section IV.
A full suite of both ARP and QPP interleaver designs for LTE
and a performance summary is provided in Section V before
the paper draws conclusions in Section VI.
II. THE BASELINE WCDMA TURBO CODE
The turbo code (TC) in the WCDMA standard is a
systematic code that consists of a parallel concatenation of two
identical eight-state recursive convolutional codes interlinked
by an interleaver [3]. For an information block of size K bits,
the turbo encoder generates a codeword of length 3K +12 bits,
with a nominal code rate of 1/3 and 12 tail bits for trellis
termination of the constituent encoders. The WCDMA TC
supports all input block sizes between 40 and 5114 bits.
Therefore over 5000 interleavers are defined based on an
interleaving method that includes intra-row, inter-row
permutations and pruning [3].
Though the WCDMA TC interleaver is remarkable in that
it ensures good performance at most of the 5000+ interleaver
sizes, its performance is a concern at high code rates.
Simulations indicate that the error floors of the WCDMA TC
occur at Frame error rates (FERs) above 10
-4
in some cases [4],
resulting in severe link-level performance loss. This
performance inadequacy is due to the poor minimum distances
of the interleaver at many block sizes [5]; with puncturing, the
distance properties are degraded even further. In contrast,
recently developed interleavers such as DRP [6], ARP [7] and
QPP [8] provide better performance than the WCDMA
interleaver. This paper only discusses performance for the
unpunctured rate-1/3 turbo code. The performance with
puncturing for other code rates is considered as part of rate-
matching. For the interested reader, details on rate-matching
can be found in the 3GPP RAN1 contributions [25-27].
More importantly, the WCDMA turbo code interleaver
does not allow an efficient decoder which satisfies LTE
requirements. The WCDMA turbo code was designed to
support data rates up to 2 Mbps while the peak data rates for
LTE is 100+ Mbps. Although WCDMA decoder throughput
can be increased beyond 2 Mbps by techniques such as
increasing the clock rate or by radix-4 processing (e.g., [9]),
replacing the WCDMA interleaver with a CF interleaver allows
parallelized decoding with high throughput, low latency, and
efficient hardware usage.
III. HIGH-THROUGHPUT TURBO DECODING
A. Parallelized Decoding
Given current achievable clock rates on FPGAs and ASICs,
it is clear that the LTE throughputs require decoder parallelism.
1525-3511/08/$25.00 2008 IEEE
This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the WCNC 2008 proceedings.
Although parallelism can be obtained using multiple hardware
instances of a single decoder, this solution increases the
memory requirements (each decoder requires separate
memory) and also incurring a long latency. Recognizing these
deficiencies, the LTE working group decided upon an approach
that enables internal parallelism within a fast serial decoder.
The method of internal parallelism is also known as the
method of parallel windows [10]. In this method, the trellis of a
constituent convolutional code is divided into M windows of
equal length W, where the information block length is K = MW.
In the decoder, M processors, one per window, are used to
process the trellis of a constituent code in parallel [10], thus
increasing the throughput by a factor of M. To reduce
(de)interleaving latency, the LLR and other memories are also
designed to enable parallel data transfers between the memory
banks and processors. However, in actual designs, for high
decoding speeds, the parallelization requires M extrinsic values
to be concurrently written to or read from M memory banks.
Memory access contentions arise when two or more processors
attempt to access the same memory bank concurrently.
Existence of memory contentions is determined by the
turbo code interleaver and the parallelization factor M.
Contentions may cause significant throughput loss, and require
specialized hardware contention resolution [11]. For example,
parallelizing with the WCDMA turbo interleaver results in
memory access contentions for almost all block sizes and
parallelization factors (except trivial ones), thus leading to an
overall inefficient design. Other methods of memory
organization that exist ([12]) for resolving contentions based on
WCDMA interleaver also lead to inefficient memory
organization. Therefore, interleavers that are inherently
contention-free are preferable for LTE turbo coding.
B. Contention-Free and Vectorizable Interleavers
An interleaver (i), 0 i < K, is said to be contention-free
for a window size W if and only if it satisfies the following
for both interleaver = and deinterleaver =
-1
[13]:

( ) ( )
(

+
W
v W u
W
v W u
2 1

(1)
where 0 v < W, 0 u
1
, u
2
< M for all u
1
u
2
. The terms
on both sides of Inequality (1) are the memory bank indices
that are accessed by the M processors on the v-th step.
Inequality (1) requires that for any given position v of each
window the memory banks accessed be unique between any
two windows, thus eliminating access contentions as shown
in Fig. 1.
window 0
W
v v+
W
window 0
window1
window1
window2
window2
window
M-1
window
M-1
v
+
2
W
v+(M
-1)W

Figure 1. Contention-free interleaver memory access.
Interleavers that satisfy Inequality (1) guarantee that the
extrinsic data generated by the constituent decoders can be
stored and fetched from M different memories without
contentions. As M increases, using M physically separate
memories leads to memory inefficiency due to duplication of
the address decode logic. A better solution would be to use a
single physical memory and fetch/store M values on each
cycle from a single address. This requires an interleaver that
satisfies the following:
( ) ( ) W v W v uW mod mod = + (2)
for all 1 u <M and 0 v < W. An interleaver (i) that
satisfies (2) must have the form

( ) ,
y u
w W m v uW + = +
(3)
where 0 m
u
< M with m
x
m
y
for x y and 0 w
y
< W with
w
x
w
y
for x y. Using notation of [13], m
u
defines the inter-
window shuffle and w
y
defines the intra-window permutation.
Since the floor operation of (1) extracts m
u
, an interleaver
satisfying (2) also satisfies (1). It is also straightforward to
show that when an interleaver (i) satisfies (2) its inverse
must also satisfy the same relation and therefore (1) as well.
When (2) holds, rather than using M individual memory
banks, the decoder memory can be unified into a single bank
leading to a very efficient memory organization. Extrinsic
data can be stored and fetched as vectors with one address,
leading to a vectorized decoding algorithm. The vector
fetched by the address contains M LLR values that the M
parallel decoding windows utilize simultaneously.
Preferably, the block sizes K and their interleavers are
defined such that the decoder can be implemented with
various parallelism factors M, so that the M value can be
chosen to suit the receiver capability under consideration
without performance degradation. For a given K, very small
window sizes W can degrade performance, and hence in such
cases, the choice of decoder parallelism may be driven by
performance. For example, simulations show that the
minimum window size that can be allowed without significant
performance loss is W
min
= 32 for practical block size (~2000
to 6000 bits).
In LTE system, it is likely that the parallelism for each
data packet (e.g., interleaver size or code block size in [2]) is
fine-tuned according to factors such as required data rate,
latency and performance. For instance, a voice over IP (VoIP)
packet with small interleaver size may have a low target data
rate that could be served by a single processor (i.e., M=1) of
the turbo decoder hardware. In LTE, smaller data blocks (i.e.,
transport blocks) are associated with a single turbo codeword
with small interleaver sizes, while a large data block can be
associated with a larger number of turbo codewords with each
codeword using a larger interleaver size [2]. Therefore, for a
fixed latency, the desired parallelism factors (M) is expected
to increase with block size.
The class of CF interleavers has many candidates suitable
for LTE (See Sec 3.4, [14]). Of these, the ARP and QPP
interleavers always satisfy (2) for efficient high-speed turbo
decoder design, while providing performance equivalent to or
better than the WCDMA interleaver.
This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the WCNC 2008 proceedings.
IV. ARP AND QPP INTERLEAVERS
A. The ARP Interleaver
An ARP interleaver [7] is expressed by

( ) ( ) ( ) , mod
0
K i d A iP i + + =
(4)
where 0 i K-1 is the sequential index of the bit positions
after interleaving, (i) is the bit index before interleaving
corresponding to position i, K is the information block size in
bits, P
0
is an integer relatively prime to K, A is a constant
offset, and d(i) is a dither vector of length C where C is a
small number (e.g., 4, 8) called the cycle length. For all block
sizes, the dither d(i) assumes the form

( ) ( ) ( ), mod mod
0
C i P C i i d + =
(5)
where () and () are vectors each of length C, periodically
applied for 0 i K-1. Both the dither vectors () and () are
composed of multiples of the cycle length C.
For an ARP interleaver, since the block size K has to be a
multiple of C, certain block sizes (e.g., primes) are not suitable
for ARP interleaver design. However, this constraint is
acceptable in practice since block sizes (K) that are multiples of
small integers (C) tend to have more choices for parallelism
factors M.
A major benefit of the ARP design is that it is vectorizable
for many different parallelism factors. In general, for a block
size K, and cycle length C, the ARP is CF for any parallelism
M where K/C is a multiple of M. For example, suppose a 2048-
bit interleaver is designed with C=8, then any number from the
set {1, 2, 4, 8, 16, 32, 64, 128, 256} is a valid choice for the
parallelism factor M.
Since (4) is equivalent to a linear permutation with a
constant that is a function of index i, (4) and its inverse have
identical format. This enables using a single circuit for both
interleaver and deinterleaver.
B. The QPP Interleaver
For an information block size K, a QPP interleaver of size
K is defined by the following polynomial [8,15].
( ) ( ) K i f i f i mod
2
2 1
+ = (6)
where 0 i K-1 is the sequential index of the bit position
after interleaving, (i) is the bit index before interleaving
corresponding to position i, and f
1
and f
2
are the coefficients
that define the permutation. The conditions on f
1
and f
2
for
which (6) defines a valid permutation are extensively
considered in [8]. Possibilities of these coefficients are related
to the factorization of K. For e.g., when K is even, the
conditions are: i) f
1
is odd (relatively prime to K), and ii) all
prime factors of K are also factors of f
2
.
QPP interleavers (and permutation polynomials in general)
can be computed recursively with only adders (i.e., the
multiplications in Equation (6) can be rewritten with additions
for recursive realization) [16]. QPP interleavers are maximum
contention-free and maximum vectorizable, i.e., they provide
CF memory access for any M that factors K [14]. For example,
for a QPP interleaver with K=2048, any M =2
x
, 0<x11, is a
valid choice for M. It should be noted that very large values of
M (thus very small window sizes) are impractical.
Though the inverse of (6) is also a permutation polynomial,
it is not always quadratic. A method of computing inverse of
QPP permutation was described in [16]. The degree of inverse
polynomial is a function of the block size K and second order
coefficient f
2
. Reference [17] derives conditions on f
2
under
which the inverse is also a quadratic polynomial. For some
block sizes, a stringent requirement of quadratic inverses
results in QPP ensembles with inferior performance and low
minimum distances. Therefore, a better design is to choose
QPP interleavers that have the lowest degree inverse
polynomial (for reduced complexity) while incurring no
performance penalty.
C. Designing ARP and QPP Interleavers
The ARP and QPP interleavers may be designed based on
conventional interleaver design metrics such as the spread,
dither and the minimum distance d
min
. Moreover, these
permutations have periodic distance properties that help to
reduce the search complexity. In addition, the effect of trellis
termination on minimum distance needs to be handled
appropriately. For QPP-based interleavers, [18] provides a new
design metric based on combining the spread-dispersion
metrics, while [7] discusses ARP interleaver design based on
minimum distance computation using error impulse method. A
suitable combination of these design techniques may be used to
find candidate interleavers for each block size.
ARP and QPP interleavers have the even-even (or odd-odd)
property which means that even (odd) positions in the input are
mapped to even (odd) positions in the output. Therefore, they
are both very suitable for Radix-4 processing. Both interleavers
can also provide significantly larger minimum distances
compared to the WCDMA interleaver (see next section for
details). The two designs allow efficient inverse permutations
using a single hardware circuitry.
Of these two closely competing designs, the QPP was
selected as the final choice for LTE as it holds a slight edge: i)
it has more parallelism factors M available due to maximum
contention-free property, ii) it has a fully algebraic description,
and iii) it requires slightly less interleaver parameter storage.
However, it is noted that ARP design has some advantages
over QPP: i) ARP interleavers have slightly better minimum
distance than QPP for interleaver sizes that are multiples of 7
(i.e., period of the constituent convolutional code in LTE Turbo
code.), ii) deinterleavers of ARP are guaranteed to be ARP,
while the deinterleavers of QPP may not be QPP (i.e., a higher
degree polynomial).
V. ARP AND QPP INTERLEAVER FOR LTE
A. Block Sizes
Though the WCDMA turbo code specifies 5000+
interleaver sizes with granularity of one bit, such fine
granularity is not desirable for CF interleavers. Many
interleaver sizes K are not be supportable by the high-speed
decoder, for e.g., Ks that are prime numbers, or those that
This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the WCNC 2008 proceedings.
cannot be divided into useful windows sizes. In practice, a
designer can choose a limited set of block sizes for which CF
interleavers are defined. For information block sizes that are
not directly defined with a CF interleaver, traditional
shortening (e.g., zero padding) and puncturing techniques may
be applied. This has several advantages, including reduced
interleaver storage from the complexity perspective and better
parallelism from the decoding speed perspective. Moreover,
this approach has been shown to work well with either ARP or
QPP interleavers to cover the entire range of sizes supported by
WCDMA turbo code (40K5114).
The LTE Turbo code will support input block sizes between
40 and 6144 bits [2, 14]. The maximum information block size
of 6144 bits ensures that an IP packet (MTU=1500bytes over
Ethernet) is segmented into a maximum of two code blocks.
Therefore, a limited set of interleaver sizes (100~200), suitably
distributed between K
min
=40 and K
max
=6144 is desired. In this
set, CF interleavers can be designed and tested rigorously based
on preferred criteria, such as i) limiting the fraction of filler bits
(or zero-padding), ii) storage, and iii) achievable parallelism
orders, etc.
Considering the above criteria, the set of interleaver sizes K
may be defined such that each interleaver has the following
factorization.

, 2 f K
p
=
(7)
where p and f are suitably defined parameters. 2
p

denotes the
step size for a set of continuous f.

With (7), the interleaver sizes
can be selected such that they are distributed approximately
uniformly in logarithmic domain. Thus, the maximum fraction
of filler bits can be adjusted by appropriately tuning p and f.
Since (7) shows the factorization of every block size in the set,
it basically characterizes the parallelism supported by each
interleaver size (for both ARP and QPP).

B. Interleaver Parameters
The ARP and QPP interleavers are both suitable for LTE
turbo coding as they have many similarities - low-complexity
implementation while allowing flexible parallelism orders for
each block size. For LTE, the following set of 188 interleaver
sizes covering information block sizes between 40 and 6144
bits was standardized [2].

< +
< +
< +
+
=
64 0 , 64 2048
32 0 , 32 1024
32 0 , 16 512
59 0 , 8 40
f f
f f
f f
f f
K
(8)
For the ARP interleaver, the cycle length C is chosen to be
4 for K<1024, and C = 8 for K1024. A larger cycle length C
leads to better minimum distance and hence better
performance [7]. Storage is reduced via indexing method; for
each interleaver, the dither vectors are chosen from a set of pre-
defined dither vector tables and . The indices a and b (for
each block size) index into and tables, where 0a<2,
0b<2C. This method substantially reduces the ARP
interleaver storage as only P
0
(8 bits), index a (1 bit) and b (3-4
bits) are stored per interleaver.
In this paper, for cycle length C=4, the following dither
vector set is used (see [19, 21] for a complete design).

(
(
(
(
(
(
(
(
(
(
(

=
(

=
12 8 4 0
24 20 8 0
24 16 12 0
4 24 12 0
4 8 16 0
12 8 24 0
8 24 12 0
8 12 4 0
,
0 4 4 0
4 4 0 0


For the QPP design, two integers per block size (i.e., f
1
and
f
2
) are sufficient, and these parameters are chosen such that the
inverse polynomial has a small degree.
Table 1 shows some selected ARP and QPP interleaver
parameters. References [20, 21] contain an entire set of QPP
parameters and the ARP parameters proposed for LTE turbo
coding. These two proposals had suggested using 172
interleavers sizes. An alternate QPP proposal was presented
in [28]. The final harmonized LTE proposal contained a total of
188 interleaver sizes as described earlier. The final set of QPP
parameters selected for LTE is available in [2].
TABLE I. SELECTED ARP AND QPP PARAMETERS.
ARP QPP
K P
0
-index -index f
1
f
2

56 13 0 0 19 42
120 73 0 7 103 90
280 33 1 0 103 210
4352 179 0 2 477 408
5632 237 0 6 45 176
6144 253 1 12 263 480
C. Performance
Figures 2 and 3 compare the performance of proposed LTE
turbo code based on the ARP and QPP interleavers vs the
WCDMA turbo interleaver (referred to as Rel-6). All
simulations were performed using 3GPP trellis termination
with 12 tail bits. ARP and QPP interleavers were found up to
K=8192 although maximum K is limited to 6144 in the final
LTE specification. Although Rel-6 is only defined for K up to
5114, the performance of Rel-6 is extended to K values up to
8192 by applying the code block segmentation rule in [3]. In
the figures, the SNR required (E
b
/N
0
) to achieve different target
Frame error rates (FER) is plotted against the block size for the
172 interleaver sizes. The turbo coding rate is assumed to be
nominal 1/3 (no puncturing, 12 tail bits), and the turbo decoder
uses the max-log-map algorithm with eight full iterations. The
results indicate that both ARP and QPP interleaver designs
have a performance equivalent to or better than the WCDMA
turbo code.
This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the WCNC 2008 proceedings.
10
1
10
2
10
3
10
4
0.5
1
1.5
2
2.5
3
3.5
4
4.5
FER =10%
FER =1%
FER =0.1%
FER =0.01%
Information Block Size (bits)
E
b

/

N
0

R
e
q
u
i
r
e
d

(
d
B
)


Rel6
ARP

Figure 2. Proposed LTE Turbo code based on ARP Interleaver vs.
WCDMA turbo code.
Since the proposed LTE designs necessitate filler bit
insertion and puncturing to support all other information block
sizes that have no interleavers directly defined for, during the
standardization process a set of randomly chosen block sizes
was selected for simulations to ensure good performance of the
final design. It was found that both ARP and QPP interleavers
provide near-WCDMA performance even for the block sizes
that are handled via filler bit insertion and puncturing. For
testing with a random block size, filler bits (zeros) are pre-
padded, and the bits associated with the filler bits in the output
of the turbo coder are punctured out.
10
1
10
2
10
3
10
4
0.5
1
1.5
2
2.5
3
3.5
4
4.5
FER =10%
FER =1%
FER =0.1%
FER =0.01%
Information Block Size (bits)
E
b

/

N
0

R
e
q
u
i
r
e
d

(
d
B
)


Rel6
QPP

Figure 3. Proposed LTE Turbo code based on QPP Interleaver vs.
WCDMA turbo code.
D. Minimum Distance of LTE turbo code
Figure 4 compares the estimated minimum distances (d
min
)
of the LTE turbo code (188 QPP interleavers) with the true
minimum distances of the WCDMA turbo code at rate-1/3 (no
puncturing). The minimum distance estimates for the LTE
turbo code were obtained with a combination of the single and
double error impulse methods [7, 24], which was found to be
fairly quick but it does not sweep through all possible
codewords like the algorithm in [5]. The minimum distance
estimates are an upper bound, but when it compared fairly well
with some true minimum distance results found in
literature [23]. The true minimum distance results in Fig. 4 for
WCDMA turbo code were obtained from [5].
Figure 4 shows that the LTE turbo code outperforms the
WCDMA turbo code in terms of the achievable minimum
distances. While the maximum d
min
of the WCDMA turbo code
caps out at 28, the LTE turbo code provides a fairly larger d
min

than 28. The performance improvement is due to the
potentially increased d
min
to as much as 38 at small to medium
block sizes (e.g., K<1000 bits) and 50 and above at large sizes
(e.g., K>4500 bits). For the LTE turbo code, it was found that
for the block sizes that are multiples of 7, the QPP design has
slightly weaker minimum distance but still higher than that of
the WCDMA interleaver. Therefore, the performance of the
QPP interleavers shows consistency across the wide range of
block sizes and coding rates.
1000 2000 3000 4000 5000 6000
10
15
20
25
30
35
40
45
50
55
Information Block size (bits)
M
i
n
i
m
u
m

d
i
s
t
a
n
c
e


Rel6 Turbo Code
LTE Turbo Code

Figure 4. Comparison of estimated minimum distances of LTE turbo code
and true minimum distances of WCDMA turbo code.

VI. CONCLUSIONS

The paper discussed two attractive turbo interleaver candidates
(QPP and ARP) for Long Term Evolution (LTE) turbo coding.
These interleavers are perfectly suited for LTE as they
facilitate efficient high throughput turbo decoding required to
support the high date rates envisioned for LTE systems. Some
key features of these inteleavers include flexible parallelism,
efficient memory organization, and efficient support for
Radix-4 decoding. The QPP interleaver held a slight edge over
ARP due to its maximum contention-free property and its fully
algebraic structure; hence it was selected for LTE turbo
coding. Simulation results indicated that QPP and ARP
designs for LTE have a performance equivalent to or better
than the existing WCDMA turbo code.


This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the WCNC 2008 proceedings.
ACKNOWLEDGMENTS
We thank 3GPP RAN1 colleagues for the productive
discussions on the turbo interleaver. Special thanks to Dr.
Thomas Cheng of Ericsson for a constructive and fruitful
collaboration on the turbo interleaver selection for LTE. A.
Nimbalker would also like to thank Dr. Oscar Takeshita for
sharing his insights on the QPP interleaver. Finally, we deeply
appreciate the comments from the five anonymous reviewers.
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This full text paper was peer reviewed at the direction of IEEE Communications Society subject matter experts for publication in the WCNC 2008 proceedings.