IEEE POWER ELECTRONICS LETTERS, VOL. 2, NO.

4, DECEMBER 2004 125

Multilevel Dynamic Voltage Restorer

Poh Chiang Loh, Member, IEEE, D Mahinda Vilathgamuwa, Senior Member, IEEE, Seng Khai Tang, and
Hian Lih Long

Abstract—This letter presents the implementation and control

of a high voltage dynamic voltage restorer (HVDVR) for use in
power distribution network to compensate for sags in utility volt-
ages. The proposed HVDVR is implemented using a multilevel in-
verter topology with isolated dc energy storages, allowing the di-
rect connection of the HVDVR to the distribution network without
using a bulky and costly series injection transformer. A control al-
+
gorithm, incorporating P resonant and Posicast compensators, is
Fig. 1. System configuration with dynamic voltage restoration.
also presented for controlling the HVDVR with perfect reference
voltage tracking and effective damping of transient voltage oscilla-
tions at the instant of sag compensation. Finally, simulation results
are presented to verify the performance of the proposed multilevel
HVDVR.
Index Terms—Dynamic damping, dynamic voltage restorers
(DVR), multilevel inverters, Posicast control.

I. INTRODUCTION

F IG. 1 SHOWS the series connection of a dynamic voltage

restorer (DVR) between the utility source and loads,
through a coupling transformer. During normal operating
conditions, the DVR can be switched offline [1] or controlled
to compensate for any injected harmonic voltages in the utility
grid [2]. Upon the occurrence of a voltage sag (decrease in
), the DVR is commanded to inject a voltage such
that the magnitude of remains essentially
constant throughout the sag period. However, the phase of
can either be shifted or remain unchanged, depending on the
compensation techniques adopted.
Conventionally, the series voltage is injected through Fig. 2. Direct connection of multilevel HVDVR to utility grid.
a coupling transformer, Fig. 1, whose main functions are to
provide voltage boosting and electrical isolation The letter begins by analyzing different topological possibil-
between the phases. Usage of a transformer, however, has the ities for implementing the HVDVR with the main aim of de-
disadvantage of making the DVR bulky and costly, and other signing a reliable custom power conditioner. The letter next
disadvantages, as summarized in [1]. To overcome these dis- presents an open-loop control scheme with Posicast compen-
advantages, [1] has proposed the series/parallel connection of sator [3] incorporated for damping transient voltage oscillations
semiconductor switches, or H-bridges, to develop high voltage at the instant of voltage injection (an issue which has not been
DVR (HVDVR), which can be connected directly to the utility actively investigated for DVR). The Posicast-based open-loop
grid without a coupling transformer. This letter now extends the control is subsequently improved by adding a parallel multifeed-
concept to address issues that have not been discussed in [1]. back-loop control path to give two-degrees-of-freedom in con-
(Note that only the series connection of H-bridges is considered trol tuning. This feedback path uses the P resonant compen-
here, since the other option of series-connecting semiconductor sator [4] to force the steady-state voltage error to zero, hence,
switches usually require the use of complex snubber and gate enhancing the DVR load voltage regulation performance. All
driver circuitries, which can limit the speed of response of the principles presented have been verified in Matlab/Simulink sim-
HVDVR). ulation using a cascaded five-level and a binary seven-level in-
verter.
Manuscript received June 14, 2004; revised November 8, 2004. Recom-
mended by Associate Editor V. G. Agelidis.
II. TOPOLOGY OF MULTILEVEL HVDVR
The authors are with the Center for Advanced Power Electronics, School of Fig. 2 shows the single-phase representation of a HVDVR im-
Electrical and Electronic Engineering, Nanyang Technological University, Sin-
gapore (e-mail: pcloh@ieee.org). plemented using multiple series-connected H-bridges, each with
Digital Object Identifier 10.1109/LPEL.2004.840441 its own isolated dc energy storage. This inverter arrangement is
1540-7985/04$20.00 © 2004 IEEE
126
TABLE I
DC CAPACITOR VOLTAGES AND NUMBER OF OUTPUT VOLTAGE LEVELS OF DIFFERENT MULTILEVEL INVERTERS (N
commonly referred to as multilevel inverter in the power conver-
sion literature, and its overall output voltage is given by the
sum of voltages to ) of the H-bridges. Depending on
its switching state, the output of each H-bridge can assume the
three discrete dc voltage levels of , 0 V and . When
series-connected, the resultant output of the multilevel in-
verter can then switch among a greater number of voltage levels,
giving rise to an improved waveform quality. In addition, de-
pending on the dc capacitor potentials used, the total number of
voltage levels that can be assumed by varies, giving rise to
four types of multilevel inverters, namely, cascaded [5], binary
[6], [7], quasilinear [7] and tri-nary [7] inverters (the latter three
inverters are referred to as hybrid inverters in this letter). The dc
source potentials needed for implementing these inverters and
expressions for their total number of output voltage levels are
summarized in Table I.
Referring to Table I and Fig. 2, it is noted that the output
voltage of a hybrid inverter can assume a larger number of dc
voltage levels than a cascaded inverter with the same number of
series-connected H-bridges, by designing its upper H-bridges
to block higher dc voltages . Therefore, the
upper H-bridges of a hybrid inverter should be implemented
using high-voltage thyristor-based power devices [e.g., inte-
grated gate commutated thyristors (IGCTs)], while the lower
H-bridges should be implemented using fast-switching power
devices [e.g., insulated gate bipolar transistors (IGBTs)], as
indicated in Fig. 2 [6]. In addition, the switching frequen-
cies of the H-bridges should vary with the lowest H-bridge
(with dc link voltage of ) pulse-width modulated at a
high switching frequency, and while moving up the inverter
phase-leg in Fig. 2, each H-bridge should be switched at a
progressively slower switching frequency.
Naturally, hybrid inverters offer the attractive advantage
of significantly improving the inverter harmonic performance
using the same number of H-bridges as a cascaded inverter.
However, when considering cases of semiconductor failure,
hybrid inverters are less reliable (especially trinary inverter)
since a fault in the higher voltage H-bridge will significantly
limit the sag compensation ability of the HVDVR and also
increase the overall inverter harmonic content. With a greater
emphasis on reliability rather than harmonic performance, the
HVDVR studied in this letter is therefore implemented using
either a cascaded five-level inverter or a binary seven-level
inverter with two series-connected H-bridges.
III. OPEN-LOOP CONTROL OF MULTILEVEL HVDVR USING
POSICAST COMPENSATOR
To date, both open- and closed-loop control schemes [2], [8]
have been reported for use with a DVR. Most of these reported
IEEE POWER ELECTRONICS LETTERS, VOL. 2, NO. 4, DECEMBER 2004
= NUMBER OF H-BRIDGES)
Fig. 3. Open-loop control using Posicast compensator.
schemes however do not address the damping of transient
voltage oscillations that can occur at the start of DVR voltage
injection, as observed in [1], [2], [8]. As part of the development
of HVDVR, this section first proposes an open-loop control
algorithm with a Posicast compensator [3] integrated to achieve
improved transient damping. The presented Posicast-based
open-loop control is subsequently, extended to a closed-loop
algorithm in the next section.
As seen in Fig. 3, open-loop control involves subtracting the
source-side voltage of the HVDVR from a preset load-
side reference voltage , to give the desired sinusoidal voltage
to be injected by the inverter. Conventionally, is di-
rectly fed to a pulse-width modulator, which in turn drives the
inverter to inject the desired compensating voltage. A short-
coming of this method of control is its inability to damp transient
voltage oscillations at the start of HVDVR voltage injection.
To improve damping, Fig. 3 shows the inclusion of a half-cycle
Posicast compensator for conditioning , before feeding it to
the pulse-width modulator. Mathematically, the transfer func-
tion of a Posicast compensator can be expressed as
(1)
where and are the step response overshoot and damped
response period of .
An example showing the operating principle of Posicast com-
pensator is given in Fig. 4. The figure shows the Posicast com-
pensator taking in a unit step as input, and outputting an in-
termediate signal [second term in (1)] in addition to [first
term in (1)]. is a negative pulse whose height and width de-
pend on and , respectively. The impact of on the plant
step response can be analyzed by passing
both and through two identical second order plants 1
and 2, respectively, before adding up their outputs to give the
overall plant response. Observing the third and fourth traces of
Fig. 4, it is noted that by tuning and , oscillations of the
two plant outputs and can be made 180 -out-of-phase
with the same oscillating amplitude. Summation of these two
signals then produces a well-damped resultant plant output ,
LOH et al.: MULTILEVEL DYNAMIC VOLTAGE RESTORER
Fig. 4. Posicast compensator intermediate waveforms. Top to bottom:
v ;v ;v ;v , and v .
revealing the dynamic damping performance of Posicast com-
pensator.
Alternatively, by analyzing the frequency response in Fig. 5,
Posicast compensator can be viewed as a multiple-notch filter
with an infinite number of zeros spaced at odd multiples of the
damped natural frequency. By tuning and , the first pair of
zeros (first notch) can be made to cancel the dominant pair of
poles of the lightly damped plant, resulting in a less oscillatory
plant output. Note however that Posicast pole cancellation is not
the same as pole cancellation using model inversion. Posicast
has limited high frequency gain (see Fig. 5) and therefore, is
less sensitive to noise, as compared to model inversion, which
has increasing gain at high frequency.
IV. CLOSED-LOOP CONTROL OF MULTILEVEL HVDVR USING
P RESONANT AND POSICAST COMPENSATORS
A. Principles of Closed-Loop Control Algorithm
As noted in Section III, Posicast functions by pole can-
cellation through the proper tuning of its control parameters.
It is therefore very sensitive to inaccurate knowledge of the
plant damped resonant frequency, which is common to feedfor-
ward techniques that rely on dynamic cancellation. To reduce
parametric and load sensitivities of the controller, this section
improves the open-loop control scheme in Fig. 3 by adding a
parallel multiloop feedback path to the original feedforward
path, as shown in Fig. 6. Inclusion of both a feedforward
and a feedback path is commonly referred to as two-de-
grees-of-freedom (2-DOF) control in the literature [9]. As the
name implies, 2-DOF control, provides a degree of freedom for
ensuring fast dynamic tracking through the feedforward path
127
Fig. 5. Bode plots of Posicast compensator given by (1).
and a second degree of freedom for independent tuning of the
system disturbance compensation through the feedback path,
and thus gives the performance merits of both feedforward and
feedback controls.
As shown in Fig. 6, the feedback path consists of an outer
voltage loop and a fast inner current loop. To eliminate the
steady-state voltage tracking error , a computation-
ally less intensive P resonant compensator is added to the outer
voltage loop. The ideal P resonant compensator can be
mathematically derived by transforming an ideal synchronous
frame PI compensator to the stationary frame [4], and is ex-
pressed as
(2)
where and are gain constants and rad/s)
is the compensator resonant frequency.
Theoretically, the resonant compensator compensates by in-
troducing an infinite gain at the resonant frequency of 50 Hz (see
Fig. 7) to force the steady-state voltage error to zero. The ideal
resonant compensator however acts like a network with an in-
finite quality factor, which is not realizable in practice. A more
practical (nonideal) compensator is therefore used here, and is
expressed as [4]
(3)
where is the compensator cutoff frequency (= 1rad/s in this
application). Plotting the frequency response of (3) in Fig. 8, it is
noted that the resonant peak now has a finite gain of 40 dB which
is satisfactorily high for eliminating the voltage tracking error.
In addition, a wider bandwidth is observed around the resonant
frequency, which minimizes the sensitivity of the compensator
to slight utility frequency variations. At other harmonic frequen-
cies, the response of the nonideal compensator is comparable to
that of the ideal compensator.
The output of the outer voltage P+resonant compensator
serves as reference current signal which is compared with
the measured capacitor current . The current error
128 IEEE POWER ELECTRONICS LETTERS, VOL. 2, NO. 4, DECEMBER 2004

Fig. 6. +
Multiloop control using P resonant and Posicast compensators.

Fig. 7. +
Magnitude response of ideal P resonant compensator using (2) with +
Fig. 8. Magnitude response of nonideal P resonant compensator using (3)
K =1 ;K = 100 , and w = 314 rad/s. with K =1
;K = 100
;w = 314
rad/s and w =1
rad/s.

is then fed to a proportional compensator whose output, when

added to the feedforward signal , gives the desired
voltage to be injected by the HVDVR (only a proportional
compensator is used here since the inner current loop does
not influence the tracking accuracy of the outer voltage loop).
Indeed, to improve the system dynamic damping, is con-
ditioned by the Posicast compensator before being fed to the
inverter pulse-width modulator.

B. Design of P Resonant Outer Voltage Compensator

With the chosen voltage and current compensators described
above, and representing the inner current loop as a constant gain
block (due to its dynamically fast response), the closed-loop
transfer function of the control algorithm in Fig. 6 is derived,
as shown in the equation at the bottom of the page.
Note that for the frequency response analysis presented here,
the Posicast expression in (1) is not included in the transfer
function of (4) since it behaves as a unity gain block in the
steady-state. The corresponding bode plot of (4) is then shown
in Fig. 9 with and chosen as 0.1, 100, 314 rad/s
and 1 rad/s respectively (other system parameters are listed in
Section VI). This figure clearly shows the controller good per-
formance with a unity gain at the fundamental frequency, and
its immunity to high frequency distortion (fast gain roll-off as
frequency increases).
V. PULSEWIDTH MODULATION TECHNIQUE
To date, two carrier-based pulsewidth modulation (PWM)
techniques have been reported for modulating multilevel in-
verters, namely the disposition and phase-shifted carrier tech-
niques [5], [6]. Both techniques are well-established and there-
Fig. 9. Closed-loop Bode plot of multiloop voltage control with K =
1 ;K = 100 ;w = 314 rad/s, and w =1 rad/s.
fore, are not described in this letter. For HVDVR application,
preference is given to the use of phase-shifted carrier PWM for
modulating the cascaded five-level and binary seven-level in-
verters because it ensures more uniform switch utilization under
all modulation conditions, which is important for HVDVR de-
signed to compensate for grid harmonic voltages during normal
(low modulation) operating conditions. (Switch utilization of a
multilevel inverter is relatively poor under low modulation con-
dition when disposition PWM technique is used [5].)
VI. SIMULATION RESULTS
The performance of the Posicast-controlled HVDVR has
been verified in simulation for a cascaded five-level and

(4)
LOH et al.: MULTILEVEL DYNAMIC VOLTAGE RESTORER 129

Fig. 10. Cascaded five-level HVDVR controlled using multi-loop feedback Fig. 12. Cascaded five-level HVDVR switched waveforms. Top to bottom:
and feedforward control (without Posicast). Top to bottom: v ; v , and v
upper H-bridge voltage, lower H-bridge voltage and resultant inverter voltage
(see Fig. 1: System configuration with dynamic voltage restoration. Fig. 2). (see Fig. 1: System configuration with dynamic voltage restoration. Fig. 2).

Fig. 13. Binary seven-level HVDVR switched waveforms. Top to bottom:

Fig. 11. Cascaded five-level HVDVR controlled using multi-loop feedback upper H-bridge voltage, lower H-bridge voltage and resultant inverter voltage
and feedforward control (with Posicast). Top to bottom: v ; v , and v (see
(see Fig. 1: System configuration with dynamic voltage restoration. Fig. 2).
Fig. 1: System configuration with dynamic voltage restoration. Fig. 2).

cascaded inverter, revealing the equal distribution of three-level

a binary seven-level inverter using Matlab/Simulink. The
switching among the H-bridges and the five-level switching of
simulated circuit layout is as given in Fig. 2 with only
the cascaded inverter.
two series-connected H-bridges. The HVDVR parameters
Results ( , and ) for the binary seven-level
used are given as: mH,
HVDVR are similar to those in Fig. 10 and Fig. 11, and are
for the cascaded
therefore not repeated here. However, to show the differences
inverter and for the binary
in switching for the binary inverter, the switching waveforms
inverter.
of the two H-bridges and binary inverter are shown in Fig. 13.
Fig. 10 shows the oscillatory results when the cascaded
The figure obviously shows one H-bridge switching under
HVDVR is controlled using the 2-DOF control scheme in
fundamental quasisquare modulation while the other H-bridge
Fig. 6 without the Posicast compensator. As shown, at the in-
is pulse-width modulated at a high frequency. As anticipated,
stant of voltage sag ( ms), the outer voltage P resonant
the resulting binary inverter appears to switch between seven
compensator forces the HVDVR to inject a series voltage to
voltage levels, giving a better (unfiltered) harmonic perfor-
keep the load voltage constant with nearly zero steady-state
mance as compared to the cascaded five-level inverter using the
error, even when the source-side voltage drops by 40%.
same number of H-bridges.
Fig. 11 shows the corresponding waveforms when the Posicast
compensator is added to the 2-DOF control scheme. This
figure clearly shows the improved dynamic damping that is VII. CONCLUSION.
achieved with the use of Posicast compensator. Fig. 12 shows This letter presents the implementation and control of a
the switching waveforms of the two H-bridges and overall HVDVR for compensating utility voltage sags. The HVDVR is
130
TABLE II
SUMMARY OF PERFORMANCE FEATURES OF HVDVR CONTROLLED USING DIFFERENT CONTROL STRATEGIES
implemented using the cascaded multilevel inverter topology
with the advantages of improved reliability and direct connec-
tion of the HVDVR to the distribution network without the use
of a bulky and costly series injection transformer. Other iso-
lated inverter topologies can also be used for the same pur-
pose as demonstrated using the binary inverter, but the resulting
HVDVR can be less reliable under semiconductor failure condi-
tions. The cascaded HVDVR is controlled using a 2-DOF con-
trol scheme incorporating both P resonant and Posicast com-
pensators, to achieve perfect reference voltage tracking and ef-
fective damping of transient voltage oscillations. The perfor-
mance of the HVDVR, controlled using different control strate-
gies, has been tested extensively in Matlab/Simulink simulation
with its major performance features summarized in Table II.
REFERENCES
[1] B. H. Li, S. S. Choi, and D. M. Vilathgamuwa, “Transformerless dy-
namic voltage restorer,” Proc. Instit. Elec. Eng. Gener. Transm. Distrib.,
vol. 149, pp. 263–273, May 2002.
IEEE POWER ELECTRONICS LETTERS, VOL. 2, NO. 4, DECEMBER 2004
[2] M. J. Newman, D. G. Holmes, J. G. Nielsen, and F. Blaabjerg, “A dy-
namic voltage restorer (DVR) with selective harmonic compensation at
medium voltage level,” in Conf. Rec. IEEE-IAS Annu. Meet., 2003, pp.
1228–1235.
[3] J. Y. Hung, “Feedback control with Posicast,” IEEE Trans. Ind. Elec-
tron., vol. 50, pp. 94–99, Feb. 2003.
[4] D. N. Zmood, D. G. Holmes, and G. Bode, “Frequency domain analysis
of three phase linear current regulators,” IEEE Trans. Ind. Applicat., vol.
37, pp. 601–610, Mar./Apr. 2001.
[5] P. C. Loh, D. G. Holmes, Y. Fukuta, and T. A. Lipo, “Reduced common
mode modulation strategies for cascaded multilevel inverters,” IEEE
Trans. Ind. Applicat., vol. 39, pp. 1386–1395, Sept./Oct. 2003.
[6] M. D. Manjrekar, P. K. Steimer, and T. A. Lipo, “Hybrid multilevel
power conversion system: A competitive solution for high-power ap-
plications,” IEEE Trans. Ind. Applicat., vol. 36, pp. 834–841, May/Jun.
2000.
[7] Y. S. Lai and F. S. Shyu, “Topology for hybrid multilevel inverter,” in
IEE Proc.—Electric Power Applicat., vol. 149, Nov. 2002, pp. 449–458.
[8] J. G. Nielsen, M. Newman, H. Nielsen, and F. Blaabjerg, “Control and
testing of a dynamic voltage restorer (DVR) at medium voltage level,”
IEEE Trans. Power Electron., vol. 19, pp. 806–813, May 2004.
[9] N. Hur, K. Nam, and S. Won, “A two-degrees-of-freedom current control
scheme for deadtime compensation,” IEEE Trans. Ind. Electron., vol. 47,
pp. 557–564, June 2000.