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ICS9LPRS365
Advance Information
Pin Define
Pin Configuration
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SCLK SDATA REF0/FSLC/TEST_SEL VDDREF X1 X2 GNDREF FSLB/TEST_MODE CK_PWRGD/PD# VDDCPU CPUT0 CPUC0 GNDCPU CPUT1_F CPUC1_F VDDCPU_IO NC CPUT2_ITP/SRCT8 CPUC2_ITP/SRCC8 VDDSRC_IO SRCT7/CR#_F SRCC7/CR#_E GNDSRC SRCT6 SRCC6 VDDSRC PCI_STOP# CPU_STOP# VDDSRC_IO SRCC10 SRCT10 SRCT11/CR#_H
Top View
9LPRS365
FSLB B0b6 0 0 1 1 0 0 1 1
FS LA B0b5 0 1 0 1 0 1 0 1
SRC MHz
PCI MHz
REF MHz
USB MHz
DOT MHz
100.00
33.33
14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
121807/11/06
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
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Pin Description
PIN # PIN NAME TYPE DESCRIPTION 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the logic value on this pin determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the function talbe for the pin17 and pin18. Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V. Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs. 1.05V to 3.3V from external power supply True clock of SRC or DOT96. The power-up default function depends on 27_Select,1= SRC0 0=DOT96 True clock of SRC or DOT96. The power-up default function depends on 27_Select,1= SRC0 0=DOT96 Ground pin for the DOT96 clocks. Power supply for SRC / SE1 and SE2 clocks, 3.3V nominal.
PCI0/CR#_A
I/O
VDDPCI
PWR
PCI1/CR#_B
I/O
PCI2/TME
I/O
5 6
PCI3 PCI4/27_Select
OUT I/O
PCI_F5/ITP_EN
I/O
8 9 10 11 12 13 14 15 16
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18 19 20 21 22 23
24
SRCT3/CR#_C
I/O
25
SRCC3/CR#_D
I/O
26 27 28 29 30 31
32
SRCC11/CR#_G
I/O
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33
SRCT11/CR#_H
I/O
34 35 36 37 38 39 40 41 42
43
SRCC7/CR#_E
I/O
44
SRCT7/CR#_F
I/O
45
VDDSRC_IO
PWR
46
CPUC2_ITP/SRCC8
OUT
47
CPUT2_ITP/SRCT8
OUT
48
NC
N/A
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Pin Configuration
CPUC2_ITP/SRCC8
FSLB/TEST_MODE
CPUT2_ITP/SRCT8
CK_PWRGD/PD#
SRCC7/CR#_E
SRCT7/CR#_F
VDDCPU_IO
VDDSRC_IO
CPUC1_F
CPUT1_F
GNDCPU
61
60 59 58
57
56 55 54
53
52 51 50
SCLK 7 PCI0/CR#_A 8 VDDPCI 9 PCI1/CR#_B 10 PCI2/TME 11 PCI3 12 PCI4/27_Select 13 PCI_F5/ITP_EN 14 GNDPCI 15 VDD48 16 17 18 19 VDD96_IO GND48 USB_48MHz/FSLA 20 SRCT0/DOTT_96
GNDSRC 42 SRCC10 41 SRCT10 40 SRCT11/CR#_H 39 SRCC11/CR#_G 38 SRCC9 37 SRCT9 36 GNDSRC 35 SRCC4 34 SRCT4 33 VDDSRC_IO 32 SRCC3/CR#_D
VDDCPU
CPUC0
CPUT0
9LPRS365
24 27MHz_NonSS/SRCT1/SE1
NC
28 SRCT2/SATAT
64-pin MLF
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Pin Description
PIN #
1 2 3 4 5 6 7
GNDREF X2 X1 VDDREF REF0/FSLC/TEST_SEL SDATA SCLK
PIN NAME
TYPE
PWR OUT IN PWR I/O I/O IN
DESCRIPTION
Ground pin for crystal oscillator circuit Crystal output, nominally 14.318MHz. Crystal input, Nominally 14.318MHz. Power pin for the REF outputs, 3.3V nominal. 3.3V 14.318MHz reference clock/3.3V tolerant low threshold input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values/ TEST_SEL: 3-level latched input to enable test mode. Refer to Test Clarification Table. Data pin for SMBus circuitry, 5V tolerant. Clock pin of SMBus circuitry, 5V tolerant. 3.3V PCI clock output or Clock Request control A for either SRC0 or SRC2 pair The power-up default is PCI0 output, but this pin may also be used as a Clock Request control of SRC pair 0 or SRC pair 2 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 0 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 2 or pair 0 using the CR#_A_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 7 0 = PCI0 enabled (default) 1= CR#_A enabled. Byte 5, bit 6 controls whether CR#_A controls SRC0 or SRC2 pair Byte 5, bit 6 0 = CR#_A controls SRC0 pair (default), 1= CR#_A controls SRC2 pair Power supply pin for the PCI outputs, 3.3V nominal 3.3V PCI clock output/Clock Request control B for either SRC1 or SRC4 pair The power-up default is PCI1 output, but this pin may also be used as a Clock Request control of SRC pair 1 or SRC pair 4 via SMBus. Before configuring this pin as a Clock Request Pin, the PCI output must first be disabled in byte 2, bit 1 of SMBus address space . After the PCI output is disabled (high-Z), the pin can then be set to serve as a Clock Request pin for either SRC pair 1 or pair 4 using the CR#_B_EN bit located in byte 5 of SMBUs address space. Byte 5, bit 5 0 = PCI1 enabled (default) 1= CR#_B enabled. Byte 5, bit 6 controls whether CR#_B controls SRC1 or SRC4 pair Byte 5, bit 4 0 = CR#_B controls SRC1 pair (default) 1= CR#_B controls SRC4 pair 3.3V PCI clock output / Trusted Mode Enable (TME) Latched Input. This pin is sampled on power-up as follows 0 = Overclocking of CPU and SRC Allowed 1 = Overclocking of CPU and SRC NOT allowed After being sampled on power-up, this pin becomes a 3.3V PCI Output 3.3V PCI clock output. 3.3V PCI clock output / 27MH mode select for pin17, 18 strap. On powerup, the logic value on this pin determines the power-up default of DOT_96/SRC0 and 27MHz/SRC1 output and the function talbe for the pin17 and pin18. Free running PCI clock output and ITP/SRC8 enable strap. This output is not affected by the state of the PCI_STOP# pin. On powerup, the state of this pin determines whether pins 38 and 39 are an ITP or SRC pair. 0 =SRC8/SRC8# 1 = ITP/ITP# Ground for PCI clocks. Power supply for USB clock, nominal 3.3V.
PCI0/CR#_A
I/O
VDDPCI
PWR
10
PCI1/CR#_B
I/O
11
PCI2/TME
I/O
12 13
PCI3 PCI4/27_Select
OUT I/O
14
PCI_F5/ITP_EN
I/O
15 16
GNDPCI VDD48
PWR PWR
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TYPE
I/O PWR PWR OUT
DESCRIPTION
Fixed 48MHz USB clock output. 3.3V./ 3.3V tolerant input for CPU frequency selection. Refer to input electrical characteristics for Vil_FS and Vih_FS values. Ground pin for the 48MHz outputs.
21 22 23 24 25 26 27 28 29 30
OUT PWR PWR OUT OUT PWR PWR OUT OUT PWR
27MHz_NonSS/SRCT1/SE1 27MHz_SS/SRCC1/SE2
GND VDDPLL3_IO SRCT2/SATAT SRCC2/SATAC GNDSRC
31
SRCT3/CR#_C
I/O
32
SRCC3/CR#_D
I/O
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TYPE
PWR I/O I/O PWR OUT OUT
39
SRCC11/CR#_G
I/O
40
SRCT11/CR#_H
I/O
41 42 43 44 45 46 47 48
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PIN NAME
TYPE
PWR
DESCRIPTION
Ground for SRC clocks SRC7 complement or Clock Request control E for SRC6 pair The power-up default is SRC7#, but this pin may also be used as a Clock Request control of SRC6 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space . After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC6 pair using byte 6, bit 7 of SMBus configuration space Byte 6, bit 7 0 = SRC7# enabled (default) 1= CR#_E controls SRC6. SRC7 true or Clock Request control 8 for SRC8 pair The power-up default is SRC7, but this pin may also be used as a Clock Request control of SRC8 via SMBus. Before configuring this pin as a Clock Request Pin, the SRC7 output pair must first be disabled in byte 3, bit 3 of SMBus configuration space After the SRC output is disabled (high-Z), the pin can then be set to serve as a Clock Request for SRC8 pair using byte 6, bit 6 of SMBus configuration space Byte 6, bit 6 0 = SRC7# enabled (default) 1 = CR#_F controls SRC8.
50
SRCC7/CR#_E
I/O
51
SRCT7/CR#_F
I/O
52
VDDSRC_IO
PWR
53
CPUC2_ITP/SRCC8
OUT
54
CPUT2_ITP/SRCT8
OUT
55 56 57 58 59 60 61 62 63 64
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ICS9LPRS365
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General Description
ICS9LPRS365 follows Intel CK505 Yellow Cover specification. This clock synthesizer provides a single chip solution for next generation P4 Intel processors and Intel chipsets. ICS9LPRS365 is driven with a 14.318MHz crystal. It also provides a tight ppm accuracy output for Serial ATA and PCI-Express support.
Block Diagram
X1 R EF X2
REF CPU(1:0)
OSC
SRC8/CPU_ITP
CPU
CPU PLL1 SS
SRC
SR C _M A IN
SRC(11-9,4:3, 7:6)
PLL3 SS
PCI33MHz
SRC2/SATA FSLA CKPWRGD/PD# PCI_STOP# CPU_STOP# CR#_(A:H) 27_Select TME, ITP_EN FSLC/TESTSEL FSLB/TESTMODE 27MHz/SRC1/SE(2:1)
Control Logic
Differential Output
SE Outputs
27MHz_NonSS
SRC0/DOT96
PLL2 Non-SS
Power Groups
Pin Number VDD GND 49 52 55 52 26, 36, 45 23, 29, 42 39 23, 29, 42 20 19 16 19 12 11 9 11 61 58 2 8
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Description CPUCLK Low power outputs Master Clock, Analog Low power outputs SRCCLK PLL 1 Low power outputs PLL3/SE PLL 3 DOT 96Mhz Low power outputs USB 48 Xtal, REF PCICLK
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CONDITIONS Supply Voltage Low-Voltage Differential I/O Supply Single-ended inputs Single-ended inputs VIN = VDD , VIN = GND Inputs with pull or pull down resistors VIN = VDD , VIN = GND Single-ended outputs, IOH = -1mA Single-ended outputs, IOL = 1 mA Differential Outputs, IOH = TBD mA Differential Outputs, IOL = TBD mA 3.3 V +/-5% 3.3 V +/-5% 3.3 V +/-5% 3.3V supply, PLL3 off 3.3V supply, PLL3 Differential Out 3.3V supply, PLL3 Single-ended Out 0.8V supply, Differential IO current, all outputs enabled 3.3V supply, Power Down Mode 0.8V IO supply, Power Down Mode 3.3V supply, iAMT Mode 0.8V IO supply, iAMTMode VDD = 3.3 V Logic Inputs Output pin capacitance X1 & X2 pins Triangular Modulation
TYPICAL
UNITS C V V V V uA uA V
Notes 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1
0.4 0.7 0.9 0.4 2 0.7 VSS - 0.3 95 106 101 25 32 31 0.23 113 31 VDD + 0.3 1.5 0.35 250 250 250 80 1 0.1 TBD 0.8 14.318 7 1.5 5 6 5 30 33
V V V V V V mA mA mA mA mA mA mA mA MHz nH pF pF pF kHz
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CONDITIONS see Tperiod min-max values 27.000MHz output nominal IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Rising/Falling edge rate VOL = 0.4 V, VOH = 2.4 V VOH = 2.4 V, VOL = 0.4 V VT = 1.5 V Long Term (10us)
TYP
MAX 50 15 37.0376
UNITS ppm
VT = 1.5 V
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ICS9LPRS365
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SYMBOL ppm Tperiod Tabs VOH VOL IOH IOL tSLR tFLR dt1 tjcyc-cyc
CONDITIONS see Tperiod min-max values 48.00MHz output nominal 48.00MHz output nominal IOH = -1 mA IOL = 1 mA V OH @MIN = 1.0 V VOH@MAX = 3.135 V VOL @ MIN = 1.95 V VOL @ MAX = 0.4 V Measured from 0.8 to 2.0 V Measured from 2.0 to 0.8 V VT = 1.5 V VT = 1.5 V
NOTES 1,2 2 2 1 1 1 1 1 1 1 1 1 1
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Guaranteed by design and characterization, not 100% tested in production. Slew rate measured through Vswing centered around differential zero Vxabs is defined as the voltage where CLK = CLK#
Only applies to the differential rising edge (CLK rising and CLK# falling) Defined as the total variation of all crossing voltages of CLK rising and CLK# falling. Matching applies to rising edge rate of CLK and falling edge of CLK#. It is measured using a +/-75mV window centered on the average cross point where CLK meets CLK#. The average cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate calculations.
6 7 8 9
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz Operation under these conditions is neither implied, nor guaranteed. Maximum input voltage is not to exceed maximum VDD See PCI Clock-to-Clock Delay Figure
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FSLB B0b6 0 0 1 1 0 0 1 1
FS LA B0b5 0 1 0 1 0 1 0 1
SRC MHz
PCI MHz
REF MHz
USB MHz
DOT MHz
100.00
33.33
14.318
48.00
96.00
Reserved
1. FSLA and FSLB are low-threshold inputs.Please see VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values. Also refer to the Test Clarification Table. 2. FSLC is a three-level input. Please see the VIL_FS and VIH_FS specifications in the Input/Supply/Common Output Parameters Table for correct values.
B1b4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
B1b3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
B1b2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
B1b1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Pin 17
MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 24.576 98.304 27.000 25.000 N/A N/A N/A N/A
Pin 18
MHz 100.00 100.00 100.00 100.00 100.00 100.00 N/A 24.576 98.304 98.304 27.000 25.000 N/A N/A N/A N/A
Spread % PLL 3 disabled -0.50% -1% -1.50% (+/-0.25) (+/-0.5) N/A None None None None None N/A N/A N/A N/A
Comment
SRCCLK1 from SRC_MAIN Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 Only SRCCLK1 from PLL3 N/A 24.576Mhz on SE1 and SE2 24.576Mhz on SE1, 98.304Mhz on SE2 98.304Mhz on SE1 and SE2 27Mhz on SE1 and SE2 25Mhz on SE1 and SE2 N/A N/A N/A
-0.5%
-1% -1.5% -2% -0.75% -1.25%
-1.75%
+-0.5% +-0.75%
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ICS9LPRS365
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Table 3: IO_Vout select table B9b2 B9b1 B9b0 IO_Vout 0.3V 0 0 0 0.4V 0 0 1 0.5V 0 1 0 0.6V 0 1 1 0.7V 1 0 0 0.8V 1 0 1 0.9V 1 1 0 1.0V 1 1 1
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ICS9LPRS365
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General SMBus serial interface information for the ICS9LPRS365 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) sends the data byte count = X ICS clock will acknowledge Controller (host) starts sending Byte N through Byte N + X -1 (see Note 2) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends the begining byte location = N ICS clock will acknowledge Controller (host) will send a separate start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the data byte count = X ICS clock sends Byte N + X -1 ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controllor (host) will send a not acknowledge bit Controller (host) will send a stop bit
ACK
ACK
ACK
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PCI_SEL
Note 1 : When 27_Select pin = 0, B1b7 PWO = 1, , when 27_Select pin = 1, PWO = 0
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Free Running
SRC_STP_CRTL
RW
Free Running
Vendor specific
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Test Mode Entry Allows entry into test mode, ignores FSB/TestMode IO_VOUT2 IO_VOUT1 IO_VOUT0 IO Output Voltage Select (Most Significant Bit) IO Output Voltage Select IO Output Voltage Select (Least Significant Bit)
Enables control of CPU1 with CPU_STOP# Enables control of CPU 0 with CPU_STOP#
Stoppable Stoppable
Strength control
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ICS9LPRS365
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The decimal representation of N Div (9:0) +8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table.
These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values.
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These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values.
The decimal representation of N Div (9:0) +8 is equal to VCO divider value. Default at power up = latch-in or Byte 0 Rom table.
These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values.
These Spread Spectrum bits will program the spread pecentage. Contact ICS for the correct values.
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ICS9LPRS365
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HW
SW
REF/N or HI-Z B9b4
Power-up w/ TEST_SEL = 1 to enter test mode Cycle power to disable test mode FSLC./TEST_SEL -->3-level latched input If power-up w/ V>2.0V then use TEST_SEL If power-up w/ V<2.0V then use FSLC FSLB/TEST_MODE -->low Vth input TEST_MODE is a real time input If TEST_SEL HW pin is 0 during power-up, test mode can be invoked through B9b3. If test mode is invoked by B9b3, only B9b4 is used to select HI-Z or REF/N FSLB/TEST_Mode pin is not used. Cycle power to disable test mode, one shot control
X 0 0 1
0 X X X
0 0 1 0
>2.0V
REF/N
<2.0V
HI-Z
<2.0V
REF/N
B9b3: 1= ENTER TEST MODE, Default = 0 (NORMAL OPERATION) B9b4: 1= REF/N, Default = 0 (HI-Z)
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ICS9LPRS365
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Dimension
P64
P33
Top View
INDEX AREA E1 E
1 2 D
P32
6.10 mm. Body, 0.50 mm. Pitch TSSOP (240 mil) (20 mil) In Millimeters In Inches COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX -1.20 -.047 0.05 0.15 .002 .006 0.80 1.05 .032 .041 0.17 0.27 .007 .011 0.09 0.20 .0035 .008 SEE VARIATIONS SEE VARIATIONS 8.10 BASIC 0.319 BASIC 6.00 6.20 .236 .244 0.50 BASIC 0.020 BASIC 0.45 0.75 .018 .030 SEE VARIATIONS SEE VARIATIONS 0 8 0 8 -0.10 -.004
A2 A1
-Ce
b SEATING PLANE
N 64
aaa C
10-0039
Ordering Information
Vendor P/N
ICS9LPRS365 y GLFT
Example:
ICS XXXX y G LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type G = TSSOP Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device
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THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE
DIMENSIONS SYMBOL A A1 A3 b e
DIMENSIONS MIN. MAX. 0.8 1.0 0 0.05 0.25 Reference 0.18 0.3 0.50 BASIC SYMBOL N ND NE D x E BASIC D2 MIN. / MAX. E2 MIN. / MAX. L MIN. / MAX. ICS 64L TOLERANCE 64 16 16 9.00 x 9.00 7.00 / 7.25 7.00 / 7.25 0.30 /0 .50
Ordering Information
ICS9LPRS365y KLFT
Example:
ICS XXXX y K LF T
Designation for tape and reel packaging Lead Free, RoHS Compliant Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type (consists of 3 to 7 digit numbers) Prefix ICS, AV = Standard Device
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ICS9LPRS365
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Systems, Inc.
Revision History
Rev. 0.1 0.2 Issue Date 4/5/2006 7/11/2006 Description Initial Release Updated Electrical Characteristics. Page # 12
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