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US 8,527,741 B2
*Sep. 3, 2013
(54)
SYSTEM FOR SELECTIVELY SYNCHRONIZING HIGH-ASSURANCE SOFTWARE TASKS ON MULTIPLE PROCESSORS AT A SOFTWARE ROUTINE LEVEL
References Cited
U.S. PATENT DOCUMENTS
5,249,188 A * 9/1993 McDonald .................... .. 714/53
5,255,367 A
(75)
(Continued)
FOREIGN PATENT DOCUMENTS
EP GB W0 W0 0674262 2399426 WO 2007/006011 WO 2007/006013 A A A2 A2 9/1995 9/2004 1/2007 1/2007
OTHER PUBLICATIONS
Deconnick, Geert et al., The EFTOS Approach to dependability in embedded Supercomputing, IEEE Transactions on Reality, Mar. 2002, vol. 51, Issue 1, p. 76-90, Posted online Sep. 7, 2002 at:
http://www.esatkuleuven.be/electa/publications/fullteXts/pubi884. pdf.
(Continued)
Primary Examiner * David J Huisman
US 2007/0113224 A1
(57)
ABSTRACT
A task matching circuit for synchronizing software on a plu rality of processors is disclosed. The task matching circuit includes ?rst and second inputs, an analysis sub-circuit, and an output. The ?rst input is from a ?rst processor con?gured to receive a ?rst software routine identi?er. The second input
is from a second processor con?gured to receive a second
(200601)
software routine identi?er. The analysis sub-circuit deter mines if the ?rst software routine identi?er corresponds with the second software routine identi?er. The output is coupled
to at least one of the ?rst or second processors and indicates when the ?rst and second software routine identi?ers do not correspond One Ofthe ?rst and Second processors is delayed until the ?rst and second software routine identi?ers corre Spend
G06F 11/14 (200601) US Cl USPC ......................................... .. 712/220; 712/229 Field of Classi?cation Search USPC ............. .. 712/15, 43, 220, 227, 229; 714/11,
7 1 4/ 1 2, 797
r144
Status
Lights
01ml f120-1
Processor
First
(1244
1004
,A/
Synchromzer
(112
r108
> 35?:
M12255,
1 f
F132 313311?
s o t
120-2
124_2
lError
pfjggsnsir
Synchronizer
US 8,527,741 B2
Page 2
(56) References Cited
U.S. PATENT DOCUMENTS
5,751,932 A * 5/1998 Horstet a1. ................... .. 714/12
5,845,060 A *
5,896,523 A * 6,065,135 A *
12/1998 Vrbaetal. ..
4/1999 5/2000
714/12
Extended Search Report mailed on May 27, 2011 for EP Patent Application No. EP 06786507, 7 pages. International Search Report and Written Opinion for PCT/US2006/ 026374 mailed on Apr. 1, 2008, 4 pages. International Search Report and Written Opinion for PCT/US2006/
026376 mailed on Feb. 4, 2008, 7 pages.
A A B1 B1 B1
Robbins et a1. Harrison etal. Takedaet a1. Jakubowskiet al. Bissett etal.
Barthel et a1. ................ .. 700/82 Esposito et al. ................ .. 711/2
Non-Final Of?ce Action of Aug. 15, 2011 for US. Appl. No. 11/428,505, 12 pages. Notice ofAlloWance ofMay 18, 2010 for US. Appl. No. 11/428,5 16,
8 pages.
6,363,464 B1
6,434,712 B1*
3/2002 Mangione
8/2002 Urban et al. .................. .. 714/12
6,665,700 B1
7,107,484 B2*
7,802,075 2001/0044912 2003/0039354 2003/0140255 2004/0230729 2005/0021949 2005/0102244 2005/0120218 2007/0113230 2007/0245141
B2 A1 A1 A1 A1 A1 A1 A1 A1 A1
9/2010 11/2001 2/ 2003 7/ 2003 11/2004 1/2005 5/2005 6/ 2005 5/2007 10/2007
Bourdon et al. Francis et a1. Kimble et a1. Ricchetti et al. Ho et al. IZaWa et al. Dickinson et al. EchiZen et al. Bourdon et al. OKeefe et al.
Non-Final Of?ce Action 11/428,505, 12 pages. Non-Final Of?ce Action 11/428,516, 25 pages. Non-Final Of?ce Action 11/428,505, 11 pages. Non-Final Of?ce Action 11/428,516, 23 pages. Non-Final Of?ce Action 11/428,505, 9 pages.
of Dec. 16, 2009 for US. Appl. No. of Nov. 20, 2009 for US. Appl. No.
OTHER PUBLICATIONS
Examiner Interview Summary ofAug. 21, 2008 for US. Appl. No. 11/428,516, 4 pages. Non-Final Of?ce Action of May 13, 2008 for US. Appl. No. 11/428,516, 22 pages. Notice ofAlloWance ofJan. 31, 2012 for US. Appl. No. 11/428,505,
17 pages.
* cited by examiner
US. Patent
Sep. 3, 2013
Sheet 3 of7
US 8,527,741 B2
CLKl r120-1
J
Task_Match Next_Task
r108
Manager >
Task Error
Processor
New_Task
Task_|D(7:O)
CLK
Y
(120-2
J
New_Task
Processor
Task_|D(7:O)
-|-;:1Sk_|\/|at(;h+
Fig. 2A
Kl r120-1
/
Task_Match
f108
>
Task Error
Next_Task
cl-Kl I120'2
New_Task
Task_|D(7:0) Processor 4 Task_Match > Next_Task
Manager _>
Fig. 2B
US. Patent
Sep. 3, 2013
Sheet 4 of7
US 8,527,741 B2
108-1
Processor
New Task
a
CLK
120-2
Task
Error
Manager
.
New Task
a
Processor
108-2
Task_Match
Task
Error
Manager
Fig. 2C
US. Patent
Sep. 3, 2013
Sheet 5 of7
US 8,527,741 B2
( START )
304
300
//
r 308
312
Both Processors Activate New_Task With the First Being Recognized as Master
316
Slave Processor Cycles Through Tasks while Both Processors Wait for Task_Match Before Continuing
l
/
r320
324
Jr
Any Errors
328
Reported
END
Fig. 3
US. Patent
Sep. 3, 2013
Sheet 6 of7
US 8,527,741 B2
( START )
iv
Synchronous Task Initiated
404 ~
400-1
by First Processor
/\/
l
Indicated by New_Task
f 408
' 412
Task Match?
YES
440
420
Activate Next_Task to
Second Processor
424
f
Both Processors Execute Task
v
'
If
tr
( END
A
}
All Tasks Reviewed Report Error of Missing Task
r 432
Fig. 4A
US. Patent
Sep. 3, 2013
Sheet 7 on
US 8,527,741 B2
I START I
r 404
v I
4002
by Initiating Processor
/\/
f 408
412
Task Match?
YES
l
420
Assert Task_Match Signals
{440
r
Non-Initiating Processor
424
Activate Next_Task to
V
l
Both Processors Execute Task
444
(
All Tasks Reviewed
432
Fig. 4B
US 8,527,741 B2
1
SYSTEM FOR SELECTIVELY SYNCHRONIZING HIGH-ASSURANCE SOFTWARE TASKS ON MULTIPLE PROCESSORS AT A SOFTWARE ROUTINE LEVEL
2
?rst softWare routine identi?er corresponds With the second softWare routine identi?er. The output is coupled to at least
one of the ?rst or second processors and indicates When the ?rst and second softWare routine identi?ers do not corre
This application claims the bene?t of and is a non-provi sional of both US. Provisional Application Ser. No. 60/697, 072 ?led on Jul. 5, 2005; and US. Provisional Application
Ser. No. 60/697,071 ?led on Jul. 5, 2005, Which are both
spond. One of the ?rst and second processors is delayed until the ?rst and second softWare routine identi?ers correspond. Further areas of applicability of the present disclosure Will
appended ?gures:
20
FIGS. 1A and 1B depict block diagrams of embodiments of a redundant processing system; FIGS. 2A, 2B and 2C depict block diagrams of embodi ments of a task management circuit interacting With tWo
processors;
FIG. 3 illustrates a ?owchart of an embodiment of a process
This disclosure relates in general to high-assurance pro cessing and, but not by Way of limitation, to redundant cir
25
for aligning processing of some tasks on tWo circuits; and FIGS. 4A and 4B illustrate ?oWcharts of embodiments of a
process for managing task alignment for tWo circuits. In the appended ?gures, similar components and/or fea
tures may have the same reference label. Further, various
distinguishes among the similar components. If only the ?rst reference label is used in the speci?cation, the description is
35
the problem.
Under many circumstances, the same processors Working in unison Will eventually drift apart. PoWer conservation cir
cuits can throttle-back sub-circuits to save poWer and/ or pre
applicable to any one of the similar components having the same ?rst reference label irrespective of the second reference label.
DETAILED DESCRIPTION
unsuitable for lock-step operation. Lock-step designs require circuits that match very closely
to prevent one from getting out of synchronization With
another. Synchronizers are used to align events that occur at different times. Where circuits cannot be matched or are
45
changed during repair, the lock-step design may no longer operate in synchronization.
For lock-step operation, the softWare on all mirrored
50
Ware tasks are appropriate for lock-step operation, While oth ers do not require that level of harmonization. Redundant
execution of all softWare Wastes resources on routines that have no need for harmonization.
55
SUMMARY
In one embodiment, the present disclosure provides a task matching circuit for synchronizing softWare on a plurality of processors is disclosed. The task matching circuit includes ?rst and second inputs, an analysis sub-circuit, and an output. The ?rst input is from a ?rst processor con?gured to receive a ?rst softWare routine identi?er. The second input is from a second processor con?gured to receive a second softWare routine identi?er. The analysis sub-circuit determines if the
60
and output ports is high-assurance, but operating status lights is loW-assurance. When performing high-assurance tasks,
redundant processing is performed Where the results are com pared to assure a match. Even though this embodiment only shoWs tWo redundant sub-circuits, other embodiments could
65
have any number of redundant sub-circuits, e.g., four, six, eight, etc. High-assurance tasks include servicing an input and output ports 112, 104. The input port 112 receives information that is
US 8,527,741 B2
3
redundantly sent to a ?rst processor 120-1 and a second
4
tion. In this embodiment, the tWo processors 120 could be different designs or clocked at different frequencies such that
lock-step synchronization is not realized. The task managers 108 keep the processors 120 task aligned for some high
assurance tasks despite any differences in the processors 120. Should the task managers 108 disagree at some point, an error
viced such as servicing the status lights 144. When running the same high-assurance tasks, the processors 120 could dis
able further interrupts to avoid one or both processors 120
from Wandering aWay from the current task and risking a loss
of synchronization.
A task manager 108 is used in this embodiment to alloW
spersed betWeen the shared tasks. One of the processors 120 initiates a high-assurance task and noti?es the task manager 108 Which makes sure the other processor 120 is ready to initiate the same high-assurance task. When both processors 120 are ready, the task manager 108 noti?es both to begin execution. An example can illustrate the task synchronization process. A message is received on the input port and both processors 120 are interrupted to gather and process the message. The ?rst processor 120-1 to execute its interrupt service routine
For a high-assurance task, the second processor 120-2 acti vates the NeW_Task signal. The task manager 108 reads the Task_ID value from the second processor 120-2. Activation
20
25
ti?er, but other embodiments could use a 16-bit, 32-bit value or any other sized value. The Task_ID is unique to a particular high-assurance task run on both processors 120. With the Task_ID, the task manager 108 activates the Next_Task signal to ask the ?rst processor 120-1 to indicate the next task queued for execution. The ?rst processor acti
30
vates its NeW_Task signal to indicate validity of a Task_ID. Where there is no match of both Task_IDs, the task manager
108 asks the ?rst processor to move to the next task by
this embodiment does not require lock-step processing of high-assurance tasks, other embodiments could use lock-step
execute the same task indicated by the Task_IDs. If no task match is produced Within a pre-determined time or number of trials, the processor Would discard that task from its queue
and continue in one embodiment.
With reference to FIG. 2B, a block diagram of another embodiment of a task management circuit 108 interacting With tWo processors 120 is shoWn. In this embodiment, either
processor can initiate a task synchronization. The ?rst to initiate Would act as the master of the process and the other processor Would act as the slave. The task manager 108 Would Work With the master processor 120 until matching tasks are
found and executed before alloWing another initiation of the task matching process. Alternative embodiments could redundantly implement the task manager 108 and still alloW dynamically assigning the master of the process. Disagree
ment betWeen redundant task managers 108 Would be recog
nized as an error.
redundancy in the task management circuits 108 to provide high-assurance. Both task management circuits 108 compare tasks and report task incrementing and matching tasks to each
other. Where the tWo task managers 108 are not in agreement,
With reference to FIG. 1B, a block diagram of another embodiment of a redundant processing system 100-2 is
shoWn. This embodiment has tWo task managers 108 that are
assurance task. The ?rst processor is directly manipulated by the ?rst task manager 108-1, and the second processor is directly manipulated the second task manager 108-2.
65
used to achieve redundancy in the task management function. Each processor 120 responds to its respective task manager 108-1, 108-2, Who then coordinate aligning the task execu
Referring next to FIG. 3, a ?owchart of an embodiment of a process 300 for aligning processing of some tasks on tWo
US 8,527,741 B2
5
in block 304 where the ?rst and second processors 120 receive an interrupt to perform some sort of high-assurance task. Alternatively, the processors 120 could poll a register to determine when a high-assurance task should be initiated. An ISR indicated by the interrupts is started on both processors 120. The two processors 120 may start processing the inter
6
low-assurance tasks for a possible match. The next Task_ID for the second processor 120 is received by the task manager 108 in block 424.
Inblock 428, a determination is made to see if all tasks have
rupts at different times in block 308. Further, processing could be rearranged or interrupted such that both processors
120 are not performing the same actions at the same time.
been presented. This could be done by waiting for the same task to be presented again, by a signal from the processor, or a time delay that would permit review of all tasks. Where all have been reviewed and a match wasnt found, processing
goes from block 428 to block 432 where an error is reported.
In this embodiment, both processors could potentially be the master initiating the task matching process, but only one
is allowed to master the process. Where both activate their
If all the tasks have not been reviewed in block 428, process ing loops back to block 416 to determine if there is a match before further processing as described above. With reference to FIG. 4B, a ?owchart of another embodi ment of a process 400-2 for managing task alignment for two circuits is shown. In this embodiment, both processors 120
can initiate a task check. The initiating processor masters the process and the non-initiating processor is a slave in the
activate the New_Task line and one is recogniZed as master. In block 316, the slave processor 120 is tested to determine if the Task_ID matches with the master processor 120. Where there is no match, the slave processor cycles through tasks as
process. The ?rst processor to identify the high-assurance task and activate the New_Task becomes the initiating pro
20
Next_Task is activated successively. At some point in block 316, Task_Match goes active to indicate that both processors
120 have the same Task_ID at the top of their execution queue.
ces sor. The initiating processor could be chosen in other ways in other embodiments. Speci?c details are given in the above description to pro
vide a thorough understanding of the embodiments. However, it is understood that the embodiments may be practiced with out these speci?c details. For example, circuits may be shown
in block diagrams in order not to obscure the embodiments in
step during execution of the high-assurance task. Some, all or low-priority interrupts may be disabled during execution of the high-assurance task to control the interrupts tolerated.
Synchronization and/or buffering may or may not be done on
unnecessary detail. In other instances, well-known circuits, processes, algorithms, structures, and techniques may be shown without unnecessary detail in order to avoid obscuring
30
the embodiments. Also, it is noted that the embodiments may be described as a process which is depicted as a ?owchart, a ?ow diagram, a data ?ow diagram, a structure diagram, or a block diagram.
Although a ?owchart may describe the operations as a
sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the opera tions may be re-arranged. A process is terminated when its operations are completed, but could have additional steps not included in the ?gure. A process may correspond to a method,
a function, a procedure, a subroutine, a subprogram, etc. When a process corresponds to a function, its termination corresponds to a return of the function to the calling function or the main function.
embodiment, the New_Task line serves to latch the Task_ID into a register of the task manager 108. If operating correctly, both processors have the task ready to execute, but on the second processor, the task may not be at the top of the queue. A test in block 416 determines if the Task_IDs for both
processors match. In some embodiments this could be an
45
Moreover, as disclosed herein, the term storage medium may represent one or more devices for storing data, including
read only memory (ROM), random access memory (RAM), magnetic RAM, core memory, magnetic disk storage medi ums, optical storage mediums, ?ash memory devices and/or other machine readable mediums for storing information. The
50
to portable or ?xed storage devices, optical storage devices, wireless channels, and/or various other mediums capable of storing, containing or carrying instruction(s) and/ or data. Furthermore, embodiments may be implemented by hard
Should the tasks not match in block 416, the second pro cessor rotates through its tasks until they do correspond. In
block 420, the Next_Task signal is activated by the task man ager 108. This signal tells the second processor to present the
Task_ID for another task. The second processor may ran domly, sequentially or use some other scheme to present the next task for a possible match. This embodiment presents
65
age medium. A code segment or machine-executable instruc tion may represent a procedure, a function, a subprogram, a program, a routine, a subroutine, a module, a software pack age, a script, a class, or any combination of instructions, data structures, and/or program statements. A code segment may be coupled to another code segment or a hardware circuit by
US 8,527,741 B2
7
parameters, and/or memory contents. Information, argu ments, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means including memory shar
8
the analysis sub-circuit is con?gured to delay the ?rst
processor, and select each of the plurality of second software routine identi?ers in the queue of second software routine identi?ers, without the second pro
cessor executing a second routine corresponding to a
a hardware implementation, the processing units may be implemented within one or more application speci?c inte
grated circuits (ASlCs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable
logic devices (PLDs), ?eld programmable gate arrays (FP GAs), processors, controllers, micro-controllers, micropro
cessors, other electronic units designed to perform the func
tions described above, and/or a combination thereof. For a software implementation, the techniques, processes
25
known techniques.
While the principles of the disclosure have been described above in connection with speci?c apparatuses and methods, it is to be clearly understood that this description is made only
by way of example and not as limitation on the scope of the disclosure.
30
to synchronize the ?rst and second processors in executing the ?rst routine. 4. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1, wherein the output indicates that the ?rst software routine identi?er and the presently selected second software routine identi?er cor respond to the same routine only when the second software routine produces a result that the ?rst software routine also
produces.
5. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1, wherein the analysis sub-circuit is con?gured to delay at least one of the ?rst and second processors from executing a software routine corresponding to one of the ?rst software routine identi?er and the presently selected second software routine identi?er until the output indicates that the ?rst and second software routine identi?ers correspond to the same routine. 6. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1, further com prising the ?rst processor and the second processor wherein the ?rst processor operates off a ?rst clock signal different from a second clock signal of the second processor. 7. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1, wherein the ?rst processor cannot communicate directly with the second processor. 8. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1, wherein the ?rst software routine identi?er is created from contents of the ?rst routine. 9. The task matching circuit for synchronizing software on the plurality of processors as recited in claim 1, wherein the ?rst processor is a different design from the second processor.
35
identi?er, a ?rst routine to be executed by the ?rst pro cessor, the ?rst routine being one of a plurality of rou
40
receive a plurality of second software routine identi?ers from a queue of second software routine identi?ers, wherein: each of the plurality of second software routine identi ?ers uniquely identi?es a corresponding one of a plu
45
50
routines and comprises a predetermined plurality of software instructions; an analysis sub-circuit, at least partially embodied in hard
ware, con?gured to compare the ?rst software routine identi?er with each of the plurality of second software routine identi?ers and determine if the ?rst software routine identi?er and a presently compared one of the
second software routine identi?ers correspond to a same
routine, at least partially simultaneously in time. 11. The task matching circuit for synchronizing software
on the plurality of processors as recited in claim 1, wherein
60
routine; and
an output coupled to at least one of the ?rst or second
the analysis sub-circuit is con?gured to determine, for a sub set of a plurality of software routine identi?ers, that the ?rst software routine identi?er and the presently selected second software routine identi?ers correspond, and the analysis sub
circuit does not delay the ?rst processor unless at least one of
processors, wherein: the output indicates when the ?rst software routine iden ti?er and one of the plurality of second software rou tine identi?ers do not correspond to the same routine, and
prising:
US 8,527,741 B2
10
a ?rst input from a ?rst sub-circuit con?gured to receive a
?rst operation identi?er, Wherein one value of the ?rst operation identi?er uniquely identi?es, based on the one value of the ?rst operation identi?er, a ?rst softWare
Wherein the analysis sub-circuit is con?gured to cause the ?rst sub-circuit to perform more functions than the second
sub-circuit during normal operation. 14. The high-assurance circuit for coordinating perfor
mance on the plurality of sub-circuits as recited in claim 12,
softWare operations;
a second input from a second sub-circuit con?gured to receive a plurality of second operation identi?ers from a
queue of second operation identi?ers, Wherein: each of the plurality of second operation identi?ers
uniquely identi?es a corresponding one of a plurality
of second softWare operations to be executed by the second sub-circuit, and each of the second softWare operations comprises a pre
Wherein the ?rst sub-circuit operates off a ?rst clock signal different from a second clock signal of the second sub-circuit.
sub-circuits, Wherein:
the output indicates When the ?rst operation identi?er and one of the plurality of second operation identi?ers do not correspond to functionally overlapping soft
Ware operations, and
30
softWare operation corresponding to the ?rst operation iden ti?er and the presently selected second operation identi?er until the output indicates that the ?rst operation identi?er and
the analysis sub-circuit is con?gured to delay the ?rst sub-circuit, and select each of the plurality of second operation identi?ers in the queue of second operation
identi?ers, Without the second sub-circuit executing a second softWare operation corresponding to a pres
35
the presently selected second operation identi?er correspond. 19. The high-assurance circuit for coordinating perfor
mance on the plurality of sub-circuits as recited in claim 12,
ently selected second operation identi?er, until the ?rst operation identi?er and the presently selected second operation identi?er correspond to functionally