CMPEN 411 VLSI Digital Circuits Spring 2012 Lecture 20: Multiplier Design

[Adapted from Rabaeys Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

Sp12 CMPEN 411 L20 S.1

Review: Basic Building Blocks

Datapath

Execution units
- Adder, multiplier, divider, shifter, etc.

Register file and pipeline registers Multiplexers, decoders

Control

Finite state machines (PLA, ROM, random logic)

Interconnect

Switches, arbiters, buses

Memory

Caches (SRAMs), TLBs, DRAMs, buffers

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The Binary Multiplication

1 0 1 0 1 0 x
1 0 1 1 1 0 1 0 1 0

Multiplicand Multiplier

1 0 1 0 1 0
0 0 0 0 0 0

Partial products

1 0 1 0 1 0

1 1 1 0 0 1 1 1 0

Result

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Multiply Operation

Multiplication is just a a lot of additions

N
multiplicand multiplier partial product array

can be formed in parallel

double precision product

2N

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Multiplication Approaches

Right shift and add

Partial product array rows are accumulated from top to bottom on an N-bit adder
- After each addition, right shift (by one bit) the accumulated partial product to align it with the next row to add

Time for N bits

Tserial_mult = O(N Tadder) = O(N2) for a RCA

Making it faster

Use a faster adder Use higher radix (e.g., base 4) multiplication O(N/2 Tadder)
- Use multiplier recoding to simplify multiple formation (booth)

Form the partial product array in parallel and add it in parallel Use serial-parallel mult Use an array multiplier

Making it smaller (i.e., slower)

Sp12

- Very regular structure with only short wires to nearest neighbor cells. Thus, very simple and efficient layout in VLSI Can be easily CMPEN 411 L20 S.5 and efficiently pipelined

Serial-parallel multiplier structure

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The Array Multiplier

X3 X3
HA X3 X2

X2 X2
FA X1

X1 X1
FA X0

X0 X0
HA Y1 Z0

Y0

Y2

Z1

FA X3
FA

FA X1
FA

FA X0
HA Y3

HA
Z2

X2
FA

Z7

Z6

Z5

Z4

Z3

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Booth multiplier

Encoding scheme to reduce number of stages in multiplication.

Performs two bits of multiplication at oncerequires half the stages. Each stage is slightly more complex than simple multiplier, but adder/subtracter is almost as small/fast as adder.

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Booth encoding

Twos-complement form of multiplier:

y = -2nyn + 2n-1yn-1 + 2n-2yn-2 + ... (first bit is the sign bit) (example, y=18=010010 y= -18 = 101110 )

Rewrite using 2a = 2a+1 - 2a:

y = 2n(yn-1-yn) + 2n-1(yn-2 -yn-1) + 2n-2(yn-3 -yn-2) + ...

Consider first two terms: by looking at three bits of y, we can determine whether to add x, 2x to partial product.

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Booth actions

y = 2n(yn-1-yn) + 2n-1(yn-2 -yn-1) + 2n-2(yn-3 -yn-2) + ...

Consider first two terms: by looking at three bits of y, we can determine whether to add x, 2x to partial product.
yi yi-1 yi-2 increment 000 001 010 011 100 101 0 x x 2x -2x -x

110
111
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-x
0

Booth example

x = 1001 (910), y = 0111 (710).

P0 = 00000000 y3y2y1=011 y1y0y-1=11(0)

y1y0y-1 = 110, P1 = P0 - (1001) = 11110111

x shift left for 2 bits to be 100100 y3y2y1 = 011, P2 = P1 (10*100100) =

11110111+01001000 = 001111111 (6310)

An array multiplier needs N addtions, booth multiplier needs only N/2 additions

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Review: A 64-bit Adder/Subtractor

add/subt

Ripple Carry Adder (RCA) built out of 64 FAs Subtraction complement all subtrahend bits (xor gates) and set the low order carry-in RCA

C0=Cin A0 B0 A1 B1 A2 1-bit FA C1 1-bit FA C2 1-bit FA C3 ... S0

S1

S2

B2

advantage: simple logic, so small (low cost)

disadvantage: slow (O(N) for N bits) and lots of glitching (so lots of energy consumption)

C63

A63
B63

1-bit FA

S63

C64=Cout

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Booth structure

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Wallace-Tree Multiplier
Partial products 6 5 4 3 2 1 0 First stage 6 5 4 3 2 1 0 Bit position

(a) Second stage 6 5 4 3 2 1 0

(b) Final adder 6 5 4 3 2 1 0

FA

HA

(c)

(d)

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Wallace-Tree Multiplier

Full adder = (3,2) compressor

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Making it Faster: Tree Multiplier Structure

0 D 0 D multiple forming circuits partial product array reduction tree fast carry propagate adder (CPA) 0 D 0 D (icand) Q (ier)

mux + reduction tree (log N) + CPA (log N)

P (product)

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interconnect

(4,2) Counter

Built out of two (3,2) counters (just FAs!)

all of the inputs (4 external plus one internal) have the same weight (i.e., are in the same bit position) the internal carry output is fed to the next higher weight position (indicated by the )

(3,2)

(3,2)

Note: Two carry outs - one internal and one external

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Tiling (4,2) Counters

(3,2)

(3,2)

(3,2)

(3,2)

(3,2)

(3,2)

Reduces columns four high to columns only two high

Tiles with neighboring (4,2) counters Internal carry in at same level (i.e., bit position weight) as the internal carry out

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4x4 Partial Product Array Reduction

Fast 4x4 multiplication using (4,2) counters How would you lay it out?
multiplicand multiplier partial product array reduced pp array (to CPA) double precision product five (4,2) counters 5-bit CPA

multiplicand
multiplier

8-bit product

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8x8 Partial Product Array Reduction

Wallace tree multiplier

icand ier

partial product array

two rows of nine (4,2) counters

reduced partial product array

one row of thirteen (4,2) counters

to a 13-bit fast CPA

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An 8x8 Multiplier Layout

How should it be laid out?

multiplicand multiplier

nine (4,2) counters

nine (4,2) counters thirteen (4,2) counters 13-bit CPA

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Multipliers Summary
Optimization Goals Different Vs Binary Adder Once Again: Identify Critical Path Other possible techniques - Logarithmic versus Linear (Wallace Tree Mult) - Data encoding (Booth) - Pipelining FIRST GLIMPSE AT SYSTEM LEVEL OPTIMIZATION

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Next Lecture and Reminders

Next lecture

Shifters, decoders, and multiplexers

- Reading assignment Rabaey, et al, 11.5-11.6

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