Project 6: Latches and flip-flops

Yuan-Ze University
Department oI Computer Science and Engineering
Copvright bv Rung-Bin Lin, 1999
All rights reserved
Date out. 06/18/2001
Date due. 06/28/2001
Purpose:
This project is to design CMOS latches and Ilip-Ilops. Characterization oI setup and
hold times is also carried out.
Introduction:
Latches and Ilip-Ilops not only Iorm the basic components oI a Iinite state machine,
but also serve as memory elements Ior data path. The most commonly used latches
are level-sensitive D latches, while the most commonly used Ilip-Ilops are edge-
triggered D and T Ilip-Ilops. Choice oI latches or Ilip-Ilops depends on design
methodology and area and timing requirements. In general, latches are employed Ior
high-speed and high-density designs, but the use oI latches may impose very strict
timing requirement Ior the design and thus poses a diIIicult challenge Ior timing
veriIication. While the use oI edge-triggered Ilip-Ilops may be easier to deal with
timing-related problems Ior the design, but Ilip-Ilops are slower and take more area.
Since a D Ilip-Ilop usually consists oI two D latches, understanding the operation oI D
latches is indispensable to designing oI Ilip-Ilops.
Latches and Ilip-Ilips can be static or dynamic. A dynamic latch or Ilip-Ilop gradually
loses its content as time goes, while a static one retains its content no matter how
much time is elapsed. Eigure 6.1 shows a static D latch, while Eigure 6.2 shows a
dynamic one. As one can see in Eigure 6.2, the charge will leak out oI the output
capacitor oI the dynamic latch as time goes and thus the content oI the latch is lost. So
the use oI a dynamic latch should be careIully scrutinized. Eigure 6.3 shows a positive
edge-triggered D Ilip-Ilop. This is a static D Ilip-Ilop which consists oI two static
latches. The data is allowed to enter the Iirst latch during CLK0 whereas the second
latch is closed (not allowing the data to enter the latch). When the clock goes Irom 0
to 1, the Iirst latch is closed, while the second latch is opened to allow data to enter
the latch. At other moments, the output oI D Ilip-Ilop remains the same. Eigure 6.4
shows a dynamic D Ilip-Ilop whose content will be lost as time goes. Some oI the
latches or Ilip-Ilops can have set or/and reset inputs such that they can be set to a
desired value synchronously or asynchronously. A latch or Ilip-Ilop is said to be
synchronously set or reset iI set or reset Iunction is controlled by a clock. Eigure 6.5
shows a static D Ilip-Ilop that has asynchronous set and reset inputs.
Eigure 6.1. A static D latch
Eigure 6.2. A dynamic D latch

D
clk
-clk clk
-clk
Q

Eigure 6.3. A static and positive edge-triggered D Ilip-Ilop

Eigure 6.4. A dynamic D Ilip-Ilop
Eigure 6.5. A static D Ilip-Ilop with asynchronous set and reset
In general, the operation oI a latch or Ilip-Ilop involves two timing parameters- setup
and hold times. The input data must arrive earlier than the clock and remains
unchanged Ior a period aIter the clock arrives. Thus, setup time is deIined as the
diIIerence between the latest input arrival time and the clock arrival time, while hold
time is the diIIerence between the clock arrival time and the time the input data can be
changed. Thus, to design a latch or Ilip-Ilop, one should know how to characterize
setup and hold time. See the appendix Ior the method employed to characterize setup
and hold times.
The designing oI D latches and Ilip-Ilops is oI great important to a standard cell
library. Since the cells oI a standard cell library have the same height and its height is
usually deIined by the cell height oI the Ilip-Ilops. II the cell height is improperly set,
one may have diIIiculties to complete the layout design oI other cells by the same cell
height. II the cell height is set to 64 ( is the basic dimension used by the lambda
rules to characterize a process technology), the designing oI Ilip-Ilops may be quite a

challenge because routing resources become scarce. Basically, the larger is the cell
height, the easier is the layout design.
Problem descriptions:
1. Suppose input rise/Iall time is 0.8ns (measured Irom 0.1J

to 0.9J

), assign the
sizes to the transistors respectively in the two D latches shown in Eigure 6.1 and 6.2
such that the propagation delay (Irom 0.5J

to 0.5J

) oI any circuit structure is

and the output rise/Iall time is Ior output load

= . Characterize setup time, hold time, minimum pulse width and power
consumption oI these two circuits under the given load.
2. Lay out the two D latches with cell height set to 80. Their layouts should have the
same cell height and power bus width.
3. PerIorm post layout timing simulation to obtain their propagation delay and rise/Iall
time. Compare these results to those obtained in problem (2).
4. PerIorm simulations to veriIy the Iunctionality oI the Ilip-Ilops shown respectively
in Eigure 6.3, 6.4 and 6.5. Eind the propagation delay, output rise/Iall time, and
power consumption oI the Ilip-Ilops with input rise/Iall time set to 0.8ns and output
load

= .
5. Repeat the tasks in problem (2) Ior Ilip-Ilops.
6. Repeat the tasks in problem (3) Ior Ilip-Ilops.
Notes:
TSMC 0.35um process technology should be employed.
Only metal 1 layer and poly layer can be used to interconnect transistors. Power
and ground bus also use metal 1 layer. The width oI power and ground buses is set
to 10 oI the cell height.
The pin must be placed on grid with metal 1. The size oI a grid is deIined as the
pitch Irom via 1 to via 1 which connects metal 1 to poly.
Under the given timing requirements Ior each circuit, one should try to minimize
the cell area.
References:
|1|. Neil H. E. Weste and Kamran Eshraghian, 'Principles oI COMS VLSI Design: A
System Perspective, Second Edition, Addison-Wesley, 1992.
|2|. HSPICE User`s Manual, Meta-SoItware, 1990.
Appendix:
Characterization oI setup time, hold time and minimum pulse width
(A). Minimum Setup Time
The minimum setup time is the smallest time interval Ior which data must
remain stable on a data output beIore it is latched in by an active transition on an
appropriate control input. Eor a D Ilip-Ilop, this is the time period Ior which the data
input D must be maintained beIore the arrival oI the active level oI the clock input
CLK. Setup time is measured Irom the clock transition relative to the input data
transition at the 50 (deIault) points. Eigure 6.6 shows the input/output waveIorms oI
a D Ilip-Ilop to describe this concept. The minimum setup time measurement is
carried out by the Iollowing steps. Eirst, let the data signal transit to a desired level at
some point. AIter a long enough period oI time is past, the clock transition is asserted.
This time period is called reference setup. The propagation delay Irom clock to output
transition is measured as a reference delav. Then, the data signal is changed to
approach the clock active edge which should be Iixed aIter the reIerence delay is
obtained. The time diIIerence between the changing data signal and the active clock
edge is called T

. The circuit designer deIines an upper-bound and a lower-bound

Ior the data transition moment around the active edge oI clock signal and a bisection
algorithm is used to search the minimum setup time within the window deIined by the
upper-bound and lower-bound. The minimum setup time is Iound when the output
delay increases by more than 10 oI the reference delav and the diIIerence between
the upper-bound and the lower-bound exceeds the user-deIined precision. Eigure 6.7
shows the measurement oI setup time Ior a positive edge-triggered D Ilip-Ilop. The
Iollowing Iormula is used to determine the accuracy oI the measurement iterations.
p w/2

}
where p: the user-deIined precision.
w: the starting-window length.
n: the number oI iterations.
So, Ior a starting window oI 5ns with 10 iterations, the minimum setup time can
be obtained with 0.01ns precision.
D
Q
Q
SET
CLR
CLK
T
setup
Q Delay
D
CLK
Q
Figure 6.6. A positive-edge triggered D Ilip-Ilop and
its input/output waveIorms
Figure 6.7. The setup time measurement
(B). Minimum Hold Time
The minimum hold time is the shortest time interval immediately Iollowing the
active transition oI a control input during which the data on the appropriate data input
must remain stable Ior the correct value to be latched. Eor a positive-edge D Ilip-Ilop,
the minimum hold time is the period oI time aIter the active edge oI clock input
during which the D input must be held constant. Eigure 6.8 shows the hold time
measurement Ior a positive-edge triggered D Ilip-Ilop. The measurement
methodology is the same as that Ior minimum setup time measurement.
D
Q
Q
SET
CLR
CLK
T
hold
Reference
Delay
D
CLK
Q
Figure 6.8. The hold time measurement Ior a positive
edge-triggered D Ilip-Ilop.
(C). Minimum Clock Pulse Width
The minimum pulse width oI a clock signal is the shortest time needed between
two edges oI a signal Ior that signal to be Iunctional. A signal can have both high and
low minimum pulse widths. The Iirst step oI minimum pulse width measurement is to
deIine a long Iixed-width pulse as a reIerence pulse (see Eigure. 6.9) and the
propagation delay measured Irom active edge oI clock signal to output transition as
the 'standard output delay. Next, move the rising edge oI measurement pulse closer
to the Ialling edge until the Ilip-Ilop Iails or until the output delay increases by more
than 10 (Iailure threshold) oI the 'standard delay. Eigure 6.10 shows the
relationship oI output delay and pulse width.
Figure 6.9. ReIerence pulse and measurement pulse
Figure 6.10. The relationship oI output delay and pulse width