Design, test and characterization of a compact

MEMS-based frequency synthesizer

Faisal Saeed Ahmad

Department of Electrical Engineering
McGill University
Montral, Qubec, Canada







A thesis submitted to McGill University in partial fulfillment of the requirements of the
degree of Master of Engineering (Electrical Engineering)

January 2011
Faisal Saeed Ahmad, 2011

ii


Abstract
Extensive microelectronics research has been conducted over the past decade to
develop integrated replacements for high quality factor off-chip components. Micro-
electromechanical systems (MEMS) based technology offers great promise as a result of
improved reliability, microscale size, integration potential and eventually lower overall
cost. In this work, the design, optimization, characterization, and test of a MEMS-based
fully integrated frequency synthesizer serves to demonstrate a proof-of-concept for using
MEMS clamped-clamped beam resonators in front-end RF systems. Details regarding
system integration of the phase-locked loop, the MEMS resonator and the associated
sustaining amplifier highlight issues related to managing circuit interfaces, system level
performance and test methodology. Design and optimization of the different on-chip
synthesizer components including the charge-pump, loop filter and voltage controlled
oscillator, provides a thorough examination of the device evolution. System-level
simulation and testing, facilitated by the design of high quality printed circuit boards,
provides performance metrics that are benchmarked against conventional crystal-based
systems.


iii

Rsum
Au cours de la dernire dcnnie, des recherches approfondies ayant le but de
dvelopper des remplacements intgrs pour les composants facteurs de qualit
suprieurs ont vu le jour. Les microsystmes lectromcaniques (MEMS) ont le potentiel
de permettre une fiabilit amliore, une minituarusation, une grande d'intgration et
finalement une rduction de couts. Dans le cadre de ce travail, la conception,
l'optimisation, la caractrisation, et le test d'un synthtiseur de frquence entirement
intgr bas sur un MEMS est une preuve de concept de l'utilisation des rsonateurs
MEMS dans les systmes radio-frquence. Les dtails quant l'intgration de la boucle
verrouillage de phase, le rsonateur MEMS et l'amplificateur soutenant l'oscillation
reprsentent les problmes relis la gstion d'interfaces des circuits, la performance du
systme et la mthodologie de test. La conception at l'optimisation des diffrents
composants du synthtiseur, y compris le convertisseur pompe de charge, le filtre de
boucle et l'oscillateur contrl en tension, consiste en un examen minutieux de l'volution
du systme. Les simulations et les tests apports au niveau du systme et facilits par la
conception de circuits imprims de haute qualit, fournissent les paramtres de
performance ncessaires pour l'valuation de ce systme MEMS par rapport aux systmes
bass sur les cristaux de quartz conventionnels.


iv

Acknowledgements
First, I would like to thank my supervisor Dr. Mourad El-Gamal, who has provided
guidance and support throughout my graduate studies. His helpful advice over the past
years made this thesis possible.
Next, I would like to thank Dr. Frederic Nabki, a former student studying in the
Wireless ICs and MEMS research group at McGill. His work on the development of SiC
surface micromachining fabrication technology and associated MEMS clamped-clamped
beam resonators, as well as MEMS-based oscillators and frequency synthesizers served as the
foundation of this work. I would also like to thank Ph.D. student Karim Allidina for his
contributions and support to the frequency synthesizer project, particularly in the
development of charge pump circuitry, IC layout and laboratory testing. Finally, I would like
to thank Ph.D. student Paul Vahe-Cicek for his contributions to enhancing the performance of
the MEMS resonators in conjunction with Dr. Nabki. This thesis would not have been
possible without the insightful discussions and exchange of ideas with these three individuals.
In addition, I would like to thank my family and friends for their support throughout
this process. My always dedicated Valerie, my father Athar, my mother Gabriele and
siblings Tania, Farah and Tariq, as well as my aunt Tajie and brother-in-law Peter who all
provided endless encouragement throughout the development of this work. Finally, I
would like to show my gratitude to my close friends, whose support over the past years
cannot go without mention.

v

Contents

List of Figures ................................................................................................................. viii
List of Tables ..................................................................................................................... xi
Acronyms ......................................................................................................................... xii

Chapter 1: Introduction .................................................................................................... 1
I. Contributions ................................................................................................................. 3
A. MEMS System Integration ....................................................................................... 3
B. Design of a High Performance RF VCO .................................................................. 3
C. High Quality PCB Development .............................................................................. 4
II. Synopsis .................................................................................................................... 5

Chapter 2: Synthesizer System Description and Noise Analysis ................................... 7
I. The Frequency Synthesizer ........................................................................................... 8
A. Phase Frequency Detector (PFD) .............................................................................. 9
B. Charge Pump (CP) .................................................................................................. 10
C. Loop Filter .............................................................................................................. 12
D. Voltage Controlled Oscillator (VCO) ..................................................................... 15
E. Multimodulus Divider ............................................................................................. 17
F. Delta-Sigma () Modulator .................................................................................. 17
II. The MEMS-Based Reference Oscillator ................................................................ 18
A. The MEMS Resonator ............................................................................................ 19
B. MEMS Resonators versus Quartz Crystals ............................................................. 21
C. The Transimpedance Amplifier (TIA) .................................................................... 23
III. Synthesizer System Noise Analysis ........................................................................ 25
A. Component Phase Noise ......................................................................................... 26
1) Reference Oscillator Noise .................................................................................. 26
2) PFD Noise ........................................................................................................... 27
3) CP Noise .............................................................................................................. 27
4) Loop Filter Noise ................................................................................................ 28
5) VCO Noise .......................................................................................................... 29
6) Multimodulus Divider Noise ............................................................................... 29
7) Delta-Sigma () Modulator Noise .................................................................... 30

vi

B. Noise Shaping ......................................................................................................... 30
C. MEMS Resonator Phase Noise ............................................................................... 33
IV. Application Development ....................................................................................... 36
V. Conclusion .............................................................................................................. 36

Chapter 3: Integrated RF VCO Design and Optimization .......................................... 38
I. VCO Theory ................................................................................................................ 39
II. Phase Noise Theory ................................................................................................ 41
A. Leeson Phase Noise Model ..................................................................................... 42
B. Limitations of Leesons Phase Noise Model .......................................................... 44
C. An Alternative Phase Noise Model ......................................................................... 45
D. Phase Noise Simulation Models ............................................................................. 49
III. High Performance RF Oscillator Design and Optimization ................................... 50
A. Baseline Oscillator Design ...................................................................................... 50
B. Phase Noise Minimization Techniques ................................................................... 52
1) Design and Optimization of the VCO Circuit Topology .................................... 52
2) Design and Optimization of the Integrated Inductor ........................................... 54
3) Optimization of the VCO Gain ........................................................................... 56
IV. Performance Evaluation .......................................................................................... 57
A. Simulation Results .................................................................................................. 57
B. Measured Results .................................................................................................... 60
V. Conclusion .............................................................................................................. 61

Chapter 4: PCB Design, Characterization and Test ..................................................... 63
I. Fully-Integrated Frequency Synthesizer PCB ............................................................. 64
A. PCB Design Overview ............................................................................................ 64
B. Design for Electromagnetic Compatibility ............................................................. 66
C. Specialized Off-Chip Circuitry ............................................................................... 68
1) Regulator Circuitry .............................................................................................. 68
2) Programming and Synchronization Circuitry ..................................................... 69
3) Off-Chip Loop Filter ........................................................................................... 70
D. PCB Design Evolution and Test Methodology ....................................................... 72
II. MEMS Resonator Demo PCB ................................................................................ 76
A. PCB Design Overview ............................................................................................ 76

vii

B. PCB Component Selection ..................................................................................... 78
C. Test Setup ................................................................................................................ 82
III. Conclusion .............................................................................................................. 83

Chapter 5: Experimental Results ................................................................................... 84
I. MEMS-Based Frequency Synthesizer ........................................................................ 84
II. MEMS-Based Frequency Synthesizer with Off-Chip Loop Filter ......................... 95
III. MEMS Resonator Demo PCB ................................................................................ 97
A. Transimpedance Amplifier ..................................................................................... 97
B. Frequency Synthesizer ............................................................................................ 99
C. Performance Summary .......................................................................................... 101
IV. Conclusion ............................................................................................................ 102

Chapter 6: Conclusion ................................................................................................... 103
I. Summary and Contributions ...................................................................................... 103
II. Future Directions .................................................................................................. 104

References ....................................................................................................................... 106



viii

List of Figures
Figure 1: Frequency synthesizer block diagram including the MEMS reference oscillator 9
Figure 2: Phase frequency detector schematic diagram ..................................................... 10
Figure 3: Charge pump circuit diagram ............................................................................. 11
Figure 4: Dual-path loop filter circuit schematic ............................................................... 12
Figure 5: Circuit schematic of the dual path loop filter adder ........................................... 14
Figure 6: Voltage controlled oscillator circuit schematic (Device 4) ................................ 16
Figure 7: Accumulator-based delta-sigma modulator schematic diagram......................... 18
Figure 8: Scanning electron micrograph (SEM) of a 45 m long by 25 m wide CC-beam
resonator (left) and a corresponding cross-section illustrating the beam to electrode gap
spacing (right) .................................................................................................................... 20
Figure 9: Resonator transfer characteristic (left) and linear circuit model (right) ............. 20
Figure 10: CC-beam cross-section showing material definition and device construction 21
Figure 11: Transimpedance amplifier schematic diagram ................................................. 24
Figure 12: Component noise shaping for TCXO, charge-pump, loop filter and RF VCO 31
Figure 13: Simulated PLL output phase noise and individual component contributions
(TCXO Reference) ............................................................................................................. 33
Figure 14: MEMS oscillator phase noise profile ............................................................... 34
Figure 15: Simulated PLL output noise and individual component contributions (MEMS
reference) ........................................................................................................................... 35
Figure 16: Waveforms and corresponding ISFs for an LC oscillator (left) and a ring
oscillator (right) ................................................................................................................ 46
Figure 17: Baseline VCO Schematic (left) and Micrograph of Fabricated Device (right) 51
Figure 18: Complementary VCO schematic ...................................................................... 53
Figure 19: Comparison of intertwined inductors of baseline VCO (left) with differential
inductor (right) ................................................................................................................... 56
Figure 20: Redesigned VCO Circuit Schematic (left) and Corresponding Micrograph
(right) ................................................................................................................................. 57
Figure 21: Simulated oscillation frequency versus tuning voltage for the redesigned VCO
............................................................................................................................................ 59

ix

Figure 22: Comparison of the measured phase noise of the baseline and redesigned VCOs
............................................................................................................................................ 60
Figure 23: Photograph of test PCB for PLL device 3 ........................................................ 64
Figure 24: Packaged PLL IC (left) and packaged MEMS resonator die (right) ................ 65
Figure 25: Voltage regulator circuit schematic .................................................................. 69
Figure 26: Pulse generating circuit schematic ................................................................... 70
Figure 27: Fourth order active loop filter circuit schematic .............................................. 71
Figure 28: Simulated synthesizer output phase noise with TCXO reference and off-chip
loop filter ............................................................................................................................ 71
Figure 29: PLL device 4 laboratory test setup ................................................................... 73
Figure 30: Photograph of test PCB for PLL device 4 ........................................................ 74
Figure 31: Schematic CLP vacuum packaged solution ..................................................... 75
Figure 32: Block diagram of MEMS resonator demo PCB ............................................... 77
Figure 33: Photograph of the MEMS resonator demo PCB .............................................. 78
Figure 34: Passive loop filter circuit schematic ................................................................. 80
Figure 35: Simulated output phase noise for demo board synthesizer with TCXO
reference using ADIsimPLL .............................................................................................. 80
Figure 36: Circuit schematic of MEMS resonator connected in Pierce oscillator
configuration ...................................................................................................................... 81
Figure 37: MEMS demo PCB laboratory test setup .......................................................... 82
Figure 38: Device 1 synthesizer die (2.5 mm by 2.5 mm) ................................................. 85
Figure 39: Device 2 synthesizer die (2.5 mm by 2.5 mm) ................................................. 85
Figure 40: Device 3 synthesizer die (2.5 mm by 2.5 mm) ................................................. 85
Figure 41: Device 4 synthesizer die (2.3 mm by 2.8 mm) ................................................. 85
Figure 42: Device 4 synthesizer die micrograph identifying the different system
components ........................................................................................................................ 86
Figure 43: 11.6 MHz MEMS-based reference oscillator phase noise ............................... 88
Figure 44: Phase noise comparison for an 1800 MHz output (device 4) ........................... 89
Figure 45: Output phase noise comparison for fractional-N and integer-N operation ...... 89
Figure 46: Synthesizer output phase noise at 1800 MHz for the different devices ........... 90

x

Figure 47: Typical example of VCO control voltage during 120 MHz change in frequency
(device 3) ........................................................................................................................... 91
Figure 48: Output spectrum of the synthesizer for frequencies spaced by 1.25 MHz about
1.8 GHz (device 3) ............................................................................................................. 92
Figure 49: Measured output spectrum of the synthesizer finely tuned in steps of 160 Hz
(approx. 0.09ppm) about 1.8 GHz (device 3) .................................................................... 92
Figure 50: Measured effect of dithering on fractional spurs (device 2) ............................ 93
Figure 51: Simulated synthesizer phase noise with on-chip and off-chip loop filter (TCXO
reference) ........................................................................................................................... 96
Figure 52: Measured synthesizer phase noise with on-chip and off-chip loop filter (device
4 - TCXO) .......................................................................................................................... 96
Figure 53: Sustaining amplifier measured open poop gain for MEMS resonator demo
PCB .................................................................................................................................... 98
Figure 54: Sustaining amplifier open loop gain measurement setup ................................. 98
Figure 55: Measured and simulated output phase noise at 1800 MHz for MEMS resonator
demo PCB .......................................................................................................................... 99
Figure 56: Measured output phase noise at 1802.4 MHz for MEMS resonator demo PCB
.......................................................................................................................................... 100

xi

List of Tables
Table 1: Evolution of charge pump currents for different synthesizer devices ................. 15
Table 2: Summary of loop filter and synthesizer loop characteristics (Device 4) ............. 15
Table 3: Transimpedance amplifier performance summary .............................................. 25
Table 4: Skin depth of aluminum for different frequency values ...................................... 55
Table 5: Comparison of VCO simulation results ............................................................... 58
Table 6: VCO measured performance comparison to recently published VCOs .............. 61
Table 7: Typical local oscillator (LO) frequency for different wireless standards ............ 79
Table 8: Crystek VCO typical performance parameters [49] ............................................ 79
Table 9: MEMS resonator oscillator performance summary (data from [3]) .................... 87
Table 10: Frequency synthesizer performance summary and benchmarking .................... 94
Table 11: Comparison between integrated and discrete loop filter implementations ........ 97
Table 12: MEMS resonator demo PCB frequency synthesizer performance summary .. 101


xii

Acronyms
AGC automatic gain control
AM amplitude modulation
ASITIC analysis and simulation of inductors and transformers for integrated circuits
BNC bayonet Neill-Concelman
CLP chip-level packaging
CMOS complimentary metal-oxide semiconductor
COTS commercial off-the-shelf
CP charge pump
DC direct current
DIP dual in-line package
EMC electromagnetic compatibility
EMI electromagnetic interference
FBAR film bulk acoustic resonator
FM frequency modulation
FoM figure-of-merit
FPGA field programmable gate array
GSM global system for mobile communications
GPS global positioning system
IC integrated circuit
I/O input/output
ISF impulse sensitivity function
LC inductor capacitor
LCC leadless chip carrier
LDO low drop-out
LTI linear time-invariant
LTV linear time varying
MASH multi-stage noise shaping
MEMS micro-electro mechanical system
MiM metal-insulator-metal

xiii

N divider ratio
NMOS n-type metal oxide semiconductor
PC personal computer
PCB printed circuit board
PED personal electronic device
PFD phase frequency detector
PLL phase-locked loop
PM phase modulation
PMOS p-type metal oxide semiconductor
PN phase noise
PVT pressure, voltage and temperature
Q quality factor
RF radio frequency
RMS root mean square
SiC silicon carbide
SoC system-on-chip
SMA subminiature version A
SMT surface mount
SONET synchronous optical networking
TCXO temperature compensated crystal oscillator
TIA transimpedance amplifier
TSPL true single phase logic
UMTS universal mobile telecommunications system
VCO voltage controlled oscillator
VGA variable gain amplifier
WLAN wireless local area network
WLP wafer-level packaging


1



Chapter 1

Introduction







For modern radio applications, performance is often dependent on the utilization of
high quality factor off-chip passives. Selected for their excellent spectral purity and low
insertion loss, these off-chip components typically also lead to increased power
consumption, larger form factor, and higher system cost. As a result, extensive research
has been conducted over the past decade to develop integrated replacements for off-chip
components. Micro-electromechanical systems (MEMS) based technology, covering a
wide range of devices and systems, offers great promise as a result of improved
reliability, microscale size, integration potential and eventually, lower overall cost due to
economies of scale. In addition to serving as the resonant tank for low-frequency
reference oscillators, such high-Q MEMS-based devices are also potentially applicable to
RF oscillators, switches, tunable capacitors and a wide range of filtering applications.
There is also the potential to revolutionize front-end transceiver architectures entirely,
with large quantities of high-Q MEMS devices used to create RF channel select filter
networks, as proposed in [1].
The fully integrated frequency synthesizer application developed by McGill's
Wireless IC & MEMS laboratory in [2] and [3] serves to demonstrate a proof-of-concept
for using MEMS-based clamped-clamped beam resonators in front-end RF systems. In
the near term, these MEMS-based oscillators are targeted towards less stringent wireline

2

and wideband wireless applications, whereas the ultimate objective is to provide noise
performance and frequency stability that is on par with modern TCXOs.
The drive behind MEMS technology is not simply miniaturization. The emergence of
small form-factor MEMS based oscillators commercially has placed increased pressure
on crystal oscillator manufacturers to develop smaller devices. Virtually inconceivable a
few years ago, crystal oscillators are commercially available as small as 2.0x1.6 mm
2
,
without sacrificing performance and cost [4]. Temperature Compensated Crystal
Oscillators (TCXO) are also available in this small form factor [4] and provide an
excellent frequency stability of 2.5 ppm. As a result, the key for MEMS technology to
become commercially competitive is to achieve monolithic integration of resonators by
depositing and patterning films directly above the CMOS circuits, thus removing the need
for off-chip passives. This objective requires low-temperature processes that are limited
to materials and chemicals that are compatible with CMOS post-processing. The low
temperature low-stress silicon carbide surface micromachining fabrication developed by
Nabki et al. in [5] was a first step towards achieving these goals. The second step is the
design and characterization of the engineering application, upon which much of this
project is based. Performance in terms of frequency stability, phase noise and power
consumption are paramount to MEMS-based oscillators becoming a technically viable
alternative to crystal oscillators.
The importance of this work is that it provides detailed characterization of a
programmable MEMS-based oscillator, including design features such as the resonator
driving mechanism and oscillator programming methodology. Although MEMS based
reference and RF oscillators are beginning to emerge commercially from companies like
Discera and SiTime, no detailed specifications are readily available in the public domain
[4].
The author's role in the project development was a complement to the work
conducted by Dr. Frederic Nabki on developing the MEMS resonator technology and a
fully-integrated frequency synthesizer as part of his Ph.D. dissertation. Specifically, the
author's contribution consisted of the original dual-path loop filter design based on [6],
design of a high performance RF VCO, all activity related to printed circuit board (PCB)
design, optimization, characterization and test, as well as an independent endeavor to

3

develop a small form-factor easy-to-use PCB dedicated to the rapid prototyping of the
MEMS resonators. The next section provides a summary of the three main contributions
of this work to microelectronics and MEMS research.
I. CONTRIBUTIONS
The three primary contributions of the work presented in this thesis are as follows:
A. MEMS System Integration
A significant challenge in the development of a MEMS-based frequency synthesizer
is addressing the system integration issues involved in combining the phase-locked loop,
the MEMS resonator, the associated sustaining amplifier and required off-chip circuitry.
Issues related to managing circuit interfaces, system level performance (e.g. noise,
power), electromagnetic compatibility (EMC) and test methodology all required careful
consideration to achieve successful integration of the frequency synthesizer system. This
integration represents an important step towards System-on-Chip technology (SoC)
whereby the MEMS resonator would be DC sputtered directly above the CMOS
electronics.
B. Design of a High Performance RF VCO
Regardless of the type of reference oscillator that is used to source the frequency
synthesizer, the far from carrier noise will be dominated by the RF VCO. Beyond the
loop bandwidth of the phase-locked loop, noise from the phase frequency detector (PFD),
charge pump (CP) and reference are all filtered out, with the VCO noise and thermal
noise remaining. As a result, a state-of-the-art RF VCO design is paramount to achieving
the stringent phase noise requirements set by different wireless communication standards.
A thorough review of modern phase noise theory and recently published VCO designs
produced a process for topology and inductor optimization that was applied to an LC
cross-coupled pair. Improved inductor quality factor, from 4.9 to 10.9, combined with a
change in circuit topology and a reduction in VCO gain translated into a phase noise
improvement from -115.5 dBc/Hz at 600 kHz offset from the carrier for the baseline to -
123.4 dBc/Hz for a complimentary cross-coupled LC VCO.

4

C. High Quality PCB Development
A series of high quality printed circuit boards were developed for the four device
iterations of the MEMS-based frequency synthesizer. In addition to supporting the system
test methodology and providing a programming interface for the various operating modes,
the PCBs needed to provide a configuration that allowed for switching between different
reference sources (MEMS and TCXOs). The PCB designs were also required to
accommodate both a chip-level packaged (CLP) solution and a standard PCB level
solution where the MEMS resonator and PLL/TIA IC are packaged separately. To
achieve the aforementioned objectives, careful selection of off-chip ICs, connectors and
lumped elements was needed, in addition to careful component layout in order to
minimize the potential for electromagnetic compatibility issues (e.g. crosstalk). For ease
of assembly, a standard thickness (1.5748 mm) FR4 laminate with silk screen and solder
mask layers was selected. A separate, small form-factor PCB using only commercial off-
the-shelf (COTS) surface mount components was designed for the purpose of rapid
prototyping of the MEMS resonators, as has been done in a number of prior publications,
including [7].
Further details regarding the above listed contributions will be addressed in subsequent
chapters of the thesis, including specifics relating to design, optimization and performance.
The next section provides an overview of those chapters.
The work contained in this thesis has led to a conference publication and a prominent
engineering journal publication. At the IEEE Custom Integrated Circuits Conference
(CICC) in February 2008, an article entitled A Compact and Programmable High-
Frequency Oscillator Based on a MEMS Resonator (pp. 337-340) described the second
iteration of the MEMS-based frequency synthesizer design described herein. A collective
effort, the authors specific contribution consisted of the integrated loop filter design,
system integration of components at the chip and board level, design of the printed circuit
boards, as well as experimental test and characterization of the complete system. In the
August 2009 edition of the IEEE Journal of Solid-State Circuits (JSSC), an article entitled
A Highly Integrated 1.8 GHz Frequency Synthesizer Based on a MEMS Resonator
(vol. 44, pp. 2154-2168) offered a more in-depth examination of the MEMS-based
frequency synthesizer, complemented by improved experimental data gathered from the

5

third iteration of the device. The author provided the same contributions as listed above
for the CICC publication, with the addition of the design of the high performance RF
VCO that served to satisfy the stringent out-of-band phase noise specifications of the
DCS-1800 standard.
II. SYNOPSIS
Chapter 2 provides an overview of the MEMS-based frequency synthesizer system,
including a detailed description and design evolution of each component. Also included
are a description of the MEMS clamped-clamped beam resonators, the process used to
fabricate them and the transimpedance amplifier (TIA) used to sustain oscillation. This
high-level system description provides a basis for presenting the contributions detailed in
the following Chapters. Finally, Chapter 2 closes with a system noise analysis based on
Cadence noise simulation and ideal noise transfer functions for a PLL system driven by a
TCXO, as well as for the same system driven by the MEMS-based reference oscillator.
Chapter 3 describes the design and optimization of the high-performance integrated
RF oscillator. The chapter begins with some basic VCO theory, followed by a discussion
of noise sources in oscillators and phase noise theory in general. The drawbacks of
Leesons phase noise model and some background theory on Hajimiris time invariant
approach are presented. Subsequently, different design and optimization strategies are
applied to a baseline LC cross-coupled pair in order to minimize phase noise and meet the
stringent DCS-1800 requirements. Finally, simulation and measured results of the free-
running VCO are provided, including a review and comparison to the current state-of-the-
art in integrated LC VCO design.
Chapter 4 describes the design of two PCBs used for characterization and test of the
fully integrated frequency synthesizer and MEMS resonators described in Chapter 2.
Whereas the first PCB design is dedicated to the PLL/TIA IC developed in-house, the
second PCB is a small form fit easy-to-use PCB designed for rapid prototyping of MEMS
resonators and built exclusively using commercial off-the-shelf surface mount
components. Included in this section are issues related to specialized PCB circuitry,
electromagnetic compatibility, test methodology and design evolution.

6

Chapter 5 provides measured results for the aforementioned PCB circuits and
integrated devices, including benchmarking to the current state-of-the-art in fully-
integrated synthesizer design. The measured data is also compared to simulated data
presented in Chapters 2 and 3.
To conclude, Chapter 6 provides a summary of the contributions and the potential for
future work, including a synthesizer linearization scheme, further PLL optimization, and
MEMS resonator development.


7


Chapter 2

Synthesizer System Description
and Noise Analysis







The purpose of this Chapter is to present an overview of the fully integrated
synthesizer system with MEMS-based reference oscillator, detailing the different building
blocks, including their circuitry and design evolution through the four device iterations.
Whereas the first edition of the synthesizer IC developed as part of this work was fully
functional, it fell short of DCS-1800 phase noise specifications and suffered from other
issues related to acquisition time and stability. For subsequent iterations, modifications
were made to correct these issues, as well as to improve the design, particularly in the
interest of phase noise performance. For device four, modifications were also made to the
component pin out to accommodate a novel vacuum packaging solution, which will be
described in Chapter 4.
Previous designs, such as the integrated synthesizer in [6], utilized a conventional off-
chip crystal reference oscillator. The design presented herein operates using a MEMS-
based reference oscillator, providing the potential for a completely integrated system. The
benefits of integration include a smaller form factor, shorter interconnects and reduced
parasitics largely associated with the elimination of off-chip passives. The IC incorporates
all synthesizer circuitry, as well as the sustaining amplifier of the reference oscillator,
which can be wire bonded to the MEMS resonator within the same package.
Alternatively, the amorphous silicon carbide used for fabrication of the resonator may be

8

DC sputtered directly above the CMOS electronics, providing a truly fully integrated
solution. Whereas thin-film bulk acoustic wave resonators (FBAR) have also
demonstrated the capability to be used above-IC [8], these devices require larger areas,
have limited frequency tuning capability and suffer from other process related drawbacks,
as described in [3].
Following the description of synthesizer components, this Chapter provides an
overview of the MEMS clamped-clamped beam resonators developed by Nabki et al. and
detailed in [9], as well as the design of the transimpedance amplifier used here to sustain
oscillation. The MEMS resonators used in this work are limited to fundamental
frequencies ranging from 4 to 30 MHz, although the process may also be applied to
higher frequency structures. More importantly, the process is also readily extensible to
more complex MEMS structures capable of achieving quality factors in excess of 10,000.
In the near term, the primary challenges for MEMS devices to become commercially
viable include issues related to power handling, insertion loss and temperature stability.
Finally, this Chapter concludes with a detailed noise analysis of the synthesizer
system, including strategies for optimizing output phase noise performance. The noise
contributed by each PLL building block to the system output noise is evaluated using
Cadence noise simulations, with noise shaping applied using the ideal noise transfer
functions based on the point of injection. The noise analysis is conducted for a system
driven by a TCXO reference oscillator, as well as by a MEMS-based version. In each
case, the dominant noise sources are identified. This simulated data will serve as a basis
of comparison for measured results in Chapter 5.
I. THE FREQUENCY SYNTHESIZER
The frequency synthesizer is a type II charge-pump based PLL with a 4th order loop
and architecture as shown in Figure 1. The highly integrated design includes an on-chip
dual-path loop filter and LC VCO, eliminating the need for discrete components. The
delta-sigma () fractional-N synthesizer architecture provides an output frequency that
can vary by a fractional amount of the input reference frequency, permitting the reference
to exceed the channel spacing of the communication system in question. In an integer-N
configuration, the reference frequency must be equal to the channel spacing, which is 200
kHz for the GSM standard. Since stability considerations limit the bandwidth of a type II

9

PLL to roughly one-tenth the reference frequency [10], the loop bandwidth of an integer-
N synthesizer is significantly limited, resulting in longer acquisition times and higher in-
band phase noise. For the fractional-N configuration, the higher reference frequency
permits a larger PLL loop bandwidth, translating into improved lock times and better in-
band phase noise performance. Also, the reference spurs in the output spectrum appear
further from the carrier and thus benefit from filtering of the PLL loop. The drawback is
that the fractional-N configuration will also produce fractional spurs that appear close to
the carrier and are difficult to filter out, requiring careful design of the division sequence.
The operation and circuit design of the individual frequency synthesizer components
shown in Figure 1 will be detailed in the following sub-sections, including their design
evolution along the four device iterations.

Figure 1: Frequency synthesizer block diagram including the MEMS reference oscillator
A. Phase Frequency Detector (PFD)
The PFD circuit outputs a DC voltage proportional to the phase and frequency
difference between the two input signals, as opposed to an ideal phase detector that
detects phase differences only. As a result, the PFD provides a significantly improved
lock time and acquisition range, two important system-level performance parameters. A

10

typical phase frequency detector produces two control signals, up and down, that are
related to the time difference between the rising edges of the reference oscillator and
divided RF oscillator waveforms. The up and down signals are fed to the charge pump to
indicate whether the charge on the loop filter capacitors should be increased or decreased,
translating to a modification of the VCO control voltage.
The PFD circuit used here is a conventional design utilizing a pair of D flip-flops and
an AND gate, as shown in the Figure 2 below. An additional delay (not shown) is also
included in the reset path to ensure that there is no dead zone. The dead zone is when the
PFD is not sensitive to small changes in phase because the switching time of the charge
pump currents is longer than the propagation delay though the reset path of the PFD. The
control signal generator in Figure 2 is a PFD output stage that was originally proposed in
[6] and is used to convert the two up and down signals to a set of control signals designed
to reduce charge injection and clock feedthrough effects in the charge pump.
The phase frequency detector circuit did not undergo any significant changes during
the optimization of the frequency synthesizer from iteration one to four.

Figure 2: Phase frequency detector schematic diagram [3]
B. Charge Pump (CP)
The role of the CP is to charge or discharge the loop filter capacitor in order to
generate a tuning voltage for the VCO. The conventional CP design utilizes two switched
current sources that are controlled by the up and down signals from the PFD. For the
implementation used here (Figure 3), eight PFD control signals are used to reduce the
non-ideal effects of charge feedthrough and charge injection, which in turn reduces ripple
on the control line and spurious levels in the output spectrum. To minimize charge
feedthrough, each switch is implemented using complimentary NMOS and PMOS

11

transistors. To reduce charge injection, the eight control signals are timed such that there
is a small overlap between the time when the output branch (M
11
-M
14
) turns on and the
time when the dummy branch (M
5
-M
8
) turns off, and vice-versa [3]. Transistors M
1
, M
2
,
M
15
and M
16
form the CP current source, whereas transistors M
3
, M
4
, M
9
and M
10
mirror
the presence of switches in the output branch, improving current match between the
biasing and output circuitry.

Figure 3: Charge pump circuit diagram
The initial version of the CP for the first iteration of the synthesizer was as shown in
Figure 3, without the active amplifier. The addition of the active amplifier between the
two branches is used to eliminate any voltage mismatch that may exist between the two
when the switches are off [11]. As such, when the switches turn on, charge sharing
between the dummy branch and output branch is minimized. The active amplifier is
implemented using a single stage op-amp in unity-gain configuration. Without this active
amplifier, the acquisition of phase lock is delayed since the amount of charge that is
transferred to the loop filter capacitor is smaller, requiring more cycles to achieve lock.
For device four, the charge pumps were resized to improve the in-band noise performance
of the synthesizer, by maximizing the output current for a given CP noise profile, as
indicated in [12].

12

In order to be used with the dual-path loop filter, two separate current-ratioed charge
pumps are needed, as well as a third for use with a discrete off-chip loop filter, to be
detailed in Chapter 4. The three charge pumps are identical, except that their current
source transistors M
1
, M
2
, M
15
and M
16
are sized appropriately to provide the necessary
output current.
C. Loop Filter
The purpose of the loop filter is to stabilize the loop, as well as to shape the output
spectrum in order to meet system-level phase noise and lock time requirements. The
response of the PFD and CP combination to a phase step is a linear ramp, meaning that
the open-loop transfer function contains a pole at the origin [10]. Since the VCO also
contributes a pole to the transfer response around the loop, a stabilizing zero is required
from the loop filter. In the simplest case, this can be achieved by a series combination of a
capacitor and resistor connected from the charge pump output to ground. In practical
cases, this arrangement is not sufficient since a substantial amount of ripple will remain
on the control line, as well as possible feedthrough of the reference signal to the VCO,
increasing spurious levels in the output waveform. To mitigate, additional filtering and
capacitors to ground are needed, requiring further stability analysis. As an alternative, an
active loop filter may be used in cases where a switch in polarity is needed, or when the
VCO control voltage range exceeds the CP supply voltage, which is a common issue in
discrete synthesizer designs. The drawback of the active loop filter is the added noise
contribution from the op-amp.

Figure 4: Dual-path loop filter circuit schematic

13


To use either the conventional passive or active loop filter configurations above
would require a large capacitance to provide the necessary low frequency stabilizing zero,
which is not amenable to on-chip integration [3]. As a result, the fourth order dual-path
loop filter architecture initially proposed in [13], and later in [6], is used (Figure 4). The
amplifier A1 is an integrator consisting of a single-stage PMOS differential pair with
active load, whereas A2 is a customized adder circuit to be described below.
The dual-path loop filter reduces the capacitance required for the low frequency
stabilizing zero by a factor equivalent to the ratio between the CP currents fed to each
branch, denoted by the variable B in Figure 4 and the equations below. In addition to the
integrator's pole from the upper branch, the pole and stabilizing zero from the parallel RC
and adder function, a third pole is added via the low-pass filter formed by R
1
and C
1
. The
purpose of this additional pole is to improve filtering at offsets far from the carrier, thus
reducing ripple that can increase spurious levels at the VCO output. The overall transfer
function and time constants of the dual-path loop filter are as given in Equation 3 below.
As shown, the effect of the adder operation is that the effective capacitance of the
stabilizing zero (
z
) is significantly larger than the required on-chip value.
P Z TUNE
V B V V + = (1)
IN
P P
P
Z
TUNE
I
C sR C sR
R
B
sC
V
+

+
+ =
1 1
1
1
1
1
(2)
( )
( )( )
1 1
1 1
1
C sR C sR sC
BC C sR
I
V
p p z
z p p
IN
TUNE
+ +
+ +
= (3)
( )
Z P P Z
BC C R + = t =
1 P
t
P P P
C R =
2
t
1 1 3
C R
P
= t

The implementation of the adder circuit (A2) is given in Figure 5 below. The
differential pair formed by M
17
and M
18
removes the DC offset (V
REF
), whereas M
20
and
M
21
source bias currents equivalent to those of the differential pair so that any difference
between the integrator and low-pass filter output voltages is mirrored to M
23
via M
22
[3].
The common-drain stage M
41
converts the integrator output voltage (V
Z
) into a current,
which adds to the drain current of M
40
. Note that the body of M
41
is tied to source in order
to eliminate the body effect and maximize voltage swing.


14


Figure 5: Circuit schematic of the dual path loop filter adder (A2)
The disadvantage of the dual-path loop filter is that the active components contribute
to increasing the in-band noise of the PLL. On the other hand, as opposed to the
conventional op-amp based loop filter, the thermal noise from the loop filter resistors is
reduced to zero since no current flows through R
p
when the synthesizer is in lock because
the DC operating voltage of both branches is set to V
REF
. Furthermore, as mentioned
previously, another drawback is that the dual-path architecture necessitates two current-
ratioed charge pumps, increasing the required chip area and power consumption of the
synthesizer.
The loop filter design determines the PLL system bandwidth, which in turn defines
the spectral noise profile of the PLL. To minimize the total integrated noise in the PLL
output, the loop filter cutoff frequency is typically chosen to be the point of intersection
between the in-band PLL noise and the VCO noise [12]. For this application, the large
divider ratio associated with the relatively low frequency of the MEMS reference (10
MHz), combined with the quantization noise from the -modulator, leads to a relatively
high in-band noise value which requires a small loop bandwidth (< 50 kHz) to preserve
the far-from-carrier noise.
From synthesizer device 1 to device 4, modifications to the loop filter design were
made at each iteration to accommodate changes to the charge pump current and VCO
gain in order to optimize the phase noise profile of the output spectrum. The most

15

significant modification was made for device four, where the multiplier ratio B was
reduced from 12 to 4. To optimize the in-band noise of the synthesizer loop, the CP
current was increased from 2.5 A to 15 A (Table 1), with the noise contribution
remaining relatively constant. In order to limit the increase in on-chip loop filter
capacitance required to achieve this increase, the multiplier ratio was reduced to 4 and the
VCO was reduced from 225 MHz/V for device 3 to 120 MHz/V for device 4. A
secondary effect of reducing the gain of the VCO was to reduce the modulation noise
from the varactor. A summary of the dual-path loop filter parameters and overall
synthesizer loop characteristics is given in Table 2 below. Note that the stability of the
loop was ensured with a phase margin of greater than 50 across the synthesizer output
frequency range.
Table 1: Evolution of charge pump currents for different synthesizer devices
Charge Pump 1
Integrator Branch
Charge Pump 2
LPF Branch
Charge Pump 3
Off-Chip
Devices 1, 2 & 3 2.5 A 30 A 110 A
Device 4 15 A 60 A 110 A
Table 2: Summary of loop filter and synthesizer loop characteristics (Device 4)
Loop Filter Parameters
Synthesizer Loop Parameters
(11.6 MHz Reference Frequency)
Charge Pump Current 1 (A) 15 Order 4
Charge Pump Current 2 (A) 60 VCO Gain (MHz/V) 120
Current Multiplier 4 Output Resolution (Hz) 11
Total On-Chip Capacitance (pF) 1959 Output Frequency Range (GHz) 1.7-2.0
Zero Frequency (kHz) 6 Cutoff Frequency (kHz) 31
Second Pole Frequency (kHz) 150 Loop Bandwidth (kHz) 51
Third Pole Frequency (kHz) 150 Phase Margin (degrees) 57
D. Voltage Controlled Oscillator (VCO)
The parameters of the VCO, such as output power, frequency range and tuning gain
each have an important role to play in the overall PLL system architecture. In particular,
the VCO phase noise performance is critical to meeting system level noise specifications
since the noise outside the PLL bandwidth is not filtered. As a result, the oscillator design

16

is largely driven by the challenging DCS-1800 phase noise specification at 600 kHz offset
of -116 dBc/Hz, while minimizing power consumption and chip area.

Figure 6: Voltage controlled oscillator circuit schematic (Device 4)
The RF oscillator for devices 1 and 2 was implemented using a single top-fed cross-
coupled pair configuration with intertwined inductors and PMOS accumulation mode
varactors. A 5-bit digitally controlled capacitor bank was also included for coarse tuning
in order to ensure the desired output range was maintained over PVT variations. For
device 3, the topology was re-designed to optimize for phase noise by utilizing
complimentary cross-coupled pairs and a differential tank to improve voltage swing, as
well as half-circuit symmetry to reduce flicker noise conversion in the
3
/ 1 f region. The
tank inductor was also redesigned in terms of size and shape for best phase noise
performance. For device 4, the gain of the VCO was reduced with the objective of
improving phase noise performance and reducing the overall loop gain and thus the
capacitance required to achieve the low frequency stabilizing zero. The gain was reduced
by modifying the varactor design and including two fixed value capacitors on each side of
the differential tank. To achieve the reduced tuning range objectives, the digitally

17

controlled capacitor bank was also reduced to 2 bits. The circuit schematic for the
oscillator implementation of device 4 is provided in Figure 6 above.
Chapter 3 provides a detailed examination of the high-performance RF VCO design
and optimization, including a review of the different oscillator designs and different phase
noise models.
E. Multimodulus Divider
The divider in the feedback loop of the PLL is used to divide down the RF output so
that it can be compared to the reference by the PFD. The frequency synthesizer design
presented here uses a programmable 6-bit multimodulus pulse-swallow divider. A delta-
sigma modulator is used to randomize the choice of modulus and suppress fractional
spurs by shaping the spectrum so that most of the energy content appears at large
frequency offsets. The divider architecture, which consists of a prescaler, program
counter and swallow counter, is similar to the design presented in [14]. To increase speed
of operation, the programmable counters and prescaler implemented using True Single
Phase Logic (TSPL).
Note that no major modifications were made to the multimodulus divider from device
1 through to device 4.
F. Delta-Sigma () Modulator
The -modulator shapes the noise spectrum, reducing the noise level close to the
carrier and forcing more energy to higher frequency offsets where it can be suppressed by
the synthesizer loop filter. This feature is particularly important for reducing fractional
spurs that are characteristic of fractional-N frequency synthesizers. The -modulator
achieves this feat by rapidly switching between multiple divider values, while
maintaining the average value to synthesize the correct frequency.
The -modulator is a digital accumulator-based single-loop 3rd-order modulator
with multiple feed-forward, which enables fractional-N division (Figure 7). The
modulator's 4-bit output permits continuous fine control of the synthesizer's output
frequency over a larger range than would be feasible with a single-bit. Furthermore, the
use of multi-bit modulation also provides a greater range of outputs than a comparable

18

multi-bit MASH architecture, minimizing the impact of PFD non-linearity and reducing
charge pump on-time when the synthesizer is in fractional-N lock [3].

Figure 7: Accumulator-based delta-sigma modulator schematic diagram [3]
To minimize the impact of switching noise on the synthesizer output spectrum during
lock, the calculation occurs on the opposite edge of the clock compared to the phase
comparisons of the PFD. A dithering feature has also been included to reduce the
quantization noise effects. As shown in Figure 7, the modulator has a 24-bit input
resulting in a stable mean output range of 3.5 to 11.5 with 20-bit dividing each integer
step. The resulting output resolution is as given in Equation 4, which results in a
theoretical value of approximately 11 Hz for an 11.6 MHz reference frequency. The
reason for such a high resolution is that it provides the potential to improve output
frequency stability, particularly in the presence of frequency drift in the MEMS reference
oscillator. The implementation of such a feature would require the addition of an
automatic frequency control loop to dynamically control the -modulator [3].
20
2
ref
f
Resolution = (4)
Note that no major modifications were made to the -modulator from device 1
through to device 4.
II. THE MEMS-BASED REFERENCE OSCILLATOR
The reference oscillator for the frequency synthesizer system shown in Figure 1
consists of a MEMS resonator and a sustaining amplifier connected in a positive feedback
loop. Alternatively, a negative feedback configuration could also have been used, with the
sustaining amplifier contributing a 180 degree phase shift, as in the case of Pierce

19

oscillator. The drawback of the Pierce configuration is that additional appropriately sized
shunt capacitors are needed to provide the additional phase shift around the loop.
In Figure 1, the application of a DC bias voltage (V
p
) to the MEMS resonator enables
electrostatic transduction of a harmonic input voltage, exciting the first flexural vibration
mode and generating an output current from the device. As such, the sustaining amplifier
that is used to compensate for the large motional resistance of the MEMS device is
required to be of the transimpedance type, that is current in and voltage out. In this
section, design details of both the MEMS resonator and transimpedance sustaining
amplifier (TIA) are discussed.
A. The MEMS Resonator
The clamped-clamped (CC) beam resonators used here are among the simplest
resonant MEMS structures, consisting of a horizontal beam that is anchored at both
extremities above an input electrode (Figure 8). The output current that is filtered by the
mechanical resonance of the device is taken from the structure's extremities. The
magnitude of the current produced is a function of the beam's displacement ((t)), the
beam-to-electrode overlap area (A
E
) and beam-to-electrode gap spacing (g
o
), as shown in
Equation 5. The resonant frequency (f
o
) of the device is determined by geometric
properties, such as beam thickness (T
B
) and beam length (L
B
), as well as the resonator
structural material properties, such as density () and Young's modulus (E) (Equation 6).
The resonant frequency is also related to the polarization voltage, represented in (6) by
the electrostatic tuning function (). Compared to a fixed frequency crystal reference, a
MEMS resonator has the added advantage of electrostatic frequency tuning, typically
with a range of approximately 10% [9].
The MEMS resonator can be modeled using the lumped element circuit given in
Figure 9. The typical resonator transfer characteristic, also in Figure 9, displays a pair of
resonant peaks. The series resonant peak, located at f
o
, is larger in magnitude than the
parallel resonance formed by the feedthrough capacitance (C
o
). Although this linear
model can be easily integrated into conventional circuit simulators, the drawback is that
mechanical and electrostatic nonlinearities such as Duffing behavior and resonant
frequency shifting with bias voltage are not included. These effects can be accounted for
by incorporating additional nonlinear relations into a behavioral model, as is done in [15].

20

Such a model is useful for system level optimization of the reference oscillator,
particularly with regards to predicting frequency tuning and phase noise performance.

Figure 8: Scanning electron micrograph (SEM) of a 45 m long by 25 m wide CC-beam resonator (left)
and a corresponding cross-section illustrating the beam to electrode gap spacing (right) [3]
( )
( )
dt
t d
g
V A
t i
o
p E o
o
e
c
2
~ (5)
( ) | |
p
B
B
p o
V
E
L
T
V f I ~ 1 03 . 1 ) (
2

(6)

Figure 9: Resonator transfer characteristic (left) and linear circuit model (right)
The structural material used here for fabrication of the MEMS CC-beam resonator is
silicon carbide (SiC) (Figure 10), which is known to have superior mechanical properties
than silicon [3]. Whereas other research teams have used polysilicon as structural material
(e.g. CC-beams in [16]), SiC is preferable on account of its higher acoustic velocity that
permits higher resonant frequencies for equally sized devices [9]. Similarly, for the same
resonant frequency the larger SiC device would have greater power handling capability,
leading to lower insertion loss and improved noise performance. Prior to the work
conducted by Nabki et al. in [5] and [9], the use of SiC was limited due to fabrication
processes requiring high temperature and/or materials that are incompatible with CMOS.
f
0
T
r
a
n
s
m
i
s
s
i
o
n

21

For the novel MEMS process detailed in [5] and used here for CC-beam resonator
fabrication, amorphous SiC is DC sputtered at low temperature (< 300C) utilizing
materials and chemicals that are entirely compatible with CMOS processing.

Figure 10: CC-beam cross-section showing material definition and device construction [3]
The resonators fabricated for this work have a thickness of 2 m, a width of 25 m
and lengths ranging from 24 m to 64 m, corresponding to resonant frequencies of 30.5
MHz to 4 MHz, respectively. Including test pads, the entire MEMS structure measures
350 m by 130 m. With the addition of the area required for the transimpedance
amplifier, the area still compares favorably to typical crystal oscillators. The original
resonators used in conjunction with device two had a gap spacing of 200 nm, requiring a
larger polarization voltage to achieve a low motional resistance. For devices three and
four, the resonator gap was reduced to 100 nm, enabling operation with polarization
voltages as low as 2V for an 8.3 MHz device, a significant reduction from the 26V
required for the original version. In [16] a resonator's polarization voltage is shown to be
proportional to the fourth power of the gap size, consistent with the reduction observed
here. To realize the gap reduction, careful attention is needed during fabrication,
particularly with regards to gap uniformity, etch cleanliness and the release process [3].
The drawback of a smaller gap spacing is reduced power handling capability, affecting
linearity and potentially degrading phase noise performance.
B. MEMS Resonators versus Quartz Crystals
MEMS resonators operate somewhat differently than the conventional quartz crystals
they are being designed to replace. Whereas MEMS resonators rely on electrostatic
transduction, crystals use piezoelectric transduction. The greater efficiency of
piezoelectric transduction results in a smaller motional resistance, typically around 30

22

for MHz crystals, compared to 2 to 26 k for the MEMS CC-beams described here. A
similar disparity exists for quality factor, with the MEMS resonators tested here ranging
from 900 to 1600, compared to conventional AT-cut crystals that range from 10
4
to 10
5

[3]. Higher quality factors, which translate into lower jitter and lower power
consumption, have been reported for polysilicon CC-beam resonators in [16], albeit using
a thermal budget that is incompatible with CMOS post-processing. More complex
resonant MEMS devices (e.g. disk resonators in [1]) have also been shown to provide
high quality factors, in excess of 10,000 in some cases. These more complex MEMS
structures could potentially be fabricated using the same low-temperature silicon carbide
CMOS-compatible process described here without changes to the process methodology
[3].
For reference oscillators, output frequency stability over time and temperature is
imperative to providing an environmentally robust solution. A typical uncompensated
MEMS resonator has a frequency drift of 640 ppm over an 80C range [3]. On the other
hand, the AT-cut quartz crystal is the only known resonant element which can provide
less than 50 ppm frequency stability over temperature without compensation [4]. For a
TCXO, which is a crystal based oscillator that uses a thermistor or equivalent means to
generate a correction voltage that compensates for frequency drift, stability is 2.5 ppm
over temperature (-35C to + 85C). For the MEMS resonators characterized and tested
here, thermal compensation is incorporated by means of an integrated heater (Figure 10)
to improve frequency stability and extend tuning range. Note that the frequency stability
that is ultimately required from the reference oscillator depends on the communication
protocol in question. Whereas wireline protocols and wideband wireless protocols can
generally tolerate frequency accuracies of greater than 100 ppm, narrowband protocols
such as 3G cellular typically require 1.5 ppm in initial frequency accuracy and 2.5 ppm
over temperature [17].
Power handling is another area where quartz crystals outperform MEMS resonators,
with drive levels on the order of 100 W compared to only a few microwatts for MEMS
devices [3]. Greater power handling corresponds to a potentially larger voltage swing
across the resonator and thus superior phase noise performance.

23

Finally, with regards to manufacturing, a quartz crystal requires several months to be
grown. Fortunately, these crystals have achieved sufficient widespread use to make them
economical. For the MEMS resonators presented herein, being fully compatible with
standard CMOS post-processing provides them with a much shorter cycle time that is
comparable with standard integrated circuits.
C. The Transimpedance Amplifier (TIA)
The purpose of the TIA is to compensate for the high motional resistance (R
x
) of the
MEMS resonator and hence sustain oscillation in the loop. To achieve steady-state
oscillation, two conditions described by the well-known Barkhausen stability criterion
must be simultaneously met: 1) the loop gain must be equal to unity and 2) the phase shift
around the loop must be zero or an integer multiple of 2. Although steady-state
oscillation requires a unity loop gain, a value of 2 to 3 is typically required to guarantee
startup. To meet the phase shift requirement, a bandwidth that is an order of magnitude
greater than the frequency of oscillation is needed to ensure small phase shift around the
positive feedback loop.
In addition, to minimize the phase noise in the oscillator output spectrum, the TIA
design requires low input and output resistances to minimize loading of the resonator
quality factor, as shown in Equation 7, where R
i
and R
o
are the input and output
resistances of the TIA, respectively. Also in the interest of noise, the TIA circuitry needs
to be equipped with automatic gain control (AGC) capability to prevent large oscillations
from exerting the MEMS resonator non-linearities. Such non-ideal effects can degrade
phase noise both close to the carrier and far-out if the amplitude is not appropriately
optimized, as demonstrated in [7] and [15].
|
|
.
|

\
| +
+
=
x
o i
Unloaded
Loaded
R
R R
Q
Q
1
(7)
The TIA operates by amplifying the resonator output current and supplying the
associated output voltage waveform back to the MEMS device to sustain oscillation
(Figure 11). A second output is used to drive the synthesizer reference input in order to
minimize the effect on the oscillator loop gain.

24

The input stage of the TIA is based on a g
m
-boosted common-gate amplifier, which
serves the dual purpose of providing a large gain and small input resistance to reduce
loading of the resonator's Q-factor. The variable gain amplifier stage, which consists of a
differential pair with common-mode feedback to stabilize the output voltage at mid-rail,
provides a large adjustable gain in response to V
CTRL
from the AGC. The AGC circuitry,
consisting of an envelope detector circuit and comparator circuit, controls the variable
gain amplifier. The variable gain amplifier feeds an output buffer that has a small output
resistance, serving to minimize loading effects on the resonator. A performance summary
of the TIA circuit is provided in Table 3. Note that the given power consumption does not
include test buffers, and that the highest gain corresponds to the lowest bandwidth and
vice-versa.

Figure 11: Transimpedance amplifier schematic diagram
The transimpedance amplifier design underwent relatively minor modifications
during the design evolution. It is important to note that this circuit only underwent three
iterations since the TIA for device one was of an entirely different design that will not be
considered here. For device two, the basic configuration described above was
implemented. For the third iteration, the layout was reworked to widen the input traces in
order to tolerate higher input currents from the MEMS device. Additional external buffers
were also included to facilitate testing and the power supply was completely separated
from the rest of the IC synthesizer components to reduce noise coupling. For device four,

25

capacitive compensation was added to the TIA, which resulted in a slightly smaller
bandwidth, but also improved stability. In addition, on-chip decoupling capacitors were
included to permit the CMOS synthesizer/TIA IC and resonator die to be packaged
together without the use of external capacitors. Finally, also for device four, the buffers
were reworked to reduce the circuit's power consumption.
Table 3: Transimpedance amplifier performance summary
Performance Parameter
Simulated Value
(4 pF Loads)
Input Resistance () 100
Output Resistance () 60
Gain (k) 11.2 to 398.1
Bandwidth (MHz) 74 to 217
Power Consumption (mW) 2.8
Supply Voltage (V) 2
Chip Area (mm
2
) 0.24
III. SYNTHESIZER SYSTEM NOISE ANALYSIS
There are two types of noise that are of concern for synthesizer designers: spurious
noise and phase noise. Deterministic in nature, spurious noise is typically caused by
periodic disturbances in the supply voltage or control line voltage, the latter of which can
be caused by regularities in the divider sequence or charge injection from the output stage
of the PFD or CP. As mentioned previously, the synthesizer design implemented here
uses dithering to reduce spurious associated with the divider sequence, whereas dummy
branches are used to minimize the effects of charge injection from the PFD and CP.
Contrary to spurious noise, phase noise is caused by random noise sources, such as
thermal noise, device flicker noise and shot noise. To minimize phase noise, a number of
strategies were employed, which are the main subject of this section. Whereas spurious
noise appears as easily recognizable spikes in the output spectrum, phase noise appears as
a skirt around the carrier frequency.
By reducing the phase noise in the PLL system, higher modulation rates may be used,
resulting in increased capacity. Lower phase noise also translates to reduced interferer
effects such as reciprocal mixing, permitting narrower channel spacing and more efficient

26

use of bandwidth. As a result, the objective of every synthesizer design is to minimize
phase noise, while also minimizing power consumption and chip area. This section will
focus on design strategies for minimizing output phase noise of fully integrated
synthesizer circuits.
A. Component Phase Noise
Predicting PLL output phase noise, through simulation and sometimes measurement,
is an important part of synthesizer design. Each system component needs to be analyzed
to determine the noise voltage or current it generates. This noise value can then be
multiplied by the appropriate noise transfer function, depending on the location of
injection in the loop, with the result providing the component's contribution to the
synthesizer output phase noise. Assuming the different noise sources in the system are not
correlated, the output phase noise spectrum can then be calculated using superposition.
Note that this assumption fails if the dominant source of noise is common to the different
system components, as would be the case if substrate or supply noise were strongest [18].
In the following sub-sections, each PLL component is reviewed in the context of its
contribution to synthesizer output phase noise.
1) Reference Oscillator Noise
The reference oscillator noise is an important contributor to the output phase noise of
the system. Depending on the in-band noise requirements, different types of reference
sources may suffice. For GSM, the spot phase noise for the reference at 1 kHz offset from
the carrier is a stringent -130 dBc/Hz, which has typically required the use of a crystal
based oscillator such as a TCXO. According to Leeson's phase noise model, oscillator
phase noise is determined by the loaded quality factor of the tank, the device noise factor
and the average output power. The main difference between a reference oscillator and an
RF oscillator is in the quality factor of the tank, which can be three orders of magnitude
higher for the reference. Other phase noise models also exist, which consider the time-
varying and non-linear properties of the oscillator. These models, as well as other
oscillator phase noise concepts, are closely examined in Chapter 3.
When fed into the synthesizer loop, the reference phase noise is multiplied by the
closed loop gain of the PLL, which is equivalent to 20log(N) within the loop bandwidth.
As a result, the motivation has been to minimize the divider ratio by maximizing the

27

reference frequency. The fractional-N architecture, in which the output frequency can be
produced at fractional multiples of the reference frequency, was developed with this
objective in mind.
2) PFD Noise
The noise from the PFD undergoes the same noise transfer function as the reference,
except that the PFD typically has a significantly lower noise voltage and is therefore not a
major contributor to output phase noise in the PLL system [18]. Nonetheless, as with all
active devices, particular attention should be paid to minimize device flicker noise, as
well as substrate and supply noise.
3) CP Noise
The CP noise contribution to the PLL output phase noise is determined by the
magnitude of the current noise and the PFD dead zone pulse width. Whereas the CP noise
magnitude is determined by device noise, the effect of the dead zone pulse width is less
obvious. As mentioned previously, in order to ensure that the PLL is sensitive to small
differences in input phase, a delay is added to the reset path of the PFD flip flops.
Although the average current to the loop filter remains zero, this small phase difference
causes the CP to source and sink current even when the PLL is in lock. The noise injected
by the CP during lock is given by Equation 8 below, where
dz
is the delay in the reset
path and T is the period of the reference signal [12]. This leads to two important
conclusions about CP noise: 1) The dead-zone pulse width should be minimized, and 2)
The charge pump will inject more noise for higher reference frequencies.
2
,
2
,
2
noise CP
dz
CP n
I
T
i |
.
|

\
|
=
t
(8)
Equation 9 illustrates the noise transfer function for the CP current noise, where G(s)
is the open loop gain, H(s) is the feedback factor, Z() is the loop filter transfer function,
K
VCO
is the VCO gain, N is the divider ratio and I
CP
is the charge pump current. Observe
that the output phase noise contribution from the CP can be minimized by maximizing the
output current for a given noise level. Note that optimization of the CP is such a way also
requires adjustment to loop filter component values if the same loop parameters
(bandwidth, phase margin, etc.) are to be maintained.

28

VCO
CP
VCO
CP CP n
out
K Z
N
I
j
K Z
s H s G
s G
I s i
s
+

=
+
=
) (
) ( 2
) ( ) ( 1
) ( 2
) (
) (
,
e e
e t t u
(9)
4) Loop Filter Noise
The loop filter noise contribution varies depending on the particular design approach.
For discrete circuit implementations, there is the option of using a passive loop filter or an
active loop filter. While the passive version benefits from lower noise, consisting only of
thermal noise from loop filter resistors, it requires a very large capacitance to provide the
necessary low-frequency zero. For the active design, device noise associated with the op-
amp and thermal noise from the resistors typically provides higher total noise at the VCO
input, albeit with slightly smaller capacitance values. The other advantage of the active
design is that the VCO control voltage is limited only by the op-amp supply voltage,
permitting its use with RF oscillators that require extended tuning voltages, often 15 V or
more. Although typically restricted to discrete designs, these oscillators can achieve the
desired frequency range with a very low tuning sensitivity, allowing for improved phase
noise performance. Note that for both active and passive instances, the size of resistors
used should be kept to a minimum to minimize thermal noise contributions and thus the
system noise floor. For fully integrated loop filter designs, even the capacitance
associated with the conventional single op-amp active design is too large for effective on-
chip integration. As such, the dual-path approach is selected, requiring the addition of a
significant amount of active circuitry to save on overall chip area, increasing device
flicker and shot noise.
The noise transfer function for the loop filter noise, which is the same as noise on the
VCO control line, is as given in Equation 10 below. As can be observed the noise
contribution from the loop filter is strongly related to the gain of the VCO, and is also
shaped differently than for the previously mentioned PLL components. The loop filter
transfer function, Z(), has a strong influence on the noise shaping, as well as other PLL
system performance parameters, such as lock time. Noise shaping will be reviewed in-
depth in the next section.
VCO
CP
VCO VCO
LF n
out
K Z
N
I
j
K
s H s G j
K
s v
s
+
=
+

=
) (
) ( ) ( 1
1 2
) (
) (
,
e e
e
t u
(10)

29

5) VCO Noise
Noise from the VCO is determined by several factors, as shown in Leeson's equation
(Equation 11). Resonator implementation, varactor design and active circuitry all have an
important role in determining the VCO's contribution to output phase noise. The transfer
function of the VCO contains a pole at the origin, which shapes the noise injected by the
active and passive devices in the oscillator circuit. As such, the noise close to the carrier
decreases at a rate of
3
/ 1 f due to flicker noise contribution of active devices, and reduces
to
2
/ 1 f beyond the flicker corner frequency, until the resonator half-bandwidth, where
the noise spectrum flattens out. For reference oscillators, where the quality factor of the
resonator is much larger, the resonator half-bandwidth generally lies inside the flicker
corner frequency, resulting in a slightly different spectrum profile. Not accounted for in
the Leeson model are the time-varying properties of the oscillator, as well as non-linear
effects, two phenomena that make VCO noise the difficult to predict. A detailed
discussion of alternative phase noise models and strategies for minimizing VCO noise
will be discussed in Chapter 3.
{ }

A
+
|
|
.
|

\
|
A
+
(
(

|
|
.
|

\
|
A
+ = A
2
2 2
2
_
8
1
2
1
2
log 10
e
t
e
e
e
e
e
o c o
avg s
kTRK
Q P
FkT
L
(11)
{ }
resistance noise equivalent varactor
gain tuning oscillator
power output oscillator average
e temperatur absolute
constant s Boltzman'
factor noise excess device
circuit tuned of Q loaded
frequency corner flicker
frequency n oscillatio
carrier the from frequency offset
dB in power total to at bandwidth Hz 1 a in power sideband of ratio
=
=
=
=
=
=
=
=
=
= A
A = A
R
K
P
T
k
F
Q
L
o
s_avg
c
o
e
e
e
e e

6) Multimodulus Divider Noise
The noise from the multimodulus divider that appears at the input to the PFD also
experiences the same noise transfer function as noise from the reference. Digital dividers,
as in the current implementation, typically exhibit substantial white noise, which adds to
the noise of the reference oscillator at the PFD input. If the divider is implemented using

30

active devices with large device flicker noise, it is possible that it may swamp the
reference noise completely [18].
7) Delta-Sigma () Modulator Noise
As mentioned previously, the -modulator shapes the noise spectrum, reducing the
noise level close to the carrier and forcing more energy to higher frequency offsets where
it can be suppressed by synthesizer loop filter. As a result, a well-designed delta sigma
fractional PLL with a third-order loop can shape noise to levels far below other noise
contributors [19].
B. Noise Shaping
The phase noise produced by each of the PLL components is uniquely shaped,
depending on the point of injection. The reference oscillator, PFD, and divider noise are
all shaped by the same low-pass noise transfer function (Equation 12). Inside the PLL
loop bandwidth, this transfer function effectively multiplies the component noise by the
divider ratio, N. The CP noise is shaped by the same low-pass relation, except that the
magnitude is increased by a factor equal to 2 divided by the charge-pump current
(Equation 9). For the loop filter and VCO noise, a high-pass transfer function provides
attenuation inside the synthesizer loop bandwidth.
VCO
CP
VCO CP
div
out
PFD
out
ref
out
K Z
N
I
j
K Z I
s H s G
s G
s
s
s
s
s
s
+

=
+
= = =
) (
) (
) ( ) ( 1
) (
) (
) (
) (
) (
) (
) (
e e
e
u
u
u
u
u
u
(12)
Figure 12 illustrates the effect of shaping on the noise of the TCXO, CP, loop filter
and VCO, respectively. The component noise profiles in the left hand column are
obtained either from specification data, as in the case of the commercial TCXO, or
Cadence noise simulations for the remaining components. Using MathCAD calculation
software, the component noise curves were then multiplied by their corresponding ideal
noise transfer functions to obtain the shaped noise profiles in the right hand column.
Clearly evident are the low-pass and high-pass shaping associated with the different
components.

31


a) TCXO component noise profile (left) and contribution to system noise following noise shaping (right)

b) Charge pump component noise profile (left) and contribution to system noise following noise shaping (right)

c) Loop filter component noise profile (left) and contribution to system noise following noise shaping (right)

d) RF VCO component noise profile (left) and contribution to system noise following noise shaping (right)
Figure 12: Component noise shaping for TCXO, charge-pump, loop filter and RF VCO

32

A determining factor in the way the noise is shaped by the PLL is the design of the
loop filter. The choice of bandwidth determines how the different component noise
profiles are translated into synthesizer output noise. Whereas a small loop bandwidth
improves rejection of out-of band noise, a wider loop bandwidth provides better
suppression of close-to-carrier VCO noise, as well as a faster lock transient. A good
strategy to minimize the integrated phase noise of the PLL output is to design the loop
filter bandwidth to be where the in-band noise and VCO noise intersect. If the loop is too
narrow, the VCO noise will cause an overshoot in the phase noise plot, which is
sometimes incorrectly diagnosed as a stability issue. On the other hand, if the loop is too
wide, the out-of band noise is degraded unnecessarily. To ensure stability across all
operating conditions, a phase margin of at least 45 degrees should be maintained at all
times.
Compared to discrete designs, optimization of a PLL with fully integrated loop filter
requires accurate characterization and modeling of component noise a priori. For discrete
designs, optimization of noise may be done iteratively, by cycling though CP current
values and subsequently modifying loop filter components as needed. For this reason,
component noise modeling and simulation, as shown here for this design, is a necessary
step in evaluating and optimizing fully integrated frequency synthesizers.
Using superposition to combine the shaped component noise contributions shown
above, the overall PLL output noise can be evaluated (Figure 13). For this design, noise
simulation in Cadence followed by shaping and summation in MathCAD indicates that
the in-band noise is dominated by the dual-path loop filter. This same behavior was also
observed in [6], where the dual-path loop filter design was initially presented. Compared
to a conventional passive filter that requires no biasing circuitry, or to a conventional
single op-amp active loop filter, the dual-path loop filter is relatively power hungry on
account of the adder circuitry.
Also evident in Figure 13 is that the synthesizer output phase noise is dominated by
different noise sources at varying frequency offsets. For small offset frequencies (10 Hz
to 1 kHz), the noise is dominated by the reference phase noise, by the loop filter for
intermediate offset frequencies and by the VCO for large offset frequencies. The far from
carrier noise floor is determined by the circuit's thermal noise sources.

33

In the next section, simulation of the PLL system is revisited using simulated phase
noise data from the MEMS-based reference oscillator.

Figure 13: Simulated PLL output phase noise and individual component contributions (TCXO Reference)
C. MEMS Resonator Phase Noise
For all resonators, the higher the quality factor, the better the noise filtering and the
lower the phase noise of the output. Similarly, a higher power handling capability of the
resonator corresponds to better phase noise since a higher voltage swing can be
maintained. On a system level, a higher resonator operating frequency corresponds to
lower in-band noise because of lower multiplier factors, which is equally true for any type
of reference. Designing the sustaining amplifier to minimize device flicker and shot noise
is imperative for oscillator performance optimization, as this noise is shaped by the
feedback loop.
Designing a MEMS based oscillator for minimum phase noise also requires careful
balancing of both the resonator drive level and bias voltage. Equipping the TIA with
automatic gain control capability limits the resonator drive level, reducing the effects of
non-linearities and improving close-in phase noise. The higher the quality factor of the
resonant device, the greater the sensitivity to drive level due to the increased mechanical
displacement that is inherent to higher-Q structures [15]. For optimal far out phase noise,
maximizing the drive level provides best performance. As a result there is an optimal
amplitude of oscillation for best overall phase noise.

34

A similar tradeoff is apparent for the resonator polarization voltage level. The optimal
polarization voltage is where V
p
is sufficiently high to provide a low motional resistance,
but not to excite resonator nonlinearities. The lower the motional resistance, the lower the
gain needed from the TIA to sustain oscillation, reducing the amplification of noise. At
high bias voltages, non-uniform static bending of the beam is more pronounced, initiating
the non-linear phenomenon and degrading close-in phase noise [15]. Observing the
forward transmission coefficient, S21, the resonator non-linearities cause a noticeable
slant in the peak, as well as a resonant frequency shift in some instances. Finally,
operating the MEMS device in vacuum reduces the effects of air damping, increasing
resonator displacement and providing improved phase noise both close-in and far-out.

Figure 14: MEMS oscillator phase noise profile
Because of the low quality factor of the MEMS resonators presented here compared
to a crystal, the shape of the noise spectrum is likely to be somewhat different. Depending
of the relative position of the flicker noise corner frequency and the resonator bandwidth
(f
o
/2Q), the slope of the phase noise spectrum at different frequency offsets varies. For
high Q-factor oscillators, such as MEMS-based and crystal based oscillators, the
resonator bandwidth lies within the flicker noise corner, resulting in a
3
/ 1 f region and a
f / 1 region (Figure 14), as opposed to a low-Q RF oscillator, which also has a
2
/ 1 f
region because of a larger resonator bandwidth. For the MEMS based oscillator designed

35

here, compared to a crystal based version, the f / 1 can be expected to be much smaller on
account of the difference in Q-factor.
In [15], Nabki and El-Gamal developed a modeling and simulation approach for
MEMS CC-beam resonator based oscillators that accounts for the electrostatic and
mechanical non-linearities described earlier. As opposed to conventional linear models,
this approach captures non-linear effects such as Duffing behavior and shifting of the
resonant frequency. The approach was also been validated against measured forward
transmission coefficient data as part of the research. Using the noise predicted by the
MEMS based beam oscillator model in [15], the PLL system output noise simulation
analysis was revisited, using the MEMS based oscillator as reference (Figure 15).

Figure 15: Simulated PLL output noise and individual component contributions (MEMS reference)
As can be observed, while the noise from the MEMS reference undergoes the same
shaping as the TCXO shown earlier, the significantly higher noise level swamps the noise
generated by all of the other PLL components combined. As a result, it is evident that the
design of the synthesizer components has little to do with the output phase noise
spectrum, except at offsets far from the carrier where filtering from the loop filter makes
the RF VCO noise dominant.

36

IV. APPLICATION DEVELOPMENT
Based on the above analysis, although the proof-of-concept for MEMS-based
oscillators is clear, the MEMS resonators presented herein will be restricted to
applications with less stringent noise requirements until their performance can be
improved. One such utilization could be in digital applications where the synthesizer
output is divided down for use in low frequency clocking. For narrowband wireless
applications such as DCS-1800, GPS and WiFi, stringent requirements in terms of
frequency stability, phase noise and power consumption provided by TCXOs have made
developing an integrated alternative quite a challenge. Although strategies to improve
these parameters are currently underway for the MEMS-based solution described herein,
applications in the near term are targeted more towards wireline protocols, such as USB,
PCI or CANbus because of their relaxed reference frequency stability requirements.
Further details regarding application development and future directions for this
research are provided in Chapter 6.
V. CONCLUSION
This Chapter provided an overview of the frequency synthesizer system with MEMS-
based reference oscillator, detailing the different building blocks, including their circuitry
and design evolution through the four device iterations. This high-level system
description provides a basis for presenting the contributions detailed in the following
Chapters. Also included here was a section on phase noise analysis, providing each
component's potential contribution to PLL output phase noise.
With regards to MEMS resonators, the advantages they have over crystals were
shown to be a greater frequency tuning range, fabrication compatibility with CMOS
processing and a significantly reduced form factor. As indicated by simulation and
analysis data above, where the MEMS resonators need improvement compared to crystals
is in terms of quality factor, power handling, frequency stability and phase noise
performance. To optimize the output phase noise provided by the MEMS based
oscillators shown here, higher frequency devices are needed, as well as more complex
structures using the same low-temperature silicon carbide CMOS-compatible process.

37

In Chapter 5, the simulated data presented herein will be compared to measured data,
providing validation of the modeling approach.


38


Chapter 3

Integrated RF VCO Design and
Optimization







Voltage Controlled Oscillators (VCOs) are critically important for the performance of
front-end RF systems. Contrary to other PLL components, there is currently no
comparable digital replacement in sight. The parameters of the VCO, including output
power, frequency range and tuning gain each have an important role to play in the overall
PLL system design. Similarly, the phase noise introduced by the VCO to the PLL system
determines important system performance parameters, such as speed and capacity. Lower
phase noise systems permit higher modulation rates and thus more efficient use of
bandwidth, while also benefiting from higher sensitivity and reduced interferer effects
such as reciprocal mixing. As the drive for the fully integrated, single-chip radio has
advanced, the need for phase noise minimization techniques has intensified in order to
have integrated VCOs that match their discrete counterparts. The simultaneous need for
multiple integrated VCOs to accommodate the various communication standards within a
single personal electronic device (PED) has also fueled research in this area.
Until recently, Leesons phase noise theory has served as an unrivaled basis for VCO
design. Based on the linear time-invariant approach, the Leeson model has drawn
criticism as to its effectiveness to quantitatively predict phase noise, particularly since
some input parameters, such as device excess noise factor and loaded Q, are difficult to
compute a priori. More recently developed phase noise theories, such as the work

39

conducted by Hajimiri [20]-[24], takes a different route, basing itself on the time-varying
properties of the oscillator output waveform. These novel strategies, combined with the
availability of improved simulation tools, have given rise to some new insights into
oscillator design and resulted in some alternative design approaches.
This Chapter will review some basic VCO theory, followed by a discussion of noise
sources in oscillators and phase noise theory in general. The drawbacks of Leesons phase
noise model and some background theory on Hajimiris time variant approach will then
be presented. Subsequently, in Section III, different design and optimization strategies
will be applied to a baseline LC cross-coupled pair in order to minimize phase noise and
meet the stringent DCS-1800 requirements. The oscillators in question are fabricated
using CMOS 0.18m technology. Simulation and measured results of the free-running
VCO are provided in Section IV, including a review and comparison to the current state-
of-the-art in LC VCO design. The measured closed loop data within the high resolution
fractional-N PLL system is provided in Chapter 5.
I. VCO THEORY
An ideal oscillator provides a periodic output waveform at a single frequency and its
harmonics, which is subsequently used in RF communications systems, as well as to
provide a timing reference for digital electronics. Using a simple feedback circuit with a
frequency selective network in the loop, the oscillator transfer function may be given as
follows:
) ( ) ( 1
) (
) (
) (
o o
o
o
o
j j A
j A
j X
j Y
e | e
e
e
e

= (13)
To achieve steady-state oscillation at a frequency
o
, two conditions described by the
well-known Barkhausen stability criterion must be simultaneously met [10]: 1) the loop
gain, |A(j
o
)|, must be equal to unity and 2) the phase shift around the loop must be zero
or an integer multiple of 2. Note that the Barkhausen criterion is a necessary, but not
sufficient requirement for oscillation, since in some circumstances the circuit may latch
up rather than oscillate [10]. Additionally, while unity loop gain is a sufficient condition
for steady-state oscillation, a loop gain of 2 to 3 is typically required to guarantee start-up
[25]. Once the circuit begins to oscillate, the amplitude grows until ultimately limited by

40

saturation of the amplifier, or resonant device, as may be the case for MEMS based
oscillators.
An alternative view of the oscillator is the negative resistance model in which two
one-port networks are connected to each other. Whereas one network represents the
frequency selective resonator circuit, the second network is the sustaining amplifier
circuit used to compensate for energy loss in the former. While this view is intuitively
obvious for single transistor oscillators, it is equally applicable for cross-coupled pairs
where the input impedance is known to be
m
g / 2 , g
m
being the transconductance of
each transistor. In this case, the condition for oscillation is simply that the negative input
impedance be greater that the loss in the resonator. The same start-up considerations
listed above are equally applicable to this model.
Different types of oscillators are typically characterized by their circuit topology and
resonator implementation. In the former, Colpitts and Hartley oscillator configurations
utilize transformation networks in their feedback path to increase the impedance observed
by the tank [10], whereas negative-Gm differential oscillators connect the resonator
directly in parallel with a cross-coupled pair. Because of their simplicity, most CMOS
oscillators, including the version examined here, are of the negative-Gm type [26].
As for resonator implementation, a number of different options exist depending on the
intended application and associated performance requirements. A resonator`s
performance is measured by its quality factor, which is defined as the ratio of the energy
stored to the energy dissipated per cycle [10]. As a result, the higher the quality factor of
the resonator, the lower the loss in the circuit. For discrete oscillators, quality factors well
in excess of 1000 are achievable for ceramic resonators, although microstrip resonators
offer a lower cost, albeit less performing option. For integrated GHz oscillators, LC tanks
are the most commonly used resonators, although the emergence of high-Q alternatives,
such as the wine glass MEMS resonator presented in [8] and the thin-film bulk acoustic
wave resonators (FBAR) in [1], bode well for future implementations. For LC-based
oscillators, the frequency of oscillation is given by (14), and the quality factor of the
resonator is given by (15), where R
P
is the equivalent parallel resistance of the tank.
LC
O
1
= e (14)

41

O P
O
P
C R
L
R
Q e
e
= = (15)
An alternative to LC oscillators for GHz applications is the ring oscillator, which
requires no resonator at all. For ring oscillators, which consist of an odd number of
identical inverters connected in a closed loop, the period of oscillation is equivalent to
twice the sum of the gate delay in the ring [27]. Although the omission of the resonator
allows these circuits to be much more compact and simpler to design [10], they consume
more power and are much noisier, making them impractical for use in wireless cellular
receivers [27], and primarily restricted to digital clock type applications.
II. PHASE NOISE THEORY
Noise generated by oscillator components, as well as external noise sources, such as
power supply noise or noise on the control line, has been known to perturb the oscillator
output waveform, both in amplitude and frequency. Whereas variations in amplitude are
generally ignored on account of the fact that they are limited by the gain control
mechanism of the oscillator [22], frequency deviations cause the ideal zero-crossing
points to shift in the time-domain output waveform [10], a process known as timing jitter
or phase noise. In the frequency domain, phase noise causes the spectrum to exhibit
undesired frequency components around the carrier, sometimes referred to as a "skirt"
[10]. Phase noise is quantified as the noise power contained in a 1 Hz bandwidth at a
particular offset from the carrier, measured relative to the average power of the carrier, in
units of dBc/Hz.
The effect of phase noise on the system level is significant, which is why a substantial
amount of research has been conducted into understanding and explaining the generation
mechanisms [20][27]-[30]. In digital electronics, excessive timing jitter can amount to
synchronization problems, whereas in RF communication systems, the phase noise of the
reference oscillator, the local oscillator and the RF oscillator all influence the noise
profile of the output signal. By reducing the phase noise in the PLL system, higher
modulation rates may be used, resulting in increased capacity. In addition, reduced phase
noise also translates to reduced interferer effects such as reciprocal mixing, permitting
narrower channel spacing and more efficient use of bandwidth. With respect to phase

42

noise performance, different communication standards will impose different
requirements, either in terms of a spot noise specification (e.g. DCS-1800, UMTS, GPS),
an integrated noise specification (e.g. WLAN), a time domain specification in terms of
jitter (e.g. SONET) or as a combination of the above.
Phase noise is caused by different elements, both internal and external to the
oscillator. Device noise such as flicker noise, thermal noise and shot noise are examples
of internal noise sources, whereas power supply noise, substrate noise and control line
noise are examples of external noise sources.
Apart from the transistor noise effects listed above, the varactor, as part of the LC
tank, is susceptible to variations in the oscillation amplitude, power supply and control
voltage, each of which can modulate its capacitance by a small amount and slightly alter
the oscillation frequency, as described in [31]. Similarly, any change in the bias current,
which translates into a change in oscillation amplitude assuming operation in the current-
limited regime, can also modulate the parasitic capacitance of the transistors and cause a
shift in frequency [32]. The current-limited regime is the mode of operation whereby an
increase in bias current increases the oscillation amplitude [21], improving the phase
noise of the oscillator. On the contrary, in the voltage-limited regime, the oscillation
amplitude is limited by the power supply and no benefit to the voltage swing is achieved
by an increased bias current [21]. Each of the above cases are examples of AM-to-FM
conversion and are considered modulation noise sources [25].
A. Leeson Phase Noise Model
The Leeson phase noise model, first presented in [28], is a linear, time-invariant
model that has served as a basis for evaluating the spectral behavior of oscillators for
quite some time. The simple derivation, summarized hereunder, starts with the basic
assumption that the only source of noise in the oscillator is the white thermal noise of the
tank [22]:
f
R
kT
i
n
A =
4
2
(16)
bandwidth frequency
resistance tank
e temperatur absolute
constant s Boltzman'
= A
=
=
=
f
R
T
k


43

For the negative resistance model of an oscillator, recall that in steady-state the
negative resistance of the active circuit exactly cancels the loss in the tank. As a result,
the impedance seen by the current noise source above is simply a lossless LC network
[22]. For a small offset from the carrier, e A , the impedance of the LC tank may be
approximated as shown in (17). Recalling the expression for resonator quality factor from
Equation (15), the magnitude of the tank impedance is as given in (18).
( )
e
e
e e
A
~ A +
2
2
L
j Z
o
o
(17)
( )
e
e
e e
A
= A +
Q
R
Z
o
o
2
(18)
To solve for the mean-square voltage spectral density, multiply the mean-square noise
current in (16) by the square magnitude of the impedance defined in (18). The result in
(19) contains the effect of thermal noise on both amplitude and phase of the oscillator
output. According to the thermodynamics law of equipartition, the amplitude noise and
phase noise are equal at equilibrium [22], meaning the expression should be divided by
two to account for phase noise only. Normalizing the result by the mean square voltage
density of the carrier and writing in terms of decibels, the single-sideband noise spectral
density is as shown in (20), with units in dBc/Hz.
2
2
2 2
2
4
|
|
.
|

\
|
A
=
A
=
A e
e
Q
kTR Z
f
i
f
v
o n n
(19)
{ }
(
(

|
|
.
|

\
|
A
= A
2
_
2
2
log 10
e
e
e
Q P
kT
L
o
avg s
(20)
To this point, the noise model is still incomplete as other important noise sources
have not yet been accounted for. As such, the phase noise spectrum in (20), with only a
single
2
/ 1 f region, does not exhibit the shape typically expected for an oscillator. In a
practical oscillator, the phase noise flattens out at large offsets from the carrier. This noise
floor has a level that is largely determined by thermal noise generated within the circuit,
whereas its corner is a function of the resonator half-bandwidth. In addition, there is also
the
3
/ 1 f noise region at small offsets from the carrier. For the Leeson model, the

44

assumption is that the
3
/ 1 f corner of the spectrum is the same as the flicker noise corner
frequency of the active device [20]. Finally, there is the effect of the modulation noise of
the varactor for which Leeson's model is sometimes modified to include. For instance, in
[25], a term that incorporates the tuning gain of the oscillator, K
o
, as well as the thermal
noise associated with the tuning diode's equivalent resistance, has been added. Equation
(21) accounts for all of the above effects, providing a closed-form expression for the
phase noise spectrum of an oscillator. Note that the quality factor term in (21) has been
generalized to represent the loaded quality factor, which accounts for tank loading by
other loss mechanisms in the oscillator.
{ }

A
+
|
|
.
|

\
|
A
+
(
(

|
|
.
|

\
|
A
+ = A
2
2 2
2
_
8
1
2
1
2
log 10
e
t
e
e
e
e
e
o c o
avg s
kTRK
Q P
FkT
L
(21)
{ }
resistance noise equivalent varactor
gain tuning oscillator
power output oscillator average
e temperatur absolute
constant s Boltzman'
factor noise excess device
circuit tuned of Q loaded
frequency corner flicker
frequency n oscillatio
carrier the from frequency offset
dB in power total to at bandwidth Hz 1 a in power sideband of ratio
=
=
=
=
=
=
=
=
=
= A
A = A
R
K
P
T
k
F
Q
L
o
s_avg
c
o
e
e
e
e e

B. Limitations of Leesons Phase Noise Model
Leesons phase noise model is practical in that it provides important qualitative
design insights, such as the tendency of phase noise with respect to loaded quality factor
and voltage swing. While these qualitative insights are useful to consider during oscillator
design, Leesons phase noise model lacks predictive power when it comes to providing an
accurate quantitative assessment of phase noise performance at a particular offset from
the carrier. A primary reason for this is that some of the input parameters, such as device
excess noise factor, loaded Q and output power are difficult to predict a priori and
therefore must be estimated in most cases [25]. Similarly, the portion of Leeson's
equation equating the
3
/ 1 f corner to the flicker corner frequency of the device is
completely empirical and has no theoretical basis [20].

45

Critics argue that the underlying theory of Leesons model is fundamentally flawed in
that it uses a linear approach to quantify non-linear phenomena. From Leeson's model the
best oscillator phase noise requires a large signal amplitude, which means the active
circuit needs to be driven well beyond its linear range [33]. For a linear relationship, an
increase in the injected noise should result in a directly proportional increase in the
disturbance; which is not always the case due to the limiting effect of the oscillator active
devices, particularly in the voltage limited regime. As a result, the one half factor
introduced based on the thermodynamics law of equipartition is not valid in all modes of
operation.
The basis of Leeson's equation, being LTI, only models noise sources in the vicinity
of the carrier [20], not considering frequency conversion phenomena capable of
downconverting noise. The Leeson model assumes that the quality factor of the tank is
sufficiently high that it filters out all harmonics [25], although it has been shown that the
noise surrounding those components are subject to folding that can significantly increase
the device noise factor [33]. In addition, the time-invariant assumption of the Leeson
model treats the oscillator noise mechanism under steady-state conditions [27], meaning
the time dependency of the injected impulse is not considered and all noise sources are
treated as stationary processes.
C. An Alternative Phase Noise Model
As opposed to Leeson's model, the Hajimiri model treats oscillators as linear time-
varying (LTV) systems. In [20], the linearity assumption is demonstrated by injecting
current impulses to the circuit and measuring the corresponding phase change. As the
magnitude of injected charge increases, so does the observed excess phase, in practically
linear proportion. Although the current-to-phase relationship is linear, note that the phase-
to-voltage relationship is nonlinear on account of the oscillator active device.
A useful analogy in understanding the basis of Hajimiris time-varying theory is to
observe the effect of a noise impulse on a periodic signal. Basically, there are three
different instances when the noise impulse can be injected on the periodic signal; at a
peak, at a zero crossing, or somewhere in between. When the noise is injected at the peak
of the waveform, the result is strictly a change in amplitude. Similarly, when the noise
impulse is injected at the zero crossing, the result is solely a change in phase. Finally,

46

when the injection is somewhere in between the peak and the zero crossing, both the
amplitude and phase are affected. A previously mentioned, variations in oscillation
amplitude are generally ignored on account of the fact that they are limited by the gain
control mechanism of the oscillator [25]. As a result, according to Hajimiris theory, in
order to minimize phase noise, techniques should be adopted to ensure that the noise
impulse coincides with the time of the output voltage peaks [25].
Hajimiri introduced the impulse sensitivity function (ISF) to model this time-varying
sensitivity and quantify the circuits susceptibility to injected noise. The impulse
sensitivity function is determined by the shape of the oscillation waveform, which is in
turn is governed by the nonlinearity of the active device and the topology of the oscillator
[20]. The ISF is also dimensionless and periodic with a period of 2. The best way to
understand the significance of the impulse sensitivity function is through an example.
Figure 16 illustrates the oscillation waveforms and the corresponding ISFs of an LC
oscillator and a ring oscillator that were originally presented in [20]. As can be observed,
a maximum value in the oscillation waveform corresponds to an ISF value of zero, and a
zero crossing in the oscillation waveform corresponds to a maximum in the ISF.

Figure 16: Waveforms and corresponding ISFs for an LC oscillator (left) and a ring oscillator (right) [20]
Exact analytical derivations of the ISF are not simple for most oscillators, although
three different methods to calculate the ISF are provided in [20]. The first method is a
direct measurement of the impulse response by sweeping the impulse injection time
across one cycle of the waveform and measuring the resulting time shift. Although
seemingly simple, this method is prone to numerical errors as the impulses must be kept
sufficiently small in order not to excite a nonlinear response from the oscillator [34]. The
second method is a closed-form representation that expresses the ISF as a function of the

47

first and second derivatives of the oscillation waveform, as shown in Equation (22)
[20][22]. Finally, the third method is an approximation of the ISF based on the first
derivative, where the denominator of the closed-form formula of the ISF is approximated
by a constant, as shown in Equation (23) [20].
2 2
' ' '
'
) (
f f
f
w
o
+
= I t
(22)
2
max
'
) ( '
) (
f
x f
w
o i
= I t
(23)
To derive an expression for the output signal phase noise spectrum as a result of an
injected disturbance, the LTV current-to-phase conversion needs to be combined with a
second nonlinear phase modulation process representing the phase-to-voltage
transformation [20]. Hajimiri represents this overall conversion as a cascade of the excess
phase transfer function with a second transfer function representing the well known
fundamental harmonic of the oscillator output ( ) | | t t t V
o
| e + = cos ) ( .
To evaluate the excess phase using Hajimiri's approach, the impulse response of the
current-to-phase conversion is needed. Based on the assumptions of linearity and time-
invariance provided above, the impulse response may be written as given in Equation
(24), where
max
q is the maximum charge swing across the capacitor at the node where the
disturbance is injected [20]. As can be seen, the impulse response is a step whose
amplitude depends on the time at which the impulse was injected [20]. Using the
superposition integral and expressing the periodic ISF as a Fourier series, an expression
for excess phase can subsequently be obtained [20], which explains how sidebands can
appear in a oscillator's output spectrum (Equation (25)). Observe that for an injected
current close to any integer multiple of the oscillation frequency, of the form
( ) | | t n I t i
o n
A + = e e cos ) ( , two equal sidebands will result at e A from the carrier in
the frequency spectrum. Note that the presence of these sidebands cannot be explained by
a simple LTI model, such as Leeson's, since such a system cannot produce any
frequencies except for those associated with the input or the system poles [20].
( )
( )
( )
( )
( ) t
t e |
t
|

I
= = t u
q t i
t
t h
o
max
, (24)

48

( ) ( ) ( ) ( ) ( )
(

+ = =
}

} }

t
n
t
o n
o
d n i c d i
c
q
d t i t h t
1 max
cos
2
1
) ( , t t e t t t t t |
|

(25)
In addition to Hajimiri, other researchers have also come to the same conclusion
regarding the conversion of noise sources around harmonics of the oscillation frequencies
into phase noise. In [33], thermal noise around odd harmonics and shot noise around even
harmonics of the oscillation frequency are shown to cause an increase in the
transconductor noise factor by means of noise folding, also creating sidebands around the
carrier, which in turn become close-in phase noise.
Calculating the sideband power relative to the carrier for the overall cascaded
conversion expression, and subsequently converting to units of dBc/Hz, the total single
sideband phase noise spectral density in the
2
/ 1 f region is given as in (26). For the
3
/ 1 f
region, located at small offsets from the carrier, the only relevant coefficient is
o
c , which
simplifies the noise expression to (27) [20].
{ } region
f
f
i
q
L
n
rms
2 2
2
2
max
2
1
4
log 10
(
(
(

A
A

I
= A
e
e
(26)
{ } region
f
f
i
q
c
L
f
n
O
3
/ 1
2
2
2
max
2
1
8
log 10
(
(
(

A
A
= A
e
e
e
e
(27)
capacitor resonator on charge maximum
frequency corner flicker device
carrier the from frequency offset
ts coefficien series Fourier
(ISF) function y sensitivit impulse
bandwidth current noise input
density spectral power current noise input
max
/ 1
2
2
=
=
= A
=
= I
= A
=
A
q
c
f
f
i
f
n
rms
n
e
e

Equating the two expressions to solve for the
3
/ 1 f corner frequency leads to the
expression in (28). Contrary to Leeson's model, this approach shows that the
3
/ 1 f phase
noise corner is actually smaller than the f / 1 device noise corner [20].

49

2
2
/ 1
/ 1
2
3
rms
o
f
f
c
I
=e e (28)
The analysis addressed thus far quantified the phase noise contribution of a single
noise source. To extend this approach to multiple noise sources at multiple nodes, the
concept of superposition needs to be employed, with special attention paid to any
potential correlations between noise sources [20]. Superposition holds because the
aforementioned current-to-phase relationship is linear [20]. To obtain the total noise
power below the carrier, identify all potential noise sources, compute the transfer
characteristic from each source to the output excess phase and sum or square sum the
individual output phase noise powers, depending if any correlation exists.
The Hajimiri noise model is not without its own critics. In [29], Demir et al. claim
that the oscillator output with phase noise is a stationary random process, contrary to
Hajimiri's theory of some noise sources being cyclostationary. Further, Demir also
advocates that the approach used by Hajimiri to decompose perturbations in two
orthogonal components of phase and amplitude deviation is not valid [29], instead
defining a perturbation projection vector to obtain a nonlinear equation for phase error. In
[25], Rohde uses a similar assessment of the Hajimiri model as for the Leeson model,
stating that the model provides good results once all data is known, but does not lead to
exact design rules.
D. Phase Noise Simulation Models
Apart from the development of some new phase noise theory, the drive for lower
phase noise oscillators has been stimulated by the availability of advanced simulation
tools. These tools, such as Agilent ADS or Cadence SpectreRF, use iterative solution
techniques such as harmonic balance in the frequency domain or shooting methods in the
time domain to evaluate oscillator performance. Although they cannot be represented by a
closed-form set of equations and are computationally intensive, these approaches are
currently the most accurate means of quantifying phase noise and will serve as the basis
for accurately evaluating the different oscillator designs in this work.

50

III. HIGH PERFORMANCE RF OSCILLATOR DESIGN AND OPTIMIZATION
The MEMS-based frequency synthesizer designed as part of this work necessitates a
low phase noise RF oscillator in order to minimize both in-band and out-of-band noise
performance. The design objectives are to exceed the stringent DCS-1800 specifications,
as well as to have a design that is on par with the current state-of-the-art in integrated LC
oscillators. This section will present the baseline oscillator design, followed by the design
improvement and optimization steps applied to the circuit topology and LC resonator.
A. Baseline Oscillator Design
The baseline oscillator design is a top-fed cross-coupled VCO that was initially
presented by this research group as part of the system in [2]. The reason for the top-biased
topology is that it reduces flicker noise compared to the tail biased approach on account
of the higher transconductance of PMOS transistors. The VCO is fabricated in a 0.18m
CMOS process, occupies a total area of approximately 0.65 mm
2
and consumes 4.6 mW
from a 2V supply. The total tuning range of the VCO is 1.65 GHz to 2.10 GHz and makes
use of two tuning mechanisms; varactors and a 5-bit digitally switched capacitor bank.
The gain of the VCO has an average value of 150 MHz/V, with a peak value of 320
MHz/V. The circuit schematic for the baseline top-fed cross-coupled VCO is provided in
Figure 17, alongside a micrograph of the device.
The current mirror consisting of M
5
and M
6
serves to reduce sensitivity to power
supply variations, particularly across the tank inductors. The fine tuning of the VCO is
provided by accumulation mode PMOS varactors M
3
and M
4
, where the transistor gate
serves as one terminal and the source and drain are tied together to provide the second.
The term accumulation mode refers to the fact that the capacitance is maximum when the
surface under the gate is in accumulation, and minimum when it's in inversion. As the
control voltage is increased, the capacitance also increases and reduces the resonant
frequency, meaning the tuning sensitivity of the oscillator is actually negative. The coarse
tuning is implemented with a bank of five externally controlled digitally switched
capacitors that serve to ensure coverage of the total DCS-1800 range of 1710 to 1880
MHz over PVT variations. The tank inductors are intertwined in a hexagonal shape to
minimize area and also help to ensure good symmetry. The differential LC VCO provides

51

two outputs, one to feed the divider through an inverter chain, and a second to feed an
output buffer that is capable of driving a 50 load for measurement purposes.
The capacitor C1 serves to provide pulsed biasing to the oscillator circuit, limiting the
drain current at zero-crossings of the tank waveform, when the oscillator is most sensitive
to injected noise. Injecting the current when the voltage across the tank is maximum, or
equivalently when the ISF is minimum, helps to minimize the output phase noise.

Figure 17: Baseline VCO Schematic (left) and Micrograph of Fabricated Device (right)
(1 = current mirror, 2 = integrated inductor, 3 = varactors & 4 = capacitor bank)
In [35], the phase noise of a differential LC NMOS VCO is reduced by replacing the
constant current source with a pulsed current source outputting the same average current.
This modification results in better DC-to-RF conversion and a larger oscillation
amplitude compared to a constant current biasing, as well as reduced ISFs for the current
noise of the switching pair and bias current source [35]. In [35] the addition of the
current-shaping capacitor results in reductions of 3 dB and 5 dB at 100 kHz and 1 MHz
offset from the 1.755 GHz carrier, respectively. Note that [36] proposed a similar circuit
topology, although the purpose of the capacitor is explained differently, serving instead as
a filter of second harmonic noise at the biasing node. In [36], the oscillator is analyzed as
a single-balanced mixer and it is shown that the second harmonic is downconverted to the
1
2
3
4

52

oscillation frequency. Since the filtering method requires a much larger area compared to
the current-shaping approach in [35], it was not selected for use in the baseline VCO.
B. Phase Noise Minimization Techniques
The optimization of the baseline VCO outlined above is achieved in two steps. In the
first step, a redesign of the circuit topology and tank inductor is carried out, with the
results having been presented as part of the system in [3]. For the second step, the
objective was to optimize the gain of the VCO in order to improve the phase noise
performance and reduce the total capacitance required to stabilize the integrated loop
filter. In this section, each of the implemented design and optimization techniques will be
closely examined in the scope of the aforementioned phase noise models. The simulated
results are presented in Section IV, along with the measured free-running data and a
comparison to the current-state-of-the-art in LC oscillators.
1) Design and Optimization of the VCO Circuit Topology
Instead of using a single NMOS cross-coupled pair as in the baseline oscillator, a
complementary configuration is used that provides several advantages to improve circuit
performance (Figure 18).
The complementary structure provides increased transconductance for a given
current, resulting in faster switching of the cross-coupled pair [21]. Faster switching
translates into lower sensitivity to injected noise since the duration of the zero-crossing
periods becomes shorter. In addition, since there are more active devices in the
complementary structure, the DC voltage drop across the channel is smaller for each of
the transistors, reducing the effect of velocity saturation, corresponding to improved
phase noise [21]. Furthermore, the complimentary configuration also offers better
symmetry in the half-circuit, resulting in improved symmetry of the output waveform. As
shown in Equation (28), conversion of low frequency flicker noise is weighted by the DC
value of the ISF (c
o
), which

depends on the rise and fall time symmetry of the oscillators
waveform, as suggested by Hajimiri in [20]. In order to reduce c
o
, the optimum ratio of
W
p
/W
n
must be found, where W
p
and W
n
are the widths of the PMOS and the NMOS
transistors respectively. Although differential circuits may be considered symmetric with
regards to desired signals, that symmetry disappears for sources that are independent of

53

each other, such as noise [20]. As a result, it is the symmetry in the half-circuit that leads
to symmetry in the output waveform.

Figure 18: Complementary VCO schematic
The complimentary configuration also necessitates the use of a differential tank, as
shown in Figure 18. Compared to the intertwined inductors of the baseline VCO, a single
differential inductor is less susceptible to common mode effects such as supply and
substrate noise, and also simplifies the inductor design since the matching concerns of the
baseline VCO topology are no longer an issue. Another advantage of the differential tank
is that the voltage swing across the LC resonator almost doubles in amplitude since the
tail current passes through the resonator inductor during both positive and negative cycles
[21]. Recall that both the Leeson and Hajimiri models suggest that the phase noise is
inversely proportional to the voltage swing across the tank. As a result, doubling the
voltage swing across the LC resonator could potentially improve the phase noise in the
2
/ 1 f region by up to 6 dB/Hz.
In short, although this modified topology has two additional active devices, its noise
performance is actually better on account of the symmetry properties it introduces to the
circuit.

54

2) Design and Optimization of the Integrated Inductor
The additional PMOS transistors of the complimentary configuration add parasitic
capacitance to the to the VCO circuit, necessitating a re-design of the LC tank in order to
maintain the output frequency range. There are two options available for achieving this; a
modification to either the inductor or the varactor. Since the inductor also needs to be
redesigned to accommodate the differential topology, that was the first option taken, with
the primary objective of maximizing the quality factor of the component, while also
considering area constraints and self-resonant frequency. The self-resonant frequency of
the inductor needs to be sufficiently above the desired oscillation frequency to ensure
effects due to parasitic capacitance are minimized.
An important observation that can be made from Leeson's equation is the quality
factor versus power tradeoff. Notice that the higher the quality factor of the device, the
lower the power required to meet the same phase noise performance. As a result, there is
perpetual drive for higher quality factor resonators, leading to lower power consumption
and more robust communication systems.
The quality factor of an integrated inductor is influenced by three loss mechanisms:
capacitive coupling to the substrate, magnetic coupling to the substrate and metal wire
resistance [10]. The substrate coupling mechanisms are largely determined by the area of
the inductor and the resistivity of the substrate, the latter of which is a property of the
fabrication process and could not be modified as part of this redesign. For both the
baseline intertwined inductors and the improved version presented here, the metal-6 layer
was used to layout the inductor since it is the furthest from the substrate and thus is least
susceptible to capacitive coupling effects. To minimize metal wire resistance, the
objective is to maximize the cross-sectional area of the inductor. The first potential
solution is to increase the trace width, although this would also reduce the inductance per
unit length and increase capacitive coupling, degrading Q and lowering the self-resonant
frequency. As a result, the preferred approach is to use thick metal, which provides a
larger cross-section for current to flow without the aforementioned drawbacks. In the low
GHz range , the quality factor is often limited by the skin depth (Equation 29), which can
be quite large (Table 4). As a result, the use of a thicker metal reduces current density at
the surface of the conductor, reducing losses. In [37], increasing the metal thickness of

55

the integrated inductor from 1 m to 3 m was shown to provide the greatest
improvement compared to any other optimization method, increasing the Q-factor from 5
to 10. For the redesigned inductor described here, the thick metal-6 option is used, having
a thickness of 2.3 m compared to the baseline VCO that uses a standard metal-6 layer of
0.99 m. Note that an increase in thickness will provide diminishing returns as the
thickness is increased much beyond the skin depth at the frequency of interest.
f to
o
1
= (29)
Table 4: Skin depth of aluminum for different frequency values
Frequency (GHz) Skin Depth of Aluminum (m)
0.5 3.66
1.0 2.59
1.8 1.93
2.5 1.64
6.7 1.00
10.0 0.82
Other strategies for improving the quality factor of an inductor are related to the
conductor line spacing, the number of turns and shape. In [37], narrow line spacing is
shown to increase magnetic coupling between windings, resulting in an increased
inductance and Q for a given area. Regarding number of turns, the inner turns of the
integrated inductor contribute little in terms of inductance, but suffer from all the
previously mentioned loss mechanisms [10], and as such should be removed. Finally, a
circular shape exhibits less metal resistance for a given inductance compared to a
rectangular shape [22] due to reduced current crowding at the corners. For the redesigned
inductor described here, a circular shape is used to provide a modest improvement over
the octagonal shape used in the baseline version (Figure 19).
Although there are empirical formulas available for predicting the inductance of an
integrated inductor, an electromagnetic field-solver is a better option since it also has the
ability to predict the self-resonant frequency and quality factor. Field-solver simulation of
the redesigned inductor using ASITIC (Analysis and Simulation of Inductors and
Transformers for Integrated Circuits) predicts an inductance of 3.1 nH, with an effective

56

quality factor of 10.9 at 1.8 GHz, which translates to an effective series resistance of 3.2
. The predicted self-resonant frequency is 7.2 GHz. This compares to the baseline
inductors, each of which had a simulated inductance of 5.8 nH and a Q-factor of 4.9 at 1.8
GHz, translating into an effective series resistance of 7.5 .

Figure 19: Comparison of intertwined inductors of baseline VCO (left) with differential inductor (right)
3) Optimization of the VCO Gain
The design of the integrated loop filter considers several component parameters,
including CP current, the PLL divider ratio and the VCO gain. As presented in Chapter 2,
an increase in the CP current, while maintaining the CP noise, results in better in-band
phase noise performance. Increasing the CP current also increases the overall PLL loop
gain, which is proportional to the size of the loop filter capacitors required to achieve a
particular loop bandwidth. As a result, in order to maintain the same chip area and same
cutoff frequency as the PLL system utilizing the baseline VCO, the oscillator tuning gain
needed to be reduced. As shown in Equation (21), a reduction in the VCO gain also
minimizes the noise contribution from the tuning diode, as well as any other perturbations
on the control line, helping to improve overall phase noise performance.
With the above reasoning in mind, the design objective is to develop a VCO with the
smallest tuning gain possible that is capable of covering the entire DCS-1800 frequency
range, including approximately 20% margin at the upper and lower ends to account for
PVT variations. To achieve this goal, modifications are needed to the varactor, as well as
the switched capacitor bank. As shown in Figure 20 below, the varactor count is reduced,
with the total capacitance in the circuit maintained by the addition of two fixed capacitors

57

on each side of the differential tank. For the switched capacitor bank, the number of
switchable banks was reduced from 5 to 2, optimized in order to achieve the
aforementioned tuning range objectives. A reduction in the number of banks also reduces
the loading of the tank quality factor by the on-resistance of the switches.

Figure 20: Redesigned VCO Circuit Schematic (left) and Corresponding Micrograph (right)
(1 = integrated inductor, 2 = current mirror, 3 = varactors & 4 = capacitor bank)
IV. PERFORMANCE EVALUATION
This section presents the performance evaluation of the redesigned RF VCO
compared to the baseline version. The simulation data for each device is given, followed
by the measured experimental results, including a comparison to some recently published
integrated LC oscillators.
A. Simulation Results
Simulation of both VCOs was carried out using Cadence SpectreRF. A summary of
the simulation data is provided in Table 5 below. The phase noise performance of the
redesigned oscillator showed a 6-7 dBc/Hz improvement over the baseline in the
2
/ 1 f
region. In the
3
/ 1 f region, the phase noise simulated at offsets of 1 and 10-kHz was
2
1
3
3 3
4

58

comparable to the phase noise of the original VCO. A more significant improvement
could have been expected because of the improved symmetry in the half-circuit in the
complimentary cross-coupled topology, although in practice the increased number of
active devices possibly balances out any reduction in c
o
. The simulations also showed a
bandwidth reduction for the redesigned oscillator, from 600 MHz to 240 MHz, which was
a consequence of the adopted optimization strategy to minimize tuning gain. The
simulated power consumption also increased by 1.3-mW to 5.7-mW for the
complimentary configuration.
Table 5: Comparison of VCO simulation results
The overall performance of the two oscillators is compared in Table 5 using a
standard Figure-of-Merit (FoM) that has previously been used in [31], [35] and [38]. Note
that this FoM does not consider chip area or tuning range, since the areas of the two
devices are equivalent and no effort was made to extend the oscillator tuning range
significantly beyond the DCS-1800 requirements.
Performance Parameter
Baseline VCO Redesigned VCO
f
min
f
cent
f
max
f
min
f
cent
f
max
Technology CMOS 0.18 m
Chip Area (mm
2
) 0.65
Inductor Topology Intertwined Differential
Frequency (GHz) 1.64 1.80 2.24 1.68 1.80 1.92
PN at 1 kHz (dBc/Hz) -56.0 -51.3 -47.2 -53.8 -52.3 -50.0
PN at 10 kHz (dBc/Hz) -81.3 -79.0 -76.1 -82.8 -81.6 -79.4
PN at 100 kHz (dBc/Hz) -102.7 -101.8 -100.3 -108.7 -107.4 -106.0
PN at 600 kHz (dBc/Hz) -118.5 -117.7 -116.6 -125.6 -124.6 -123.3
PN at 1 MHz (dBc/Hz) -122.9 -122.2 -121.1 -130.2 -129.1 -128.0
PN at 3 MHz (dBc/Hz) -132.4 -131.7 -130.6 -139.9 -138.8 -137.7
Tuning Range 27% 13%
Average Gain (MHz/V) 150 75
Peak Gain (MHz/V) 320 110
Core Power (mW) 4.4 5.7
FoM 180.8 186.6

59

( )
(
(

A
|
.
|

\
|
A
=
P L
FoM
o
e e
e 1
log 10
2
(30)
The modification of the oscillator topology and improvement to the inductor design
accounted for most of the simulated phase noise improvement. Optimization of the tuning
gain provided only a slight improvement in simulated noise ( 1 dBc/Hz at 600 kHz), but
allowed a significant reduction in total capacitance, reducing the chip area required for
the integrated loop filter. The modest improvement in noise resulting from the significant
reduction in tuning gain demonstrates that the modulation noise contributed by the
varactor in Equation (21) is not a dominant factor.
While the baseline VCO was able to cover the entire DCS-1800 frequency range
without the use of the switched capacitor bank, the redesigned version could not on
account of the reduced tuning gain. As a result, the bank of capacitors, which was
included in the baseline version for PVT effects alone, is need to meet the range
requirements in the redesigned device. From simulation results shown in Figure 21, it
appears that using a single-bit capacitive bank may have sufficed, although a second bank
was included as a precaution considering potential PVT effects. Since the phase noise
maintained good performance across the band, it is feasible that the frequency range
could be extended by the addition of supplementary switched capacitors if need be for
other applications. As mentioned earlier, the effect of switch on-resistance loading of the
oscillator tank Q must also be considered.

Figure 21: Simulated oscillation frequency versus tuning voltage for the redesigned VCO
1650
1700
1750
1800
1850
1900
1950
0 0.5 1 1.5 2
F
r
e
q
u
e
n
c
y

(
G
H
z
)

Control Voltage (V)
Bank 00
Bank 01
Bank 10
Bank 11

60

B. Measured Results
The VCOs were fabricated in a commercially available 0.18 m CMOS process. An
Agilent E4440A performance spectrum analyzer was connected to a buffered output to
monitor the oscillation signal and provide phase noise measurements. During
measurements, each of the VCOs were powered using an off-chip regulated power
supply. The data presented in this section was taken with the oscillators in free-running
operation. The data for the oscillators running closed-loop within the high resolution
fractional-N PLL system will be provided in Chapter 5.
Compared to the simulated data, the frequency range for the redesigned VCO
decreased slightly, spanning from 1700 to 1890 MHz. The measured phase noise for the
redesigned version at 10 and 600 kHz offsets were -75.4 and -123.4 dBc/Hz, respectively,
compared to -63.42 and -115.5 dBc/Hz for the baseline version. The phase noise plots for
the baseline and redesigned VCOs at an oscillation frequency of 1.8 GHz are provided in
Figure 22. Comparing the two traces shows an improvement of between 6 and 8 dB
across the offset frequency range. Note that the measured value of -123.4 dBc/Hz at 600
kHz offset for the redesigned device is slightly higher than the -122 dBc/Hz of the same
VCO without the gain adjustments that was presented in [3]. This small differential is
consistent with what was observed in simulation.

Figure 22: Comparison of the measured phase noise of the baseline and redesigned VCOs
-160
-140
-120
-100
-80
-60
-40
1.0E+04 1.0E+05 1.0E+06 1.0E+07 1.0E+08
P
h
a
s
e

N
o
i
s
e

(
d
B
c
/
H
z
)

Frequency Offset (Hz)
Baseline VCO
Redesigned VCO

61

Table 6 compares the baseline and redesigned VCOs presented herein to a selection
of recently published oscillators. The basis of comparison is the same FoM parameter
described earlier. The oscillator in [23] is a noise-shifting differential Colpitts VCO, [31]
is a differential LC VCO with tail filtering, [35] is an LC VCO with tail current shaping,
[38] is a low power CMOS VCO that uses helical inductors, [39] is a wideband
differential LC VCO, and [40] is an LC CMOS VCO that uses high-Q bondwire
inductors. Each of these oscillators has its own merits in terms of chip area, power
consumption and tuning range. At the onset of this study, the objective was to design a
VCO that compared favorably with the current state-of-the-art in oscillators, and judging
by Table 6 this goal has been realized.
Table 6: VCO measured performance comparison to recently published VCOs
Reference Technology
Inductor
Q
Oscillation
Frequency
(MHz)
Offset
Frequency
(kHz)
Phase
Noise at
Offset
(dBc/Hz)
Core
Power
(mW)
Tuning
Range
(%)
Chip
Area
(mm
2
)
FoM
[23]
0.35 m
BiCMOS
6 1800 3000 -139 10 31 1.0 184.6
[31]
0.35 m
CMOS
10 2100 3000 -134 10.8 N/A N/A 180.6
[35]
0.25 m
BiCMOS
12 1755 600 -120 2.25 19 0.32 185.8
[38]
0.18 m
CMOS
9 2550 1000 -119.2 1.5 6 0.16 185.6
[39]
0.18 m
CMOS
9 1800 600 -123.5 4.8 73 1.70 186.2
[40]
0.35 m
CMOS
14-35 1900 600 -120.5 2 15 N/A 187.5
Baseline
VCO
0.18 m
CMOS
4.9 1800 600 -115.5 4.4 20 0.65 178.6
Redesigned
VCO
0.18 m
CMOS
10.9 1800 600 -123.4 5.7 10 0.65 185.4
V. CONCLUSION
This Chapter reviewed some basic VCO theory, including Leesons phase noise
model and some background theory on Hajimiris time variant approach. Subsequently,
different design and optimization strategies were applied to a baseline CMOS LC cross-
coupled pair in order to minimize phase noise and meet the stringent DCS-1800
requirements. A complimentary circuit topology was used to provide a differential tank

62

and improve symmetry of the half-circuit in order to minimize the upconversion of device
flicker noise. The tank inductor was redesigned in shape and geometry to minimize loss
mechanisms and maximize quality factor. The gain of the oscillator was reduced to
improve phase noise performance and more importantly impose less of a burden on the
design of the integrated dual-path loop filter.
Simulated and measured data showed that the oscillator redesign resulted in
considerable phase noise improvement in the
2
/ 1 f region at the cost of a small increase
in power consumption. Overall, a 6.8 dB improvement in FoM was achieved for the
redesigned VCO compared to the baseline version, which is comparable to the current
state-of-the art in high-performance CMOS LC VCOs.


63


Chapter 4

PCB Design, Characterization
and Test






To properly characterize the synthesizer system IC and MEMS-based reference
oscillator described in Chapter 2, a series of printed circuit boards (PCBs) are developed.
Important considerations made during the design process ensure that all the necessary
functionality is incorporated into the PCB. An emphasis on performance and ease of
testability requires specialized circuitry dedicated to PLL programming, bias voltage
tuning, MEMS resonator assessment and reference/RF oscillator evaluation.
Printed circuit board design requires special attention to certain electromagnetic
compatibility (EMC) issues in order to maximize circuit performance, particularly as the
operating frequency increases. The higher the functional frequency, the greater the
likelihood for radiated coupling between circuits, whereas lower frequencies exhibit a
greater likelihood of conducted coupling. At high frequencies, the PCB traces and
interconnects are electrically long and capable of acting as antennae [41]. For low
frequencies, the physical size of PCB traces is electrically small, providing an inefficient
radiating element, and conducted coupling is dominant. Filtering, component placement,
grounding and electromagnetic shielding are important considerations that must be made
during PCB design to minimize interference effects.
This Chapter describes the design of the two PCBs used for characterization and test
of the fully integrated frequency synthesizer and MEMS resonators described in Chapter

64

2. The first PCB design is dedicated to the synthesizer system developed in-house and
underwent multiple iterations to accommodate the modifications that were made for the
four versions of the synthesizer/TIA IC. The second PCB is a small form fit easy-to-use
PCB designed for rapid prototyping of MEMS resonators and is built exclusively using
commercial off-the-shelf (COTS) surface mount components. Included in this Chapter are
aspects related to specialized PCB circuitry, as well as issues related to electromagnetic
compatibility (EMC), test methodology and design evolution.
I. FULLY-INTEGRATED FREQUENCY SYNTHESIZER PCB
This section is divided into several parts covering the design, evolution and test
methodology of the PCB produced for use with the MEMS-based reference oscillator and
synthesizer system described in Chapter 2. Along with the four device iterations of the
PLL IC, the PCB design also underwent a series of changes to ease testability, reduce the
likelihood of electromagnetic interference (EMI) and accommodate IC functionality.

Figure 23: Photograph of test PCB for PLL device 3
A. PCB Design Overview
The finished PCB measures 17 cm by 19 cm and has an overall part count of well
over 500 (Figure 23). The first three iterations each had four BNC connectors used for
power supply voltages, including one for the resonator polarization voltage. A series of

65

SMA connectors are also provided for RF outputs, the reference frequency input, the
VCO control voltage input and MEMS resonator characterization.
To afford all of the required functionality during prototyping, the PLL IC is packaged
using a large 84-pin leadless chip carrier (LCC) package (Figure 24). A through-hole
mounted IC socket is used to facilitate testing of multiple ICs since the package does not
need to be soldered to the PCB. The drawback of this arrangement is increased parasitic
effects associated with the longer interconnects, although no detrimental effects were
observed here during testing. In addition, to accommodate such a large package, careful
consideration is needed both on-chip and off-chip to be able to achieve efficient trace
fanout. An advantage of the through-hole mounted socket configuration is that traces can
be routed to the pins on either side of the PCB, simplifying layout.

Figure 24: Packaged PLL IC (left) and packaged MEMS resonator die (right)
For the MEMS resonator die, a similar arrangement was used, with multiple
resonators being packaged in a single 28-pin LCC package (Figure 24) that is inserted
into a through-hole mounted IC socket. The different resonators are individually selected
using adjacent terminal strips or DIP switches (Figure 23). The PCB also includes
circuitry that could be manually configured to test the MEMS resonator open loop, both
with and without the TIA. This allowed for evaluation of the device resonant frequency,
quality factor, open loop gain and other performance metrics. The resonator socket was
positioned as close as possible to the PLL IC socket in order to minimize the oscillation
loop area. For devices 1 to 3, the arrangement of testing the MEMS device and PLL IC in
separate sockets was the only option. For device 4, modifications to the PCB were made
to accommodate packaging the PLL IC and the MEMS resonator together, as well as to
accommodate a novel vacuum packaging solution from CMC Microsystems. Details
regarding the PCB design evolution and test setup are provided in part two of this section.

66

To allow for thorough evaluation of PLL performance, the PCB was designed with
the ability to use both a MEMS based reference oscillator and a TCXO. The TCXO
circuitry, located adjacent to the PLL IC socket (Figure 23), includes a transistor based
buffer to limit the oscillation amplitude to less than 2V. The same signal was also divided
down in frequency and used as the synchronizing clock for all digital circuitry.
For the design presented here, a standard thickness (1.5748 mm) fibreglass-resin
(FR4) laminate was used as the PCB material. The dielectric constant of FR4 material
used was 4.0 to 4.6, corresponding to a tolerance of approximately 7% from the median
[42]. Compared to Rogers 4350 laminate, the tolerance of the dielectric constant is
relatively high, however because of the small quantity of high frequency traces, FR4 was
deemed acceptable. The drawback of using a 1.5748 mm thick board is that the distance
between the signal plane and the image plane is relatively large, resulting in little flux
cancellation [43] and thus slightly augmenting the likelihood of EMI issues.
The PCB was designed using a simple two sided board. A typical PCB used in GSM
mobiles is of either a four layer or six layer construction [44]. Multilayer PCBs provide
the advantage of reducing required board area, providing better impedance control of
traces routed on internal conductor layers and potentially permitting the use of image
planes for flux cancellation since the internal layers are spaced closer together. Since
board area was not of significant concern for initial prototyping, a double sided PCB was
deemed sufficient. Additional advantages are that the two sided board is simpler and more
cost effective to fabricate. Note that a silk screen and solder mask layer were included top
and bottom for ease of assembly (Figure 23).
B. Design for Electromagnetic Compatibility
Electromagnetic compatibility relates to the capability of electronic systems and
devices to operate in their intended electromagnetic environment without suffering from
or causing unacceptable functional degradation or damage [43]. For PCB design, EMC is
achieved through the appropriate use of different design measures, including board
layout, grounding, filtering, shielding, decoupling and bypassing. This section describes
some PCB features incorporated here to reduce the likelihood of EMI.
At higher frequencies, the parasitics associated with lumped elements such as the
inductance of long traces or the capacitance of component pads begin to impact circuit

67

performance. As a result, for high frequency traces such as the RF output of the frequency
synthesizer system, models of relevant PCB structures were included in Cadence circuit
simulations. In this way, impedance matching could be properly designed to maximize
power transfer using discrete components and appropriately sized trace widths.
An important consideration to make when routing PCB traces is that the current
return path to ground must be kept as short as possible, in order to minimize ground loops
and the likelihood of interference. It is also important for return paths to be kept close to
their respective source trace in order to allow for flux minimization [43]. For low-
frequency circuits, the return current is the path of least resistance, whereas for high-
frequency energy, the inductance of the path becomes important. To minimize the overall
path impedance, the RF traces need to be sufficiently wide and the return loop area needs
to be as small as possible. For the PCB design described here, vias were placed as close
as possible to IC ground pins to minimize the return loop and ensure that the ground
planes top and bottom were well connected. Multiple vias were used where feasible in
order to reduce the parasitic via inductance and all unused IC pins were grounded in an
effort to reduce the ground impedance.
For the PCB ground, a single low-impedance ground plane was used to minimize
interference between the radio and digital circuits. While splitting the ground plane
between digital and analog circuitry was initially considered, such an arrangement can be
complicated to implement and often causes more problems than it solves [41]. Instead,
appropriate use of layout partitioning was adopted, which consists of grouping
components based on function and signal quality to prevent high-bandwidth emitters from
corrupting more sensitive components [43]. For the PCB design described here, the layout
objective was to group the same family of electronics together (e.g. digital, analog,
interface, etc.), as well as to place the reference oscillator circuits as close to the PLL IC
as possible.
For trace routing, the strategy was to route RF traces first, followed by clock signals
and finally DC traces. Except for RF traces, the top layer of the PCB was used for routing
in one direction, and the bottom layer for the orthogonal direction. RF traces were routed
manually, with the auto-route feature used for the remainder, followed by careful
inspection of the resulting layout. PCB crosstalk was minimized by maximizing trace-to-

68

trace separation and avoiding routing traces parallel to each other, particularly over long
runs. Finally, the use of chamfered corners for PCB RF traces was also used to help
maintain a constant line impedance and minimize reflections.
C. Specialized Off-Chip Circuitry
The PCB design includes some specialized circuits to improve synthesizer
performance, accommodate the PLL programming methodology and simplify testing.
This section provide an overview of these circuit designs.
1) Regulator Circuitry
In the interest of performance evaluation, separate voltage regulator circuits were
used to power the different PLL components and allow for tuning of some critical on-chip
bias voltages. In addition to providing the ability to turn off individual synthesizer
components, separate regulators ensure minimal power supply noise coupling, as well as
an effective means to optimize the various bias voltages. This feature was of particular
benefit for evaluating the TIA automatic gain control (AGC) open loop. The drawback of
this approach is a significant increase in the number of pins required on the IC package,
as well as PCB board area. Ultimately, most of these off-chip regulators could be
substituted with on-chip band-gap voltage references once the design matures.
The discrete regulator circuits used here make use of a low noise, low drop-out
(LDO) voltage linear regulator, a set of capacitors for noise filtering and potentiometers
to provide tuning capability (Figure 25). The same regulator IC was used for all the
regulator circuits, except the polarization voltage, which used a high-input voltage
version of the same device. The use of multiple differently sized capacitors at the
regulator output is due to practical issues associated with discrete capacitors. Large
capacitors have a low self-resonance frequency, preventing their use for decoupling high
frequency noise, whereas smaller capacitors present a high impedance to lower frequency
noise, providing poor filtering. The 10 F tantalum capacitor at the output of the regulator
IC is specified by the manufacturer and used to maintain stability. The different power
supplies are decoupled from the common 5V PCB reference using a bulk 10 F
electrolytic capacitor at the power entry point. In some instances, such as for the VCO
power supply, an appropriately sized series resistor or inductor is used between C3 and
C4 to provide added low-pass noise filtering.

69


Figure 25: Voltage regulator circuit schematic
2) Programming and Synchronization Circuitry
The PLL is programmed using a series of off-chip dip switches in conjunction with
some digital circuitry. Although a large 84-pin package was used to contain the integrated
circuitry, the number of pins available for programming was limited. Using a counter and
a set of digital multiplexers (Figure 23), the data could be shifted into the PLL IC using
serial bit streams. As a result, only four pins were required to input data for the delta-
sigma modulator (24 bits), coarse tuning of the VCO (2 bits), the PLL program counter (6
bits) and the PLL channel selection (6 bits).
The programming methodology described above requires additional on-chip circuitry
to convert the serial data streams into a parallel format, as well as a mechanism to
synchronize the on-chip and off-chip circuits. The on-chip de-serializer circuit is a
counter that is programmed to count 24 times and simultaneously shift in data from the
serial input to a shift register. Once the counter has reached its limit and 24 bits have been
shifted in, the parallel data is loaded into a 24-bit register that provides the input to the
delta-sigma modulator. This entire process is initialized by a short pulse and self-
terminates when the operation is complete. Self-termination consists of the system
resetting and cutting out the clock to the shift register. Note that the same basic de-
serializer circuit was appropriately modified to accommodate the different bit counts of
the coarse tuning of the VCO, the PLL program counter and PLL channel selection.
The short pulse is generated using the specialized off-chip circuit shown in Figure 26.
The requirement on the pulse is that it must have a width that is smaller than 24 times the
system clock period to allow for correct circuit operation. The input to the standard D
flip-flop is provided by a dip switch. When the input signal goes high, the output toggles
high, charging the capacitor C2. Once the capacitor charges up to a sufficiently high
voltage, the D flip-flop is reset to zero. The purpose of the diode, specially chosen for its

70

high switching speed, is to discharge C2 following reset. The width of the pulse is
determined by the RC time constant, set to 10s for this application. The system clock
used to synchronize the off-chip digital circuitry with the on-chip circuitry consists of a
frequency divided version of the buffered 10 MHz TCXO output. For this application, a
100 kHz clocking signal is used, although the clock is only activated during programming
so as to eliminate any possibility of modulating the synthesizer output. Ultimately, a
MEMS-based oscillator could also be used to provide this clocking signal.

Figure 26: Pulse generating circuit schematic [45]
3) Off-Chip Loop Filter
An important conclusion from the phase noise simulation results in Chapter 2 was
that the fully integrated frequency synthesizer driven by the TCXO reference had an
output phase noise that was dominated by the noise of the integrated loop filter. As a
result, for the PCB design, a discrete fourth order active off-chip loop filter was included
to evaluate the system's optimal potential performance (Figure 27). This implementation
also required an additional integrated charge pump with a nominal output current of 111
mA. The reason why an active configuration was used is because the existing CP and
VCO designs required a negative polarity loop filter. The disadvantage of using an active
loop filter over a passive version is higher cost, increased complexity and most
importantly, higher in-band phase noise.
A primary drawback of the fully integrated loop filter is that it does not allow for
iterative evaluation and optimization of PLL performance. Optimization of close-in PLL
phase noise involves iterating the charge pump current for minimum noise while keeping

71

the loop characteristics constant. This typically requires adjustment of the loop filter
component values when the CP current value is changed. Note that the ability to vary the
off-chip loop filter components also allows for effective characterization of the VCO
phase noise from measurement with a locked PLL by setting the loop bandwidth to a very
narrow value.

Figure 27: Fourth order active loop filter circuit schematic

Figure 28: Simulated synthesizer output phase noise with TCXO reference and off-chip loop filter
Using the same method described in Chapter 2, the simulated output phase noise of
the synthesizer circuit with the off-chip loop filter is given above (Figure 28). Evidently,
the loop filter no longer dominates PLL noise performance and the simulated overall in-
band noise has been reduced from -82 dBc/Hz for the integrated loop filter design to -86
dBc/Hz. The design constraints imposed on the integrated loop filter make it no surprise
that the off-chip filter provides better performance. What the off-chip loop filter also

72

affords is the ability to validate other noise sources in the system, improve testability and
quantify the phase noise performance to board area trade-off. Note that a further reduction
of in-band noise could be achieved by increasing the loop bandwidth, at the expense of
far-from carrier noise.
D. PCB Design Evolution and Test Methodology
The evolution of the PCB design largely followed the changes in the four PLL IC
iterations described in Chapter 2, with additional modifications to improve performance
and facilitate testing. For the first version of the PCB, the de-serializer circuit was used
only for programming the 24-bit delta-sigma modulator. As such, seventeen additional
pins were dedicated to the parallel input of the program counter, channel select and coarse
VCO tuning bits. Fewer available pins allowed for less tuning capability of the circuit
bias voltages, and those that were tunable often shared a common regulator. For the
second iteration of the PCB, the on-chip TIA was completely redesigned, requiring
thorough characterization and thus several new input signals. A high-input voltage
regulator was added for the MEMS resonator polarization voltage, as well as a means to
control the VCO from an off-chip regulator. Also for PCB two, many of the bias voltages
were provided with dedicated voltage regulator circuits, crowding the PCB and somewhat
hampering testability. For the third version of the PCB (Figure 23), the resonator circuitry
was relocated closer to the PLL IC in order to minimize the oscillation loop area.
Additional 8:1 multiplexers were included to support serial programming of the program
counter, channel select and VCO coarse tuning. The latter modification alone liberated
fourteen pins which were used for other purposes.
For devices one to three, all circuitry was located on a single PCB. During testing that
involved the MEMS-based reference oscillator, the entire PCB needed to be programmed
and subsequently placed inside the vacuum chamber. During that time, the effect of
vacuum was to reduce air damping of the resonator and improve its Q. With less loss in
the oscillation loop, the polarization voltage that could be handled by the MEMS device
was reduced. To avoid burning the MEMS resonators, a sufficiently high vacuum level
needed to achieved prior to augmenting the polarization voltage. Once vacuum has
reached the millitorr range, the polarization voltage was slowly increased, causing a
downward shift in resonant frequency. Because of this setup, the final synthesizer output

73

frequency was difficult to know a priori and could not be changed without removing the
PCB from the chamber. It was also impossible to tune the TIA bias voltages with the PCB
inside the chamber, making any type of iterative testing with the MEMS-based reference
oscillator quite difficult.
To remedy the shortcomings posed by a single PCB solution, the fourth iteration of
the PCB utilized a two-board solution in order to have the ability to place one PCB inside
the vacuum chamber and dynamically change the programming and bias voltages from
the outside using the other. Figure 29 below illustrates the laboratory test setup for
evaluation of the with MEMS-based reference oscillator.

Figure 29: PLL device 4 laboratory test setup
The two boards illustrated in Figure 29, the chip board and the control board, are
interconnected using a pair of standard D-sub connectors and a specialized feedthrough
adapter for the vacuum chamber. The vacuum pump comes complete with millitorr
pressure gauge. Note that for testing with a TCXO reference, the PLL IC may be tested
using a conventional laboratory setup.
In separating the circuit into two PCBs (Figure 30), careful consideration was needed
in order to preserve signal integrity. For all lines entering and leaving the PCB, bypass
capacitors were provided to prevent high frequency energy from entering or leaving the
boards. Secondly, it was of utmost importance to ensure that the two PCBs shared a
common low-impedance ground plane. To achieve this, at least one pin on each I/O
connector was assigned to ground, although for best performance a typical rule of thumb

74

is to plan for a ground return for every 3 to 6 pins [46]. For the I/O connector pins, it is
also good practice to keep the lowest and highest voltage pins furthest apart. To maintain
signal integrity of the clock and other synchronizing signals, appropriate drivers were
added on the second PCB to regenerate the synchronizing clock and serial input data
streams.

Figure 30: Photograph of test PCB for PLL device 4
Another improvement that was made for the fourth iteration of the PCB was the
addition of multiple TCXOs. The objective was to have crystal reference oscillators that
operate at the same frequencies as the different MEMS resonators, permitting more
accurate benchmarking of synthesizer performance. Furthermore, the additional available
space afforded by having two PCBs allowed for improved component positioning and
board annotation.
The fourth iteration of the PCB was also designed to accommodate a novel vacuum
packaging solution from CMC Microsystems. Although the test setup using the vacuum
chamber is effective in a laboratory environment, the ultimate objective of developing
MEMS resonator technology is to provide a single-chip solution, for which vacuum
packaging is a necessity. The solution from CMC is a conventional chip-level package
(CLP) that is capable of achieving less than 10 mTorr after sealing and less that 100
mTorr for 1.5 years thereafter. Internal to the package, the PLL IC die and the MEMS
resonator die are appropriately wire bonded together and to the pads of the LCC package
(Figure 31). The dies are attached using a low outgassing epoxy, which is important for

75

maintaining a high-vacuum environment over time. In the laboratory setup, the
outgassing of cables and other items placed inside the chamber can sometimes make it
difficult to achieve the desired level of vacuum. To accommodate the CMC solution at
the PCB level, additional pins were liberated and the off-chip resonator circuitry
modified, including the addition of a switch to control resonator selection inside the
package.

Figure 31: Schematic CLP vacuum packaged solution
In terms of packaging solutions, the conventional chip-level approach described
above suffers from a number of drawbacks, including high cost, large capacitive and
inductive parasitics and the potential to damage the MEMS device during chip dicing.
Wafer-level packaging (WLP), on the other hand, has emerged as a promising substitute
capable of providing device encapsulation as part of the fabrication flow [47]. For
instance, the technology developed by members of the McGill Wireless IC & MEMS
laboratory in [47] provides a wafer-level packaging solution designed for the
encapsulation of MEMS in vacuum that is also fully compatible with the low-temperature
resonator fabrication process described in Chapter 2. Once packaged, the encapsulated

76

dies can be directly surface mounted onto a PCB using standard processes [47], providing
an attractive solution for future applications.
II. MEMS RESONATOR DEMO PCB
One of the other mandates of this project was to develop a small form fit easy-to-use
PCB that could be utilized for rapid prototyping of MEMS resonators. Although the PCB
developed for testing of the PLL IC was fully functional, it was somewhat bulky and
would require a significant level of optimization to achieve the aforementioned objective.
Achieving this for the integrated synthesizer device would require the creation of several
band-gap references on-chip to reduce the need for individual off-chip bias voltages, as
well as to reduce the number of interface pins so that a smaller package could be used. A
change to the programming methodology would also be needed to reduce the quantity of
DIP switches off-chip and hence board area. A possible implementation could have been
to incorporate an FPGA onto the PCB, which could provide the necessary digital
circuitry.
In lieu of making the aforementioned changes, a separate endeavor was undertaken to
construct a MEMS resonator test circuit using only commercial off-the-shelf (COTS)
surface mount components, as had been done in a number of prior publications, including
[7]. As was the case for the synthesizer PCB, circuitry to characterize the MEMS
resonator open loop, both with and without the TIA, was also incorporated to the demo
PCB. This approach provides a benchmarking standard for the PLL IC, flexibility to
adjust for different wireless standards, a small-form factor and an efficient means to
characterize different resonators.
This section provides an overview of the PCB design, including component selection
and test methodology. Note that many of the same features employed to maintain EMC
on the fully integrated synthesizer PCB, such as bypassing at the I/O connector,
decoupling and grounding, were similarly applied to the design of the MEMS resonator
demo board.
A. PCB Design Overview
The block diagram of the MEMS resonator demo board is illustrated in Figure 32
below. Contrary to the PLL IC, the MEMS resonator is connected in a Pierce

77

configuration, whereby a 180 degree phase shift is provided by the series combination of
the TIA and variable gain amplifier (VGA), with the remaining 180 degree phase shift
provided by the shunt capacitors. For the phase-locked loop, the selected PLL IC
encapsulates the delta-sigma modulator, divider, PFD, charge-pump and supporting
digital circuitry. As such, all that is needed externally are the loop filter and VCO. A
resistive divider is used to split the VCO output into feedback and synthesizer output,
whereas a resistive attenuator in the feedback limits the power of the signal fed to the
PLL IC. Details of the individual component selections are provided in the next section.

Figure 32: Block diagram of MEMS resonator demo PCB
A photograph of the assembled MEMS resonator demo PCB is provided in Figure 33.
The board has dimensions measuring approximately 7.5 cm by 13 cm and a total
component count of 120. There are two BNC inputs for the component bias and the
resonator polarization voltages, as well as six SMA connectors. The PCB does not have
its own TCXO circuit, although one of the SMA connectors is provided for testing with
an external reference source. The other SMA connectors are used for resonator
characterization, MEMS-based oscillator output and synthesizer RF output. For
programming purposes, there is also a 9-pin D-sub connector used to interface with a PC.
As was the case for the synthesizer PCB, multiple resonators are packaged using a single
28-pin LCC package that is inserted into a through-hole mounted IC socket, with adjacent
DIP switches provided for individual selection. The resonator die is vacuum packaged
using the same CLP solution described earlier, or alternatively the entire PCB can be
placed inside a vacuum chamber for laboratory testing. There are four fixed output
voltage regulator circuits similar to the version described for the PLL IC PCB, except

78

without the tuning capability. There is also one high voltage-input voltage regulator for
the resonator polarization voltage, as well as three potentiometers, one for adjusting the
polarization voltage level and two others for controlling the variable gain amplifiers.

Figure 33: Photograph of the MEMS resonator demo PCB
B. PCB Component Selection
The PLL IC that was chosen for the MEMS resonator demo board is the ADF4153
from Analog Devices. The ADF4153 is a fractional-N frequency synthesizer IC that is
typically used to implement local oscillators in wireless transceiver applications [48]. The
device includes a low noise digital PFD, a precision CP, a programmable reference
divider and a delta-sigma modulator. As such, all that is needed to complete the PLL
system are an off chip loop filter and VCO. Programming of all on-chip registers is
achieved via a simple 3-wire interface. For test purposes, Analog Devices provides
software available online to easily program the device from a PC using a specially
configured D-sub cable connected to the PC's printer port. The PLL IC operates from a
supply voltage of 2.7 to 3.3V, and also provides a separate high voltage charge pump
output that can be used to extend the tuning voltage range if needed. The maximum RF
frequency of the PLL IC is 4 GHz, providing flexibility to adjust for different wireless
standards (Table 7) by a simple re-design of the loop filter and substitution of the VCO.
This later feature allows the PCB to be used as a proof-of-concept for MEMS resonators
in a multitude of different wireless applications without re-layout. The ADF4153 is also
operable for reference frequencies ranging from 10 to 250 MHz. Finally, the PLL IC

79

provides a MUXOUT feature, which can be configured to provide a digital lock detect
function.
Table 7: Typical local oscillator (LO) frequency for different wireless standards
Wireless
Standard
LO Frequency
(MHz)
DCS-1800 1800
WLAN 3840
Bluetooth 2400
SONET 622
GPS 1600
The selected VCO from Crystek Corporation consists of a 0.5" by 0.5" daughter card
mounted on the PCB. The VCO is constructed using discrete components and a
microstrip resonator, resulting in a phase noise performance that far exceeds the current
state-of-the-art in integrated LC VCO designs (e.g. -130 dBc/Hz at 600 kHz offset). Other
typical performance parameters, including tuning gain, output power and power
consumption are provided in Table 8 below. As can be observed, the VCO requires a
maximum control voltage of 5V. Since the PLL IC operates with a supply voltage of 2.7
to 3.3V, an active loop filter would typically be required to meet the tuning range
requirements. However, because the ADF4153 provides a separate high voltage charge
pump output of up to 5V, a passive loop filter is used, although the drawback is that an
additional voltage regulator circuit is also needed. For the PCB layout, a large amount of
vias were placed directly below the VCO with no traces being routed directly in its
vicinity in order to minimize the possibility of interference.
Table 8: Crystek VCO typical performance parameters [49]
Frequency Range (MHz) 1690 - 2062
Tuning Gain (MHz/V) 145
2nd Harmonic Suppression (dBc) -22
Output Power (dBm) +5.0
Maximum PN at 10 kHz Offset (dBc/Hz) -90
Maximum PN at 100 kHz Offset (dBc/Hz) -114
Supply Voltage (V) 5.0
Maximum Control Voltage (V) 5.0
Power Consumption (mW) 100

80

An active loop filter is necessary in cases where the VCO requires a higher voltage
than the synthesizer charge pump can provide. Because the ADF4153 PLL IC includes a
separate high voltage charge pump output to extend the tuning voltage range to up to 5V,
a passive loop filter design was possible (Figure 34). Compared to an active loop filter, a
passive loop filter uses fewer components, requires less PCB area and most importantly,
generates only thermal noise.

Figure 34: Passive loop filter circuit schematic

Figure 35: Simulated output phase noise for demo board synthesizer with TCXO reference using
ADIsimPLL
The 4th order passive loop filter was simulated using the ADIsimPLL tool available
online from Analog Devices. The advantage of this software compared to the analytical
approach carried out for the fully integrated synthesizer in Chapter 2 is that the software
package includes the noise profile of the PLL IC, providing an accurate estimate of output
phase noise (Figure 35). As opposed to the fully integrated frequency synthesizer, the
output phase noise does not appear to be dominated by any single component, exhibiting

81

an in-band phase noise of -92 dBc/Hz. Note that in designing the PCB, effort was made to
keep the physical size of the oscillator loop as small as possible, with the loop filter and
RF VCO placed as close as possible to the PLL IC.
The MEMS-based reference oscillator for the discrete synthesizer system described
above consists of the MEMS resonator configured in negative feedback Pierce topology
(Figure 36). The Pierce configuration is commonly used for crystal based oscillators and
is well known for its high reliability since stray reactances tend to appear across the shunt
capacitors in lieu of the crystal. Using the 180 degrees in the loop from the inverting
amplifier, a Pierce oscillator may be constructed whereby the additional 180 degrees is
contributed by the reactance of the -network consisting of the resonator and parallel
capacitors. The main difficulty with this approach is that proper characterization of the
resonator's parallel and series capacitance is needed to accurately size the circuit
components for a given frequency of oscillation (Equation 32).

Figure 36: Circuit schematic of MEMS resonator connected in Pierce oscillator configuration
X X
Series
C L
f

=
t 2
1
(31)
(
(

+ =
eq
X
Series Parallel
C
C
f f
2
1 (32)
2 1
2
1
C C
C
C C C
o eq
+
+ = (33)
The TIA IC that was selected for the sustaining amplifier is the SA5211 from NXP
Semiconductors. The device is characterized by a 14 k single-ended output
transresistance, a 180 MHz bandwidth, an extremely low noise of 1.8 pA/Hz and a 5V
supply voltage. The IC also has low input and output impedances to help reduce loading

82

on the resonant MEMS device. Because the options for a commercial high gain TIA are
limited, a variable gain amplifier (VGA) was also included within the reference loop to
provide the flexibility to increase the gain beyond the 14 k provided by the TIA.
Considering that typical oscillators can require a loop gain as high as 3 to ensure start-up,
the 14 k provided by the TIA may only be functional for MEMS devices that have a
motional resistance of 4.7 k or less, illustrating why additional gain is necessary. Also
consider that there are other loss mechanisms within the circuit that will further contribute
to reducing the loop gain. Note that a second VGA was included outside the loop for
adjusting the power feeding the reference input of the ADF4153 PLL IC. The additional
amplifier was included in the event that a higher input power level would be needed. In
both cases, the VGA device that was selected is the AD8367 from Analog Devices, which
is capable of providing 45 dB of gain up to several hundred megahertz.
C. Test Setup
Figure 37 below illustrates the laboratory test setup for the MEMS resonator demo
PCB. The setup shown assumes that the resonators are packaged using the
aforementioned vacuum packaging solution from CMC Microsystems, the only difference
being that the smaller 28-pin LCC package is used (Figure 24). Alternatively, if standard
packaging is used, the entire PCB needs to be placed inside the vacuum chamber, similar
to the setup illustrated in Figure 29. The PCB interfaces with the PC using a specially
configured D-sub cable connected to the PC's printer port.

Figure 37: MEMS demo PCB laboratory test setup

83

III. CONCLUSION
This Chapter presented the design of two PCBs fabricated to evaluate the fully
integrated frequency synthesizer and MEMS-based reference oscillator described in
Chapter 2. Whereas the first PCB design was dedicated to testing the MEMS-based
frequency synthesizer system in its entirety, the second PCB design was conceived
exclusively for the evaluation of the MEMS resonators using only COTS surface mount
components. The first PCB design incorporated a great deal of flexibility to ensure that all
potential test cases were considered. For the second PCB design, the small form-factor
could easily be adjusted to accommodate different wireless standards and is easy to use
with software available online from Analog Devices. Included in this Chapter for both
designs were aspects related to specialized PCB circuitry, electromagnetic compatibility
(EMC), test methodology and design evolution.
In Chapter 5, the measured data for each of the different devices mounted in their
respective PCBs will be presented.

84


Chapter 5

Experimental Results







Experimental evaluation of the MEMS-based frequency synthesizer and MEMS
resonator demo PCB are presented in this Chapter. Included are important system level
characteristics and a comparison to noise simulation results where relevant. For the
MEMS-based frequency synthesizer, benchmarking against recently published
synthesizer designs is also covered.
I. MEMS-BASED FREQUENCY SYNTHESIZER
The four device iterations of the frequency synthesizer and TIA IC were fabricated
using an 0.18 m CMOS process. Micrographs of each of the four dies are provided in
Figures 38 to 41. Devices 1 to 3 had identical dimensions of 2.5 mm by 2.5 mm for a total
area of 6.25 mm
2
. For device 4, the dimensions were slightly modified to 2.3 mm by 2.8
mm in order to accommodate a request from the fabrication house, translating into a
slightly larger area of 6.44 mm
2
. The MEMS CC-beam resonator has dimensions of 25
m by 114 m, which increases to 350 m by 130 m with bond pads. For the
experimental data gathered here, the resonator was interconnected with the frequency
synthesizer using a two-chip solution at the PCB level, rather than the novel vacuum
packaged solution from CMC described in Chapter 4. In Figure 42, the micrograph of
device 4 is annotated to illustrate where the different system components have been
located on the die.

85


Figure 38: Device 1 synthesizer die (2.5 mm by 2.5 mm) Figure 39: Device 2 synthesizer die (2.5 mm by 2.5 mm)


Figure 40: Device 3 synthesizer die (2.5 mm by 2.5 mm) Figure 41: Device 4 synthesizer die (2.3 mm by 2.8 mm)

Observing the micrographs of the four different devices, some aspects of the design
evolution described in Chapter 2 become apparent. Most obvious are the RF VCO, loop
filter and TIA design modifications.
Devices 1 and 2 have each been equipped with two VCOs; a low gain version
requiring a switched capacitor bank to cover the desired output range, and a high gain
version capable of covering the same range using a single voltage tuning cycle. For

86

device 3, the high gain VCO is replaced by an improved version characterized by a
complimentary topology and differential inductor, as described in Chapter 3. For device 4
the low gain VCO is removed to liberate chip area for the loop filter and integrated
decoupling capacitor. While the topology of the loop filter did not change from one
device to the next, the size of capacitors are adjusted to optimize the loop bandwidth and
improve system stability as needed. For the TIA, located on the top right hand side of the
micrographs, changes to the stabilizing capacitors are apparent in the different images.

Figure 42: Device 4 synthesizer die micrograph identifying the different system components
Decoupling
Capacitor
Complimentary
VCO
Loop Filter
-
Modulator
& Divider
Capacitor
Bank
CP & PFD
Loop Filter
Capacitors
I/O
Logic
TIA

87

As demonstrated in Chapter 2, the noise of the frequency synthesizer output is largely
influenced by the noise of the reference oscillator. Prior to delving into the measured
performance of the frequency synthesizer, a performance summary of the MEMS-based
reference oscillator is provided in Table 9 for an 8.3 MHz device and an 11.6 MHz
device. The interconnection between the integrated TIA and the resonator is as was
shown in Figure 11. An Agilent E4440A performance spectrum analyzer was used to
record the measurements via a buffered oscillator output so as not to load the loop.
Table 9: MEMS resonator oscillator performance summary (data from [3])
Parameter Value
Resonant Frequency (MHz) 8.3 11.6
Resonator Material SiC Composite
Resonator Quality Factor 1040 700
Calculated Resonator Power Handling (W) 1.01 3.39
Polarization Voltage (V) 2 5
Phase Noise at 100 kHz (dBc/Hz) -89 -85
Phase Noise at 100 kHz (dBc/Hz) -106 -115
From Table 9, the phase noise performance of the 8.3 MHz MEMS oscillator is
superior that the 11.6 MHz version at small frequency offsets, but worse at larger offsets.
The higher quality factor of the 8.3 MHz device translates into lower damping resulting
from the reduced anchor loss [3], translating into improved phase noise performance at
small offsets from the carrier. At larger offsets, the better power handling of the 11.6
MHz resonator provides higher beam stiffness and improved phase noise compared to the
lower frequency device.
Figure 43 provide the measured output phase noise spectrum for the 11.6 MHz
MEMS reference oscillator in various operating modes. Although a vacuum environment
is preferred, the oscillator is still able to startup and sustain oscillation in air. Clearly, the
phase noise performance is degraded, although it may be tolerable for certain
applications. Figure 43 also illustrates the benefits of automatic gain control to reduce
noise-folding due to resonator non-linearities [15] and improve phase noise close to the
carrier. The red curve illustrating the phase noise spectrum for the 11.6 MHz MEMS
oscillator in a vacuum environment with the AGC enabled and illustrates the best
achievable compromise between close-in and far-out phase noise.

88


Figure 43: 11.6 MHz MEMS-based reference oscillator phase noise (data from [2])
Figure 44 shows the simulated and measured output phase noise for the fully-
integrated frequency synthesizer with a 10 MHz TCXO reference, as well as with a 11.6
MHz MEMS reference. The system output frequency for all traces shown is 1800 MHz.
The measured data in Figure 44 is taken from device 4, the most mature version of the
synthesizer developed as part of this project. As expected, the higher quality factor and
power handling capability of the crystal provides a significantly better output phase noise
compared to the MEMS implementation. Comparing the measured data for the TCXO
reference to the simulation data, the noise in-band of the loop is degraded by a maximum
of 12 dB, which causes a significant difference in terms of integrated phase noise. The
large discrepancy can possibly be attributed to some noise contributors, such as the
modulator and divider, absent from the simulation model. Alternatively, noise generated
by off-chip sources (e.g. discrete digital circuitry, power supplies) may also have had an
impact. Despite the difference in magnitude, the shape of the measured noise profile
follows simulation rather well, indicating that the in-band noise is dominated by the
integrated loop filter. For simulation with the MEMS oscillator, the noise of the reference
swamps the in-band phase noise, as was previously shown in Chapter 2.
Figure 45 illustrates operation at an output frequency where the fractional spurs are
more apparent. At 1800 MHz, the RF frequency is an integer multiple of the 10 MHz
TCXO reference and fractional spurs are not apparent, although reference spurs are

89

clearly visible. At 1802.5 MHz, fractional spurs appear, with the largest spur occurring at
2.5 MHz offset from the carrier at a level of -80 dBc. Also of note is a 4 dB increase in
in-band noise, which could have several different explanations, even though the is
operating at both output frequencies.

Figure 44: Phase noise comparison for an 1800 MHz output (device 4)

Figure 45: Output phase noise comparison for fractional-N and integer-N operation
(TCXO reference - device 4)
Figure 46 provides a comparison of the output phase noise for the different PLL IC
devices. For device 1, a connectivity issue with one of the output buffers caused the
output power to be upwards of 10 dB lower than expected, significantly degrading several

90

performance metrics. As such, device 1 is excluded from the following performance
comparison that follows. Note that the data for devices 2 and 3 is as was published in [2]
and [3], respectively. As such, device 2 utilizes an 8.3 MHz MEMS reference, whereas
device 3 utilizes an 11.6 MHz resonator. The measured phase noise spectrum for device 4
is provided for the TCXO reference oscillator as the MEMS resonators were in
fabrication and not available at the time of measurement.

Figure 46: Synthesizer output phase noise at 1800 MHz for the different devices
The most notable disparity between the different plots is the out-of-band phase noise,
where the VCO contribution is dominant. Device 2, which utilizes the original LC cross-
coupled pair VCO, has a phase noise of -118.4 dBc/Hz at a 1 MHz offset from the carrier.
Devices 3 and 4, on the other hand, utilize the complimentary VCO described in Chapter
3 which produces a phase noise of -126.3 at the same 1 MHz offset. The small difference
in the out-of-band noise of devices 3 and 4 illustrates that the nature of the reference
oscillator has little effect on the phase noise of the synthesizer at large offsets from the
carrier. The improvement of in-band noise from device 2 to device 3 is a result of a
number of factors including a higher frequency reference (lower divider ratio), as well as
improvements to the TIA and loop filter, as described in Chapter 2. A summary of the
various measured performance metrics for the different devices is provided later in this
Chapter.
Figure 47 illustrates the transient response of the frequency synthesizer when the
divider value is changed. The 120 MHz frequency transition causes a sudden adjustment

91

of the VCO control voltage, providing the waveforms shown below. The measurement,
performed on device 3, illustrates both a step-up and a step-down in frequency. The
ringing shows that the loop is underdamped and good symmetry in the up and down
waveforms illustrates good matching between the charge pump current sources. The
worst-case synthesizer lock time observed is 200 s, which is fast enough to meet the
requirements of a number of different wireless standards (e.g. DCS-1800, WLAN and
Bluetooth).

Figure 47: Typical example of VCO control voltage during 120 MHz change in frequency (device 3)
Figures 48 provides an output spectrum illustrating five closely spaced output
frequencies. The synthesizer, operating in fractional-N mode, has been tuned in steps of
1.25 MHz to demonstrate output power and reference spur levels. The worst-case
reference spur level of -72 dBc for device 3 remains short of the DCS-1800 requirement
of -80 dBc. In this particular instance, reference spurs at an offset equal to the second
harmonic of the 10 MHz TCXO provided the worst case levels, a trend that is not
observed in general.
Figure 49 shows that smaller frequency tuning steps are possible, illustrating a 160
Hz step size (~0.09 ppm) around a 1.8 GHz carrier. Although it was shown in Chapter 2
that a frequency resolution of 11 Hz (~0.006 ppm) was theoretically possible given the
24-bit modulator, the reality is the stability of the reference oscillator limits the step
size that can be practically measured.

92


Figure 48: Output spectrum of the synthesizer for frequencies spaced by 1.25 MHz about 1.8 GHz
(device 3)

Figure 49: Measured output spectrum of the synthesizer finely tuned in steps of 160 Hz (approx.
0.09ppm) about 1.8 GHz (device 3)
Another important feature of the MEMS-based frequency synthesizer developed here
is dithering. Dithering is used to randomize the divider sequence produced by the
modulator and reduce quantization noise effects, potentially lowering fractional spur
levels. Figure 50 shows the output spectrum with and without dithering enabled. Note that
averaging has been used on the right hand plot to make the fractional spurs more visible.
As can be observed, the effect of dithering is to reduce the level of sub-fractional spurs,
rather than the main fractional spurs, as described in [50]. Sub-fractional spurs are spurs
that occur at a fraction of the channel spacing. These spurs are more pronounced for
-100
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
1770 1780 1790 1800 1810 1820 1830
O
u
t
p
u
t

P
o
w
e
r

(
d
B
m
)
Frequency (MHz)
fo = 1797.5 MHz
fo = 1798.75 MHz
fo = 1800 MHz
fo = 1801.25 MHz
fo = 1802.5 MHz
-72 dBc
-70
-60
-50
-40
-30
-20
-10
0
-0.25 -0.2 -0.15 -0.1 -0.05 0 0.05 0.1 0.15 0.2 0.25
O
u
t
p
u
t

P
o
w
e
r

(
d
B
m
)
Frequency Deviation (ppm)
160 Hz

93

higher order delta-sigma modulators [50]. For the case shown in Figure 50, dithering
reduced the sub-fractional spurs at 5 kHz offset from the carrier by approximately 15 dB.

Figure 50: Measured effect of dithering on fractional spurs (device 2)
Table 10 provides a performance summary of the frequency synthesizer reported
here. The first column lists the DCS-1800 cellular network specifications as given in [51]
and [52]. Subsequently, data for device iterations 2, 3 and 4 are provided, as well as some
benchmarking information for two similar crystal-based frequency synthesizer systems.
Some of the listed performance parameters, such as in-band phase noise, are provided for
both a TCXO reference and a MEMS reference. The purpose of including both sources is
to ease comparison between the different device iterations, as well as the benchmarking
information.
For DCS-1800, two settling time requirements are listed in Table 10; 865 s for
standard communication and 288 s for the high-speed data communication service [52].
For DCS-1800, the standard frequency step is 95 MHz and the required frequency
tolerance is 180 Hz. Since the PLL must complete the required frequency step in less than
1.5 time slots, where each time slot is 577 s, the resulting settling time is 865 s.
The term loop bandwidth in Table 10 refers to the design target rather than the 3 dB
bandwidth observed on the plots.
The integrated RMS phase error in Table 10 is calculated applying a brick wall filter
to the output phase noise spectrum between 10 kHz and 100 MHz (Equation 36). Note
that for the IPN values provided for devices 2, 3 and 4, spurs in the output spectrum were
not omitted from the calculation.

94

( )df f L
b
a
radians degrees
}
= = 2
180 180
t
o
t
o (36)
Table 10: Frequency synthesizer performance summary and benchmarking
Reference DCS-1800 Device 2 Device 3 Device 4 [6] [51]
Fabrication
Technology
- 0.18 m 0.18 m 0.18 m 0.40 m 0.25 m
Output Frequency
Range (MHz)
1710 to
1880
1650 to 2000 1650 to 1980 1710 to 1890
1700 to
1890
1583 to
2093
Reference
Frequency (MHz)
- 8.3 11.6 11.6 26.6 26
Loop Bandwidth
(kHz)
- 25 42 51 45 35
Supply Voltage (V) - 2 2 2 3 2
In-Band Phase Noise
(dBc/Hz)
-
-48 (TCXO)
-50 (MEMS)
-74 (TCXO)
-60 (MEMS)
-77 (TCXO)
-87
(TCXO)
-60
(TCXO)
Phase Noise at 600
kHz (dBc/Hz)
-116 -116 -122 -123 -121 -120
Phase Noise at 3
MHz (dBc/Hz)
-133 -131 -137 -137
Not
Reported
-139
RMS Phase Error
10 kHz to 100 MHz
(degrees)
2
43.8 (TCXO)
44.0 (MEMS)
12.6 (TCXO)
19.6 (MEMS)
3.6 (TCXO)
Not
Reported
3 (TCXO)
Frequency
Resolution (kHz)
200 0.22 0.16 0.16 200 0.4
Reference Spurs
(dBc)
-80 -56 -72 -70 -75 -75
Fractional Spurs
(dBc)
-80 Not Measured -79 -80
Not
Reported
-100
Settling Time (s) 865/288 Not Measured 200 190 300 226
Power Consumption
(mW)
- 50 39 41 51 70

Observing Table 10, it is clear that the performance of the synthesizer improves
steadily with each device iteration. The measured data also compares well to the
benchmarking information when the synthesizer is driven by a TCXO. For the case of a
MEMS reference, the in-band phase noise and integrated phase noise both degraded
significantly on account of the degraded quality of the reference source. To improve in-
band and integrated phase noise of the synthesizer, higher frequency MEMS devices
could be used that would lower divider ratios. Notice that the two synthesizers in [6] and
[51] each used a 26 MHz frequency reference, which would theoretically improve in-

95

band phase noise by more than 7 dB compared to an 11.6 MHz reference. Alternatively,
the in-band and integrated phase noise performance can also be improved by using higher
quality factor MEMS resonators. As described in Chapter 2, more complex resonant
MEMS devices (e.g. disk resonators in [1]) have been shown to provide high quality
factors, in excess of 10,000 in some cases. These more complex MEMS structures could
potentially be fabricated using the same low-temperature silicon carbide CMOS-
compatible process used here for the CC-beam resonators without changes to the process
methodology [3]. Theoretically, according to Leeson's equation in (21), this improvement
by a factor of ten would potentially improve phase noise by 20 dB.
Another area where the synthesizer falls short compared to the DCS-1800
requirements is reference spurs (Table 10). One method to reduce feedthrough of the
reference is to further optimize matching of the charge-pump current sources. Poorly
matched up and down currents deposit charge at the loop filter input, triggering a
frequency adjustment from the VCO and other synthesizer components. For this reason,
proper biasing of the charge pumps is imperative to ensure the currents are matched.
II. MEMS-BASED FREQUENCY SYNTHESIZER WITH OFF-CHIP LOOP FILTER
As described in Chapter 4, the MEMS resonator frequency synthesizer IC and PCB
has been equipped with an active off-chip loop filter to allow for iterative evaluation and
optimization of PLL performance. A passive loop filter could also have been used, except
that because of the negative VCO gain and particulars of the charge pump design, a
change in polarity is needed.
Figures 51 provides a comparison of the simulated synthesizer output phase noise
performance between the original integrated loop filter and the off-chip loop filter. As can
be observed, the off-chip loop filter provides an improvement of more than 6 dB in-band,
as well as a significant reduction in integrated phase noise. Figure 52 illustrates the same
comparison for measured data. Although the improvement provided by the discrete loop
filter is somewhat smaller in this instance, the overall result is similar. Also of note is how
the output phase noise with off-chip loop filter exhibits a much cleaner profile outside the
loop bandwidth. On account of larger capacitors and thus a lower frequency zero, better
suppression of the out-of-band spurious is provided.

96


Figure 51: Simulated synthesizer phase noise with on-chip and off-chip loop filter (TCXO reference)

Figure 52: Measured synthesizer phase noise with on-chip and off-chip loop filter (device 4 - TCXO)
Table 11 provides a summary of the synthesizer performance with each of the
aforementioned loop filters. As can be observed, the modest improvement to the output
phase noise results in an RMS phase error that is well within the requirements of DCS-
1800. Also of note is the phase noise improvement at 600 kHz offset from the carrier,
which demonstrates the increased damping provided by the off-chip loop filter. Despite
the improved performance, a discrete loop filter is generally not an option for high

97

volume applications considering the PCB area and cost required. Another alternative
worth investigation is the use of a passive integrated loop filter based on the same dual
path concept as the integrated loop filter presented here.
Table 11: Comparison between integrated and discrete loop filter implementations
Reference
Device 4 with On-
Chip Loop Filter
Device 4 with Off-
Chip Loop Filter
Minimum In-Band Phase Noise (dBc/Hz) -77 (TCXO) -77 (TCXO)
Phase Noise at 600 kHz (dBc/Hz) -121 -123
Phase Noise at 3 MHz (dBc/Hz) -136 -137
RMS Phase Error 10 kHz to 100 MHz (degrees) 3.6 (TCXO) 1.3 (TCXO)
III. MEMS RESONATOR DEMO PCB
The MEMS resonator demo PCB was fabricated as per the description provided in
Chapter 4. For test purposes, the synthesizer is programmed from a PC using software
available from Analog Devices and a specially configured D-sub cable connected to the
PC's printer port. The complete test setup is as previously shown in Figure 37.
A. Transimpedance Amplifier
The purpose of the sustaining amplifier is to compensate for the high motional
resistance of the MEMS resonator and hence maintain continuous oscillation in the loop.
As described in Chapter 1, two conditions are required to achieve steady-state oscillation:
1) the loop gain must be equal to unity and 2) the phase shift around the loop must be
zero or an integer multiple of 2. To meet the phase shift requirement, a bandwidth that is
an order of magnitude greater than the frequency of oscillation is needed to ensure small
phase shift around the positive feedback loop. For a negative feedback loop, such as the
Pierce oscillator configuration used here, the 180 degrees is contributed by the negative
output of the TIA, meaning the phase shift still needs to be kept small. Since the resonant
frequencies of the CC-beam devices ranged from 4 MHz to 30.5 MHz, a bandwidth of
greater than 300 MHz is needed.
Figure 53 illustrates the measured open loop gain for the sustaining amplifier
consisting of the TIA IC and VGA described in Chapter 4. The measurement was carried
out using a Hewlett Packard 8753D network analyzer. Note that it is possible to increase
the gain beyond the level shown, up to a theoretical maximum of approximately 63 dB. It

98

is also important to note that the decibel values shown are for voltage gain. Although a
transimpedance amplifier has a current input and voltage output, conventional test
equipment used for measuring the gain and bandwidth of amplifiers is for voltage input
and voltage output. As a result, for gain measurements, a series resistor is added at the
input port of the TIA IC to convert the input voltage to a current. The sizing of the series
resistor is selected such that it is sufficiently large to limit the input current level from
damaging the TIA IC. Such a resistor is also included in the loop with the MEMS
resonator for the same purpose. Figure 54 is a schematic of the test setup, and includes the
input and output resistances of the measurement equipment and ICs involved. Equations
35 to 37 demonstrate how the single-ended TIA gain converts into a voltage gain in dB,
ranging between 21 and 63 dB, depending on the VGA setting.

Figure 53: Sustaining amplifier measured open poop gain for MEMS resonator demo PCB

Figure 54: Sustaining amplifier open loop gain measurement setup
VGA AD8367
14 200
0
50
RES IN
1k
TIA SA5211
200
0
RES OUT
50 50

99

O = =

k
I
V
Gain TIA
IN
OUT
Ended Single
4 . 14 (35)
Gain VGA k
V
V
IN
LOAD
+
|
.
|

\
|
+
O =
14 200
200
1200
1
4 . 14 log 20
10
(36)
dB dB dB Gain VGA dB
V
V
IN
LOAD
5 . 63 5 . 42 0 . 21 0 . 21
max
max
= + = + + = (37)
B. Frequency Synthesizer
Figure 55 provides the measured and simulated phase noise output spectrum for the
MEMS resonator demo PCB frequency synthesizer. The measurements are performed
with the synthesizer output set to 1800 MHz. The measured PLL phase noise is -131
dBc/Hz at 600 kHz offset and -143 dBc/Hz at 3 MHz offset. Observing the measured
output spectrum, fractional spurs are not visible whereas reference spurs appear far from
the carrier, as expected. There is a small noise perturbation at around 50 kHz offset from
the carrier that slightly increases the measured integrated phase noise and makes the 3dB
bandwidth appear larger than it actually is.

Figure 55: Measured and simulated output phase noise at 1800 MHz for MEMS resonator demo PCB
Comparing the measured and simulated synthesizer output performance for a 10 MHz
TCXO reference (Figure 55) shows relatively good agreement across the output
frequency spectrum. Inside the synthesizer loop bandwidth, the noise of the measured

100

data is degraded by a maximum of 8 dB compared to simulation, similar to the fully-
integrated frequency synthesizer in Figure 44. Outside the loop, the measured phase noise
is actually slightly better than the value predicted by simulation since the simulation
model utilized the maximum phase noise specification as provided by the VCO
manufacturer.
For the simulated data using the MEMS reference, the significantly higher noise level
of the reference oscillator swamps the noise generated by all the other PLL components
combined, except at large offsets where the VCO noise is dominant.
Figure 56 illustrates the output phase noise for the MEMS resonator demo PCB
operating at 1802.4 MHz. Since the output frequency is no longer an integer multiple of
the reference, fractional spurs are apparent in the output spectrum. Note that apart from
those spurs, the remainder of the noise profile is not affected by the change in output
frequency.

Figure 56: Measured output phase noise at 1802.4 MHz for MEMS resonator demo PCB
The level of the fractional spurs can be reduced by programming the PLL IC in low
spur mode at the expense of approximately 6 dBc/Hz in-band of the loop. In low spur
mode, dithering is enabled and the repeat length of the code sequence in the -
modulator is extended, increasing the interval between fractional spurs and making the
quantization noise appear more like broadband noise [48]. For the measurements and
results provided here, the PLL IC is consistently set to operate in low noise mode

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(dithering disabled), which provides the best output phase noise performance. As the loop
is widened however, the rejection of fractional spurs degrades and a change in operating
mode may be in order.
C. Performance Summary
A summary of the measured synthesizer performance is provided in Table 12 below.
The output frequency range is over 500 MHz and the output power is relatively flat. The
out-of-band phase noise performance is significantly better than the integrated synthesizer
as a result of the discrete VCO. Compared to the -124 dBc/Hz at 600 kHz offset observed
for the integrated complimentary VCO, the discrete version exhibits -131 dBc/Hz at the
same offset. This difference comes as no surprise considering the greater voltage swing
and higher current provided to the oscillator circuit. The 12-bit modulus of the PLL IC
does not achieve the same low frequency resolution of the fully-integrated frequency
synthesizer in Section I. Finally, note that the power consumption of 119 mA includes all
surface mount components for both the frequency synthesizer and sustaining amplifier.
Table 12: MEMS resonator demo PCB frequency synthesizer performance summary
Parameter Value
Output Frequency Range (MHz) 1590 to 2110
Reference Source TCXO
Reference Frequency (MHz) 10
PLL IC Operating Mode Low Noise
3dB Bandwidth (kHz) 30
Supply Voltage (V) Various
Charge Pump Current (mA) 5
Output Power (dBm) -5 to +1
In-Band Phase Noise (dBc/Hz) -87
Phase Noise at 600 kHz (dBc/Hz) -131
Phase Noise at 3 MHz (dBc/Hz) -143
RMS Phase Error 10 kHz to 100 MHz (degrees) 0.8
Frequency Resolution (kHz) 2.4
Reference Spurs (dBc) -75
Fractional Spurs in Low Noise Mode (dBc) -78
Settling Time (s) 250
Total PCB Power Consumption (mW) 119

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IV. CONCLUSION
This Chapter provided an experimental performance summary of the MEMS-based
frequency synthesizer and MEMS resonator demo PCB. Included for the former were
micrographs of the four fully integrated synthesizer design iterations, measured data
characterizing the MEMS-based reference oscillator, several performance metrics (e.g.
phase noise, spurious, settling time) of the frequency synthesizer with TCXO and MEMS-
based references, as well as benchmarking against recently published synthesizer designs.
The shortcomings of the integrated loop filter were also highlighted by the evaluation of
synthesizer performance using a discrete fourth order active off-chip loop filter. For the
MEMS resonator demo PCB, experimental data characterizing the gain and bandwidth of
the discrete transimpedance amplifier was presented. Finally, simulation data of the
discrete frequency synthesizer driven by a MEMS-based reference and crystal reference
was also provided, as well as experimental data for the latter.

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Chapter 6

Conclusion








I. SUMMARY AND CONTRIBUTIONS
Extensive research has been conducted over the past decade to develop integrated
replacements for high quality factor off-chip components. Micro-electromechanical
systems based technology offers great promise as a result of improved reliability,
microscale size, integration potential and ultimately lower overall cost. In this work, the
design, optimization, characterization, and test of a fully integrated frequency synthesizer
served to demonstrate a proof-of-concept for using MEMS-based clamped-clamped beam
resonators in front-end RF systems. In the near term, these MEMS-based oscillators are
targeted towards less stringent wideband wireless and wireline applications, with an
ongoing objective of meeting the specifications of high-end communication standards
such as DCS-1800, WLAN and SONET.
The importance of this work is that it provided a detailed characterization of a
programmable MEMS-based oscillator, including features such as the resonator driving
mechanism and oscillator programming methodology. Details regarding system
integration of the phase-locked loop, the MEMS resonator and the associated sustaining
amplifier have highlighted issues related to managing circuit interfaces, system level
performance and test methodology. Design and optimization of the different synthesizer
components over the four device iterations, including the charge-pump, loop filter and

104

digital logic, provided a thorough evaluation of the system development. A systematic
review of current phase noise theory and recent publications provided a roadmap for
topology and inductor redesign that was applied to a baseline LC VCO. Finally,
simulation and test of the complete system, facilitated by the design of dedicated high
quality printed circuit boards, provided performance metrics that could be benchmarked
against conventional crystal based systems to identify where deficiencies exist. In
addition to supporting the system test methodology and providing a programming
interface for the various operating modes, the PCBs needed to present the ability to
switch between different reference sources and accommodate novel packaging solutions.
As a separate endeavor, a small form-factor PCB dedicated to the rapid prototyping of
the MEMS resonators was developed. Included as part of the design was circuitry to
characterize the MEMS resonator open loop, both with and without the TIA. This
approach offered a simplified programming interface, a compact structure and the
flexibility to adjust for different wireless standards, among other benefits.
II. FUTURE DIRECTIONS
The most useful application of this work in the near term would be to incorporate a
programmable frequency divider circuit at the output and use the complete system as a
MEMS-based reference clock in applications with less stringent noise requirements. It
can be shown using the measured data provided in Chapter 5 that a division of the
MEMS-based frequency synthesizer output would yield jitter in the sub-picosecond
range. As previously discussed, wideband wireless applications and wireline protocols,
such as USB, PCI or CANbus are suitable targets because of their relaxed reference
frequency stability requirements.
For other future work, additional optimization of the fully integrated synthesizer
could be achieved by employing schemes to improve spurious performance by better
matching the charge-pump current sources to reduce feedthrough of the reference.
Another potential improvement would be to incorporate a passive integrated loop filter
based on the same dual path concept as the integrated loop filter presented here. Such a
modification would remove the active component and presumably improve in-band phase
noise. The drawback of using a passive loop filter implementation is the compliance

105

voltage requirement on the charge-pump current sources, making it difficult to reduce
noise without making the transistors too large [53].
Incorporating a linearization scheme to reduce the effects of the highly nonlinear
VCO gain on the stability of the synthesizer is another interesting option. One scheme
would be to adjust the current sources according to the VCO gain in order to maintain the
loop gain, as in [6]. Alternatively, a second linearization strategy would be to adjust the
VCO capacitor bank such that any output frequency may be produced in the low gain
region of the VCO. This latter approach has already been applied manually during the
performance evaluation of the system in Chapter 5.
MEMS resonator development is likely the area most in need of further development.
As illustrated throughout this work, where MEMS resonators need improvement is in
terms of quality factor, power handling and output frequency stability. To optimize the
output phase noise provided by the MEMS based oscillators shown here, higher
frequency devices are needed to reduce divider ratios, as well as more complex structures
using the same low-temperature silicon carbide CMOS-compatible process. These
improvement strategies are currently underway at the Wireless ICs and MEMS research
group at McGill University.
Finally, for the MEMS resonator demo PCB, the most useful improvement going
forward would be the addition of automatic gain control functionality to prevent large
oscillations in the loop from exerting the MEMS resonator non-linearities. As previously
discussed, those non-ideal effects can degrade phase noise both close to the carrier and
far-out if the amplitude is not appropriately controlled. Typically, a rectifier, peak
detector and comparator would need to be incorporated on the PCB to accomplish this
task.


106

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