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Presentation Outline
Chapter 1 -------------------------------Introduction to VME Chapter 2 -------------------------------VME Architecture Chapter 3 -------------------------------Data Acquisition Setup under VME Chapter 4 -------------------------------Data Acquisition with VME Modules using LAMPS
Introduction to VME
VME stands for VERSA-Module Euro card introduced in 1981 for industrial, commercial and military applications. Electrical and mechanical specifications are defined by the standard. VME bus is a master-slave computer architecture. The signaling scheme is asynchronous, meaning that the transfer is not tied to the timing of a bus clock. VITA (VME International Trade Association) is the organisation whose purpose is to promote and develop the VME
VME Components
VME master VME slave VME Crate
power supply
Single Width 6 U Module having 32 Peak Sensing Analog to Digital conversion channel. High channel density 12-bit resolution 5.7 s / 32 channel conversion time Zero and overflow suppression for each channel 32 event buffer memory
Single Width 6 U Module 32 Channel Latching Scaler The counters values can be read on the fly from VME without interfering on data acquisition process.
Besides these, as of date, LAMPS provides support for V862 32 Channel Multi event Individual Gate QDC; support for V775 32 Channel Multievent TDC and MesyTec High resolution(11 to 13 bit) ADCs MADC-32
Chapter 2 --------------------------------
VME Architecture
MASTER BACKPLANE INTERFACE LOGIC
BG[3..0]OUT*
SLAVE
BG[3..0]IN*
IRQ[7..1]*
IRQ[7..1]*
LW ORD*
LW ORD*
SYSRESET*
BR[3..0]*
DTACK*
AM[5..0]
DTACK*
AM[5..0]
W RITE*
W RITE*
BERR* D[31..0]
D[31..0]
A[31..1]
Electrical Properties All lines use TTL levels ; Low = 0 .. 0.6 V; High = 2.4 .. 5 V Address, Address Modifier and data lines are active high; Protocol lines are active low.
A[31..1]
SYSRESET*
BERR*
ACFAIL*
BCLR*
BBSY*
SYSCLK
IACK*
IACK*
DS0*
DS1*
DS0*
DS1*
AS*
AS*
DATA TRANSFER BUS (DTB) DTB ARBITRATION BUS PRIORITY INTERRUPT BUS UTILITY BUS
FIFO Memories
Many VME acquisition boards use FIFO memories to store the data. This is particularly suitable for physics applications in which the events occur randomly in time and are readout sequentially A read access to any address within that range causes the non repeatable extraction of one word from the FIFO. CAEN ADC modules are endowed with 32 Events Buffer.
Interrupts in VME
The VME features a 7 level prioritized interrupt architecture; the request lines IRQ[7:1] are shared between all the slots The interrupt is initiated by the interrupter (this can be any board in any slot) that asserts one IRQ. The interrupt handlers (usually the board in slot 1) monitor the IRQ lines and generate an interrupt acknowledge cycle in response to the request The interrupt handler reads the STATUS/ID of the interrupter from the data bus If more interrupters had asserted the same IRQ line, the IACKINIACKOUT daisy chain allows the uppermost left to respond first (priority given by the position)
Chapter 3 --------------------------------
C. A. E. N.
C. A. E. N.
FPGA
VMEbus
A2818 FPGA
PCI-int
RAM buffer Optical Link RAM buffer
CONET
Optical Link
PCI bus
C 2
B CD E B CD E B CD E F01 F01 F01
4
2 2
3 45 6 3 45 6
8
B CD E F01
OFFSET
Address Space: 16 Kbytes from 0xC2480000 to 0xC248FFFF OFFSET: which register inside the board
2
3 45 6
2
3 45 6
A24 mode
31 24 23 16 15 0
unused
B CD E F01
4
2
3 45 6
8
B CD E F01
7 89
7 89
2
3 45 6
7 89
7 89
7 89
7 89
OFFSET
Operational Aspects
Controller should be inserted in slot 1 of the VME Crate. While setting up the CBLT Chain, the modules forming the chain should be contiguous; last module should be terminated with a 50 Ohm resistance. Scalars can be inserted in any empty slot. MesyTec ADCs, if used along with CAEN Modules, should be inserted first in the chain.
Chapter 4 --------------------------------
Hardware/Software layers
DAQ Software (LAMPS)
A2818 Driver
Digitizer Modules
VME Bus
V2818 Controller
PCI Bus
CONET
Software Installation
Installation of A2818 (PCI CONET Controller) driver
- CAEN A2818 PCI CARD - Linux kernel Rel. 2.4 or 2.6 with gnu C/C++ compiler PCI CONET Controller
Installation of LAMPS
No changes in the LAMPS installation procedure.
Post hardware setup and software installation, basic connectivity with the Bus Adapter can be checked using the Test Feature of the LAMPS software. Indication of an error at this stage implies an incorrect hardware/software setup.
Bus Adapter needs no Base Address configuration. For other modules, setting up of Base Address in software is compulsory.
Blue Rectangular region VME Controller ; Green Rectangular Region- CBLT Chain ; Purple rectangular region - Scaler
Conclusion
The VME DAQ in the current form provides us with a powerful system because of the large number of parameters which can be acquired simultaneously and high event rates. The zero suppressed readout option along with the availability of variety of digitizers with higher channel density presents a very good system in front of users, before we eventually migrate to digital DAQ.