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SERVICE MANUAL FOR

8575A

8 5 7 5 A

BY: Sissel Diao

TESTING TESTING TECHNOLOGY TECHNOLOGY DEPARTMENT DEPARTMENT // TSSC TSSC Aug . 2002

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Contents
1. Hardware Engineering Specification
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1.1 Introduction . 4 1.2 System Hardware Parts . 6 1.3 Other Functions .. 42 1.4 Peripheral Components .. 47 1.5 Power Management 50 1.6 Appendix 1: SiS961 GPIO Definitions .. 52 1.7 Appendix 2: H8 Pins Definitions 53

2. System View and Disassembly ...

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2.1 System View . 59 2.2 System Disassembly 62

3. Definition & Location of Connectors / Switches ..

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3.1 Mother Board .. 81 3.2 DC Power Board . 84 3.3 ESB Board ... 85 3.4 Touch-pad 86 3.5 Daughter Board .. 86

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Contents
4. Definition & Location of Major Component
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4.1 Mother Board .. 87

5. Pin Description of Major Component ...

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5.1 Intel Pentium 4 Processor mPGA478 Socket ... 89 5.2 SiS650 IGUI Host / Memory Controller ... 95 5.3 SiS691 MuTIOL Media I/O Controller 100 5.4 SiS301LV / Chrontel CH7019 TV/LVDS Encoder .. 106 5.5 PCI1410GGU PCMCIA Controller .. 109 5.6 uPD72872 IEEE1394 Controller 114

6. System Block Diagram 7. Maintenance Diagnostics

116 117

7.1 Introduction . 117 7.2 Error Codes . 118 7.3 Maintenance Diagnostics 120

8. Trouble Shooting .

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8.1 No Power .. 122

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8.2 No Display 8.3 VGA Controller Failure LCD No Display 8.4 External Monitor No Display 8.5 Memory Test Error 8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error . 8.7 Hard Disk Drive Test Error .. 8.8 CD-ROM Driver Test Error .. 8.9 USB Test Error 8.10 PIO Port Test Error . 8.11 Audio Failure 8.12 LAN Test Error 8.13 PC Card Socket Failure 8.14 IEEE 1394 Failure
129 133 135 137 139 141 143 145 148 150 153 155 157 159 182 184 217

9. Spare Parts List .. 10. System Exploded Views 11. Circuit Diagram 12. Reference Material

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1. Hardware Engineering Specification
1.1 Introduction
The 8575A motherboard would support the Intel Pentium 4 processor with FC-PGA2 packaged, using 478-Pin micro PGA (mPGA478) socket, which will supports different speeds up to Willamette P4 1.7GHz (Throttling)/Northwood above 2.0GHz (Throttling). This system is based on PCI architecture, which have standard hardware peripheral interface. The power management complies with Advanced Configuration and Power Interface (ACPI) 1.0. It also provides easy configuration through CMOS setup, which is built in system BIOS software and can be pop-up by pressing F2 at system start up or warm reset. System also provides icon LEDs to display system status, such as power indicator, HDD/CDROM, NUM LOCK, CAP LOCK, SCROLL LOCK, SUSPEND MODE and Battery charging status. It also equipped 2 USB ports. The memory subsystem supports 0MB on board memory, two JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM), support PC2100 & PC2700. SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS MuTIOL Technology connecting w/ SiS961 MuTIOL Media I/O.

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The SiS961 MuTIOL Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet MAC, the Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL Connect to PCI bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O, I/O Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated. The SiS961 also incorporates an universal interface supporting the asynchronous inputs/outputs of the X86 compatible microprocessors like P4. The SiS301LV is a Display device which has two data operation paths. Channel B path is selected when SiS301LV performs TV or LCD only display function. Theres scaling hardware in this path. In LCD display mode, this hardware can make lower VGA resolution display to fit up to 1280x1024 LCD panel. In TV display mode, this scaler can provide overscan and underscan option for TV. At TV and LCD simultaneous display mode, TV data stream run through Channel B and LCD data stream run through Channel A. To provide for the increasing number of multimedia applications, the AC97 CODEC ALC201 is integrated onto the motherboard. A full set of software drivers and utilities are available to allow advanced operating systems such as Windows Me and Windows 2000 to take full advantage of the hardware capabilities such as bus mastering IDE, Windows 95-ready Plug & Play, Advanced Power Management (APM) and Advance configuration and power interface (ACPI). Following chapters will have more detail description for each individual sub-systems and functions.
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1.2 System Hardware Parts
CPU Mobile Intel Pentium 4 Processor M Built on 0.13-micron process Available speeds 1.80GHz, 1.70GHz, 1.60GHz, 1.50GHz, 1.40GHz Intel Pentium 4 processor; Willamette/Northwood with mFCPGA2 Package, mPGA 478 Socket Support up to Willamette P4 1.7GHz (Throttling) / Northwood above 2.0 GHz(Throttling) FSB 400MHz /PC 2100/1600 SiS 650+SiS961: Host & Memory & AGP Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance memory controller, a AGP interface, and SiS MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO. SiS301LV 256KB Flash EPROM Inside -Includes System BIOS, VGA BIOS, and plug & Play capability, ACPI 0MB on board memory -Two JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM) -Support PC2100 & PC2700 8/16/32/64 UMA ICS 952001 ICS 93722 Hitachi H8 3437S Card Bus Controller: TI PCI1410 One type II slot/ Card Bus support/ No ZV port support Power Switch : TI TPS2211 AC97 CODEC: Advance Logic, Inc, ALC201 Power Amplifier: TI TPA0202 NS PC87393 56Kbps (V.90, worldwide) MDC Modem ICS1893Y-10 10/100 base T PHY IEEE1394 OHCI Controller : NEC uPD72872
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Core logic

VGA Control System BIOS Memory

Video Memory Clock Generator DDR Clock Buffer Embedded controller PCMCIA

Audio System Super I/O Modem PHY of LAN IEEE1394

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1.2.1 CPU_Intel Pentium 4 Processor
Built on 0.13-micron process technology and Intel NetBurst micro-architecture, the Mobile Intel Pentium 4 Processor - M represents a new generation of mobile computing. It provides superior capabilities for graphics-intensive multimedia applications, and processor-intensive background computing tasks such as compression, encryption, and virus scanning. Enhanced Intel SpeedStep technology helps to optimize application performance and power consumption, and Deeper Sleep Alert State, a dynamic power management mode, adjusts voltage during brief periods of inactivity - even between keystrokes - for longer battery life. Innovative Micro FCPGA packaging technology enables the processor to fit into small form factors, such as thin-and-light notebooks. The Intel Pentium 4 processor, Intels most advanced, most powerful processor, is based on the new Intel NetBurst micro-architecture. The Pentium 4 processor is designed to deliver performance across applications and usages where end users can truly appreciate and experience the performance. These applications include Internet audio and streaming video, image processing, video content creation, speech, 3D, CAD, games, multimedia, and multi-tasking user environments. The Intel Pentium 4 processor delivers this world-class performance for consumer enthusiast and business professional desktop users as well as for entry-level workstation users. Highlights of the Pentium 4 Processor : Available at speeds ranging from 1.50 to 2 GHz Featuring the new Intel NetBurst micro-architecture

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Supported by the SiS650 chipset Fully compatible with existing Intel Architecture-based software Internet Streaming SIMD Extensions 2 Intel MMX media enhancement technology Memory cache ability up to 4 GB of addressable memory space and system memory scalability up to 64GB of physical memory Support for uni-processor designs Based upon Intels 0.18 micron manufacturing process Intel Pentium 4 Processor Product Feature Highlights The Intel NetBurst micro-architecture delivers a number of new and innovative features including Hyper Pipelined Technology, 400 MHz System Bus, Execution Trace Cache, and Rapid Execution Engine as well as a number of enhanced features Advanced Transfer Cache, Advanced Dynamic Execution, Enhanced Floatingpoint and Multi-media Unit, and Streaming SIMD Extensions 2. Many of these new innovations and advances were made possible with improvements in processor technology, process technology, and circuit design that could not previously be implemented in high-volume, manufacturable solutions. The features and resulting benefits of the new micro-architecture are defined below.

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Hyper Pipelined Technology: The hyper-pipelined technology of the NetBurst micro-architecture doubles the pipeline depth compared to the P6 micro-architecture used on todays Pentium III processors. One of the key pipelines, the branch prediction/ recovery pipeline, is implemented in 20 stages in the NetBurst micro-architecture, compared to 10 stages in the P6 micro-architecture. This technology significantly increases the performance, frequency, and scalability of the processor. 400 MHZ System Bus: The Pentium4 processor supports Intels highest performance desktop system bus by delivering 3.2 GB of data per second into and out of the processor. This is accomplished through a physical signaling scheme of quad pumping the data transfers over a 100-MHz clocked system bus and a buffering scheme allowing for sustained 400-MHz data transfers. This compares to 1.06 GB/s delivered on the Pentium III processors 133-MHz system bus. Level 1 Execution Trace Cache: In addition to the 8KB data cache, the Pentium 4 processor includes an Execution Trace Cache that stores up to 12K decoded micro-ops in the order of program execution. This increases performance by removing the decoder from the main execution loop and makes more efficient usage of the cache storage space since instructions that are branched around are not stored. The result is a means to deliver a high volume of instructions to the processors execution units and a reduction in the overall time required to recover from branches that have been mis-predicted.

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Rapid Execution Engine: Two Arithmetic Logic Units (ALUs) on the Pentium 4 processor are clocked at twice the core processor frequency. This allows basic integer instructions such as Add, Subtract, Logical AND, Logical OR, etc. to execute in half a clock cycle. For example, the Rapid Execution Engine on a 1.50 GHz Pentium 4 processor runs at 3 GHz. 256KB, Level 2 Advanced Transfer Cache: The Level 2 Advanced Transfer Cache (ATC) is 256KB in size and delivers a much higher data throughput channel between the Level 2 cache and the processor core. The Advanced Transfer Cache consists of a 256bit (32-byte) interface that transfers data on each core clock. As a result, the Pentium 4 processor 1.50 GHz can deliver a data transfer rate of 48 GB/s. This compares to a transfer rate of 16 GB/s on the Pentium III processor at 1 GHz. Features of the ATC include: Non-Blocking, full speed, on-die Level 2 cache 8-way set associativity 256-bit data bus to the level 2 cache Data clocked into and out of the cache every clock cycle Advanced Dynamic Execution: The Advanced Dynamic Execution engine is a very deep, out-of-order speculative execution engine that keeps the execution units executing instructions. The Pentium 4 processor can also view 126 instructions in flight and handle up to 48 loads and 24 stores in the pipeline. It also includes an enhanced branch prediction algorithm that has the net effect of reducing the number of branch mis-predictions by about 33% over the P6 generation processors branch prediction capability. It does this by implementing a 4KB branch target buffer that stores more detail on the history of past branches, as well as by implementing a more advanced branch prediction algorithm.
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Enhanced Floating-Point and Multimedia Unit: The Pentium 4 processor expands the floating-point registers to a full 128-bit and adds an additional register for data movement which improves performance on both floating-point and multimedia applications. Internet Streaming SIMD Extensions 2 (SSE2): With the introduction of SSE2, the NetBurst micro-architecture now extends the SIMD capabilities that MMX technology and SSE technology delivered by adding 144 new instructions. These instructions include 128-bit SIMD integer arithmetic and 128-bit SIMD double-precision floating-point operations. These new instructions reduce the overall number of instructions required to execute a particular program task and as a result can contribute to an overall performance increase. They accelerate a broad range of applications, including video, speech, and image, photo processing, encryption, financial, engineering and scientific applications. Features Used for Test and Performance / Thermal Monitoring: Built-in Self Test (BIST) provides single stuck-at fault coverage of the micro-code and large logic arrays, as well as testing of the instruction cache, data cache, Translation Lookaside Buffers (TLBs), and ROMs. IEEE 1149.1 Standard Test Access Port and Boundary Scan mechanism enables testing of the Pentium 4 processor and system connections through a standard interface. Internal performance counters can be used for performance monitoring and event counting. Includes a new Thermal Monitor feature that allows motherboards to be cost effectively designed to expected application power usages rather than theoretical maximums.

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1.2.2 System Frequency
1.2.2.1 System frequency synthesizer_ICS952001
Programmable Timing Control Hub for P4 processor General Description : The ICS952001 is a two chip clock solution for desktop designs using SIS 645/650 style chipsets. When used with a zero delay buffer such as the ICS9179-06 for PC133 or the ICS93705 for DDR applications it provides all the necessary clocks signals for such a system. The ICS952001 is part of a whole new line of ICS clock generators and buffers called TCH (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology and a reset feature to provide a safe setting under unstable system conditions. M/N control can configure output frequency with resolution up to 0.1MHz increment.

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Recommended Application: SiS645/650 style chipsets Output features: 2 - Pairs of differential CPUCLKs @ 3.3V 1 - SDRAM @ 3.3V 8 - PCI @3.3V 2 - AGP @ 3.3V 2 - ZCLKs @ 3.3V 1 - 48MHz, @3.3V fixed 1 - 24/48MHz, @3.3V selectable by I2 C 3 - REF @3.3V, 14.318MHz Key Specifications: PCI - PCI output skew: < 500ps CPU - SDRAM output skew: < 1ns AGP - AGP output skew: <150ps

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Features/Benefits: Programmable output frequency, divider ratios, output rise/fall time, output skew. Programmable spread percentage for EMI control. Watchdog timer technology to reset system if system malfunctions Programmable watch dog safe frequency. Support I2 C Index read/write and block read/write operations For PC133 SDRAM system use the ICS9179-06 as the memory buffer. For DDR SDRAM system use the ICS93705 as the memory buffer. Uses external 14.318MHz crystal.

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1.2.2.2 DDR buffer frequency synthesizer_ICS93722
Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: SiS645/650 style chipsets Product description/features: Low skew, low jitter PLL clock driver I2 C for functional and output control Feedback pins for input to output synchronization Spread Spectrum tolerant inputs 3.3V tolerant CLK_INT input Switching Characteristics PEAK - PEAK jitter (66MHz): <120ps PEAK - PEAK jitter (>100MHz): <75ps CYCLE - CYCLE jitter (66MHz): <120ps CYCLE - CYCLE jitter (>100MHz): <65ps OUTPUT - OUTPUT skew: <100ps Output Rise and Fall Time: 650ps - 950ps DUTY CYCLE: 49.5% - 50.5%
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1.2.3 Core Logic_SiS650 + SiS961
1.2.3.1 SiS650 IGUI Host/Memory Controller
SiS650 IGUI Host Memory Controller integrates a high performance host interface for Intel Pentium 4 processor, a high performance 2D/3D Graphic Engine, a high performance memory controller, an AGP 4X interface, and SiS MuTIOL Technology connecting w/ SiS961 MuTIOL Media IO. SiS650 Host Interface features the AGTL & AGTL+ compliant bus driver technology with integrated ondie termination to support Intel Pentium 4 processors. SiS650 provides a 12-level In-Order-Queue to support maximum outstanding transactions up to 12. It integrated a high performance 2D/3D Graphic Engine, Video Accelerator and Advanced Hardware Acceleration MPEGI/MPEGII Video Decoder for the Intel Pentium 4 series based PC systems. It also integrates a high performance 2.1GB/s DDR266 Memory controller to sustain the bandwidth demand from the integrated GUI or external AGP master, host processor, as well as the multi I/O masters. In addition to integrated GUI, SiS650 also can support external AGP slot with AGP 1X/2X/4X capability and Fast Write Transactions. A high bandwidth and mature SiS MuTIOL technology is incorporated to connect SiS650 and SiS961 MuTIOL Media I/O together. SiS MuTIOL technology is developed into three layers, the Multi-threaded I/O Link Layer delivering 1.2GB bandwidth to connect embedded DMA Master devices and external PCI masters to interface to Multi-threaded I/O Link layer, the Multi-threaded I/O Link Encoder/Decoder in SiS961 to transfer data w/ 533 MB/s bandwidth from/to Multithreaded I/O Link layer to/from SiS650, and the Multi-threaded I/O Link Encoder/Decoder in SiS650 to transfer data w/ 533 MB/s from/to Multi-threaded I/O Link layer to/from SiS961.
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An Unified Memory Controller supporting PC133 or DDR266 DRAM is incorporated, delivering a high performance data transfer to/from memory subsystem from/to the Host processor, the integrated graphic engine or external AGP master, or the I/O bus masters. The memory controller also supports the Suspend to RAM function by retaining the CKE# pins asserted in ACPI S3 state in which only AUX source deliver power. The SiS650 adopts the Shared Memory Architecture, eliminating the need and thus the cost of the frame buffer memory by organizing the frame buffer in the system memory. The frame buffer size can be allocated from 8MB to 64MB. The Integrated GUI features a high performance 3D accelerator with 2 Pixel / 4 Texture, and a 128 bit 2D accelerator with 1T pipeline BITBLT engine. It also features a Video Accelerator and advanced hardware acceleration logic to deliver high quality DVD playback. A Dual 12 bit DDR digital video link interfaced to SiS 301B Video Bridge packaged in 100-pin PQFP is incorporated to expand the SiS650 functionality to support the secondary display, in addition to the default primary CRT display. The SiS301B Video Bridge integrates an NTSL/PAL video encoder with Macro Vision Ver. 7.1.L1 option for TV display, a TMDS transmitter with Bi-linear scaling capability for TFT LCD panel support, and an analog RGB port to support a secondary CRT. The primary CRT display and the extended secondary display (TV, TFT LCD Panel, 2'nd CRT) features the Dual View Capability in the sense that both can generate the display in independent resolutions, color depths, and frame rates.

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Two separate buses, Host-t-GUI in the width of 64 bit, and GUI-t-Memory Controller in the width of 128 bit are devised to ensure concurrency of Host-t-GUI streaming, and GUI-t-MC streaming. In PC133, or DDR266 memory subsystem, the 128 bit GUI-t-MC bus will attain the AGP4X or AGP 8X equivalent texture transfer rate, respectively. The Memory Controller mainly comprises the Memory Arbiter, the M-data/MCommand Queues, and the Memory Interface. The Memory Arbiter arbitrates a plenty of memory access requests from the GUI or AGP controller, Host Controller, and I/O bus masters based on a default optimized priority list with the capability of dynamically prioritizing the I/O bus master requests in a bid to offering privileged service to 1) the isochronous downstream transfer to guarantee the min. latency & timely delivery, or 2) the PCI master upstream transfer to curb the latency within the maximum tolerant period of 10us. Prior to the memory access requests pushed into the M-data queue, any command compliant to the paging mechanism is generated and pushed into the M-CMD queue. The M-data/M-CMD Queues further orders and forwards these queuing requests to the Memory Interface in an effort to utilizing the memory bandwidth to its utmost by scheduling the command requests in the background when the data requests streamlines in the foreground.

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1.2.3.2 SiS961 MuTIOL Media I/O overview
The SiS961 MuTIOL Media I/O integrates the Audio Controller with AC 97 Interface, the Ethernet MAC, the Dual Universal Serial Bus Host Controllers, the IDE Master/Slave controllers, and the MuTIOL Connect to PCI bridge. The PCI to LPC bridge, I/O Advanced Programmable Interrupt Controller, legacy system I/O, I/O Advanced Programmable Interrupt Controller and legacy power management functionalities are also integrated. The SiS961 also incorporates an universal interface supporting the asynchronous inputs/outputs of the X86 compatible microprocessors like PIII, K7 and P4. The Integrated Audio Controller features a 6 channels of AC 97 v2.2 compliance audio to present 5.1channel Dolby digital material or to generate stereo audio with simultaneous V.90 HSP modem operation. Besides, 4 separate SDATAIN pins are provided to support multiple audio Codecs + one modem Codec maximally, effectuating the realization of 5.1 channel Dolby digital material in theater quality sound. Both traditional consumer digital audio channel as well as the AC 97 v2.2 compliant consumer digital audio slot are supported. VRA mode is also associated with both the AC 97 audio link and the traditional consumer digital audio channel. The integrated Fast Ethernet MAC features an IEEE 802.3 and IEEE 802.3x compliant MAC supporting full duplex 10 Base-T, 100 Base-T Ethernet, or 1Mb/s & 10Mb/s Home networking. 5 wake-up Frames, Magic Packet and link status change wake-up functions in G1/G2 states are supported. Besides, the integrated MAC provides a scheme to store the MAC address without the need of an external EEPROM. The 25 MHz oscillating circuit is integrated so as only an external low cost 25 MHz crystal is needed for the clocking system.
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The integrated Universal Serial Bus Host Controllers features Dual Independent OHCI Compliant Host controllers with six USB ports delivering 2 x 12 Mb/s bandwidth and rich connectivity. Besides, each port can be optionally configured as the wake-up source. Legacy USB devices as well as over current detection are also implemented. The integrated IDE Master/Slave controllers features Dual Independent IDE channels supporting PIO mode 0,1,2,3,4, and Ultra DMA 33/66/100. It provides two separate data paths for the dual IDE channels that sustain the high data transfer rate in the multitasking environment. The MuTIOL Connect to PCI bridge supporting 6 PCI master is compliant to PCI 2.2 specification. The SiS961 also incorporates the legacy system I/O like: two 8237A compatible DMA controllers, three 8254 compatible programmable 16-bit counters, hardwired keyboard controller and PS2 mouse interface, Real Time clock with 256B CMOS SRAM and two 8259A compatible Interrupt controllers. Besides, the I/O APIC managing up to 24 interrupts with both Serial and FSB interrupt delivery modes is supported. The integrated power management module incorporates the ACPI 1.0b compliance functions, the APM 1.2 compliance functions, and the PCI bus power management interface spec. v1.1. Numerous power-up events and power down events are also supported. 21 general purposed I/O pins are provided to give an easy to use logic for specific application. In addition, the SiS961 supports Intel Speed Step technology and Deeper Sleep power state for Intel Mobile processor. For AMD processor, the SiS961 use the CPUSTP# signal to reduce processor voltage during C3 and S1 state.

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1.2.4 SiS301LV TV Encoder / LVDS Transmitter
General Description SiS301LV, which is an accompany chip of SiS VGA chip, integrates : A NTSC/PAL video encoder with Macrovision Ver.7.1.L1 option for TV display. A LVDS transmitter with bi-linear scaling capability for TFT LCD panel display. All the above functions can support dual-display features. It means that the second display device driven by SiS301LV can display independent resolutions, color depths and frame rates different from the traditional CRT monitor driven by primary VGA chip. SiS301LV receives digital video signals and control signals from the primary VGA chip then transforms them into composite, S-Video or component video output for TV display, LVDS signals for LCD display. The output display combination can be one of the three : (1) Primary CRT+SiS301LV TV (2) Primary CRT+SiS301LV LCD (3) SiS301LV TV + SiS301LV LCD.
V ide o D e co de r

The package type of SiS301LV is 128-pin LQFP.

Fra m e B u ffe r

F ea ture C on n ector CRT M o n itor

P rim a ry VG A (S iS 65 0/ S iS 33 0 )

1st cha nne l 2 nd c hannel S iS 30 1 LV N TS C /P A L TV LC D M on ito r

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1.2.4.1 TV-Out :
Supports PAL and NTSC Systems. Supports Composite, S-Video, and Component RGB( SCART) Output Signals Supports Macrovision Copy Protection Process Rev. 7.1.L1 Support Progressive TV 525P YPbPr Output Signals. Support Macrovision Conpy Protection Waveforms for 525p Progressive Scan Output Supports TV/Primary VGA Independent Display Resolution and Frame Rate at Enhanced Mode Provides Adaptive 6-Line Anti-Flicker Filtering. Provides Hardware Interpolation for Programmable Under-Scan/Over-Scan Adjustment. Provides Programmable Display Position Adjustment. Provides Programmable Notch Filter for Cross Color Elimination. Provides Chrominance Filter for Cross Luminance Elimination. Provides Color Saturation Adjustment for Vivid TV Output. Provides Gamma Correction Independent of That of Primary VGA. Auto-Sense of TV Connection

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1.2.4.2 LVDS
Supports LVDS Transmitter Function. Single LVDS supports pixel rate up to 110M pixel/sec. Compatible with TIA/EIA-644 LVDS standard. Provides Bi-linear Scaling to Scale VGA Low Resolution Mode up for LCD Display up to 1280x1024 Supports LCD/Primary VGA Independent Display Resolution and Frame Rate at Enhanced Mode. Support 2D dither for 18-bit panels. Provides Programmable Display Centering. Compliant with VESA DDC2B Compliant with VESA Plug & Display, Hot Plugging Function. Provides Correction Independent of That of Primary VGA

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1.2.5 PC Card Interface Controller: TI PCI1410
The TI PCI1410 is a high-performance PCI-to-PC Card controller that supports a single PC Card socket compliant with the 1997 PC Card Standard. The PCI1410 provides features that make it the best choice for bridging between PCI and PC Cards in both notebook and desktop computers. The 1997 PC Card Standard retains the 16-bit PC Card specification defined in PCI Local Bus Specification and defines the new 32-bit PC Card, CardBus, capable of full 32-bit data transfers at 33 MHz. The PCI1410 supports both 16-bit and CardBus PC Cards, powered at 5 V or 3.3 V, as required. . The PCI1410 is compliant with the PCI Local Bus Specification, and its PCI interface can act as either a PCI master device or a PCI slave device. The PCI bus mastering is initiated during 16-bit PC Card DMA transfers or CardBus PC Card bridging transactions. The PCI1410 is also compliant with the latest PCI Bus Power Management Interface Specification and PCI Bus Power Management Interface Specification for PCI to CardBus Bridges. All card signals are internally buffered to allow hot insertion and removal without external buffering. The PCI1410 is register compatible with the IntelE 82365SL-DF and 82365SL ExCA controllers. The PCI1410 internal data path logic allows the host to access 8-, 16-, and 32-bit cards using full 32-bit PCI cycles for maximum performance. Independent buffering and a pipeline architecture provide an unsurpassed performance level with sustained bursting. The PCI1410 can also be programmed to accept fast posted writes to improve system-bus utilization.

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Multiple system-interrupt signaling options are provided, including: parallel PCI, parallel ISA, serialized ISA, and serialized PCI. Furthermore, general-purpose inputs and outputs are provided for the board designer to implement sideband functions. Many other features designed into the PCI1410, such as socket activity lightemitting diode (LED) outputs, are discussed in detail throughout the design specification. An advanced complementary metal-oxide semiconductor (CMOS) process achieves low system power consumption while operating at PCI clock rates up to 33 MHz. Several low-power modes enable the host power management system to further reduce power consumption. Features Ability to wake from D3hot and D3cold Fully compatible with the Intel 430TX (Mobile Triton II) chipset A 144-terminal low-profile QFP (PGE), 144-terminal MicroStar BGAE ball grid array (GGU) package, or 209-terminal MicroStar BGAE (GHK) package 3.3-V core logic with universal PCI interfaces compatible with 3.3-V and 5-V PCI signaling environments Mix-and-match 5-V/3.3-V 16-bit PC Cards and 3.3-V CardBus Cards Single PC Card or CardBus slot with hot insertion and removal Burst transfers to maximize data throughput on the PCI bus and the CardBus bus Parallel PCI interrupts, parallel ISA IRQ and parallel PCI interrupts, serial ISA IRQ with parallel PCI interrupts, and serial ISA IRQ and PCI interrupts

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1.2.5.1 Single-Slot PC Card Power Interface Switch: TPS2211A
The TPS2211A PC Card power-interface switch provides an integrated power-management solution for a single PC Card. All of the discrete power MOSFETs, a logic section, current limiting, and thermal protection for PC Card control are combined on a single integrated circuit, using the Texas Instruments LinBiCMOSTM process. The circuit allows the distribution of 3.3-V, 5-V, and/or 12-V card power, and is compatible with many PCMCIA controllers. The current-limiting feature eliminates the need for fuses, which reduces component count and improves reliability. Current-limit reporting can help the user isolate a system fault to the PC Card. The TPS2211A features a 3.3-V low-voltage mode that allows for 3.3-V switching without the need for 5 V. Bias power can be derived from either the 3.3-V or 5-V inputs. This facilitates low-power system designs such as sleep mode and pager mode where only 3.3 V is available. End equipment for the TPS2211A includes notebook computers, desktop computers, personal digital assistants (PDAs), digital cameras, and bar-code scanners.

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Features Fully Integrated VCC and Vpp Switching for Single-Slot PC CardTM Interface Low rDS(on) (70-m 5-V VCC Switch and 3.3-V VCC Switch) Compatible With Industry-Standard Controllers 3.3-V Low-Voltage Mode Meets PC Card Standards 12-V Supply Can Be Disabled Except During 12-V Flash Programming Short-Circuit and Thermal Protection Space-Saving 16-Pin SSOP (DB) Compatible With 3.3-V, 5-V, and 12-V PC Cards Break-Before-Make Switching PC Card is a trademark of PCMCIA (Personal Computer Memory Card International Association) LinBiCMO is a trademark of Texas Instruments

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1.2.6 IEEE1394 : NEC PD72872 OHCI-Link Layer Controller
The PD72872 is NECs 1-chip solution of an OHCI-LINK layer controller and a two port, physical layer implementation compliant to P1394a specification draft 2.0. It supports the connection with transmission speeds up to 400Mbps. The two-port shrink version of the PD72870 chip with PCI/CardBus Interface offers a compact and low-cost solution for implementing applications in PC, PC-Cards as PD72872 supports the 1394 Open Host Controller Interface 1.0 Features Link Layer compliant with 1394 Open Host Controller Interface specification release 1.0 Physical layer compliant with definition in P1394a draft 2.0 (Data Rate 100/200/400 Mbps) Selectable active port number (1, 2 ports) Modular 32-bit host interface compliant with PCI specification release 2.1 Supports PCI Bus Power Management Interface specification release 1.1 Modular 32-bit host interface compliant with CardBus specification Cycle Master and Isochronous Resource Manager support 32-bit CRC generation and checking for receive/transmit packets Supports 4 isochronous transmit DMAs and 4 isochronous receive DMAs 2-wire Serial EEPROM interface supported

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Separate power supply Link and PHY Programmable latency timer from serial EEPROM in CardBus mode (CARD_ON = 1) Temperature range: 0 to 70C Operating voltage: 3.3 V 10%, single power supply

1.2.7 AC97 Audio System: Advance Logic, Inc, ALC201


SiS961 is an AC97 2.1 compliant controller that communicates with companion Codecs SiS a digital serial link called the AC-link. The ALC201 is an AC97 2.2 compatible stereo audio codec designed for PC multimedia systems.The ALC201 provides the way for PC98 and PC99-compliant desktop, portable and entertainment PCs, where high-quality audio is required. The ALC201 AC97 CODEC provides a complete high quality audio solution. Features Single chip audio CODEC with high S/N ratio (>90 dB) 18-bit ADC and DAC resolution Compliant with AC97 2.2 specification Meet performance requirements for audio on PC2001 systems

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18-bit stereo full-duplex CODEC with independent and variable sampling rate 4 analog line-level stereo input with 5-bit volume control: LINE_IN, CD, VIDEO, AUX 2 analog line-level mono input: PC_BEEP, PHONE_IN Mono output with 5-bit volume control Stereo output with 5-bit volume control 2 MIC inputs: Software selectable Power management 3D Stereo Enhancement Headphone output with 50mW/20ohm driving capability (ALC201) Line output with 50mW/20ohm driving capability (ALC201A) Headphone jack-detect function to mute LINE output Multiple CODEC extension MC97 chained in allowed for multi-channel application External Amplifier power down capability Support S/PDIF out is fully compliant with AC97 specification rev2.2 DC offset cancellation Power support: Digital: 3.3V Analog: 5V Standard 48-Pin LQFP Package

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1.2.8 MDC: PCTel Modem Daughter Card PCT2303W
The PCT2303W chipset is designed to meet the demand of this emerging worldwide AMR/MDC market. The combination of PC-TELs well proven PCT2303W chipset and the HSP56TM MR software modem driver allows systems manufactures to implement modem functions in PCs at a lower bill of materials (BOM) while maintaining higher system performance. PC-TEL has streamlined the traditional modem into the Host Signal Processing (HSP) solution. Operating with the Pentium class processors, HSP becomes part of the host computers system software. It requires less power to operate and less physical space than standard modem solutions. PC-TELs HSP modem is an easily integrated, cost-effective communications solution that is flexible enough to carry you into the future. The PCT2303W chip set is an integrated direct access arrangement (DAA) and Codec that provides a programmable line interface to meet international telephone line requirements. The PCT2303W chip set is available in two 16-pin small outline packages (AC97 interface on PCT303A and phone-line interface on PCT303W). The chip set eliminates the need for an AFE, an isolation transformer, relays, opto-isolators, and 2-to 4-wire hybrid. The PCT2303W chip set dramatically reduces the number of discrete components and cost required to achieve compliance with international regulatory requirements. The PCT2303W complies with AC97 Interface specification Rev. 2.1.

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The chip set is fully programmable to meet worldwide telephone line interface requirements including those described by CTR21, NET4, JATE, FCC, and various country-specific PTT specifications. The programmable parameters of the PCT2303W chip set include AC termination, DC termination, ringer impedance, and ringer threshold. The PCT2303W chip set has been designed to meet stringent worldwide requirements for out-ofband energy, billing-tone immunity, lightning surges, and safety requirements. Operating System Compatibility Windows 98 /NT4.0 /Win 2K /Win XP Compatibility ITU-T V.90 56000, 54667, 53333,52000, 50667, 49333, 48000, 46667, 45333, 42667, 41333, 40000, 38667, 37333, 36000, 34667, 33333, 32000, 30667, 29333, 28000bps 56000, 54000, 52000, 50000, 48000, 46000, 44000, 42000, 40000, 38000, 36000, 32000bps 33600,31200 bps 28800 bps 14400 bps 9600,4800 bps 2400 bps 1200 bps 300 bps 1200/75 bps
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K56Flex ITU-T V.34Annex ITU-T V.34 ITU-T V.32bis ITU-T V.32 ITU-T V.22bis ITU-T V.22 ITU-T V.21 ITU-T V.23

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ITU-T V.17 ITU-T V.29 ITU-T V.27ter Bell 212A Bell 103 Modulation 56000bps(V90&K56Flex) 33600 bps (V.34Annex) 28800 bps (V.34) 14400 bps (V.32bis) 12000 bps (V.32bis) 9600 bps (V.32bis) 7200 bps (V.32bis) 9600 bps (V.32) 4800 bps (V.32) 14400 bps (V.17) 12000 bps (V.17) 9600 bps (V.29) 7200 bps (V.29) 4800 bps (V.27ter) PCM TCM TCM TCM TCM TCM QAM TCM, QAM QAM TCM TCM QAM QAM DPSK
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14400,12000,9600,7200 bps 9600,7200 bps 4800,2400 bps 1200 bps 300 bps

8575A N/B Maintenance


2400 bps (V.27ter) 2400 bps (V.22bis) 1200/75bps (V.23) 1200bps(V.22/Bell 212A) 300bps(V.21/Bell 103) Data Compression V.42bis, MNP5 Error Correction V.42 LAPM, MNP 2-4 DTE interface DTMF Tone Frequency
Low Group Frequency (Hz) High Group Frequency (Hz) 1209 1336 1477 1633 697 1 2 3 A 770 4 5 6 B 852 7 8 9 C 941 * 0 # D

DPS QAM FSK DPSK FSK

DTMF signal level

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1.2.8.1 High Group 1.2.8.2 Low Group
Dialing Type Telephone Line interface Return Loss Flow Control Receive Level Transmit Level

-10+/-2dBm -12+/-2dBm
Tone or pulse dialing RJ-11 300HZ - 3400HZ >= 10db XOFF/XON or RTS/CTS -35 +/- 2dBm >-15 dBm

Specification and features subject to change without notice!

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1.2.9 Keyboard System: H8 (3437S) Universal Keyboard Controller
CPU Two-way general register configuration Eight 16-bit registers or sixteen 8-bit registers High-speed operation Maximum clock rate: 16Mhz at 5V Available in temperature range: 0!C~70!C Include 60KB ROM and 2KB RAM 16-bit free-running timer One 16-bit free-running counter Two output-compare lines Four input capture lines 8-bit timer (2 channels) PWM timer (2 channels) I2C bus interface (one channel) Host interface (HIF) Each channel has one 8-bit up counter, two time constant registers Resolution: 1/250 Duty cycle can be set from 0 to 100% Include single master mode and slave mode 8-bit host interface port Three hosts interrupt requests (HIRQ1, 11,12) Regular and fast A20 gate output Controls a matrix-scan keyboard by providing a keyboard scan function with wake-up Interrupts and sense ports 10-bit resolution 8 channels: single or scan mode (selectable)
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Memory

Keyboard controller A/D converter

8575A N/B Maintenance


D/A converter Interrupts Power-down modes Hardware standby mode A single chip microcomputer On-chip flash memory Maximum 64kbyte-address space Support three PS/2 port for external keyboard, mouse and internal track pad. Support SMI, SCI trigger input: Cover switch Battery charging control Smart Battery monitoring Control D/D system on/off Fan control and LED indicator serial interface 100pin TQFP 8-bit resolution 2 channels Nine external interrupt lines: NMI#, IRQ0 to 7# 26 on-chip interrupt sources Sleep mode Software standby mode

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1.2.10 System Flash Memory (BIOS)
2 M bit Flash memory Flashed by 5V only User can upgrade the system BIOS in the future just running flash program

1.2.11 Memory System


64MB, 128MB, 256MB, 512MB (x64) 200-Pin DDR SDRAM SODIMMs JEDEC-standard 200-pin, small-outline, dual in-line memory module (SODIMM) Utilizes 200 Mb/s and 266 Mb/s DDR SDRAM components 128MB (16 Meg x 64, [H] and [HD]); 256MB (32 Meg x 64 [HD]); 512MB (64 Meg x 64 [HD]) VDD= VDDQ= +2.5V !0.2V VDDSPD = +2.2V to +5.5V 2.5V I/O (SSTL_2 compatible) Commands entered on each positive CK edge DQS edge-aligned with data for READs; center-aligned with data for WRITEs Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle Bi-directional data strobe (DQS) transmitted/received with datai.e.,source-synchronous data capture Differential clock inputs (CK and CK# - can be multiple clocks, CK0/CK0#, CK1/CK1#, etc.) Four internal device banks for concurrent operation

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Selectable burst lengths: 2, 4 or 8 Auto precharge option KBC and PS2 mouse can be individually disabled Auto Refresh and Self Refresh Modes 15.6s (MT4VDDT864H, MT8VDDT1664HD), 7.8125s (MT4VDDT1664H, MT8VDDT3264HD, MT8VDDT6464HD) maximum average periodic refresh interval Serial Presence Detect (SPD) with EEPROM Serial Presence Detect (SPD) with EEPROM Fast data transfer rates PC2100 or PC1600 Selectable READ CAS latency for maximum compatibility Gold-plated edge contacts

1.2.12 PHY: 3.3-V 10Base-T/100Base-TX Integrated PHYceiver The ICS1893


General Description The ICS1893 is a low-power, physical-layer device (PHY) that supports the ISO/IEC 10Base-T and 100BaseTXCarrier-Sense Multiple Access/Collision Detection (CSMA/CD) Ethernet standards. The ICS1893 architecture is based on the ICS1892. The ICS1893 supports managed or unmanaged node, repeater, and switch applications.

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The ICS1893 incorporates digital signal processing (DSP) in its Physical Medium Dependent (PMD) sublayer. As a result, it can transmit and receive data on unshielded twisted-pair (UTP) category 5 cables with attenuation in excess of 24 dB at 100 MHz. With this ICS-patented technology, the ICS1893 can virtually eliminate errors from killer packets. The ICS1893 provides a Serial Management Interface for exchanging command and status information with a Station Management (STA) entity. The ICS1893 Media Dependent Interface (MDI) can be configured to provide either half- or full-duplex operation at data rates of 10 MHz or 100 MHz. The MDI configuration can be established manually (with input pins or control register settings) or automatically (using the Auto-Negotiation features). When the ICS1893 Auto-Negotiation sublayer is enabled, it exchanges technology capability data with its remote link partner and automatically selects the highest-performance operating mode they have in common. Features Supports category 5 cables with attenuation in excess of 24 dB at 100 MHz across a temperature range from -5 to +85 C DSP-based baseline wander correction to virtually eliminate killer packets across temperature range from -5 to +85 C Low-power, 0.35-micron CMOS (typically 400 mW) Single 3.3-V power supply
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Single-chip, fully integrated PHY provides PCS, PMA, PMD and AUTONEG sublayers of IEEE standard 10Base-T and 100Base-TX IEEE 802.3 compliant Fully integrated, DSP-based PMD includes: Adaptive equalization and baseline wander correction Transmit wave shaping and stream cipher scrambler MLT-3 encoder and NRZ/NRZI encoder Highly configurable design supports: Node, repeater, and switch applications Managed and unmanaged applications 10M or 100M half- and full-duplex modes Parallel detection Auto-negotiation, with Next Page capabilities MAC/Repeater Interface can be configured as: 10M or 100M Media Independent Interface 100M Symbol Interface (bypasses the PCS) 10M 7-wire Serial Interface Small Footprint 64-pin Thin Quad Flat Pack (TQFP)

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1.3 Other Functions
1.3.1 Hot Key Functions
Keys Combination Fn + F1 Fn + F2 Fn + F3 Fn + F4 Fn + F5 Fn + F6 Fn + F7 Fn + F8 Fn + F9 Fn + F10 Fn + F11 Fn + F12 Feature Reserve Reserve Volume Down Volume Up LCD/external CRT switching Brightness down Brightness up Brightness MAX Pause Break Panel Off/On Suspend to DRAM / HDD Meaning

Rotate display mode in LCD only, CRT only, and simultaneously display. Decreases the LCD brightness Increases the LCD brightness Toggle Max Brightness

Toggle Panel on/off Force the computer into either Suspend to HDD or Suspend to DRAM mode depending on BIOS Setup.

1.3.2 Power on/off/suspend/resume button


APM mode At APM mode, Power button is on/off system power.

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APM mode At ACPI mode. Windows power management control panel set power button behavior. You could set standby, power off or hibernate(must enable hibernate function in power Management) to power button function. Continue pushing power button over 4 seconds will force system off at ACPI mode.

1.3.3 Cover Switch


System automatically provides power saving by monitoring Cover Switch. It will save battery power and prolong the usage time when user closes the notebook cover. At ACPI mode there are four functions to be chosen at windows power management control panel. 1. 2. 3. 4. None Standby Off Hibernate (must enable hibernate function in power management)

1.3.4 Reset Switch


There is a reset switch at bottom side of notebook. It will reset embedded controller H8 and turn off system totally. When system hands up and Power button has no function, this switch is the only way to turn off system without remove power source.

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1.3.5 LED Indicators
System has eight status LED indicators to display system activity, which include three at front side and five above keyboard. 1) Three LED indicators at front side: From left to right that indicates: AC Power, Battery Power and Battery Status AC Power: This LED lights green when AC is powering the notebook, and flash (on 1 second, off 1 second) when Suspend to DRAM is active using AC power. The LED is off when the notebook is off or powered by batteries. Battery Power: This LED lights green when the notebook is being powered by Battery, and flash (on 1 second, off 1 second) when Suspend to DRAM is active using Battery power. The LED is off when the notebook is off or powered by batteries, or when Suspend to Disk. Battery Status: During normal operation, this LED stays off as long as the battery is charged. When the battery charge drops to 10% of capacity, the LED lights red, flashes per 1 second and beeps per 2 second. When AC is connected, this indicator glows green if the battery pack is fully charged or orange (amber) if the battery is being charged. 2) Five LED indicators above keyboard: From left to right that indicates LAN, CD-ROM/HARD DISK DRIVE, NUM LOCK, CAPS LOCK and SCROLL LOCK.

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1.3.6 Battery Status
Battery Warning System also provides Battery capacity monitoring and gives user a warning so that users have chance to save his data before battery dead. Also, this function protects system from mal-function while battery capacity is low. Battery Warning: Capacity below 10%, Battery Capacity LED flashes per second, system beeps per 2 seconds. System will suspend to HDD after 2 Minutes to protect users data. Battery Low State After Battery Warning State, and battery capacity is below 4%, system will generate beep for twice per second. Battery Dead State When the battery voltage level reaches 7.4 volts, system will shut down automatically in order to extend the battery packs' life.

1.3.7 Fan power on/off management


FAN is controlled by H8 embedded controller-using AD2201 to sense CPU temperature and PWM control fan speed. Fan speed is depended on CPU temperature. Higher CPU temperature faster Fan Speed.

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1.3.8 CMOS Battery
CR2032 3V 220mAh lithium battery When AC in or system main battery inside, CMOS battery will consume no power. AC or main battery not exists, CMOS battery life at less (220mAh/5.8uA) 4 years. Battery was put in battery holder, can be replaced.

1.3.9 I/O Port


One Power Supply Jack. One External CRT Connector For CRT Display Supports two USB port for all USB devices. One MODEM RJ-11 phone jack for PSTN line One RJ-45 for LAN. Headphone Out Jack. Microphone Input Jack. Line in Jack One Card Bus Sockets for one type II PC card extension

1.3.10 Battery current limit and learning


Implanted H/W current limit and battery learning circuit to enhance protection of battery.

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1.4 Peripheral Components
1.4.1 LCD Panel
LCD 14.1 Hyundai HT14X12-100A

1.4.2 Ext.Floppy Disk Drive


Mitsumi D353GU External USB 3.5 1.44MB /1.2 MB/720KB FDD (Option)

1.4.3 HDD
Hitachi 30GB Height: 9.5 mm, 2.5

1.4.4 24X CD-ROM Drive


TEAC

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1.4.5 8W/4R CD-RW
KEM Height: 12.7 mm IDE I/F

1.4.6 Keyboard
Windows 98 Keyboard, 1 color, multi languages support JP, US and Europe Keyboard with Volume UP and Volume Down word.

1.4.7 Track Pad Synaptics


Accurate positioning Low fatigue pointing action Low profile No moving part, high reliability Low power consumption Environmentally sealed Compact size. Software configurable Low weight Operating temperature: 0 to 60 degree C

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Operating humidity: 5%-95% relative humidity, non condensing Storage temperature: -40 to +65 degree C ESD: 15KV applied to front surface SEE ESD Testing specification PN 520-000270-01 Power supply voltage: 5.0Voltage 10% Power supply current: 4.0mA max operating

1.4.8 Fan
HY45J05-001

1.4.9 Memory
DDR-RAM/ATP//128M/256M DDR-RAM/Apacer//128M/256M DDR-RAM/Unidorsa//128M/256M

1.4.10 Modem MDC


Askey

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1.5 System Management
The 8575A system has built in several power saving modes to prolong the battery usage for mobile purpose. User can enable and configure different degrees of power management modes via ROM CMOS setup (booting by pressing F2 key). Following are the descriptions of the power management modes supported.

1.5.1 System Management Mode


Full on mode In this mode, each device is running with the maximal speed. CPU clock is up to its maximum. Doze Mode In this mode, CPU will be toggling between on & stop grant mode either. The technology is clock throttling. This can save battery power without loosing much computing capability. The CPU power consumption and temperature is lower in this mode. Standby mode For more power saving, it turns of the peripheral components. In this mode, the following is the status of each device: CPU: Stop grant LCD: backlight off HDD: spin down
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Suspend to DRAM The most chipset of the system is entering power down mode for more power saving. In this mode, the following is the status of each device: Suspend to DRAM: CPU: off Twister K: Partial off VGA: Suspend PCMCIA: Suspend Audio: off SDRAM: self refresh Suspend to HDD: All devices are stopped clock and power-down System status is saved in HDD All system status will be restored when powered on again

1.5.2 Other Power Management Functions


HDD & Video access System has the ability to monitor video and hard disk activity. User can enable monitoring function for video and/or hard disk individually. When there is no video and/or hard disk activity, system will enter next PMU state depending on the application. When the VGA activity monitoring is enabled, the performance of the system will have some impact.
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1.6 Appendix 1: SiS961 GPIO Definitions
SB_SiS961 GPIO
Signal Name GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 GPIO8 GPIO9 RING# AC_SDIN2 LDRQ1# THERM# EXTSMI# CLKRUN# PREQ5# PGNT5# MUX Function Mitac Definition MB_ID0 CD_IN# SB_THRM# EXTSMI# CLKRUN# LCD_ID0 LCD_ID1 LCD_ID2 WAKEUP# SCI# CRT_IN# SPK_OFF CPU_STP# MPCIACT# /DPRSLPVR CD_PWRON# VR_HILO# LO_HI# VGATEM# CD_RST SMBCLK SMBDATA Buffer Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OD I/O O O O Power Plane Main Main Main Main Main Main Main AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX AUX During Tolerant PCISRT# After PCISRT# S1 S3 Off Off Off Off Off Off Off S4/S5 Off Off Off Off Off Off Off

Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined

Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z

GPIO10 AC_SDIN3 GPIO11 GPIO12 CPUSTP# GPIO13 DPRSLPVR GPIO14 GPIO15 VR_HILO# GPIO16 LO_HI# GPIO17 VGATEM# GPIO18 PMCLK GPIO19 SMBCLK GPIO20 SMBDATA

Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined Driven Defined High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z

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1.7 Appendix 2: H8 Pins Definitions
The shadowed block is the selected function
Name Pin H8 Pin Definitions H8_MODE0 H8_MODE1 STBY# POWER BTN# RESET# Crystal Crystal RESET OUT During RESET I" I" I" I" I I I O After RESET/OFF I I I I I I I O H H H H LH ON STANDBY Function

MD0 MD1 STBY# NMI# RESET# XTAL EXTAL RESET OUT#

6 5 8 7 1 2 3 100

I I I I I I I O

H H H HL H H

I I I I I I I O

H H H H H

H H mode3 single chip mode H8 Hardware Standby input pull high Power button H8 chip reset Crystal input

Port A COMOS input level (input high min=3.5V, input low max=1.0V) PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 48 47 31 30 21 20 11 10 LID# H8 ADEN# RI# BATT DEAD# H8 SUSC H8 SUSC# BAT_CLK H8_SUSB I" I" I" I" I" I" I" I" I I I I I I I I H H/L H H H L L H I I I I I I I I L I I I I I I I I H H/L H H L H H H Invert from SUSA# to wake up H8 when system resumed by MDC modem and internal LAN. Inform system power management status AC adaptor in detect Ring detect Battery low detect System resume from S4 soft off through RTC Alarm System to S4 soft off

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PCI reset gate
Name Pin H8 Pin Definitions During RESET After RESET/OFF ON STANDBY Function

Port B TTL input voltage (input high min=2V, input low max=0.8V) PB0 PB1 PB2 PB3 PB4 PB5 PB6 PB7 PB6 PB7 91 10 81 80 69 68 58 57 58 57 H8 SB PWRBTN# H8 WAKE# Force Discharge CHARGING1 VDD5 SW H8 RCIN# CHARGING2 SMbus SW VADJ1 VADJ2 T T T T T$ T T T T T O O O O O O O O O O LLH L O O O O O O O H LH L H IHL O O O O O O O O O O O Keep H Keep H Keep H Keep Keep H Keep H Keep Keep Keep Keep Lithium ion battery charging CV mode voltage level adjust Power button trigger VIA8231 on/off Duplicate Power BTN# 5#3V Wake up SB at ACPI mode 5#3V

Power button trigger VIA8231 on 5#3V Battery charge control H8 VDD5 power source switch Reset CPU Battery charge control

Port 1 TTL input voltage (input high min=2V, input low max=0.8V) P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 79 78 77 76 75 74 73 72 KB OUT0 KB OUT1 KB OUT2 KB OUT3 KB OUT4 KB OUT5 KB OUT6 KB OUT7 L L L L L L L L O O O O O O O O L L L L L L L L O O O O O O O O LH LH LH LH LH LH LH LH O O O O O O O O Keep L Keep L Keep L Keep L Keep L Keep L Keep L Keep L Key matrix scan output 0 Key matrix scan output 1 Key matrix scan output 2 Key matrix scan output 3 Key matrix scan output 4 Key matrix scan output 5 Key matrix scan output 6 Key matrix scan output 7

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Continue to previous
Name Pin H8 Pin Definitions During RESET After RESET/OFF ON STANDBY Function

Port 2 TTL input voltage (input high min=2V, input low max=0.8V) P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 67 66 65 64 63 62 61 60 KB OUT8 KB OUT9 KB OUT10 KB OUT11 KB OUT12 KB OUT13 KB OUT14 KB OUT15 L L L L L L L L O O O O O O O O L L L 0 0 0 0 0 O O O O O O O O LH LH LH LH LH LH LH LH O O O O O O O O Keep L Keep L Keep L Keep L Keep L Keep L Keep L Keep L Key matrix scan output 8 Key matrix scan output 9 Key matrix scan output 10 Key matrix scan output 11 Key matrix scan output 12 Key matrix scan output 13 Key matrix scan output 14 Key matrix scan output 15

Port 3 TTL input voltage (input high min=2V, input low max=0.8V) P30/HDB0/D0 P31/HDB1/D1 P32/HDB2/D2 P33/HDB3/D3 P34/HDB4/D4 P35/HDB5/D5 P36/HDB6/D6 P37/HDB7/D7 82 83 84 85 86 87 88 89 ISA SD0 ISA SD1 ISA SD2 ISA SD3 ISA SD4 ISA SD5 ISA SD6 ISA SD7 T T T T T T T T I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Keep Keep Keep Keep Keep Keep Keep Keep ISA DATA bit 0 ISA DATA bit 1 ISA DATA bit 2 ISA DATA bit 3 ISA DATA bit 4 ISA DATA bit 5 ISA DATA bit 6 ISA DATA bit 7

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Continue to previous
Name Pin H8 Pin Definitions During RESET After RESET/OFF ON STANDBY Function

Port 4 TTL input voltage (input high min=2V, input low max=0.8V) P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/HIRQ1 P44/TMCO1/HIRQ1 P45/TMRI1/HIRQ1 P46/PWM0 P46/PWM0 P47/PWM1 49 50 51 52 53 54 55 55 56 H8 PWR ON H8 THRM# SCI#/ FAN SPD SW H8 SCI/ FAN SPEED ISA IRQ1 ISA IRQ12 Beep sound FAN ON#0 FAN ON#1 T$ T T T T T T T T O O O O O O O O O 1 1 0 0 L L H O O O O O O O O LH H O O O O O O O O O Keep Keep H Keep Keep Keep Keep Keep Keep Keep System power on, need pull down to define initial state during reset Thermal throttling control to Southbridge SCI output and Fan Speed Tachometer Switch Need invert to SCI# sending to SB 5#3V/ Fan speed tachometer Keyboard IRQ1 PS2 mouse IRQ12 Hot key and battery dead beep sound Fan power PWM control Fan power PWM control

Port 5 TTL input voltage (input high min=2V, input low max=0.8V) P50/TXD0 P51/RXD0 P52/SCK0 14 13 12 LED DATA H8 SMI# LED CLK T T T O O O O O O O O O Keep Keep Keep LED indicator shift data External SMI# 5#3V

LED indicator shift clock

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Continue to previous
Name Pin H8 Pin Definitions During RESET After RESET/OFF ON STANDBY Function

Port 6 Schmitt trigger input voltage (min=1.0V max=3.5V) P60/KEYIN0/FTCI P61/KEYIN1/FTOA P62/KEYIN2/FTIA P63/KEYIN3/FTIB P64/KEYIN4/FTIC P65/KEYIN5/FTID P66/KEYIN6/IRQ6 P67/KEYIN7/IRQ7 26 27 28 29 32 33 34 35 KEY IN0 KEY IN1 KEY IN2 KEY IN3 KEY IN4 KEY IN5 KEY IN6 KEY IN7 T" T" T" T" T" T" T" T" I I I I I I I I I I I I I I I I I I I I I I I I Keep Keep H Keep Keep Keep Keep Keep Keep Key matrix input 0 need pull high Key matrix input 1 need pull high Key matrix input 2 need pull high Key matrix input 3 need pull high Key matrix input 4 need pull high Key matrix input 5 need pull high Key matrix input 6 need pull high Key matrix input 7 need pull high

Port 7 TTL input voltage (input high min=2V, input low max=0.8V) P70/AN0 P71/AN1 P71/AN1 P72/AN2 P73/AN3 P73/AN3 P74/AN4 P75/AN5 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 38 39 39 40 41 41 42 43 43 44 45 BAT VOLT1 BAT VOLT2 I_LIMIT 3V/PWR ok 2.5V LI/NIMH# BAT TEMP1 BAT TEMP2 VCC CORE Charge-I_CTR BL ADJ T T T T T T T T T T T I I I I I I I I I O O I I I I I I I I I O O I I I I I I I I I O O T T T T T Keep T T T T T Charging current adjust Backlight inverter brightness adjust To differential 3S3P lithium ion battery and 9S NiMH battery Battery thermister temperature Battery thermister temperature Monitor system on/off state Battery voltage measure Battery voltage measure

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Continue to previous
Name Pin H8 Pin Definitions During RESET After RESET/OFF ON STANDBY Function

Port 8 TTL input voltage (input high min=2V, input low max=0.8V) P80/HA0 P81/GA20 P82/CS1 P83/IOR P84/IRQ2/TXD1 P85/IRQ4/RXD1 P86/IRQ5/SCK1 93 94 95 96 97 98 99 ISA SA2 X(H8 A20GATE) H8 KBCS# ISA IOR# ISA IOW# H8 MCCS# BAT CLK T T T T T T T" I O I I I I I/O I O I I I I I/O I O I I I I I/O Keep Keep H Keep Keep Keep Keep Keep CPU A20gate IO port 60/64 chip select ISA I/O read# ISA I/O write IO port 62/66 chip select SM BUS clock need pull high 5#3V

Port 9 TTL input voltage (input high min=2V, input low max=0.8V) P90/IRQ2/ESC2 P91/IRQ1/EIOW P92/IRQ0 P93/RD P94/WR P95/AS P96/0 P97/WAIT/SDA 25 24 23 22 19 18 17 16 K/M CLK M CLK H8/T CLK K/M DATA M DATA H8/T DATA ENABKL BAT DATA T" T" T" T" T" T" T" T" I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I I/O Keep Keep Keep Keep Keep Keep T Keep need pull high need pull high need pull high need pull high need pull high need pull high Read H8 send A20gate status SM BUS clock need pull high 5#3V

" Pull High $ Pull Low 5#3V Level shift

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2. System View and Disassembly
2.1 System View
2.1.1 Front View
Stereo Speaker Set Device Indicators Mini IEEE1394 Connector External Microphone Jack Line Out Phone Jack Volume Control Top Cover Latch

2.1.2 Left-side View


Kensington Lock Ventilation Openings RJ-45 Connector PC Card Slot Hard Disk Drive

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2.1.3 Right-side View
Battery Pack CD-ROM/DVD-ROM Drive

2.1.4 Rear View


Power Connector S-Video Output Connector USB Ports Parallel Port D/D Fan RJ-11 Connector VGA Port Ventilation Openings

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2.1.5 Top-open View
LCD Screen Microphone Keyboard Touch Pad Power Button Easy Start Buttons Battery Charge Indicator Battery Power Indicator AC Power Indicator

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2.2 System Disassembly
The section discusses at length each major component for disassembly/reassembly and show corresponding illustrations. Use the chart below to determine the disassembly sequence for removing components from the notebook. NOTE: Before you start to install/replace these modules, disconnect all peripheral devices and make sure the notebook is not turned on or connected to AC power. 2.2.1 Battery Pack 2.2.2 Keyboard Modular Components 2.2.3 CPU 2.2.4 HDD Module 2.2.5 CD-ROM Drive 2.2.6 SO-DIMM NOTEBOOK LCD Assembly Components 2.2.7 LCD Assembly 2.2.8 LCD Panel 2.2.9 Inverter Board 2.2.10 System Board Base Unit Components 2.2.11 Touch-pad 2.2.12 Modem Card
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2.2.1 Battery Pack
Disassembly 1. Carefully put the notebook upside down. 2. Slide the release lever to the unlock ( ) position ( ), then sliding and holding the release lever outwards while pull the battery pack out of the compartment ( ). (Figure 2-1)

Figure 2-1 Remove the battery pack

Reassembly 1. Push the battery pack into the compartment. The battery pack should be correctly connected when you hear a clicking sound. 2. Slide the release lever to the lock ( ) position.

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2.2.2 Keyboard
Disassembly 1. Open the top cover. 2. Insert a small rod, such as a straightened paper clip, into the eject hole near the power connector of the notebook. (Figure 2-2) 3. Push the rod firmly and slide the easy start buttons cover to the left ( ). Then lift the easy start buttons cover up from the left side ( ). (Figure 2-3)

Figure 2-2 Insert a rod easy to remove

Figure 2-3 Remove easy start buttons cover

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3. Remove three screws fastening keyboard on the base unit cover. (Figure 2-4) 4. Slightly lift up the keyboard and disconnect the cable from the system board to detach the keyboard. (Figure 2-5)

Figure 2-4 Remove three screws

Figure 2-5 Remove keyboard

Reassembly 1. Reconnect the keyboard cable and fit the keyboard back into place with three screws. 2. Replace the easy start buttons cover.

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2.2.3 CPU
Disassembly 1. Remove the easy start buttons cover and keyboard to access the CPU compartment. (See section 2.2.2 Disassembly) 2. Remove seven screws fastening the heatsink cover and the rail. (Figure 2-6) 3. Remove three screws fastening the heatsink. (Figure 2-7)

Figure 2-6 Remove the cover and rail

Figure 2-7 Remove the heatsink

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4. Disconnect the fans power cord from the system board, then lift up the heatsink. (Figure 2-8) 5. Loosen the screw by a flat screwdriver,upraise the CPU socket to unlock the CPU. (Figure 2-9)

Figure 2-8 Remove the fans power cord

Figure 2-9 Remove the CPU

Reassembly 1. Carefully, align the arrowhead corner of the CPU with the beveled corner of the socket, then insert CPU pins into the holes. Tighten the screw by a flat screwdriver to locking the CPU. 2. Connect the fans power cord to the system board, fit the heatsink onto the top of the CPU and secure with four screws. 3. Replace the keyboard .Then replace easy start buttons cover.

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2.2.4 HDD Module
Disassembly 1. Carefully put the notebook upside down. 2. Remove one screw and slide the HDD module out of the compartment. (Figure 2-10) 3. Remove six screws to separate the hard disk drive from the metal shield. (Figure 2-11)

Figure 2-10 Remove HDD module

Figure 2-11 Disassemble the hard disk

Reassembly 1. To install the hard disk drive, place it in the bracket and secure with six screws. 2. Slide the HDD module into the compartment and secure with one screw.

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2.2.5 CD-ROM Drive
Disassembly 1. Carefully put the notebook upside down. 2. Remove one screw fastening the CD/DVD-ROM drive. Then hold the CD/DVD-ROM drive and slide it outwards carefully. (Figure 2-12)

Figure 2-12 Remove one screw to loose the CD/DVD-ROM drive

Reassembly 1. Push the CD/DVD-ROM drive into the compartment. 2. Secure the CD/DVD-ROM drive with one screw.

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2.2.6 SO-DIMM
Disassembly 1. Carefully put the notebook upside down. 2. Remove seven screws to access the SO-DIMM socket. (Figure 2-13) 3. Full the retaining clips outwards ( ) and remove the SO-DIMM ( ). (Figure 2-14)

Figure 2-13 Remove the SO-DIMM cover

Figure 2-14 Remove the SO-DIMM

Reassembly 1. To install the SO-DIMM, match the SO-DIMMs notched part with the sockets projected part and firmly insert the OS-DIMM into the socket at 20-degree angle. Then push down until the retaining clips lock the SO-DIMM into cover. 2. Replace the SO-DIMM cover. 3. Replace seven screws to fasten the SO-DIMM socket cover.
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2.2.7 LCD
Disassembly 1.Carefully put the notebook upside down and remove seven screws to access the SO-DIMM socket. 2.Remove the tape from the antenna on the Mini-PCI socket.(Figure 2-15)

Figure 2-15 Remove the tape from the antenna

Figure 2-16 Remove the LCD hinge cover and button board

3. Open the top cover. Remove easy start buttons cover, keyboard, and heatsink . (See section 2.2.2 and 2.2.3 Disassembly) 4. Pull out the antenna from the CPU compartment. 5. Remove the two hinge covers and remove two screws fastening the easy start button board.(Figure 2-16)

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6. Disconnect the LCD cables from the system board, and remove four screws of the hinges. Now you can separate the LCD assembly from the base unit. (Figure 2-17)

Figure 2-17 Remove cables and screws to separate LCD

Reassembly 1. Attach the LCD assembly to the base unit and secure with four screws on the hinges. 2. Replace the antenna to the SO-DIMM socket. 3. Reconnect the LCD cable connectors to the system board. 4. Fit the easy start button board and secure with tow screws. 5. Replace two hinge cover, the heatsink, keyboard and easy start buttons cover.
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2.2.8 LCD Panel
Disassembly 1. Remove the LCD assembly. (See section 2.2.7 Disassembly) 2. Remove the four rubber pads and two screws on the lower part of the panel. (figure 2-18) 3. Insert a flat screwdriver to the lower part of the frame and gently pry the frame out. Repeat the process until the frame is completely separated from the housing. 4. Remove the two screws on two sides and two screws on the lower part of the LCD panel, and disconnect the cable from the inverter board. (figure 2-19)

Figure 2-18 Remove LCD frame

Figure 2-19 Remove LCD panel

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Reassembly 1. Fit the LCD panel back into place and secure with four screws, and reconnect the cable to the inverter board. 2. Fit the LCD frame back into the housing and replace the four screws and four rubber pads. 3. Replace the LCD assembly. (See section 2.2.7 Reassembly)

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2.2.9 Inverter Board
Disassembly 1. Remove the LCD assembly and detach the LCD panel. (see instructions in previous two sections) 2. To remove the inverter board on the bottom side of the LCD assembly, disconnect the cable and remove one screw. (figure 2-20)

Figure 2-20 Remove the inverter board

Reassembly 1. Fit the inverter board back into place and secure with one screw. 2. Reconnect the cable. 3. Replace the LCD frame. (See section 2.2.8 Reassembly) 4. Replace the LCD assembly. (See section 2.2.7 Reassembly)
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2.2.10 System Board
Disassembly 1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly. (See section 2.2.1 to 2.2.5 and 2.2.7 Disassembly) 2. Remove sixteen screws on the bottom of the notebook. (Figure 2-21) 3. Remove nine screws fastening the base unit cover. (figure 2-22)

Figure 2-21 Remove the bottom

Figure 2-22 Remove nine screws

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4. Lift up the base unit cover and disconnect the touch pad cord. (Figure 2-23) 5. Remove the four screws fastening the base unit. (Figure 2-24)

Figure 2-23 Remove the base unit cover

Figure 2-24 Remove the metal shield

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6. Remove three screws fastening the connectors shield and disconnect the cables. (Figure 2-25) 7. Carefully put the notebook upside down. 8. Remove seven screws and four hex nuts fastening the system board and disconnect one cable . Now you can remove the system board. (Figure 2-26)

Figure 2-25 Remove the screws and disconnect the cable

Figure 2-26 Remove the system board

Reassembly 1. Replace seven screws and four hex nuts fasten the system board. 2. Reconnect one cable of system board fan and one cable of little battery to system board. 3. Replace three screws fasten the the connectors shield . 4. Reconnect two cables of speakers and one cable to system board. 5. Reconnect the touch pad cord. 6. Replace the base unit cover and secure with nine screws 7. Carefully put the notebook upside down. Then replace the bottom frame and secure with sixteen screws. 8. Replace the battery pack, LED panel, keyboard, CPU, HDD module, CD/DVD-ROM drive and LCD assembly.
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2.2.11 Touch-pad
Disassembly 1. Remove the base unit cover. (See steps 1-6 in section 2.2.10 Disassembly.) 2. Remove the eight screws to lift up the touch pad holder and touch pad panel. (Figure 2-27)

Figure 2-27 Remove the touch-pad

Reassembly 1. Replace the touch-pad holder and touch-pad panel, and secure with eight screws. 2. Assemble the base unit cover. (See section 2.2.10 Reassembly)

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2.2.12 Modem Card
Disassembly 1. Remove the battery pack, keyboard, CPU, HDD module, CD/DVD-ROM drive, and LCD assembly. (See section 2.2.1 to 2.2.5 and 2.2.7 Disassembly) 2. Disassemble the notebook to access the system board. (See section 2.2.10 Disassembly) 3. Remove the two screws fastening the modem card,and then disconnect the cable from system board. (Figure 2-28)

Figure 2-28 Remove the Modem card

Reassembly 1. Reconnect the cable to the modem card and secure the modem card with two screws. 2. Assemble the notebook. (See section 2.2.10 Reassembly)

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3. Definition & Location of Connectors / Switches
3.1 Mother Board A-1

J12 J7 J6 J5 J1 J2 J3 J8 SW6 J11 J23 J13 J19 J4 J14 J18 J25 VR1 J21 J20 J24 J28 J27

J1 : Modem Connector (RJ11) J2 : External VGA Connector J3 : LCD Connector J4 : D/D Connector J5 : MDC Jump Wire Connector J6 : Easy Start Buttons Connector J7 : MISC Connector J8 : Fan Connector J9 : LAN Connector (RJ45) J11 : PC Card Socket J12 : Secondary IDE Connector
J509

J9

J13 : Internal Keyboard Connector J14 : Battery Connector To next page


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3. Definition & Location of Connectors / Switches
3.1 Mother Board A-2

J12 J7 J6 J5 J1 J2 J3 J8 SW6 J11 J23 J13 J19 J4 J14 J18 J25 VR1 J21 J20 J24 J28 J27

Continue to previous page J18 : MDC Connector J19 : Primary IDE Connector J20 : Touch-pad Connector J21 : Internal Micro Phone Jack J23 : L Speaker Connector J24 : Line Out Phone Jack J25 : R Speaker Connector J27 : IEEE1394 Port J28 : External Microphone Jack SW6 : CPU Model Select Switch

J9

VR1 : Volume Control

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3. Definition & Location of Connectors / Switches
3.1 Mother Board B

J503 : Fan Connector


J503 J508
ON 2 1

J505 : 200-pin expansion DDR SDRAM Socket J506 : 200-pin expansion DDR SDRAM Socket

J509

J508 : CMOS Battery Connector ? J509 : Mini PCI Socket SW503 : Country Selection for Keyboard

SW503

J506

J505 U6 U5 U3

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3. Definition & Location of Connectors / Switches
3.2 DC Power Board - A

J1 : TV Out Jack J2 : Power Jack (AC adapter)


SW1

J3 : Parallel Port Connector


J3 PJ2 J6 PJ1 J5 J7 J4 J8 J1 J2

J4 : USB Port Connector J5 : USB Port Connector J6 : Inverter Board Connector J7 : USB Port Connector J8 : USB Port Connector PJ1 : D/D Connector PJ2 : MISC Connector SW1 : Cover Switch

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3. Definition & Location of Connectors / Switches
3.3 ESB Board A,B A
SW1 SW2 SW3 SW4 SW5 SW6

J501 : Easy Start Button Connector SW1 : Programmable Easy Start Button Switch SW2 : Programmable Easy Start Button Switch SW3 : Programmable Easy Start Button Switch

B
J501

SW4 : Programmable Easy Start Button Switch SW5 : Programmable Easy Start Button Switch SW6 : Programmable Easy Start Button Power Switch

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3. Definition & Location of Connectors / Switches
3.4 Touch-pad A,B A B
J501 : Touch-pad Board to Touch-pad Connector J502 : Touch-pad Board to Main Board Connector SW1 : Scroll Up Button Switch SW2 : Left Button Switch
J501 SW2 J502 SW4 SW1 SW3

SW3 : Right Button Switch SW4 : Scroll Down Button Switch

3.5 Daughter Board -A

JP1 : MDC Jump Wire Connector


JP1 JP3

JP3 : MDC/LAN Transfer Board to M/B Connector

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4. Definition & Location of Major Components
4.1 Mother Board - A

U1 : Intel Pentium 4 Processor mPGA478 Socket U3 : LF-H80P Isolation Transformers U4 : SiS650 IGUI Host/Memory Controller
U11 PU10 U10 U16 U15

U5 : ISC1893Y LAN Controller U6 : PCI1410GGU PCMCIA Controller U9 : ICS93722 Clock Buffer

U4 U1 U14

U10 : Flash ROM (BIOS) U11 : SN74CBTD3384 Level Shift U14 : SiS961 MuTIOL Media I/O Controller U15 : ALC201 Audio CODEC
U18 J509 U3 U5 U6 U9

U16 : TPA0202 Audio Amplifier U18 : uPD72872 IEEE1394 Controller PU10 : CM8500 1.25V Generator

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4. Definition & Location of Major Components
4.1 Mother Board - B

PU508 PU510 PU511

U504 : SiS301LV/Chrontel CH7019


U509

U505 : TPS2211 PC Card Slot Power Switch


U511

U508 : ICS952001 Clock Generator


U508

U509 : H8/F3437 Micro Controller U511 : PC87393 Super I/O ?

U505 U504

PU508 : LTC3716 CPU Power Generator PU510 : LTC3707 1.8V/2.5V Generator PU511 : TL594C PWM

U6 U5 U3

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5. Pin Descriptions of Major Components
5.1 Intel Pentium 4 Processor mPGA478 Socket
Name A[35:3]# Type Input/ Output Description A[35:3]# (Address) define a 2 36 -byte physical memory address space. In sub-phase 1 of the address phase, these pins transmit the address of a transaction. In sub-phase 2, these pins transmit transaction type information. These signals must connect the appropriate pins of all agents on the Pentium 4 processor in the 478-pin package system bus. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#. On the active-to-inactive transition of RESET#, the processor samples a subset of the A[35:3]# pins to determine power-on configuration. If A20M# (Address-20 Mask) is asserted, the processor masks physical address bit 20 (A20#) before looking up a line in any internal cache and before driving a read/write transaction on the bus. Asserting A20M# emulates the 8086 processor's address wrap-around at the 1-Mbyte boundary. Assertion of A20M# is only supported in real mode. A20M# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. ADS# (Address Strobe) is asserted to indicate the validity of the transaction address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS# activation to begin parity checking, protocol checking, address decode, internal snoop, or deferred reply ID match operations associated with the new transaction. Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and falling edges. Strobes are associated with signals as shown below. Signals REQ[4:0]#, A[16:3]# A[35:17]# Associated Strobe ADSTB0# ADSTB1#

Name AP[1:0]#

Type Input/ Output

Description AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. This allows parity to be high when all the covered signals are high. AP[1:0]# should connect the appropriate pins of all Pentium 4 processor in the 478-pin package system bus agents. The following table defines Request Signals A[35:24]# A[23:3]# REQ[4:0]# subphase 1 AP0# AP1# AP1# subphase 2 AP1# AP0# AP0#

A20M#

Input

BCLK[1:0]

Input

ADS#

Input/ Output

BINIT#

Input/ Output

ADSTB[1:0]#

Input/ Output

BNR#

Input/ Output

The differential pair BCLK (Bus Clock) determines the system bus frequency. All processor system bus agents must receive these signals to drive their outputs and latch their inputs. All external timing parameters are specified with respect to the rising edge of BCLK0 crossing V CROSS . BINIT# (Bus Initialization) may be observed and driven by all processor system bus agents and if used, must connect the appropriate pins of all such agents. If the BINIT# driver is enabled during power-on configuration, BINIT# is asserted to signal any bus condition that prevents reliable future operation. If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted, symmetric agents reset their bus LOCK# activity and bus request arbitration state machines. The bus agents do not reset their IOQ and transaction tracking state machines upon observation of BINIT# activation. Once the BINIT# assertion has been observed, the bus agents will re-arbitrate for the system bus and attempt completion of their bus queue and IOQ entries. If BINIT# observation is disabled during power-on configuration, a central agent may handle an assertion of BINIT# as appropriate to the error handling architecture of the system. BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is unable to accept new bus transactions. During a bus stall, the current bus owner cannot issue any new transactions.

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5.1 Intel Pentium 4 Processor mPGA478 Socket
Name BPM[5:0]# Type Input/ Output Description
Name D[63:0]# Type Input/ Output Description D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path between the processor system bus agents, and must connect the appropriate pins on all such agents. The data driver asserts DRDY# to indicate a valid data transfer. D[63:0]# are quad-pumped signals and will thus be driven four times in a common clock period. D[63:0]# are latched off the falling edge of both DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a pair of one DSTBP# and one DSTBN#. The following table shows the grouping of data signals to data strobes and DBI#. Quad-Pumped Signal Groups Data Group D[15:0]# D[31:16]# D[47:32]# D[63:48]# DSTBN#/ DSTBP# 0 1 2 3 DBI# 0 1 2 3

BPRI#

BR0#

BSEL[1:0]

COMP[1:0]

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor signals. They are outputs from the processor which indicate the status of breakpoints and programmable counters used for monitoring processor performance. BPM[5:0]# should connect the appropriate pins of all Pentium 4 processor in the 478-pin package system bus agents. BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is a processor output used by debug tools to determine processor debug readiness. BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ# is used by debug tools to request debug operation of the processor. Please refer to the Intel Pentium 4 Processor in the 478-pin Package and Intel 850 Chipset Platform Design Guide for more detailed information. These signals do not have on-die termination. Refer to the Intel Pentium 4 Processor in the 478-pin Package and Intel 850 Chipset Platform Design Guide for termination requirements. Input BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor system bus. It must connect the appropriate pins of all processor system bus agents. Observing BPRI# active (as asserted by the priority agent) causes all other agents to stop issuing new requests, unless such requests are part of an ongoing locked operation. The priority agent keeps BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#. Input/ BR0# drives the BREQ0# signal in the system and is used by the Output processor to request the bus. During power-on configuration this pin is sampled to determine the agent ID = 0. This signal does not have on-die termination and must be terminated. Output The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the processor input clock frequency. The required frequency is determined by the processor, chipset and clock synthesizer. All agents must operate at the same frequency. The Pentium 4 processor in the 478-pin package operates currently at a 400 MHz system bus frequency (100 MHz BCLK[1:0] frequency). Analog COMP[1:0] must be terminated on the system board using precision resistors. Refer to the Intel Pentium 4 Processor in the 478-pin Package and Intel 850 Chipset Platform Design Guide for details on implementation.

DBI[3:0]#

Input/ Output

Furthermore, the DBI# pins determine the polarity of the data signals. Each group of 16 data signals corresponds to one DBI# signal. When the DBI# signal is active, the corresponding data group is inverted and therefore sampled active high. DBI[3:0]# are source synchronous and indicate the polarity of the D[63:0]# signals. The DBI[3:0]# signals are activated when the data on the data bus is inverted. The bus agent will invert the data bus signals if more than half the bits, within the covered group, would change level in the next cycle. DBI[3:0] Assignment To Data Bus Bus Signal DBI3# DBI2# DBI1# DBI0# Data Bus Signals D[63:48]# D[47:32]# D[31:16]# D[15:0]#

DBR#

Output

DBR# is used only in processor systems where no debug port is implemented on the system board. DBR# is used by a debug port interposer so that an in-target probe can drive system reset. If a debug port is implemented in the system, DBR# is a no connect in the system. DBR# is not a processor signal.

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5.1 Intel Pentium 4 Processor mPGA478 Socket
Name DBSY# Type Description HIT# Name Input/ DBSY# (Data Bus Busy) is asserted by the agent responsible for Output driving data on the processor system bus to indicate that the data bus is in use. The data bus isreleased after DBSY# is deasserted. This signal must connect the appropriate pins on all processor system bus agents. DEFER# is asserted by an agent to indicate that a transaction Input cannot be guaranteed in-order completion. Assertion of DEFER# is normally the responsibility of the addressed memory or Input/Output agent. This signal must connect the appropriate pins of all processor system bus agents. Input/ DP[3:0]# (Data parity) provide parity protection for the Output D[63:0]# signals. They are driven by the agent responsible for driving D[63:0]#, and must connect the appropriate pins of all Pentium 4 processor in the 478-pin package system bus gents. Input/ Data strobe used to latch in D[63:0]#. Output Signals Associated Strobe D[15:0]#, DBI0# DSTBN0# D[31:16]#, DBI1# DSTBN1# D[47:32]#, DBI2# DSTBN2# D[63:48]#, DBI3# DSTBN3# Input/ Data strobe used to latch in D[63:0]#. Output Signals Associated Strobe D[15:0]#, DBI0# DSTBP0# D[31:16]#, DBI1# DSTBP1# D[47:32]#, DBI2# DSTBP2# D[63:48]#, DBI3# DSTBP3# Output FERR# (Floating-point Error) is asserted when the processor detects an unmasked floating-point error. FERR# is similar to the ERROR# signal on the Intel 387 coprocessor, and is included for compatibility with systems using MSDOS*-type floating-point error reporting. Input GTLREF determines the signal reference level for AGTL+ input pins. GTLREF should be set at 2/3 VCC. GTLREF is used by the AGTL+ receivers to determine if a signal is a logical 0 or logical 1. Refer to the Intel Pentium 4 Processor in the 478-pin Package and Intel 850 Chipset Platform Design Guide for more information. Type Description Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey Output transaction snoop operation results. Any system bus agent may assert both HIT# and HITM# together to indicate that it requires Input/ a snoop stall, which can be continued by reasserting Output HIT# and HITM# together. Output IERR# (Internal Error) is asserted by a processor as the result of an internal error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction on the processor system bus. This transaction may optionally be converted to an external error signal (e.g., NMI) by system core logic. The processor will keep IERR# asserted until the assertion of RESET#, BINIT#, or INIT#. This signals does not have on-die termination. Input IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a numeric error and continue to execute noncontrol floating-point instructions. If IGNNE# is deasserted, the processor generates an exception on a noncontrol floating-point instruction if a previous floating-point instruction caused an error.IGNNE# has no effect when the NE bit in control register 0 (CR0) is set. IGNNE# is an asynchronous signal. However, to ensure recognition of this signal following an Input/Output write instruction, it must be valid along with the TRDY# assertion of the corresponding Input/Output Write bus transaction. Input INIT# (Initialization), when asserted, resets integer registers inside the processor without affecting its internal caches or floating-point registers. The processor then begins execution at the power-on Reset vector configured during power-on configuration. The processor continues to handle snoop requests during INIT# assertion. INIT# is an asynchronous signal and must connect the appropriate pins of all processor system bus agents. If INIT# is sampled active on the active to inactive transition of RESET#, then the processor executes its Built-in Self-Test (BIST). Output The ITPCLKOUT[1:0] pins do not provide any output for the Pentium 4 processor in the 478-pin package. Input ITP_CLK[1:0] are copies of BCLK that are used only in processor systems where no debug port is implemented on the system board. ITP_CLK[1:0] are used as BCLK[1:0] references for a debug port implemented on an interposer. If a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the system. These are not processor signals.

DEFER#

HITM# IERR#

DP[3:0]#

IGNNE#

DSTBN[3:0]#

DSTBP[3:0]#

INIT#

FERR#

ITPCLKOUT[1:0] ITP_CLK[1:0]

GTLREF

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5.1 Intel Pentium 4 Processor mPGA478 Socket
Name LINT[1:0] Type Description LINT[1:0] (Local APIC Interrupt) must connect the appropriate Input pins of all APIC Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable interrupt. INTR and NMI are backward compatible with the signals of those names on the Pentium processor. Both signals are asynchronous. Both of these signals must be software configured via BIOS programming of the APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is the default configuration. Input/ LOCK# indicates to the system that a transaction must occur Output atomically. This signal must connect the appropriate pins of all processor system bus agents. For a locked sequence of transactions, LOCK# is asserted from the beginning of the first transaction to the end of the last transaction. When the priority agent asserts BPRI# to arbitrate for ownership of the processor system bus, it will wait until it observes LOCK# deasserted. This enables symmetric agents to retain ownership of the processor system bus throughout the bus locked operation and ensure the atomicity of lock. Input/ MCERR# (Machine Check Error) is asserted to indicate an Output unrecoverable error without a bus protocol violation. It may be driven by all processor system bus agents. MCERR# assertion conditions are configurable at a system level. Assertion options are defined by the following options: Enabled or disabled. Asserted, if configured, for internal errors along with IERR#. Asserted, if configured, by the request initiator of a bus transaction after it observes an error. Asserted by any bus agent when it observes an error in a bus transaction. For more details regarding machine check architecture, please refer to the IA-32 Software Developers Manual, Volume 3: System Programming Guide. Output PROCHOT# will go active when the processor temperature monitoring sensor detects that the processor has reached its maximum safe operating temperature. This indicates that the processor Thermal Control Circuit has been activated, if enabled. . Name PWRGOOD Type Description Input PWRGOOD (Power Good) is a processor input. The processor requires this signal to be a clean indication that the clocks and power supplies are stable and within their specifications. Clean implies that the signal will remain low (capable of sinking leakage current), without glitches, from the time that the power supplies are turned on until they come within specification. The signal must then transition monotonically to a high state. PWRGOOD can be driven inactive at any time, but clocks and power must again be stable before a subsequent rising edge of PWRGOOD. The PWRGOOD signal must be supplied to the processor; it is used to protect internal circuits against voltage sequencing issues. It should be driven high throughout boundary scan operation. Input Asserting the RESET# signal resets the processor to a known state and invalidates its internal caches without writing back any of their contents. For a power-on Reset, RESET# must stay active for at least one millisecond after VCC and BCLK have reached their proper specifications. On observing active RESET#, all system bus agents will deassert their outputs within two clocks. RESET# must not be kept asserted for more than 10 ms while PWRGOOD is asserted. A number of bus signals are sampled at the active-to-inactive transition of RESET# for power-on configuration. This signal does not have on-die termination and must be terminated on the system board. Input RS[2:0]# (Response Status) are driven by the response agent (the agent responsible for completion of the current transaction), and must connect the appropriate pins of all processor system bus agents. Input RSP# (Response Parity) is driven by the response agent (the agent responsible for completion of the current transaction) during assertion of RS[2:0]#, the signals for which RSP# provides parity protection. It must connect to the appropriate pins of all processor system bus agents. A correct parity signal is high if an even number of covered signals are low and low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is also high, since this indicates it is not being driven by any agent guaranteeing correct parity.

LOCK#

RESET#

MCERR#

RS[2:0]#

RSP#

PROCHOT#

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5.1 Intel Pentium 4 Processor mPGA478 Socket
Name REQ[4:0]# Type Description Input/ REQ[4:0]# (Request Command) must connect the appropriate Output pins of all processor system bus agents. They are asserted by the current bus owner to define the currently active transaction type. These signals are source synchronous to ADSTB0#. Refer to the AP[1:0]# signal description for a details on parity checking of these signals. Output SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System board designers may use this pin to determine if the processor is present. Input SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter the Sleep state. During Sleep state, the processor stops providing internal clock signals to all units, leaving only the Phase-Locked Loop (PLL) still operating. Processors in this state will not recognize snoops or interrupts. The processor will recognize only assertion of the RESET# signal, deassertion of SLP#, and removal of the BCLK input while in Sleep state. If SLP# is deasserted, the processor exits Sleep state and returns to Stop-Grant state, restarting its internal clock signals to the bus and processor core units. If the BCLK input is stopped while in the Sleep state the processor will exit the Sleep state and transition to the Deep Sleep state. Input SMI# (System Management Interrupt) is asserted asynchronously by system logic. On accepting a System Management Interrupt, the processor saves the current state and enter System Management Mode (SMM). An SMI Acknowledge transaction is issued, and the processor begins program execution from the SMM handler. If SMI# is asserted during the deassertion of RESET# the processor will tristate its outputs. Input STPCLK# (Stop Clock), when asserted, causes the processor to enter a low power Stop-Grant state. The processor issues a Stop-Grant Acknowledge transaction, and stops providing internal clock signals to all processor core units except the system bus and APIC units. The processor continues to snoop bus transactions and service interrupts while in Stop-Grant state. When STPCLK# is deasserted, the processor restarts its internal clock to all units and resumes execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK# is an asynchronous input. Input TCK (Test Clock) provides the clock input for the processor Test Bus (also knownas the Test Access Port). Name TDI Type Description Input TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial input needed for JTAG specification support. Output TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the serial output needed for JTAG specification support. Input TESTHI[12:8] and TESTHI[5:0] must be connected to a VCC power source through a resistor for proper processor operation. Other Thermal Diode Anode. Other Thermal Diode Cathode. Output Assertion of THERMTRIP# (Thermal Trip) indicates the processor junction temperature has reached a level beyond which permanent silicon damage may occur. Measurement of the temperature is accomplished through an internal thermal sensor which is configured to trip at approximately 135C.Upon assertion of THERMTRIP#, the processor will shut off its internal clocks (thus halting program execution) in an attempt to reduce the processor junction temperature. To protect the processor, its core voltage (VCC) must be removed following the assertion of THERMTRIP#. Once activated, THERMTRIP# remains latched until RESET# is asserted. While the assertion of the RESET# signal will de-assert THERMTRIP# , if the processors junction temperature remains at or above the trip level, THERMTRIP# will again be asserted after RESET# is de-asserted. Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 . pull-down resistor. Input VCCA provides isolated power for the internal processor core PLLs. Refer to the Intel Pentium 4 Processor in the 478-pin Package and Intel 850 Chipset Platform Design Guide for complete implementation details.

TDO

SKTOCC#

TESTHI[12:8] TESTHI[5:0] THERMDA THERMDC THERMTRIP#

SLP#

SMI#

TMS TRDY#

STPCLK#

TRST#

VCCA

TCK

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5.1 Intel Pentium 4 Processor mPGA478 Socket
Name VCCIOPLL Type Description Input VCCIOPLL provides isolated power for internal processor system bus PLLs. Follow he guidelines for VCCA, and refer to the Intel Pentium 4 Processor in the 478-pin Package and Intel 850 Chipset Platform Design Guide for complete implementation details. Output VCCSENSE is an isolated low impedance connection to processor core power(VCC). It can be used to sense or measure power near the silicon with little noise. Input There is no imput voltage requirement for VCCVID for designs intended tosupport only the Pentium 4 processor in the 478-pin package. Refer to the Intel Pentium 4 Processor in the 478-pin Package and Intel 850 Chipset Platform Design Guide for more information. Output VID[4:0] (Voltage ID) pins can be used to support automatic selection of power supply voltages (Vcc). These pins are not signals, but are either an open circuit or a short circuit to VSS on the processor. The combination of opens and shorts defines the voltage required by the processor. The VID pins are needed to cleanly support processor voltage specification variations. The power supply must supply the voltage that is requested by these pins, or disable itself. Input VSSA is the isolated ground for internal PLLs. Output VSSSENSE is an isolated low impedance connection to processor core VSS. It can be used to sense or measure ground near the silicon with little noise Input TMS (Test Mode Select) is a JTAG specification support signal used by debug tools. Input TRDY# (Target Ready) is asserted by the target to indicate that it is ready to receive a write or implicit writeback data transfer. TRDY# must connect the appropriate pins of all system bus agents. Input TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be driven low during power on Reset. This can be done with a 680 . pull-down resistor. Input VCCA provides isolated power for the internal processor core PLLs. Refer to the Intel Pentium 4 Processor in the 478-pin Package and Intel 850 Chipset Platform Design Guide for complete implementation details.

VCCSENSE

VCCVID

VID[4:0]

VSSA VSSSENSE

TMS TRDY#

TRST#

VCCA

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5.2 SiS650 IGUI Host/Memory Controller
Host BUS Interface
Name CPUCLK CPUCLK# CPURST# Pin Attr I 0.71V M O 1.2~1.85V M Signal Description Host differential clock input. Host Bus Reset: CPURST# is used to keep all the bus agents in the same initial state before valid cycles issued. CPUPWRGD# is used to inform CPU that main power is stable Address Strobe : Address Strobe is driven by CPU or SiS650 to indicate the start of a CPU bus cycle. Source synchronous address strobe used to latch HREQ[4:0]# & HA[31:3]# at both falling and rising edge. HREQ[4:0]# & HA[16:3]# are latched by HASTB0# HA[31:17] are latched by HASTB1# Request Command: HREQ[4:0]# are used to define each transaction type during the clock when ADS# is asserted and the clock after ADS# is asserted. Host Address Bus Symmetric Agent Bus Request: BREQ0# is driven by the symmetric agent to request for the bus. Priority Agent Bus Request: BPRI# is driven by the priority agent that wants to request the bus. BPRI# has higher priority than BREQ0# to access a bus. Block Next Request: This signal can be driven asserted by any bus agent to block further requests being pipelined. Host Lock : CPU asserts HLOCK# to indicate the current bus cycle is locked. Keeping a Non-Modified Cache Line Hits a Modified Cache Line: Hit Modified indicates the snoop cycle hits a modified line in the L1/L2 cache of CPU. Defer Transaction Completion: r defer response to host bus.

Name RS[2:0]#

Pin Attr

Signal Description

CPUPWRGD# ADS#

O 1.2~1.85V M I/O
1.2~1.85V M

HADSTB[1:0]# 1.2~1.85V M

HTRDY#

HREQ[4:0]#

I/O 1.2~1.85V M

DRDY#

DBSY#

HA[31:3]# BREQ0#

I/O 1.2~1.85V M O 1.2~1.85V M O 1.2~1.85V M

HD[63:0]#

BPRI#

DBI[3:0]#

BNR#

I/O 1.2~1.85V M I 1.2~1.85V M I/O 1.2~1.85V M I/O 1.2~1.85V M O 1.2~1.85V M

HDSTBP[3:0]#

HLOCK#

HIT# HITM#

HDSTBN[3:0]#

DEFER#

HNCOMP

O Response Status: 1.2~1.85V M RS[2:0]# are driven by the response agent to indicate the transaction response type. The following shows the response type. RS[2:0] Response 000 Idle State 001 Retry 010 Defer 011 Reserved 100 Reserved 101 No data 110 Implicit Write-back 111 Normal Data O Target Ready: 1.2~1.85V M During write cycles, response agent will drive TRDY# to indicate it is ready to accept data. I/O Data Ready: 1.2~1.85V M DRDY# is driven by the bus owner whenever the data is valid on the bus. I/O Data Bus Busy: 1.2~1.85V M Whenever the data is not valid on the bus with DRDY# is deserted, DBSY# deasserted to hold the bus. I/O Data Bus Busy: 1.2~1.85V M Whenever the data is not valid on the bus with DRDY# is deserted, DBSY# deasserted to hold the bus. I/O Dynamic Bus Inversion: An active DBI# will invert 1.2~1.85V M its corresponding data group signals. DBI0# is referenced by HD[15:0], DBI1# is referenced by HD[31:16] DBI2# is referenced by HD[47:32] DBI3# is referenced by HD[63:48] I/O Source synchronous data strobe used to latch data at falling edge 1.2~1.85V M HD[15:0], DBI0# are latched by HDSTBP0# HD[31:16], DBI1# are latched by HDSTBP1# HD[47:32], DBI2# are latched by HDSTBP2# HD[63:48], DBI3# are latched by HDSTBP3# I/O Source synchronous data strobe used to latch data at falling edge 1.2~1.85V M HD[15:0], DBI0# are latched by HDSTBN0# HD[31:16], DBI1# are latched by HDSTBN1# HD[47:32], DBI2# are latched by HDSTBN2# HD[63:48], DBI3# are latched by HDSTBN3# I GTL N-MOS Compensation Input M

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5.2 SiS650 IGUI Host/Memory Controller
Host BUS Interface Continue
Name I M I HVREF[4:0] HNCOMPVREF M HPCOMP Pin Attr Signal Description GTL P-MOS Compensation Input AGTL+ I/O reference voltage

SiS MuTIOL Interface


Name ZCLK ZUREQ/ZD REQ ZSTB[1:0] ZSTB[1:0]# Pin Attr I 3.3V - M I/O 1.8V - M I/O 1.8V - M I/O 1.8V - M I/O 1.8V - M I M I M I M I 3.3V M I/O 1.5V/3.3V - M I/O 1.5V/3.3V - M I/O 1.5V/3.3V - M I/O 1.5V/3.3V - M I/O 1.5V/3.3V - M I 1.5V/3.3V - M I 1.5V/3.3V - M O 1.5V/3.3V - M I/O 1.5V/3.3V - M Signal Description SiS MuTIOL Connect SiS MuTIOL Connect Control pins SiS MuTIOL Connect Strobe Strobe Compliment I/O 1.8V - M SiS MuTIOL Connect Reference Voltage N-MOS Compensation Input P-MOS Compensation Input AGP Clock AGP Frame# AGP Initiator Ready AGP Target Ready AGP Stop# AGP Device Select AGP System Error AGP Bus Request AGP Bus Grant AGP Address/Data Bus

DRAM Controller
Name SDCLK Pin Attr Signal Description SDRAM Clock Input I 3.3V - M I SDRCLKI 2.5V/3.3V - M FWDSDCLKO O 2.5V/3.3V M O MA[14:0] 2.5V/3.3V - M O SRAS# 2.5V/3.3V - M O SCAS# 2.5V/3.3V - M O SWE# 2.5V/3.3V - M O CS[5:0]# 2.5V/3.3V - M CSB[5:0]# O DQM[7:0]# 2.5V/3.3V - M I/O DQS[7:0] 2.5V/3.3V - M I/O MD[63:0] 2.5V/3.3V - M O (open-drain) CKE[5:0] 2.5V/3.3V AUX O (open-drain) S3AUXSW# 2.5V/3.3V (CKE6) AUX DDRVREF[A:B] I M

ZAD[15:0] ZVREF ZCMP_N SDRAM Read Clock Input ZCMP_P SDRAM Forward Clock Output AGPCLK System Memory Address Bus AFRAME# SDRAM Row Address Strobe SDRAM Column Address Strobe SDRAM Write Enable ASTOP# SDRAM Chip Select CSB[5:0] multiplexed with DQS[5:0] SDRAM Input/Output Data Mask DDR Data Strobe System Memory Data Bus AGNT# SDRAM Clock Enable AAD[31:0] Aux power switch for ACPI-S3 state, low active. ADEVSEL# ASERR# AREQ# AIRDY# ATRDY#

DDR I/O Reference Voltage

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5.2 SiS650 IGUI Host/Memory Controller
SiS MuTIOL Interface Continue
Name AC/BE[3:0] Pin Attr Signal Description AGP Command/Byte Enable AGP Parity AGP Status Bus AGP Pipeline Request Side Band Address Read Buffer Full Write Buffer Full AD Bus Strobe AD Bus Strobe Compliment Side Band Strobe Side Band Strobe Compliment VBD[11:0] VAHSYNC VAVSYNC VADE I/O 1.8V/3.3V - M I/O 1.8V/3.3V - M I/O 1.8V/3.3V - M I/O 1.8V/3.3V - M I/O 1.8V/3.3V - M I/O 1.5V/3.3V - M I/O APAR 1.5V/3.3V - M O ST[2:0] 1.5V/3.3V - M I PIPE# 1.5V/3.3V - M I/O SBA[7:0] 1.5V/3.3V - M I RBF# 1.5V/3.3V - M I WBF# 1.5V/3.3V - M AD_STB[1:0] I/O 1.5V/3.3V - M AD_STB[1:0]# I/O 1.5V/3.3V - M I SB_STB 1.5V/3.3V - M I SB_STB# 1.5V/3.3V - M

VB Interface
Name VBCLK VBHCLK VBCAD VBCTL[1:0] VGPIO[3:2] VBHSYNC VBVSYNC VBDE VBGCLK Pin Attr I 1.8V/3.3V - M O 1.8V/3.3V M I/O 1.8V/3.3V M O 1.8V/3.3V - M I/O 3.3V - M I/O 1.8V/3.3V - M I/O 1.8V/3.3V - M I/O 1.8V/3.3V - M I/O 1.8V/3.3V - M Signal Description Channel B/A Clock Input VBCLK multiplexed with SBA0 VB Programming Interface Clock VBHCLK multiplexed with RBF# VB Programming Interface Data VBCAD multiplexed with AREQ# VB Data Control VBCTL[1:0] multiplexed with AAD[29:28] VB GPIO pins VGPIO[3:2] multiplexed with PIPE#/WBF# Channel B H-Sync VBHSYNC multiplexed with AAD30 Channel B V-Sync VBVSYNC multiplexed with AAD31 Channel B Data Valid VBDE multiplexed with AAD27 Channel B Clock Output. This clock is used to trigger dual edge data transfer. Perfect duty cycle is required. VBGCLK multiplexed with AD_STB1 Channel B Data VBD[11:0] multiplexed with AAD Channel A H-Sync VAHSYNC multiplexed with AAD18 Channel A V-Sync VAVSYNC multiplexed with AAD17 Channel A Data Valid VADE multiplexed with AAD16 Channel A Clock Output. This clock is used to trigger dual edge data transfer. Perfect duty cycle is required. VAGCLK multiplexed with AD_STB0 Channel A Differential Clock Output. (To support Chrontel). VAGCLK# multiplexed with AD_STB0# Channel A Data VAD[11:0] multiplexed with AAD

Stereo Glasses Interface


Name CSYNC RSYNC LSYNC Pin Attr O 3.3V - M O 3.3V - M O 3.3V - M Stereo Clock Signal Description

VAGCLK

VAGCLK#

Stereo Right Stereo Left


VAD[11:0]

I/O 1.8V/3.3V - M I/O 1.8V/3.3V - M

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5.2 SiS650 IGUI Host/Memory Controller
VGA Interface
Name VOSCI HSYNC VSYNC INTA# VGPIO[1:0] VCOMP VRSET VVBWN ROUT GOUT BOUT Pin Attr I 3.3V - M O 3.3V - M O 3.3V - M O 3.3V - M I/O 3.3V - M AI Analog - M AI Analog - M AI Analog - M AO Analog - M AO Analog - M AO Analog - M Signal Description 14.318 Reference Clock Input Horizontal Sync Vertical Sync Internal VGA Interrupt Pin Internal VGA GPIO pins Compensation Pin Reference Resistor Voltage Reference Red Signal Output Green Signal Output Blue Signal Output

Name C4XAVDD C4XAVSS DACAVDD1 DACAVDD2 DACAVSS1 DACAVSS2 DCLKAVDD DCLKAVSS DDRAVDD DDRAVSS ECLKAVDD ECLKAVSS IVDD OVDD PVDD PVDDM PVDDP PVDDZ 3.3V 0V 1.8V 1.8V 0V 0V 3.3V 0V 3.3V 0V 3.3 0V 1.8V 3.3V 3.3V 3.3V 1.8V 1.8V 3.3V 0V

Tolerance

Power Plane MAIN GROUND MAIN MAIN GROUND GROUND MAIN GROUND MAIN GROUND MAIN GROUND MAIN MAIN MAIN AUX MAIN MAIN MAIN GROUND MAIN(AUX) MAIN MAIN MAIN MAIN MAIN GROUND MAIN GROUND Analog Analog Analog Analog Analog Digital Digital Analog Analog Analog Analog Analog Digital Digital Digital Digital Digital Digital Analog Analog Digital Digitalv Digital Analog Digital Analog Analog Analog Analog

Type Attribute

Power and Ground Signals


Name A1XAVDD A1XAVSS A4XAVDD A4XAVSS 3.3V 0V 3.3V 0V Tolerance Power Plane MAIN GROUND MAIN GROUND GROUND AUX AUX MAIN GROUND Analog Analog Analog Analog Analog Digital Digital Analog Analog Type Attribute

SDAVDD SDAVSS VDDM VDDQ VDDZ VDDMCMP VTT Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS

2.5/3.3V 1.5/1.8/3.3V 1.8V 1.8V 1.2~1.85V 3.3V 0V 3.3V 0V

AGPVSSREF 0V AUX1.8 AUX3.3 C1XAVDD C1XAVSS 1.8V 3.3V 3.3V 0V

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5.2 SiS650 IGUI Host/Memory Controller
Test Mode/Hardware Trap/Power Management
Name DLLEN# DRAM_SEL TRAP[1:0] ENTEST TESTMOD E[2:0] AUXOK Pin Attr I/O 3.3V/5V - M I 3.3V/5V - AUX I 3.3V/5V - M I 3.3V/5V - M I 3.3V/5V - M I 3.3V - AUXI Signal Description Hardware Trap pin (refer to section 5) Hardware Trap pin (refer to section 5) Hardware Trap pins (refer to section 5) Test Mode enable pin Test Mode select pin Nand Tree Test: 100 Auxiliary Power OK : This signal is supplied from the power source of resume well. It is also used to reset the logic in resume power well. If there is no auxiliary power source on the system, this pin should be tied together with PWROK. PCI Bus Reset : PCIRST# is supplied from SiS MuTIOL Media IO SiS961. Main Power OK : A high-level input to this signal indicates the power being supplied to the system is in stable operating state. During the period of PWROK being low, CPURST and PCIRST# will all be asserted until after PWROK goes high for 24 ms.

PCIRST# PWROK

I 3.3V - AUXI I 3.3V - AUXI

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5.3 SiS961 MuTIOL Media I/O Controller
Host Bus Interface
Name FERR# IGNNE# NMI Pin Attr I 1.1V/2.65V -M OD 1.1V/2.65V -M OD 1.1V/2.65V -M OD 1.1V/2.65V -M I/OD 1.1V/2.65V -M OD 1.1V/2.65V -M Signal Description Floating Point Error: CPU will assert this signal upon a floating point error occurring. Ignore Numeric Error: IGNNE# is asserted to inform CPU to ignore a numeric error. Non-Maskable Interrupt: A rising edge on NMI will trigger a non-maskable interrupt to CPU. Interrupt Request: High-level voltage of this signal conveys to CPU that there is outstanding interrupt(s) needed to be serviced. APIC Data: These two signals are used to send and receive APIC data. CPU Sleep: The CPUSLP# can be used to force CPU enter the Sleep state. CPU Clock STOP: For Intel Mobile processor, this signal can be used to stop the clock to the processor. If the processor is in Quick Start state and the processor clock is stopped, the processor will enter the Deep Sleep state. For AMD processor, this signal can be to reduce processor voltage during C3/S1 state. Stop Clock: STPCLK# will be asserted to inhibit or throttle CPU activities upon a pre-defined power management event occurs Initialization: INIT is used to re-start the CPU without flushing its internal caches and registers. In Pentium III platform it is active high. This signal requires an external pull-up resistor tied to 3.3V. APIC Clock: This signal is used to determine when valid data is being sent over the APCI bus. Address 20 Mask: When A20M# is asserted, the CPU A20 signal will be forced to 0

MuTIOL Connect Interface


Name ZCLK ZUREQ ZDREQ ZSTB[1:0] ZSTB[1:0]# ZAD[15:0] ZVRE ZCMP_N ZCMP_P Pin Attr I 3.3V - M I/O 1.8V - M I/O 1.8V - M I/O 1.8V - M I/O 1.8V - M I/O 1.8V - M I -M I -M I -M Signal Description Megaband I/O Connect Clock Megaband I/O Conect Controll pins Megaband I/O Conect Controll pins Megaband I/O Connect Strobe Strobe Compliment Address/Data pins Megaband I/O Connect I/O reference voltage N-MOS Compensation Input P-MOS Compensation input

INTR

APICD[1:0] CPUSLP#/ CPUSTP#

STPCLK#

OD 1.1V/2.65V -M OD 1.1V/2.65V -M

PCI Interface
Name PCICLK Pin Attr I 3.3V/5V -M Signal Description PCI Clock: The PCICLK input provides the fundamental timing and the internal operating frequency for the SiS961. It runs at the same frequency and skew of the PCI local bus. PCI Bus Command and Byte Enables: PCI Bus Command and Byte Enables define the PCI command during the address phase of a PCI cycle, and the PCI byte enables during the data phases. C/BE[3:0]# are outputs when the SiS961 is a PCI bus master and inputs when it is a PCI slave. PCI Lock: When PLOCK# is sampled asserted at the beginning of a PCI cycle, SiS961 considers itself being locked and remains in the locked state until PLOCK# is sampled and negated at the following PCI cycle.

INIT#

APICCK

I 2.5V - M OD 1.1V/2.65V- M

C/BE[3:0]#

I/O 3.3V/5V -M

A20M#

PLOCK#

I/O 3.3V/5V -M

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5.3 SiS961 MuTIOL Media I/O Controller
PCI Interface Continue
Name AD[31:0] Pin Attr I/O 3.3V/5V -M Signal Description PCI Address /Data Bus: In address phase: 1.When the SiS961 is a PCI bus master, AD[31:0] are output signals. 2.When the SiS961 is a PCI target, AD[31:0] are input signals. In data phase: 1.When the SiS961 is a target of a memory read/write cycle, AD[31:0] are floating. 2.When the SiS961 is a target of a configuration or an I/O cycle, AD[31:0] are output signals in a read cycle, and input signals in a write cycle. Parity: SiS961 drives out Even Parity covering AD[31:0] and C/BE[3:0]#. It does not check the input parity signal. Frame#: FRAME# is an output when the SiS961 is a PCI bus master. The SiS961 drives FRAME# to indicate the beginning and duration of an access. When the SiS961 is a PCI slave device, FRAME# is an input signal. Initiator Ready: IRDY# is an output when the SiS961 is a PCI bus master. The assertion of IRDY# indicates the current PCI bus master's ability to complete the current data phase of the transaction. For a read cycle, IRDY# indicates that the PCI bus master is prepared to accept the read data on the following rising edge of the PCI clock. For a write cycle, IRDY# indicates that the bus master has driven valid data on the PCI bus. When the SiS961 is a PCI slave, IRDY# is an input pin. Target Ready: TRDY# is an output when the SiS961 is a PCI slave. The assertion of TRDY# indicates the target agent's ability to complete the current data phase of the transaction. For a read cycle, TRDY# indicates that the target has driven valid data onto the PCI bus. For a write cycle, TRDY# indicates that the target is prepared to accept data from the PCI bus. When the SiS961 is a PCI master, it is an input pin. Stop#: STOP# indicates that the bus master must start terminating its current PCI bus cycle at the next clock edge and release control of the PCI bus. STOP# is used for disconnection, retry, and target-abortion sequences on the PCI bus.
Name DEVSEL# Pin Attr I/O 3.3V/5V -M Signal Description Device Select: As a PCI target, SiS961 asserts DEVSEL# by doing positive or subtractive decoding. SiS961 positively asserts DEVSEL# when the DRAM address is being accessed by a PCI master, PCI configuration registers or embedded controllers registers are being addressed, or the BIOS memory space is being accessed. The low 16K I/O space and low 16M memory space are responded subtractively. The DEVESEL# is an input pin when SiS961 is acting as a PCI master. It is asserted by the addressed agent to claim the current transaction. PCI Bus Request: PCI Bus Master Request Signals PCI Bus Grant: PCI Bus Master Grant Signals PCI Bus Request: PCI Bus Master Request Signal PCI Bus Grant: PCI Bus Master Grant Signal PCI interrupt A,B,C,D: The PCI interrupts will be connected to the inputs of the internal Interrupt controller through the rerouting logic associated with each PCI interrupt. PCI Bus Reset: PCIRST# will be asserted during the period when PWROK is low, and will be kept on asserting until about 24ms after PWROK goes high. System Error: When sampled active low, a non-maskable interrupt (NMI) can be generated to CPU if enabled.

PREQ[4:0]# PGNT[4:0]# PREQ5# / GPIO5 PGNT5# / GPIO6 INT[A:D]#

PAR

I/O 3.3V/5V -M I/O 3.3V/5V -M

FRAME#

IRDY#

I/O 3.3V/5V -M

I 3.3V/5V -M O 3.3V M I I/O 3.3V/5V- M O I/O 3.3V- M I 3.3V/5V M

PCIRST#

O 3.3V M

TRDY#

I/O 3.3V/5V -M

SERR#

I 3.3V/5V M

STOP#

I/O 3.3V/5V -M

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IED Interface
Name IDA[15:0] IDB[15:0] IDECSA[1:0]# IDECSB[1:0]# IIOR[A:B]# IIOW[A:B]# ICHRDY[A:B] IDREQ[A:B] IDACK[A:B]# IIRQ[A:B] IDSAA[2:0] IDSAB[2:0] CBLID[A:B] Pin Attr I/O 3.3V/5V -M I/O 3.3V/5V -M O 3.3V -M O 3.3V -M O 3.3V -M O 3.3V -M I 3.3V/5V -M I 3.3V/5V -M O 3.3V -M I 3.3V/5V -M O 3.3V -M O 3.3V -M I 3.3V/5V -M Signal Description Primary Channel Data Bus Secondary Channel Data Bus Primary Channel CS[1:0] Secondary Channel CS[1:0] Primary/Secondary Channel IOR# Signals Primary/Secondary Channel IOW# Signals Primary/Secondary Channel ICHRDY# Signals Primary/Secondary Channel DMA Request Signals Primary/Secondary Channel DMACK# Signals Primary/Secondary Channel Interrupt Signals Primary Channel Address [2:0] Secondary Channel Address [2:0] Primary/Secondary Ultra-66 Cable ID
PWRBTN# I 3.3V/5V -AUX AUXOK I 3.3V -AUX PSON# OD <=5V -AUX PME# EXTSMI# / GPIO3 I I/O 3.3V/5V -M I 3.3V/5V -AUX

Power Management Interface


Name ACPILED Pin Attr OD <=5V -AUX Signal Description ACPILED : ACPILED can be used to control the blinking of an LED at the frequency of 1Hz to indicate the system is at power saving mode. External SMI#: EXTSMI# can be used to generate wakeup event, sleep event, or SCI/SMI# event to the ACPI compatible power management unit. PME# : When the system is in power-down mode, an active low event on PME# will cause the PSON# to go low and hence turn on the power supply. When the system is in suspend mode, an active PME# event will cause the system wakeup and generate an SCI/SMI#. ATX Power ON/OFF control: PSON# is used to control the on/off state of the ATX power supply. When the ATX power supply is in the OFF state, an activated power-on event will force the power supply to ON state. Auxiliary Power OK: This signal is supplied from the AUX power source. It is also used to reset the logic in AUX power well. If there is no auxiliary power source on the system, this pin should be tied together with PWROK. Power Button: This signal is from the power button switch and will be monitored by the ACPI-compatible power management unit to switch the system between working and sleeping states. Ring Indication: An active RING pulse and lasting for more than 4ms will cause a wakeup event for system to wake from S1~S5. Stop CPU clock: Output to the external clock generator for it to turn off the CPU clock during C3/Sx. Deeper Sleep: DPRSLP# can be used to lower the Intel processor voltage during C3/S1 state.

RING / GPIO8

I I/O 3.3V/5V -AUX O I/O 3.3V/5V -AUX O O 3.3V/5V -AUX

Legacy I/O and Miscellaneous Signals


Signal Name SPK ENTEST OSCI Pin Attr O 3.3V -M I 3.3V/5V -M I 3.3V -M Signal Description Speaker output: The SPK is connected to the system speaker. SiS961 Test Mode Enable Pin SiS961 Test Mode Enable Pin

BCLK_STP# GPIO12 DPRSLPVR GPIO13

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5.3 SiS961 MuTIOL Media I/O Controller
Keyboard Control Interface
Name KBDAT / GPIO15 KBCLK / GPIO16 PMDAT / GPIO17 PMCLK / GPIO18 Pin Attr I/OD O/OD 3.3V/5V -AUX I/OD O/OD 3.3V/5V -AUX I/OD O/OD 3.3V/5V -AUX I/OD O/OD 3.3V/5V -AUX Signal Description Keyboard Dada: When the internal keyboard controller is enabled, this pin is used as the keyboard data signal. Keyboard Clock: When the internal keyboard controller is enabled, this pin is used as the keyboard clock signal. PS2 Mouse Data: When the internal keyboard and PS2 mouse controllers are enabled, this pin is used as PS2 mouse data signal. PS2 Mouse Clock: When the internal keyboard and PS2 mouse controllers are enabled, this pin is used as the PS2 mouse clock signal.

Name TXEN

Pin Attr O 3.3V -AUX

Signal Description Transmit Enable: When set to a 1, and the transmit state machine is idle, then the transmit state machine becomes active. This bit will read back as a 1 whenever the transmit state machine is active. After initial power-up, software must insure that the transmitter has completely reset before setting this bit Management Data I/O: Bi-direction signal used to transfer management information for the external physical unit. Requires external pull-up resistor. Receive Data Valid. This indicates that the external physical unit is presenting recovered and decoded nibbles on the RXD[3:0] and that RXCLK is synchronous to the recovered data. This signal will encompass the frame, starting with the Start-Of-Frame delimiter and excluding the End-Of-Frame delimiter. Collision Detect: This signal is asserted high asynchronous by the external physical unit upon detection of a collision on the medium. Itll remain asserted as long as the collision condition persists. Carrier Sense: This signal is asserted high asynchronously by the physical unit upon detection of a non-idle medium. Receive Clock A continuous clock that is recovered from the incoming data. During 100Mb/s operation RXCLK is 25MHz and during 10Mb/s this is 2.5MHz. Transmit Clock A continuous clock that is sourced by the physical unit. During 100Mb/s operation RXCLK is 25MHz and during 10Mb/s this is 2.5MHz.

MDIO

I/O 3.3V/5V -AUX I 3.3V/5V -AUX

RXDV

MAC Interface
Name RXER Pin Attr I 3.3V/5V -AUX I 3.3V/5V -AUX O 3.3V -AUX Signal Description RX Packet Error This event is signaled after the last received descriptor in a failed packet reception that has been updated with valid status. PHY 25MHz Clock Input: This pin provides the 25MHz clock signal input to the built-in oscillator. Management Data Clock: Clock signal with a maximum rate of 2.5MHz used to transfer management data for the external physical unit on the MIIMDIO pin. Receive Data: This is a group of 4 data signals aligned on nibble boundaries which are driven synchronous to the RXCLK by the external physical unit. Transmit Data: This is a group of 4 data signals which are driven synchronous to the TXCLK for transmission to the external physical unit. Receive Data: This is a group of 4 data signals aligned on nibble boundaries which are driven synchronous to the RXCLK by the external physical unit.

COL

I 3.3V/5V -AUX

CRS

I 3.3V/5V -AUX I 3.3V/5V -AUX

MIICLK25M

RXCLK

MDC

TXCLK

I 3.3V/5V -AUX

TXD[0:3]

I 3.3V/5V -AUX

TXEN

O 3.3V -AUX I 3.3V/5V -AUX

RXD[0:3]

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5.3 SiS961 MuTIOL Media I/O Controller
LPC Interface
Name LAD[3:0] Pin Attr I/O 3.3V/5V-M I 3.3V/5V-M I I/O 3.3V/5V-M O 3.3V -M I/O 3.3V/5V -M Signal Description LPC Address/Data Bus: LPC controller drives these four pins to transmit LPC command, address, and data to LPC device. LPC DMA Request 0: This pin is used by LPC device to request DMA cycle. LPC DMA Request 1: This pin is used by LPC device to request DMA cycle. LPC Frame: This pin is used to notify LPC device that a start or a abort LPC cycle will occur. I/O 3.3V/5V -M

AC97 Interface
Name AC_BIT_CLK Pin Attr I 3.3V/5V -M O 3.3V -AUX I 3.3V/5V -AUX I 3.3V/5V -AUX I I/O 3.3V/5V -AUX O 3.3V -M O 3.3V -M Signal Description AC97 Bit Clock: This signal is a 12.288MHz serial data clock, which is generated by primary Codec. AC97 Reset: Hardware reset signal for external Codecs. AC97 Serial Data Input : Serial data input from primary Codec. AC97 Serial Data Input: Serial data input from secondary Codec. When Modem Codec is used, this pin dedicate to Modem Serial data input. AC97 Serial Data Input: Serial data input from third and forth Audio Codec. AC97 Serial Data Output: Serial data output to Codecs. AC97 Synchronization: This is a 48KHz signal, which is used to synchronize the Codecs

LDRQ# LDRQ1# / GPIO1 LFRAME#

AC_RESET# AC_SDIN0 AC_SDIN1

SIRQ

AC_SDIN[3:2]/ GPIO[10:9] AC_SDOUT AC_SYNC

TRC Interface
Name BATOK Pin Attr I 3.3V -RTC Signal Description Battery Power OK: When the internal RTC is enabled, this signal is used to indicate that the power of RTC well is stable. It is also used to reset the logic in RTC well. If the internal RTC is disabled, this pin should be tied low. RTC 32.768 KHz Input: When internal RTC is enabled, this pin provides the 32.768 KHz clock signal from external crystal or oscillator. RTC 32.768 KHz Output: When internal RTC is enabled, this pin should be connected with the other end of the 32.768 KHz crystal or left unconnected if an external oscillator is used. Main Power OK: A high-level input to this signal indicates the power being supplied to the system is in stable operating state. During the period of PWROK being low, PCIRST# will all be asserted until after PWROK goes high for 12 ms.

USB Interface
Name USBCLK48M Pin Attr I 3.3V/5V -M Signal Description USB 48 MHz clock input: This signal provides the fundamental clock for the USB Controller. I/O USB Port 0-5 Overcurrent Detection: 3.3V/5V - AUX OC[0:5]# are used to detect the overcurrent condition of USB Ports 0-5. I/O USB Port [2:0] Differential: 3.3V - AUX These differential pairs are used to transmit Data/Address /Command signals for ports 0-2. (USB controller 1) I/O USB Port [5:3] Differential: 3.3V - AUX These differential pairs are used to transmit Data/Address/ Command signals for ports 3-5. (USB controller 2)

OSC32KHI

I 3.3V-RTC O <3.3V -RTC

OSC32KHO

OC[0:5]#

PWROK

I 3.3V-RTC

UV[2:0]+, UV[2:0]UV[5:3]+, UV[5:3]-

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Power and Ground Signals
Name VSS VSSZ IVDD PVDDZ VDDZ VDDZCMP VSSZCMP ZVSSREF PVDD OVDD VTT IVDD_AUX PVDD_AUX OVDD_AUX MIIAVDD MIIAVSS USBVDD USBVSS RTCVDD RTCVSS Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS IDEAVDD IDEAVSS 0V 0V 1.8V 1.8V 1.8V 1.8V 0V 0V 3.3V 3.3V 1.1V-2.65V 1.8V 3.3V 3.3V 3.3V 0V 3.3V 0V 3.3V 0V 3.3V 0V 3.3V 0V 1.8V 0V Tolerance Power Plane GROUND GROUND MAIN MAIN MAIN MAIN GROUND GROUND MAIN MAIN MAIN AUX AUX AUX AUX GROUND AUX GROUND RTC GROUND MAIN GROUND MAIN GROUND MAIN GROUND Digital Digital Digital Digital Analog Analog Analog Digital Digital Digital Digital Digital Digital Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog GPIO13 GPIO[18:15] GPIO[20:19] Type Attribute

General Purpose I/O


Signal Name GPIO[6:0] GPIO14,[12:7] Pin Attr I/O 3.3V/5V -M I/O 3.3V/5V -AUX O 3.3V/5V - AUX O 3.3V/5V - AUX I/O 3.3V/5V - AUX Signal Description GPIO: Can be a general purpose input or output. GPIO : Can be a general purpose input or output. GPO: Can be a general purpose output. GPO: Can be a general purpose output. GPIO: Can be a general purpose input or output.

Digital

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5.4 SiS301LV / Chrontel CH7019 TV/LVDS Encoder
Pin # 66,101 Type In/Out Symbol H1,H2 Description Horizontal Sync Input / Output When the SYO control bit is low, these pins accept a horizontal sync inputs for use with the input data. The amplitude will be 0 to VDDV. VREF1 is the threshold level for these inputs. These pins must be used as inputs in RGB Bypass mode. When the SYO control bit is high, the TV encoder will output a horizontal sync pulse 64 pixels wide to one of these pins. The output is driven from the DVDD supply. This output is valid only when TV-Out is in operation. Vertical Sync Input / Output When the SYO control bit is low, these pins accept a vertical sync inputs for use with the input data. The amplitude will be 0 to VDDV. VREF1 signal is the threshold level. These pins must be used as inputs in RGB Bypass mode. When the SYO control bit is high, the TV encoder will output a vertical sync pulse one line wide to one of these pins. The output is driven from the DVDD supply. This output is valid only when TV-Out is in operation. Data Enable These pins accept a data enable signal which is high when active video data is input to the device, and remains low during all other times. The levels are 0 to VDDV. VREF1 is the threshold level. One of these inputs is used by the LVDS links. The TV-Out function uses H and V sync signals and values in the SAV register as reference to active video. TV Field / Flat Panel Stall Signal These outputs can be programmed to be either a TV Field output from the TV encoder or a Stall output from the flat panel Up-scaler. These outputs are tri-stated upon power up. Serial Port Data Input / Output This pin functions as the bi-directional data pin of the serial port, and uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip. Serial Port Clock Input This pin functions as the clock input of the serial port and uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip. Address Select (Internal Pull-up) This pin determines the device address of the serial port.
Pin # 112 Type In/Out Symbol SDD Description Low-Voltage DDC Serial Data Low-voltage serial data for DDC. It uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip. Low-Voltage DDC Serial Clock Low-voltage serial clock for DDC. It uses VREF2 / 2 as the threshold voltage. VREF2 divide by 2 function is generated on-chip. DDC Serial Data Serial data for DDC. (0V to 5V) . Reference Voltage 2 Used to generate the threshold level for SDD, SDC, SPD and SPC port. This pin should be tied externally to the maximum voltage seen by the ports. (1.5V to 3.3V). DDC Serial Clock Clock for DDC. (0V to 5V) General Purpose Input / Output [5:0] These pins provide general purpose I/O and are controlled via the serial port. (3.3V). Panel Power Enable Enable panel VDD. (3.3V) Back Light Enable Enable Back-Light of LCD Panel. (3.3V) Hot Plug Detect (Internal Pull-down) This input pin determines whether a CRT monitor is connected to the VGA connector. When terminated, the monitor is required to apply a voltage greater than 2.4 volts. Changes on the status of this pin will be relayed to the graphics controller via the HPINT* pin pulling low. Hot Plug Interrupt Output This pin provides an open drain output, which pulls low when a termination change has been detected on the HPD input. LVDS Voltage Swing Control This pin sets the swing level of the LVDS outputs. A 2.4K Ohm resistor should be connected between this pin and LGND ( pin 35) using short and wide traces. Reset * Input (Internal Pull-up) When this pin is low, the device is held in the power on reset condition. When this pin is high, reset is controlled through the serial port.

113

In/Out

SDC

114,116 111

In/Out In

DD1, DD2 VREF2

65,102

In/Out

V1,V2

115,117 123-126 56,57 127 128 121

In/Out In/Out

DC1,DC2 GPIO[5:0]

63,104

In

DE1,DE2

Out Out In

ENAVDD ENABLK HPD

62,105

Out

FLD/STL1 FLD/STL2

107

In/Out

SPD

122

Out

HPINT*

36

In

VSWING

108

In

SPC

58

In

RESET*

106

In

AS

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5.4 SiS301LV / Chrontel CH7019 TV/LVDS Encoder
Pin # 2 Type Symbol Analog LPLLCAP Description LVDS PLL Capacitor This pins allows coupling of any signal to the on-chip loop filter capacitor. Positive LVDS differential Clock2 & Clock1 Positive LVDS differential data[7:4]

Pin # 52

Type Symbol In XI/FIN

5,24 6,25 8,11,14,17 9,12,15,18 21,27,30,33 22,28,31,34 38

Out Out Out Out Out Out Analog

LL2C,LL1C LDC[7:4] LDC[7:4]* LDC[3:0] LDC[3:0]* ISET

LL2C*,LL1C* Negative LVDS differential Clock2 & Clock1 Negative LVDS differential data[7:4] Positive LVDS differential data[3:0] Negative LVDS differential data [3:0] Current Set Resistor Input This pin sets the DAC current. A 140-ohm resistor should be connected between this pin and DAC_GND (pin 39) using short and wide traces. DACB[3:0] DAC Output B Video Digital-to-Analog outputs. DACA[3:0] DAC Output A Video Digital-to-Analog outputs. VOUT V-Sync Output This pin is the output of a voltage translating digital buffer and is driven from V5V. VIN V-Sync Input This pin is the input of a voltage translating digital buffer. Input threshold can be programmed by serial port to equal to VREF2/2 or to DVDD/2. The amplitude will be 0 to VDDV. VREF1 is the threshold level for these inputs. HOUT H-Sync Output This pin is the output of a voltage translating digital buffer and is driven from V5V. HIN H-Sync Input This pin is the input of a voltage translating digital buffer. Input threshold can be programmed by serial port to equal to VREF2/2 or to DVDD/2. C/HSYNC Composite / Horizontal Sync Provides composite sync in TV modes and horizontal sync in bypass RGB mode. This pin is driven by the DVDD supply. BCO/VSYNC Buffered Clock Outputs / Vertical Sync This output pin provides buffered crystal oscillator clock output or VSYNC output in bypass RGB mode. This pin is driven by the DVDD supply.

53

Out

XO

59

Out

P-OUT

40,42,44,46 Out 41,43,45,47 Out 120 Out

61

In

VREF1

110

In

68-73,77-82 In

D1[11:0]

76,74

In

119

Out

XCLK1 XCLK1*

109

In

85-90,94-99 In

D2[11:0]

49

Out

93,91

In

50

Out

XCLK XCLK2*

Description Crystal Input / External Reference Input A parallel resonant 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XO. However, an external CMOS compatible clock can drive the XI/FIN input. Crystal Output A parallel resonance 14.31818MHz crystal (+ 20 ppm) should be attached between this pin and XI / FIN. However, if an external CMOS clock is attached to XI/FIN, XO should be left open. Pixel Clock Output This pin provides a pixel clock signal to the VGA controller which can be used as a reference frequency. The output is selectable between 1X and 2X of the pixel clock frequency. The output driver is driven from the VDDV supply (pin 60). This output has a programmable tri-state. The capacitive loading on this pin should be kept to a minimum. Reference Voltage Input 1 The VREF1 pin inputs a reference voltage of VDDV / 2. The signal is derived externally through a resistor divider and decoupling capacitor, and will be used as a reference level for data, sync and clock inputs. Data1[11] through Data1[0] Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to VDDV. VREF1 is the threshold level. External Clock Inputs These inputs form a differential clock signal input to the device for use with the H1, V1 and D1[11:0] data. If differential clocks are not available, the XCLK1* input should be connected to VREF1. The clock polarity can be selected by the MCP1 control bit. Data2[11] through Data2[0] Inputs These pins accept the 12 data inputs from a digital video port of a graphics controller. The levels are 0 to DVDDV. VREF1 is the threshold level. External Clock Inputs These inputs form a differential clock signal input to the device for use with the H2, V2 and D2[11:0] data. If differential clocks are not available, the XCLK2* input should be connected to VREF1. The clock polarity can be selected by the MCP2 control bit.

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5.4 SiS301LV / Chrontel CH7019 TV/LVDS Encoder
Pin # 118 64,83,84,103 67,75,92,100 60 55 54 51 37 39,48 7,13,19,20,26,32 4,10,16,23,29,35 1 3 Type Power Power Power Power Power Power Power Power Power Power Power Power Power Symbol V5V DVDD DGND VDDV TVPLL_VDD TVPLL_VCC TVPLL_GND DAC_VDD DAC_GND LVDD LGND LPLL_VDD LPLL_GND Description 5V supply for H/VOUT (5V) Digital Supply Voltage (3.3V) Digital Ground I/O Supply Voltage (1.1V to 3.3V) TV PLL Supply Voltage (3.3V) TV PLL Supply Voltage (3.3V) TV PLL Ground DAC Supply Voltage (3.3V) DAC Ground LVDS Supply Voltage (3.3V) LVDS Ground LVDS PLL Supply Voltage (3.3V) LVDS PLL Ground

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5.5 PCI1410GGU PCMCIA Controller
Power Supply
Name GND VCC VCCCB VCCI VCCP I/O Device ground terminals Power supply terminal for core logic (3.3V) Clamp voltage for PC Card interface. Matches card signaling environment, 5 V or 3.3 V. Clamp voltage for interrupt subsystem interface and miscellaneous I/O, 5 V or 3.3 V Clamp voltage for PCI signaling, 5 V or 3.3 V FRAME# I/O Description

PCI Interface Control


Name DEVSEL# I/O I/O Description PCI device select. The PCI1410 asserts DEVSEL# to claim a PCI cycle as the target device. As a PCI initiator on the bus, the PCI1410 monitors DEVSEL# until a target responds. If no target responds before timeout occurs, then the PCI1410 terminates the cycle with an initiator abort. PCI cycle frame. FRAME# is driven by the initiator of a bus cycle. FRAME# is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When FRAME# is deasserted, the PCI bus transaction is in the final data phase. PCI bus grant. GNT# is driven by the PCI bus arbiter to grant the PCI1410 access to the PCI bus after the current data transaction has completed. GNT# may or may not follow a PCI bus request, depending on the PCI bus parking algorithm. Initialization device select. IDSEL selects the PCI1410 during configuration space accesses. IDSEL can be connected to one of the upper 24 PCI address lines on the PCI bus. PCI initiator ready. IRDY# indicates the PCI bus initiators ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK where both IRDY# and TRDY# are asserted. Until IRDY# and TRDY# are both sampled asserted, wait states are inserted. PCI parity error indicator. PERR# is driven by a PCI device to indicate that calculated parity does not match PAR when PERR# is enabled through bit 6 of the command register. PCI bus request. REQ# is asserted by the PCI1410 to request access to the PCI bus as an initiator. PCI system error. SERR# is an output that is pulsed from the PCI1410 when enabled through bit 8 of the command register indicating a system error has occurred. The PCI1410 need not be the target of the PCI cycle to assert this signal. When SERR# is enabled in the command register, this signal also pulses, indicating that an address parity error has occurred on a CardBus interface. PCI cycle stop signal. STOP# is driven by a PCI target to request the initiator to stop the current PCI bus transaction. STOP# is used for target disconnects and is commonly asserted by target devices that do not support burst data transfers. PCI target ready. TRDY# indicates the primary bus targets ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of PCLK when both IRDY# and TRDY# are asserted. Until both IRDY# and TRDY# are asserted, wait states are inserted.

GNT#

PC Card Power Switch


Name VCCD0 VCCD1 VPPD0 VPPD1 I/O O O Description Logic controls to the TPS2211 PC Card power interface switch to control AVCC. Logic controls to the TPS2211 PC Card power interface switch to control AVPP. IDSEL I

IRDY#

I/O

PCI System
Name GRST# I/O I Description Global reset. When the global reset is asserted, the GRST# signal causes the PCI1410 to place all output buffers in a high-impedance state and reset all internal registers. When GRST# is asserted, the device is completely in its default state. For systems that require wake-up from D3, GRST# will normally be asserted only during initial boot. PRST# should be used following initial boot so that PME context is retained when transitioning from D3 to D0. For systems that do not require wake-up from D3, GRST# should be tied to PRST#. When the SUSPEND# mode is enabled, the device is protected from the GRST#, and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. PCI bus clock. PCLK provides timing for all transactions on the PCI bus. All PCI signals are sampled at the rising edge of PCLK. PCI reset. When the PCI bus reset is asserted, PRST# causes the PCI1410 to place all output buffers in a high-impedance state and reset internal registers. When PRST# is asserted, the device is completely nonfunctional. After PRST is deasserted, the PCI1410 is in a default state. When the SUSPEND# mode is enabled, the device is protected from the PRST#, and the internal registers are preserved. All outputs are placed in a high-impedance state, but the contents of the registers are preserved. PERR# I/O

REQ# SERR#

O O

STOP#

I/O

PCLK PRST#

I I

TRDY#

I/O

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5.5 PCI1410GGU PCMCIA Controller
Multifunction and Miscellaneous Pins
Name MFUNC0 I/O I/O Description Multifunction terminal 0. MFUNC0 can be configured as parallel PCI interrupt INTA#, GPI0, GPO0, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. Multifunction terminal 1. MFUNC1 can be configured as GPI1, GPO1, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. Serial data (SDA). When VPPD0 and VPPD1 are high after a PCI reset, the MFUNC1 terminal provides the SDA signaling for the serial bus interface. The two-pin serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset. Multifunction terminal 2. MFUNC2 can be configured as PC/PCI DMA request, GPI2, GPO2, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ. Multifunction terminal 3. MFUNC3 can be configured as a parallel IRQ or the serialized interrupt signal IRQSER. Multifunction terminal 4. MFUNC4 can be configured as PCI LOCK#, GPI3, GPO3, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, RI_OUT#, or a parallel IRQ. Serial clock (SCL). When VPPD0 and VPPD1 are high after a PCI reset, the MFUNC4 terminal provides the SCL signaling for the serial bus interface. The two-pin serial interface loads the subsystem identification and other register defaults from an EEPROM after a PCI reset. Multifunction terminal 5. MFUNC5 can be configured as PC/PCI DMA grant, GPI4, GPO4, socket activity LED output, ZV switching outputs, CardBus audio PWM, GPE#, or a parallel IRQ. Multifunction terminal 6. MFUNC6 can be configured as a PCI CLKRUN# or a parallel IRQ. Ring indicate out and power management event output. Terminal provides an output for ring-indicate or PME# signals. Speaker output. SPKROUT is the output to the host system that can carry SPKR# or CAUDIO through the PCI1410 from the PC Card interface. SPKROUT is driven as the exclusive-OR combination of card SPKR#//CAUDIO inputs. Suspend. SUSPEND# protects the internal registers from clearing when the GRST# or PRST# signal is asserted.

PCI Address and Data


Name AD[31:0] I/O I/O Description PCI address/data bus. These signals make up the multiplexed PCI address and data bus on the primary interface. During the address phase of a primary bus PCI cycle, AD31AD0 contain a 32-bit address or other destination information. During the data phase, AD31AD0 contain data. PCI bus commands and byte enables. These signals are multiplexed on the same PCI terminals. During the address phase of a primary bus PCI cycle, C/BE#3C/BE#0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. C/BE#0 applies to byte 0 (AD7AD0), C/BE#1 applies to byte 1 (AD15AD8), C/BE2 applies to byte 2 (AD23AD16), and C/BE#3 applies to byte 3 (AD31AD24). PCI bus parity. In all PCI bus read and write cycles, the PCI1410 calculates even parity across the AD31AD0 and C/BE#3C/BE#0 buses. As an initiator during PCI cycles, the PCI1410 outputs this parity indicator with a one-PCLK delay. As a target during PCI cycles, the calculated parity is compared to the initiators parity indicator. A compare error results in the assertion of a parity error (PERR#).

MFUNC1

I/O

C/BE#[3:0]

I/O

MFUNC2

I/O

PAR

I/O

MFUNC3 MFUNC4

I/O I/O

16-Bit PC Card Address and Data (Slots A and B)


Name ADDR[25:0] DATA[15:0] I/O O I/O Description PC Card address. 16-bit PC Card address lines. ADDR25 is the most significant bit. PC Card data. 16-bit PC Card data lines. DATA15 is the most significant bit.

MFUNC5

I/O

MFUNC6 RI_OUT#/PME# SPKROUT

I/O O O

SUSPEND#

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5.5 PCI1410GGU PCMCIA Controller
16-Bit PC Card Interface Control (Slots A and B)
Name BVD1 (STSCHG#/RI#) I/O I Description Battery voltage detect 1. BVD1 is generated by 16-bit memory PC Cards that include batteries. BVD1 is used with BVD2 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. Status change. STSCHG# is used to alert the system to a change in the READY, write protect, or battery voltage dead condition of a 16-bit I/O PC Card. Ring indicate. RI is used by 16-bit modem cards to indicate a ring detection. Battery voltage detect 2. BVD2 is generated by 16-bit memory PC Cards that include batteries. BVD2 is used with BVD1 as an indication of the condition of the batteries on a memory PC Card. Both BVD1 and BVD2 are high when the battery is good. When BVD2 is low and BVD1 is high, the battery is weak and should be replaced. When BVD1 is low, the battery is no longer serviceable and the data in the memory PC Card is lost. Speaker. SPKR# is an optional binary audio signal available only when the card and socket have been configured for the 16-bit I/O interface. The audio signals from cards A and B are combined by the PCI1410 and are output on SPKROUT. DMA request. BVD2 can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. The PC Card asserts BVD2 to indicate a request for a DMA operation. Card detect 1 and Card detect 2. CD1# and CD2# are internally connected to ground on the PC Card. When a PC Card is inserted into a socket, CD1# and CD2# are pulled low. Card enable 1 and card enable 2. CE1# and CE2# enable even- and odd-numbered address bytes. CE1# enables even-numbered address bytes, and CE2# enables odd-numbered address bytes. Input acknowledge. INPACK# is asserted by the PC Card when it can respond to an I/O read cycle at the current address. DMA request. INPACK# can be used as the DMA request signal during DMA operations from a 16-bit PC Card that supports DMA. If it is used as a strobe, then the PC Card asserts this signal to indicate a request for a DMA operation. I/O read. IORD# is asserted by the PCI1410 to enable 16-bit I/O PC Card data output during host I/O read cycles. DMA write. IORD# is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1410 asserts IORD# during DMA transfers from the PC Card to host memory. I/O write. IOWR# is driven low by the PCI1410 to strobe write data into 16-bit I/O PC Cards during host I/O write cycles. DMA read. IOWR# is used as the DMA write strobe during DMA operations from a 16-bit PC Card that supports DMA. The PCI1410 asserts IOWR# during transfers from host memory to the PC Card.

Name OE#

READY
(IREQ#)

BVD2 (SPKR#)

REG#

CD1# CD2# CE1# CE2# INPACK#

RESET WAIT# WE#

WP (IOIS16#)

IORD#

IOWR#

VS1# VS2#

I/O Description O Output enable. OE# is driven low by the PCI1410 to enable 16-bit memory PC Card data output during host memory read cycles. DMA terminal count. OE# is used as terminal count (TC) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts OE# to indicate TC for a DMA write operation. I Ready. The ready function is provided by READY when the 16-bit PC Card and the host socket are configured for the memory-only interface. READY is driven low by the 16-bit memory PC Cards to indicate that the memory card circuits are busy processing a previous write command. READY is driven high when the 16-bit memory PC Card is ready to accept a new data transfer command. Interrupt request. IREQ# is asserted by a 16-bit I/O PC Card to indicate to the host that a device on the 16-bit I /O PC Card requires service by the host software. IREQ# is high (deasserted) when no interrupt is requested. O Attribute memory select. REG# remains high for all common memory accesses. When REG# is asserted, access is limited to attribute memory (OE# or WE# active) and to the I/O space (IORD# or IOWR# active). Attribute memory is a separately accessed section of card memory and is generally used to record card capacity and other configuration and attribute information. DMA acknowledge. REG# is used as a DMA acknowledge (DACK#) during DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts REG to indicate a DMA operation. REG# is used in conjunction with the DMA read (IOWR#) or DMA write (IORD#) strobes to transfer data. O PC Card reset. RESET forces a hard reset to a 16-bit PC Card. I Bus cycle wait. WAIT# is driven by a 16-bit PC Card to extend the completion of the memory or I/O cycle in progress. O Write enable. WE# is used to strobe memory write data into 16-bit memory PC Cards. WE# is also used for memory PC Cards that employ programmable memory technologies. DMA terminal count. WE# is used as TC# during DMA operations to a 16-bit PC Card that supports DMA. The PCI1410 asserts WE# to indicate TC# for a DMA read operation. I Write protect. WP applies to 16-bit memory PC Cards. WP reflects the status of the write-protect switch on 16-bit memory PC Cards. For 16-bit I/O cards, WP is used for the 16-bit port (IOIS16#) function. I/O is 16 bits. IOIS16# applies to 16-bit I/O PC Cards. IOIS16# is asserted by the 16-bit PC Card when the address on the bus corresponds to an address to which the 16-bit PC Card responds, and the I/O port that is addressed is capable of 16-bit accesses. DMA request. WP can be used as the DMA request signal during DMA operations to a 16-bit PC Card that supports DMA. If used, then the PC Card asserts WP to indicate a request for a DMA operation. I/O Voltage sense 1 and voltage sense 2. VS1# and VS2#, when used in conjunction with each other, determine the operating voltage of the PC Card.

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5.5 PCI1410GGU PCMCIA Controller
CardBus PC Card Interface System (Slots A and B)
Name CCLK I/O O Description CardBus clock. CCLK provides synchronous timing for all transactions on the CardBus interface. All signals except CRST#, CCLKRUN#, CINT#, CSTSCHG, CAUDIO, CCD2#, CCD1#, CVS2, and CVS1 are sampled on the rising edge of CCLK, and all timing parameters are defined with the rising edge of this signal. CCLK operates at the PCI bus clock frequency, but it can be stopped in the low state or slowed down for power savings. CardBus clock run. CCLKRUN# is used by a CardBus PC Card to request an increase in the CCLK frequency, and by the PCI1410 to indicate that the CCLK frequency is going to be decreased. CardBus reset. CRST# brings CardBus PC Card-specific registers, sequencers, and signals to a known state. When CRST# is asserted, all CardBus PC Card signals are placed in a high-impedance state, and the PCI1410 drives these signals to a valid logic level. Assertion can be asynchronous to CCLK, but deassertion must be synchronous to CCLK.

CardBua PC Card Interface Control (Slots A and B)


Name CAUDIO I/O I Description CardBus audio. CAUDIO is a digital input signal from a PC Card to the system speaker. The PCI1410 supports the binary audio mode and outputs a binary signal from the card to SPKROUT. CardBus lock. CBLOCK# is used to gain exclusive access to a target. CardBus detect 1 and CardBus detect 2. CCD1# and CCD2# are used in conjunction with CVS1 and CVS2 to identify card insertion and interrogate cards to determine the operating voltage and card type. Card enable 1 and card enable 2. CE1# and CE2# enable even- and odd-numbered address bytes. CE1# enables even-numbered address bytes, and CE2# enables odd-numbered address bytes. CardBus device select. The PCI1410 asserts CDEVSEL# to claim a CardBus cycle as the target device. As a CardBus initiator on the bus, the PCI1410 monitors CDEVSEL# until a target responds. If no target responds before timeout occurs, then the PCI1410 terminates the cycle with an initiator abort. CardBus cycle frame. CFRAME# is driven by the initiator of a CardBus bus cycle. CFRAME# is asserted to indicate that a bus transaction is beginning, and data transfers continue while this signal is asserted. When CFRAME# is deasserted, the CardBus bus transaction is in the final data phase. CardBus bus grant. CGNT# is driven by the PCI1410 to grant a CardBus PC Card access to the CardBus bus after the current data transaction has been completed. CardBus interrupt. CINT# is asserted low by a CardBus PC Card to request interrupt servicing from the host. CardBus initiator ready. CIRDY# indicates the CardBus initiators ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK when both CIRDY# and CTRDY# are asserted. Until CIRDY# and CTRDY# are both sampled asserted, wait states are inserted.

CBLOCK# CCD1# CCD2# CE1# CE2# CDEVSEL#

I/O I

CCLKRUN#

I/O

CRST#

I/O

CardBus PC Card Address and Data (Slots A and B)


Name CAD[31:0] I/O I/O Description CardBus address and data. These signals make up the multiplexed CardBus address and data bus on the CardBus interface. During the address phase of a CardBus cycle, CAD31CAD0 contain a 32-bit address. During the data phase of a CardBus cycle, CAD31CAD0 contain data. CAD31 is the most significant bit. CardBus bus commands and byte enables. CC/BE#3CC/BE#0 are multiplexed on the same CardBus terminals. During the address phase of a CardBus cycle, CC/BE#3CC/BE#0 define the bus command. During the data phase, this 4-bit bus is used as byte enables. The byte enables determine which byte paths of the full 32-bit data bus carry meaningful data. CC/BE#0 applies to byte 0 (CAD7CAD0), CC/BE#1 applies to byte 1 (CAD15CAD8), CC/BE#2 applies to byte 2 (CAD23CAD8), and CC/BE#3 applies to byte 3 (CAD31CAD24). CardBus parity. In all CardBus read and write cycles, the PCI1410 calculates even parity across the CAD and CC/BE# buses. As an initiator during CardBus cycles, the PCI1410 outputs CPAR with a one-CCLK delay. As a target during CardBus cycles, the calculated parity is compared to the initiators parity indicator; a compare error results in a parity error assertion.

CFRAME#

I/O

CGNT#

CC/BE#[3:0]

I/O

CINT# CIRDY#

I I/O

CPAR

I/O

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5.5 PCI1410GGU PCMCIA Controller
CardBua PC Card Interface Control (Slots A and B) Continue
Name CPERR# I/O I/O Description CardBus parity error. CPERR# reports parity errors during CardBus transactions, except during special cycles. It is driven low by a target two clocks following that data when a parity error is detected. CardBus request. CREQ# indicates to the arbiter that the CardBus PC Card desires use of the CardBus bus as an initiator. CardBus system error. CSERR# reports address parity errors and other system errors that could lead to catastrophic results. CSERR# is driven by the card synchronous to CCLK, but deasserted by a weak pullup, and may take several CCLK periods. The PCI1410 can report CSERR# to the system by assertion of SERR# on the PCI interface. CardBus stop. CSTOP# is driven by a CardBus target to request the initiator to stop the current CardBus transaction. CSTOP# is used for target disconnects, and is commonly asserted by target devices that do not support burst data transfers. CardBus status change. CSTSCHG alerts the system to a change in the cards status, and is used as a wake-up mechanism. CardBus target ready. CTRDY# indicates the CardBus targets ability to complete the current data phase of the transaction. A data phase is completed on a rising edge of CCLK, when both CIRDY# and CTRDY# are asserted; until this time, wait states are inserted. CardBus voltage sense 1 and CardBus voltage sense 2. CVS1 and CVS2 are used in conjunction with CCD1# and CCD2# to identify card insertion and interrogate cards to determine the operating voltage and card type.

CREQ# CSERR#

I I

CSTOP#

I/O

CSTSCHG CTRDY#

I I/O

CVS1 CVS2

I/O

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5.6 uPD72872 IEEE1394 Controller
PCI/Cardbus Interface Signals: (52 pins)
Name PAR I/O I/O PIN NO. 44 IOL PCI/Cardbus Volts(V) 5/3.3 Function Block*
Name REQ I/O O PIN NO. 8 IOL PCI/Cardbus Volts(V) 5/3.3 Function Bus_master Request indicates to the bus arbiter that this device wants to become a bus master. Block* Link

Parity is even parity across Link AD0-AD31 and CBE0-CBE3. It is an input when AD0-AD31 is an input; it is an output when AD0-AD31 is an output. PCI Multiplexed Address and Data Link

GNT

5/3.3

I/O 9, 10, 12, 13, PCI/Cardbus 15-18, 23, 24, 26-29, 32, 33, 47-50, 52, 53, 55, 56, 58,59, 62, 63, 65-68 CBE0-CBE3 I 21, 34, 45, 57 AD0-AD31

5/3.3

Link Bus_master Grant indicates to this device that access to the bus has been granted. Initialization Device Select Link is used as chip select for configuration read/write transaction during the phase of device initialization. If Cardbus mode (CARD_ON = 1), this pin should be pulled up to VDD. Device Select when actively Link driven, indicates that the driving device has decoded its address as the target of the current access. PCI Stop when actively driven, indicates that the target is requesting the current bus master to stop the transaction. Link

IDSEL

22

5/3.3

5/3.3

Link Command/Byte Enables are multiplexed Bus Commands & Byte enables. Link Frame is asserted by the initiator to indicate the cycle beginning and is kept asserted during the burst cycle. If Cardbus mode (CARD_ON = 1), this pin should be pulled up to VDD. Target Ready indicates that Link the current data phase of the transaction is ready to be completed.
PME O I/O 3 2 PCI/Cardbus PCI/Cardbus 5/3.3 5/3.3 DEVSEL I/O 39 PCI/Cardbus 5/3.3

FRAME

I/O

35

PCI/Cardbus

5/3.3

STOP

I/O

40

PCI/Cardbus

5/3.3

TRDY

I/O

37

PCI/Cardbus

5/3.3

IRDY

I/O

36

PCI/Cardbus

5/3.3

Initiator Ready indicates Link that the current bus master is ready to complete the current data phase. During a write, its assertion indicates that the initiator is driving valid data onto the data bus. During a read, its assertion indicates that the initiator is ready to accept data from the currently-addressed target.

CLKRUN

PME Output for power Link management enable. PCICLK Running as input, Link to determine the status of PCLK; as output, to request starting or speeding up clock. Interrupt the PCI interrupt Link request A.

INTA

PCI/Cardbus

5/3.3

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5.6 uPD72872 IEEE1394 Controller
PCI/Cardbus Interface Signals: (52 pins) Continue
Name PERR I/O I/O PIN NO. 41 IOL PCI/Cardbus Volts(V) 5/3.3 Function Block* Parity Error is used for Link reporting data parity errors during all PCI transactions, except a Special Cycle. It is an output when AD0-AD31 and PAR are both inputs. It is an input when AD0-AD31 and PAR are both outputs. System Error is used for Link reporting address parity errors, data parity errors during the Special Cycle, or any other system error where the effect can be catastrophic. When reporting address parity errors, it is an output. Reset PCI reset Link

SERR

42

PCI/Cardbus

5/3.3

PRST PCLK

I I

5 6

5/3.3 5/3.3

PCI Clock 33 MHz system Link bus clock. Remark *: If the Link pin is pulled up, it should be connected to L_VDD.

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6. System Block Diagram
U1 Pentium 4 Processor-M Willamette/Northwood Micro-FCPGA2 478 pin
LCD PANEL J509 MINI PCI Socket CRT TV S-VIDEO U504 TV-Encoder SiS301LV/ CH7019 U2 Thermal Sensor ADM1032

U4 IGUI Host/Memory Controller SiS650


Hyperzip Data Bus

200 pin DDR SO-DIMM Socket * 2

PCI BUS

USB

External Microphone Internal Microphone

U6 PCMCIA Controller PCI 1410


HDD CDROM Cover Switch U5 LAN PHY

U14 MuTIOL Media I/O Controller SiS961


LPC

AC Link

U15 Audio Codec

U16 Amplifier

Internal Speaker SPDIF JACK

U505 Power Switch

RJ-45 Jack

J18 M.D.C

RJ-11 Jack

FAN ISA BUS

PCMCIA/ CARDBUS Socket

U18 IEEE 1394 Controller uPD72872

IR Module Print Port

U511 Super I/O PC87393

U509 Micro Controller

Power Button

U10 Flash ROM

H8/F3437

Touch Pad Keyboard

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7. Maintenance Diagnostics
7.1 Introduction
Each time the computer is turned on, the system bios runs a series of internal checks on the hardware. This power-on self test (post) allows the computer to detect problems as early as the power-on stage. Error messages of post can alert you to the problems of your computer. If an error is detected during these tests, you will see an error message displayed on the screen. If the error occurs before the display is initialized,then the screen cannot display the error message. Error codes or system beeps are used to identify a post error that occurs when the screen is not available. The value for the diagnostic port (378H) is written at the beginning of the test. Therefore, if the test failed, the user can determine where the problem occurred by reading the last value written to port 378H by the 378H port debug board plug at PIO PORT.

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7.2 Error Codes
Following is a list of error codes in sequent display on the PIO debug board. Code 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh POST Routine Description Some type of lone reset Turn off FAST A20 for POST Signal power on reset Initialize the chipset Search for ISA Bus VGA adapter Reset counter / Timer 1 User register config through CMOS Sizememory Dispatch to RAM test Check sum the ROM Reset PICs Initialize video adapter(s) Initialize video (6845Regs) Initialize color adapter Initialize monochrome adapter Test 8237A page registers Code 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh POST Routine Description Test keyboard Test keyboard controller Check if CMOS RAM valid Test battery fail & CMOS X-SUM Test the DMA controller Initialize 8237A controller Initialize int vectors RAM quick sizing Protected mode entered safely RAM test completed Protected mode exit successful Setup shadow Going to initialize video Search for monochrome adapter Search for color adapter Signon messages displayed
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7.2 Error Codes
Following is a list of error codes in sequent display on the PIO debug board. Code 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh POST Routine Description Special init of keyboard ctlr Test if keyboard Present Test keyboard Interrupt Test keyboard command byte Test, blank and count all RAM Protected mode entered safely(2) RAM test complete Protected mode exit successful Update output port Setup cache controller Test if 18.2Hz periodic working Test for RTC ticking Initialize the hardware vectors Search and init the mouse Update NUMLOCK status Special init of COMM and LPT ports
119

Code 40h 41h 42h 43h 44h 45h 46h 47h 48h 49h 50h 51h 52h

POST Routine Description Configure the COMM and LPT ports Initialize the floppies Initialize the hard disk Initialize option ROMs OEMs init of power management Update NUMLOCK status Test for coprocessor installed OEM functions before boot Dispatch to operate system boot Jump into bootstrap code ACPI init PM init & Geyserville USB HC init

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7.3 Maintenance Diagnostics
7.3.1 Diagnostic Tools :
LED PIO CONNECTOR * * 8 OR 1 P/N:411904800001 Description: PWA; PWA-378Port Debug BD Note: Order it from MIC/TSSC

7.3.2 Circuit:

PIO Connector

25

14

13

PIN1 : STROBE PIN10: ACK# PIN11: BUSY

PIN 13 : SLCT PIN 16 : INT# PIN 17 : SELIN# PIN 14 : AUTOFD#

LED

PIN12: PTERR PIN{9:2}: PD{7:0}

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8. Trouble Shooting
8.1 No Power 8.2 No Display 8.3 VGA Controller Failure LCD No Display 8.4 External Monitor No Display 8.5 Memory Test Error 8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error 8.7 Hard Driver Test Error 8.8 CD-ROM Driver Test Error 8.9 PIO Port Test Error 8.10 USB Port Test Error 8.11 Audio Failure 8.12 LAN Test Error 8.13 PC Card Socket Failure 8.14 IEEE 1394 Failure
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8.1 No Power
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
No power

Is the notebook connected to power (either AC adaptor or battery)?

No

Connect AC adaptor or battery.

Check following parts and signals: Parts: Board-level Troubleshooting


Replace the faulty AC adaptor or Battery. Where from power source problem (first use AC to power it)? AC
J2 PF501 PL508 PL501 JS501 PU502 PD502 PD514 PD505 PD506 PD504

Try another known good battery or AC adapter.

Signals:
ADINP ALWAYS +DVMAIN +VDD5S

Power OK? No Is the M/B and charger BD connected properly? No Try another known good charger BD.

Yes

Battery Yes

Connect AC adaptor or battery.

Check following parts and signals: Parts: Signals:


PU512 PR551 PQ509 PQ508 RP553 PR552 BATT VMAIN -ADEN BAT_V BAT_T

Power OK?

No

Replace Motherboard

Replace the faulty Charger BD.

Yes

J14 PF502 PL504 PL505 PR564 PU513

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8.1 No Power
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
L32 P25 P15

BATT

MIIAVDD

Main Voltage Map


PD3,PL5,PQ1,PL6,PU9

U512

P16

+1.8V
U523 P16

Charge
PU513

NOTE:
P1 P3

USBVDD
PU10 P23

: Page 1- 3 of D/D board circuit diagram. : Page 6 - 29 of M/B board circuit diagram. : Through by part PF501.

Discharge
P27

J7 PJ2
PD514 PD505 PD506 PU2 PU3 PU4 PU4 PU5 PU6 PL3

1.25V
L543 P29

P6

P29

P2

+PHYVDD
PF501
L544 P29

PF501 PL501 PL508 JS501

+PHYAVDD
P1 JO506 JO507 P1 PU503 P2

JO502 PU502

PL504 PL505

P1

POWER IN

ADINP
P2 PD503

+DVMAIN
P2

+DVMAIN1

+3V_P
P1 JO1 JO2

+3V
P1 PU501

+3VS
P2

To next page

J2

P2

JS4 JS5

P17

PD504

+5V_P

+5V
U3

+5VS
P2 JS6 JS7

+5VS_HDD
P17

Discharge
P2

ALWAYS
U1

USB0VCC5
P3 U505

+5VS_CD
P18

P2

PJ2
JS2 JS3

USB5VCC5
P20 U505 PU4 PU5 PU6 PL3 PU507

VCCA
P18

P27

J7
F504 U506

5V_AMP
P2 JS505 L554

VCCP
P20

P1

JO505

P1

PQ1

+12V_P
P1 PJ1/J4

+12V
P27

+12VS
PL7 PU510 PU7 PU507 P24

AVDDAD
JO501 JO502

Q509 P27

P27

P27 Q8

JO503 JO504

P24

H8_AVREF1
Q511

+5VA
U17

+5VAS
P15 Q14 P15

+D/VMAIN VCC_RTC

VMAIN
PU8 PU509

+1.8V_P
P24 JO503 JO504

+1.8VS
P24

To next page

+5V

+3VA

+2.5V_P
PL501 PL502 PU505 PU506 PU501 PU502 PU508 PU1~PU6

+2.5V_DDR
P26

To next page

+VCC_CORE

123

8575A N/B Maintenance


8.1 No Power
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

Main Voltage Map


P2 P11 P24 R613 P7

L23

+3VS
From last page L14 P6 L519 P9 L19

VDDA48
P11

+2.5V_DDR
From last page R616

DDRVREFA
P7

CPUAVDD
L15 P6 L10

+DVDD
P9

VDDZ
L18 P11 L22

DDRVREFB
P11

PHYAVDD
L507 P6 L7

+VDDV
P9

VDDCPU
L21 P11 L24

CBVDDA
P11

AGPAVDD1
L511 P6 L9

+TVPLL_VCC
P9 L20

VDDAGP
P11 R95

CBVDD
P12

AGPAVDD2
R62 P6 L510

+TVPLL_VDD
P9 L17

VDDPCI
P11

+DDRVREF

AGPVREF
L13 P7 L509

+LVDD0/1
P9 L16

VDDREF
P11 P24 R557 P7

SDAVDD
L516 P7

+LVDD2
L508 P7

VDDSD
L517 P14 From last page

+1.8VS
L518

ZVREF
P7

DDRAVDD
L505 P7

+LVDD3
L512 P9

SZ1XAVDD
L26 P14 L514

VDDZCMP
P7

DCLKAVDD
L506 P7 L513 Q503 F503 L504

+DAV_VDD
P9

SZ4XAVDD
L8 P19 L524

DACAVDD1,2
P14

ECLKAVDD
L515 P7

+LPLL_VDD
P10

+3V_LAN
Q529 20 L38

SVDDZCMP
P14

Z1XAVDD
L12 P7 L520

LCDVCC
P11

+3VS_SPD
R109

IDEAVDD
P14

Z4XAVDD

VDDA

SZVREF

124

8575A N/B Maintenance


8.1 No Power
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
PD504

D/D Board
PL508 120Z/100M

ALWAYS
PD503 JO502

ADINP
8 7 6 5 D

PD514

J2 POWER IN

PF501

PL501 120Z/100M

JS501

3 2 1 G S

PD505

+DVMAIN
PD506 PC518 0.1 PR516 4.7K PC523 1000P

PC502 0.1

PC501 0.1

PD501 RLZ24D

PU502 SI4835DY

PR507 470K

PR508 100K

Step1 : Connect Adaptor to ( D/D BD ) J2 & O/P ALWAYS. Step2 : ALWAYS --> U506 Generate +5VA. Step3 : H8 O/P LEARNING for Charger Circuitry. Step4 : For MOSFET PU502 G=0,D<-->S. Step5 : O/P ADINP& +DVMAIN.
+VDD5S
PC4 0.1

PQ501 2N7002

LEARNING 45

81

P22 U509 Micro

PR509 1M PR3 10 3 VCC

P2 PJ2
OUT 6 I_LIMT 47 PC5 1

P27 J7
R674 2.2K 39

Controller H8/F3437
1

PU1 P2

4,5

RS+/-

MAX4173FEUT-T
R724 100K

-H8_RESET

ALWAYS
F504 8 7 6 3 R618 10K

U506 LP2951-02BM
IN F/B 5VTAP SHUTDN GND

H8_AVREF1
1 D508 RLZ5.6B D516 UDZ5.6B C698 10

Q509 SI2301DS D S

+5VA

Q511 SI2301DS S D

+5V

+5VA

P27

OUT

2 G 2 4 SW_+5VA From H8 Q510 DTC144WK C799 0.01 C699 4.7 R621 100K R725 10K RESET 4 3 VCC MN G

SENSE

-SW_+5VA To H8

SW502

R718 1K

P22 U515

Mother Board

125

8575A N/B Maintenance


8.1 No Power Battery Charge
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
Mother Board
PD3 EC31QS04 PL5 120Z/100M PQ1 SI4835DY 3 2 1 D PC567 0.01 PC15 100 PR4 4.7K PR14 4.7K G S 8 7 6 5 PL6 33UH 5 6

PU9B SI4925DY

PU9A SI4925DY 8 7 2 PR15 100K PD511 RLZ20C

ADINP
PC38 1000P PC39 1000P PC13 0.01 PC14 10

3 4

BATT
To next page

+5VAS
PD4 EC31QS04 PR560 130K 1.25V 3 2 + _ PU514A LMV393M 2N+ 4 8 PR562 100K

PR7 20K
LI_OVP

PR3 100K PQ3 MMBT2222A

PR16 33k

PL501

PD7 BAS32L

PC581 0.1

PR558 14K

PQ4 2N7002

LI_OVP

PR9 487K 6

PR10 13.7k

PR8 976K 4

CHARGING From H8

PQ506 DTC144WK

VADJ_2_P 12.30V 12.40V 0 0 1 1

VADJ_1_P 0 1 0 1

BAT_TYPE 0 0 0 0

NIMH_CELL 0 0 0 0

D/VADJ2 1 2 5 From H8 PR5 1M PQ2B NDC7002N PQ2A NDC7002N 3 PR6 1M

D/VADJ1

From H8

PR544 47K D G S 8,11 PC573 150P PR545 1M PC569 0.1 12 13 5 6 14 PC568 1000P PR540 10K PR542 10K VCC PQ507 2N7002

12.50V 12.60V

P25

C1,C2 2IN+

16 2

2IN+

OUTPUTCTRL CT RT REF 2IN-

PU511 PWM

PR547 249K

CHARGE_I_CTR

1IN-

+5VAS
PR543 6.19K PC575 0.01 PR546 2.49K From H8

VMAIN +5VAS

FEEDBACK

3 4

TL594C

DTC

PR561 4.7K

PC580 0.1

PR556 681K 5 6 8

PR559 100K

1.25V PC575 0.01 PC566 1 PR541 100K PC570 0.1 JS1 PQ510 SCK431LCSK-5 C898 0.1 PR557 100K

+ _

BATT_DEAD 7 To H8 PU514A LMV393M 4

126

8575A N/B Maintenance


8.1 No Power Battery Discharge
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.

Mother Board
PU513 SI4835DY 8 7 6 5 D S PU512 SI4835DY 8 7 6 5 D S G 3 2 1 G 3 2 1

BATT
PC579 1000P PC578 0.01

BATT1

VMAIN

PR553 100K

PR564 301K

PR552 33K PL504 120Z/100M -ADEN PQ508 2N7002 PR551 226K C709 0.1 PQ509 DTC144WK C708 0.1 C731 0.1

+5VA

H8_AVREF1

J14
PF502

P23

PL505 120Z/100M

C728 0.1

1,2

ADINP

+5VA
4,9,59 3 -ADEN 47 36,37

Battery Connector

PC583 0.01

PC584 1000P

+5VAS
BAT_V PR11 4.99K R672 2.2K 2 1 BAT_VOLT

D511 BAV70LT1 38

P22 U509 Micro Controller H8/F3437

BAT_T R671 22

BAT_TEMP C707 68P C737 0.1 C736 0.1 C710 68P X503 16MHZ

42

PC19 0.1

PR12 20K

PR563 100K

PC582 0.1

3 R655 1M 2

127

8575A N/B Maintenance


8.1 No Power Select CPU Model
When the power button is pressed, nothing happens, no fan activity is heard and power indicator is not light up.
VMAIN
Core_In PL502 120Z/100M PL501 120Z/100M H_PWRGD PR572 0 36 From page 7 in M/B circuit PR519 18.2K PC534 1000P PR518 43.2K 29 INTVCC_3 PD504 EC10QS04 TG1 PGOOD BOOST1 35 33 PC529 0.1 SW1 BG1 From U1 CPU VID[1:4] PC536 1000P PR522 22K 18-21 34 31 G S PU1 FDD6676 D G S D D PU501 FDD6676 G S PC516 0.1 PU515 FDD6676 INTVCC 23

PR514 5.1 VIN

+VCC_CORE
PU2 FDD6676 D PU3 FDD6672A D PD515 EC31QS04 PL1 1.2UH PR502 .005

P26
INTVCC_3 VID0_P 17

PU508 CPU_CORE Generator

G S

G S

PD501 EC31QS04

8 RUN/SS 1

PC525 0.22

4,15 16,10 PC541 470P PR511 2.2K PR513 10K INTVCC_3 JO511 JO34 PQ513 2N7002 PQ514 2N7002 DT/MOBO# PQ9 2N7002 PR20 187K 11

LTC3716
TG2 24 26

PD505 EC10QS04 G

PU502 FDD6676 G

PC517 0.1 PU516 FDD6676 S

PL2 1.2UH

PR504 .005

PR581 20K

BOOST2

PR2 10 PU4 FDD6676 D PU5 PD516 FDD6672A EC31QS04 D VCC_SENSE From U1 CPU PD503 EC31QS04 DT/MOBO#

PC538 0.1 SW2 VOSBG2 25 27 G

PU6 FDD6676 D

G S S

G S

VSS_SENSE From U1 CPU PQ10 2N7002 JO36 VID3 PR29 26.7K PQ518 2N7002 PQ519 2N7002 DPRSLPVR From U14 SiS961 PR32 0 PD6 BAS32L PQ520 2N7002 PR27 100K PQ8 2N7002 PQ6 2N7002 PR23 750K PQ7 2N7002 SW6 MOBO/DT# 1 2 3 4 8 7 6 5 PR21 20K

VID1 JO35 PR590 0 PR22 26.7K

VID2

+5VA
CPU Model Select table MOBO/DT# Mobile X Northwood Willamette OFF OFF ON ON OFF ON ON DT/MOBO# OFF W/N# OFF

+5VA

DT/MOBO# X W/N# PR35 1M PR26 2M PR34 2M

PR602 1M

PR602 1M

128

8575A N/B Maintenance


8.2 No Display
There is no display on both LCD and VGA monitor after power on although the LCD and monitor is known-good.
No Display

Monitor or LCD module OK? Yes

No

Replace monitor or LCD.

Board-level Troubleshooting

Make sure that CPU module, DIMM memory are installed Properly. Yes Correct it. Replace Motherboard System BIOS writes error code to port 378H? No 1.Try another known good CPU module, DIMM module and BIOS. 2.Remove all of I/O device (FDD, HDD, CD-ROM.) from motherboard except LCD or monitor. 1. Replace faulty part. 2. Connect the I/O device to the M/B one at a time to find out which part is causing the problem. Yes

Display OK? No

Refer to port 378H error code description section to find out which part is causing the problem.

Check system clock and reset circuit.

Display OK? No

Yes

To be continued Clock and reset checking


129

8575A N/B Maintenance


8.2 No Display
****** System Clock Check ******
+3VS
40 R644 R648 R626 4.7K 33 33 R645 49.9 R649 49.9 HCLK_CPU HCLK_CPU#

+VCC_CORE

+3VS
R673 10K

P4 U1 CPU Pentium 4

R664 10K 33 Q516 MMBT3904L PD#/VTT_PWRGD

39

R678 10K Q517 MMBT3904L

+3VS
9 31 47 2 FS0 R641 R661 R632 R630 R635 R639 22 22 22 33 33 33 R636 49.9 R875 10K 45 R624 4.7K R640 49.9 ZCLK0 AGP_CLK SDRAMCLK REFCLK0 HCLK_SIS650 HCLK_SIS650# FWDSDCLKO To next page D520 CPU_STP#

P6 P7 U4 IGUI Host/Memory Controller SiS650

+3VS
L520 300Z/100M 36 C715 0.1 C719 0.1 C718 1000P 37

P11

44 43

+3VS

U508
+3VS
L17 L19 L20 L23 L21 L18 L16 120Z/100M 120Z/100M 120Z/100M 120Z/100M 120Z/100M 120Z/100M 120Z/100M VDDREF VDDZ VDDPCI VDDA48 VDDAGP VDDCPU VDDSD 1 11 13,19 28 29 42 48

P14 P15 P16


3 FS1 R633 R625 33 33 22 33 33 REFCLK1 REFCLK3 ZCLK1 USBCLK_SB CLK_SBPCI

U14 MuTIOL Media I/O Controller SiS961 P21 U511 Super I/O PC87393 P9 To U504 SiS301LV/Chrontel CH7019
To U6 PCMCIA Controller To J509 MINI PCI Socket To U18 IEEE1394 Controller

Clock Generator ICS952001

10 26 14 FS3

R646 R667 R668

27 15 FS4

R670 R656

22 33

CLK_SIO CLK_LPC33

20 8

C702 10P 7 4 FS2

R83 33

14.318MHZ_TV

R565 0

MOD_XOUT

3 X502 14.318MHz 1 6

17

R660

33

CLK_CARDPCI

C701 10P

P18 P28 P29

23

R756

33

CLK_MINIPCI

21

R755

33

CLK_1394PCI

130

8575A N/B Maintenance


8.2 No Display
****** System Clock Check ******

P12 J505
FWDSDCLKO From previous page 1 R91 0 CLK_DDR0# 8 CLK_INT 2 R90 0 CLK_DDR0

+2.5V_DDR
L22 300Z/100M CBVDDA 10 VDDA 4 R89 0 CLK_DDR1

R88

CLK_DDR1#

C111 0.1

C101 1000P

13

R94

CLK_DDR2

P11 +2.5V_DDR
L24 600Z/100M

14

R93

CLK_DDR2#

CBVDD

3,12,23

VDD[0:2]

FBINT

20

BF_OUT

C99 10

C112 0.1

C150 0.1

C110 0.1

FB_OUTT

19 R99 22

C196 10P

U9
Bit 2 FS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Bit 6 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 4 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 5 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 66.7 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 80.00 80.00 95.00 95.00 66.67 SDRAM (MHz) 66.67 100.00 200.00 133.33 150.00 125.00 160.00 133.33 200.00 166.67 166.67 133.33 133.33 95.00 126.67 66.67 ZCLK (MHz) 66.67 66.67 66.67 66.67 60.00 62.50 66.67 80.00 66.67 62.50 71.43 66.67 66.67 63.33 63.33 50.00 AGP (MHz) 66.67 66.67 66.67 66.67 60.00 62.50 66.67 66.67 66.67 62.50 83.33 66.67 66.67 63.33 63.33 50.00

P12 J506
17 R98 0 CLK_DDR3

Clock Buffer ICS93722

16

R97

CLK8_DDR3#

24

R100

CLK_DDR4

25

R101

CLK_DDR4#

26

R102

CLK_DDR5

27

R102

CLK_DDR5#

131

8575A N/B Maintenance


8.2 No Display
****** Power Good & Reset Circuit Check ******
+5VS +3VS
3

+5VS U502 MIC5248


1,3 IN EN PG 4 5 R517 10K CPU_CORE_EN VCCPVID

U2 MAX809
VCC RESET# 2 PWROK

R894 0

P5
OUT

C514 0.1 R145 100K

C223 0.1

P7

C513 1

P4 +VCC_CORE

+3V
D513 RLS4148 PWROK

U1 P6 P7
R12 301 R512 51

CPU Pentium 4

P24 P26

CPU_CORE_EN

R705 1K

AUXOK

U4 IGUI Host/Memory Controller SiS650

CPURST# CPUPWRGD

PU510
H_PWRGD

D15 RLS4148 D14 RLS4148 H8_PWROK 68

R706 100K

C782 22

PU508 8575A Power Module

-PCIRST

+5VS

R214 10K

J19
IDE_RST# 1

P17
PWR_ON R682 1K H8_PWRON

P22
49 AUXOK

R215 10K R1 Q18 DTC144TKA 5

C732 10P

R679 20K

PWROK

P14 P15

-PCIRST

R1

Q19 DTC144TKA

Primary EIDE Connector

U509 +5VA Micro Controller H8/F3437


4 3 C799 0.01 VCC MN

P17 +3V
R665 10K SIS_PWRBTN#

J12

U14 MuTIOL Media I/O Controller SiS961


AC97_RST#

Secondary EIDE Connector

P9
-PCIRST To I/O devices

P18

P21

P28

P29

SW502

R718 1K

R725 10K

P22

RESET

-H8_RESET

1 SIS_PWRBTN

U504 U6 U511 J509 U18 SiS301LV PCMCIA LPC MINI PCI IEEE 1394 Chrotel/CH7019 Controller Super I/O Socket Controller

U515
R724 100K

91

Q515 DTC144WK

P19
J18 MDC

P20
U15 Audio Codec

132

8575A N/B Maintenance


8.3 VGA Controller Failure LCD No Display
There is no display or picture abnormal on LCD although power-on-self-test is passed.
VGA Controller Failure LCD No Display

1. Confirm LCD panel or monitor is good and check the cable are connected properly. 2. Try another known good monitor or LCD module.

Board-level Troubleshooting

Check if U504, J3 are cold solder? No

Yes

Re-soldering.

Display OK? No

Yes

Replace faulty LCD or monitor.

One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Replace Motherboard Parts:
U4 U504 U509 J3 J7 PJ2 J6 Q503 F503 L504 Q2 R828 R829 R830 L514 L512 L513 L515 SW1 R511

Remove all the I/O device & cable from motherboard except LCD panel or extended monitor.

Signals:
+3VS LCDVCC ENAVDD PID[0:2] TXCLK+ TXCLKTX2CLK+ TX2CLKTXOUT[0:2]+ TXOUT[0:2]TX2OUT[0:2]+ TX2OUT[0:2]BLADJ KH8_ENABKL -LID

Display OK? No

Yes

Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.

133

8575A N/B Maintenance


8.3 VGA Controller Failure LCD No Display
There is no display or picture abnormal on LCD although power-on-self-test is passed.
+3VS
8 7 6 5 D C506 0.1 Q503 NDS9410 3 2 1 G R505 470K S C510 0.1 C509 1000P F503 mircoSMDC110 L504 120Z/100M LCDVCC 1,2

J3
C3 0.1 C2 1000P

+12VS

+3VS
RP1 1K*4 32,34,36

P10

Q2
DTC144TKA

R1

C506 0.1

24

TXCLK+ TXCLKTX2CLK+ TX2CLKTXOUT [0:2]+ TXOUT [0:2]TX2OUT [0:2]+ TX2OUT [0:2]-

8 10 7

P9

U504
ENAVDD 127

25 5

LCD Connector

P7

U4 IGUI Host/Memory Controller SiS650

DISPLAY LCD_ID2 LCD_ID1 LCD_ID0 UNIQAC 0 0 1 HYUNDAI 0 1 0 HANNSTAR 0 1 1 CMO 1 0 0

ENABKL

128

SiS301LV/ Chrontel CH7019

6 33,30,27 34,31,28 17,14,11 18,15,12

9 20,26,25 22,28,27 13,14,19 15,16,21

LCD

PID0 PID1 PID2

R828 R829 R830

0 0 0 1 X

LCD_ID0 LCD_ID1 LCD_ID2

31 33 35

R74 100 5 6 X 8 7

RP40 10K*4

DC Power Board
P27

+5VA
R642 10K

J6
2,3 11 4 1 5,6

J7 PJ2 P2
BLADJ 8

+5V +5VS

L514

L512 L513 L515

P2
Inverter

P22

U509

45 17

BLADJ H8_ENABKL ENABKL

Micro Controller H8/F3437

ENPBLT1 R511 1K SW1

48

-LID C714 2.2

49 Signal -LID HI Normal LOW Suspend

-LID

C512 0.1 Cover Switch

C513 0.1

C522 2.2

Inverter Board

134

8575A N/B Maintenance


8.4 External Monitor No Display
There is no display or picture abnormal on CRT monitor, but it is OK for LCD.

External Monitor No Display

1. Confirm monitor is good and check the cable are connected properly. 2. Try another known good monitor.

Board-level Troubleshooting

Check if U4, J2 are cold solder? No

Yes Re-soldering.

Display OK? No

Yes

Replace faulty monitor. One of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Replace Motherboard Parts:
U4 U14 U508 J2 R1 R566 R546 R547 R548 Q505 Q502 Q501 Q506 FA501 L503 L502 L501

Remove all the I/O device & cable from motherboard except monitor.

Signals:
CRT_IN# REFCLK0 CRT_DDDA CRT_HSYNC CRT_VSYNC CRT_DDCK CRT_RED CRT_GREEN CRT_BLUE

Display OK? No

Yes

Connect the I/O device & cable to the M/B one at a time to find out which part is causing the problem.

135

8575A N/B Maintenance


8.4 External Monitor No Display
There is no display or picture abnormal on CRT monitor, but it is OK for LCD.

+3VS +3VS +3VS


REFCLK0 R2 1K 5 C1 1000P 12

P15
To U14 SiS961

P11
From U508 Clock Gen. R552 2.2K R558 2.2K S G CRT_HSYNC G CRT_VSYNC G CRT_DDCK S D Q506 2N7002 CRT_RED CRT_GREEN CRT_BLUE L503 L502 L501 120Z/100M 120Z/100M 120Z/100M 1X S D Q501 2N7002 S D Q502 2N7002 G D Q505 2N7002 FA501 120OHM/100MHZ

CRT_IN#

R1 1K

J2

P10

R566 100

CRT_DDDA

P7

R546 33 R547 33 R548 100

13

External VGA Connector

14

15

U4

1 2 3 X 6,7,8,10 4 3 2 3 2 4 1 4 3 2 1

IGUI Host/Memory Controller


VVBWN

C600 0.1 C593 0.1 L514 120Z/100M

SiS650
VCOMP DACAVDD1,2

+1.8VS
6 7 5 8 X

RP502 75*4

CP501 22P*4 5 6 7 8

CP502 22P*4
5 6 7 8 X

JL1 JL501

C583 0.1 DACAVSS1,2

C584 1 JL509

C561 10

VRSET

R545 130

136

8575A N/B Maintenance


8.5 Memory Test Error
Extend DDR SDRAM is failure or system hangs up.

Memory Test Error

1.If your system installed with expansion SO-DIMM module then check them for proper installation. 2.Make sure that your SO-DIMM sockets are OK. 3.Then try another known good SO-DIMM modules. Yes

Board-level Troubleshooting

One of the following components or signals on the motherboard may be defective ,Use an oscilloscope to check the signals or replace the parts one at A time and test after each replacement. Parts:
U4 U508 U9 J505 J506 RP8~RP12 RP13~RP15 RP16~RP20 R632 R614 R658 R662 R98 R100 R102 R97 R101 R103 R90 R91 R98 R88 R94 R93

Signals:
+2.5V_DDR +DDRVREF CKE[0:3] DDR_DQM[0:7] DDR_MD[0:63] DDR_BA [0,1] DDR_CS[0:3]# DDR_MA[0:12] DDR_DQS[0:7] DDR_RAS# DDR_CAS# DDR_WE# SDRAMCLK FWDSDCLK SMBDATA SMBCLK CLK_DDR[0:5] CLK_DDR[0:5]#

Test OK? No

Replace the faulty DDR SDRAM module.

If your system host bus clock running at 266MHZ then make sure that SO-DIMM module meet require of PC 266.

Replace Motherboard

Test Ok? No

Yes

Replace the faulty DDR SDRAM module.

137

8575A N/B Maintenance


8.5 Memory Test Error
Extend DDR SDRAM is failure or system hangs up.
+3VS
L516 120Z/100M DDRAVDD

+1.25V

C623 0.01 DDRAVSS

C624 0.1 JL507

C632 10

J505
+2.5V_DDR
RP7 470 RP21~RP33 33*8 SMBDATA SMBCLK CKE 0,1

P12 +2.5V_DDR +DDRREF


DDR SODIMM

CKE [0:3]

P7

DDR_DQM [0:7] DDR_MD [0:63] DDR_BA [0,1], DDR_CS [0:3]# DDR_MA [0:12], DDR_DQS [0:7] DDR_RAS#, DDR_CAS#, DDR_WE#

DQM [0:7] MD [0:63] BA [0,1], CS [0:3]# MA [0:12], DQS [0:7] RAS#, CAS#, WE# R90,R89,R94 R91,R88,R93 0 CS [0,1]#

U4
+2.5V_DDR
RP8~RP12 RP13~RP15 RP16~RP20 10*8 0*8 10*8

+3VS

CLK_DDR [0:2] , CLK_DDR [0:2]#

IGUI Host/Memory Controller SiS650

C689 0.01 DDRVREFA C688 0.01

R613 150

P15
From U14 SiS961 SMBDATA

R836 4.7K

R837 4.7K

J506
P12

R612 150

+2.5V_DDR
SMBCLK

C692 0.01 DDRVREFB C693 0.01 DRAM_SEL R599 4.7K

R616 150 47 R615 150

P11 U508 Clock Gen. ICS952001 P11

R658 33 35 CS [2,3]# 34 R662 33

+2.5V_DDR +DDRVREF
R95 1K

DDR SODIMM

+3VS
R632 22 7

CKE 2,3

SDRAMCLK

U9
22 CLK_DDR [0:5] , CLK_DDR [0:5]# R98,R100,R102 R97,R101,R103 0 CLK_DDR [3:5] , CLK_DDR [3:5]#

FWDSDCLKO R614 22

Clock Buffer ICS93722

R556 1K

2,1,4,5,13,14,17,16,24~27

138

8575A N/B Maintenance


8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error
Error message of keyboard or touch-pad failure is shown or any key does not work.

Keyboard or Touch-Pad Test Error Check U509, J13, J20 for cold solder? No Correct it. Board-level Troubleshooting

Yes

Re-soldering

Is K/B or T/P cable connected to notebook properly? Yes

No One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Parts Signals
L33 L31 SW503 RP48 +5VA H8_AVREF1 +3VS +5V -ROMCS -MCCS KI[0:7] KO[0:15] T_CLK_H8 T_DATA KBD_US/JP# SA2 IRQ1 IRQ12 -IOR -IOW

Try another known good Keyboard or Touch-pad. Replace Motherboard Test Ok? No Yes Replace the faulty Keyboard or Touch-Pad

U511 U11 U509 J13 J20 L521 R146 R690 F1 L29

139

8575A N/B Maintenance


8.6 Keyboard (K/B) Touch-Pad (T/P) Test Error
Error message of keyboard or touch-pad failure is shown or any key does not work.

+5VA

H8_AVREF1
L521 120Z/100M

+3VS
R737 100K SW503 19 KBD_US/JP# X 1 2 4 3 R744 10K

C709 0.1

C731 0.1

C708 0.1

9,59,4 VCC1,2,B

37,36 AVCC AVREF

C728 0.1

J13
KI [0:7] 17~24

P22

P21

P22
KO [0:15] 1~16

+5VA +3VS

U11
Level Shift

Internal Keyboard Connector


R138 10K R125 10K 95

U511
72

R245 4.7K -ROMCS

U509
F1 0.25A

R146 0

-H8_KBCS

J20
KO 0,1 KI 0,5 5,6 7,8

LPC Super I/O PC87393

73

-MCCS

R690 0

14

15 -H8_MCCS

Micro Controller
98

+5V

P21

H8/F3437
93 87 86 83 82 SA2 IRQ1 IRQ12 -IOR -IOW RP48 0 -IOW_H8 93 T_CLK_H8 53 54 96 82 23 T_DATA 18 RP48 0 T_CLK

L29 L33 L31

120Z/100M 120Z/100M 120Z/100M

1 2 3 4

C222 47P

C221 0.1

Touch-pad
C228 47P

140

8575A N/B Maintenance


8.7 Hard Drive Test Error
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk.

Hard Driver Test Error

1. Check if BIOS setup is OK?. 2. Try another working drive and cable.

Board-level Troubleshooting

One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Parts:
U14 J12 R215 Q19 Q18 R214 JS6 JS7 R202 RP42 RP45 R781 R212 R213 R211 R205 R210

Re-boot OK? No

Yes Replace the faulty parts. Signals:


+5VS +5VS_HDD -PCIRST IDE_PIORDY IDE_PDD[0:15] IDE_PDA[0:2] IDE_PDCS3# IDE_PDCS1# IDE_PDIOR# IDE_PDIOW# IDE_PDDACK# IDE_PDDREQ IDE_IRQ14

Check the system driver for proper installation.

Replace Motherboard

Re - Test OK? No

Yes

End

141

8575A N/B Maintenance


8.7 Hard Drive Test Error
Either an error message is shown, or the drive motor spins non-stop, while reading data from or writing data to hard disk.

+5VS +5VS
R214 10K JS5 R215 10K R1 -PCIRST Q18 DTC144TKA IDE_RST# 1 41, 42 C261 0.1 C273 4.7 C258 0.1 JS4

+5VS_HDD

J19

P17

R1

Q19 DTC144TKA

+5VS
R144 4.7K IDE_PIORDY R202 RP42, PR45 10*8 IDE_PDD[0:15] PDD[0:15] 10 PIORDY

R200 470

D19 PG1102W 39

+5VS

P14

Primary EDIE Connector

27

U14 MuTIOL Media I/O Controller SiS961


IDE_PDA[0:2], IDE_PDCS3# RP528

2~18

33*4

PDA[0:2], PDCS3#

33,35,36,38

IDE_PDCS1#

R781

33

PDCS1#

37 25

IDE_PDIOR#

R212

10

PDIOR#

IDE_PDIOW#

R213

22

PDIOW#

23

IDE_PDDACK#

R211

22

PDDACK#

29

IDE_PDDREQ

R205

82

PDDREQ

21

IDE_IRQ14

R210

82

IRQ14

31

142

8575A N/B Maintenance


8.8 CD-ROM Drive Test Error
An error message is shown when reading data from CD-ROM drive.

CD-ROM Driver Test Error

1. Try another known good compact disk. 2. Check install for correctly.

Board-level Troubleshooting

One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Parts:
U14 J12 R215 Q19 Q18 R214 JS6 JS7 R204 RP41 RP44 RP43 R208 R176 R203 R170 R207 R777

Test OK? No

Yes

Replace the faulty parts.

Signals:
+5VS +5VS_CD -PCIRST IDE_SIORDY IDE_SDD[0:15] IDE_SDA[0:2] IDE_SDCS3# IDE_SDCS1# IDE_SDIOR# IDE_SDIOW# IDE_SDDACK# IDE_SDDREQ IDE_IRQ15

Check the CD-ROM driver for proper installation.

Replace Motherboard

Re - Test OK? No

Yes

End

143

8575A N/B Maintenance


8.8 CD-ROM Drive Test Error
An error message is shown when reading data from CD-ROM drive.

+5VS +5VS
R214 10K JS7 R215 10K R1 -PCIRST Q18 DTC144TKA IDE_RST# 5 38~42 C648 4.7 C74 0.1 C643 0.1 JS6

+5VS_CD

J12

P17

R1

Q19 DTC144TKA

+5VS
R73 4.7K IDE_SIORDY R204 RP41, PR44 10*8 IDE_SDD[0:15] SDD[0:15] 10 SIORDY

R743 470

D18 PG1102W 37

+5VS

P14

Secondary EDIE Connector

27

U14 MuTIOL Media I/O Controller SiS961


IDE_SDA[0:2], IDE_SDCS3# RP43

7~21

33*4

SDA[0:2], SDCS3#

31,33,34.36

IDE_SDCS1#

R208

33

SDCS1#

35 24

IDE_SDIOR#

R176

10

SDIOR#

IDE_SDIOW#

R203

22

SDIOW#

25

IDE_SDDACK#

R170

22

SDDACK#

28

IDE_SDDREQ

R207

82

SDDREQ

22

IDE_IRQ15

R777

82

IRQ15

29

144

8575A N/B Maintenance


8.9 USB Test Error
An error occurs when a USB I/O device is installed.

USB Test Error

Check if the USB device is installed properly. (Including charge board.) Board-level Troubleshooting Test OK?
No Yes

Correct it

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Parts: M/B D/D
PJ2 JU3 J5 J7 D504 L524 L509 L516 L518 U1 J8 J4 D3 L520 L522 L504 L508

Signals:
+3V USBCLK_SB -USBOC0_1 USBP0+ USBP0USB0VCC5 USBP1+ USBP1-USBOC3_5 USBP5+ USBP5USB5VCC5 USBP3+ USBP3-

Replace another known good charge board or good USB device. Replace Motherboard Re-test OK?
No Yes

Correct it

U14 J7 R147 R148 R75 R518 R142 R143 R161 R163

145

8575A N/B Maintenance


8.9 USB Test Error - 1
An error occurs when a USB I/O device is installed.
DC Power Board
+3V
L523 120Z/100M USBVDD

USBCLK_SB From U508 clock generator

+3V P27

USB0VCC5 D504 BAW56 -USBOC1 2 3 1 -USBOC0 C534 1000P

L524 120Z/100M

J7 PJ2 P2
R516 10K -USBOC0_1

P16
USBVSS

C744 0.1

C745 1

C743 10

R506 33K

C506 0.1

J5
R518 47K 1

USB_OC0_1# OC0,1# USB_OC3_5# OC3,5# R147 22 R888 0 48 USBP0USBP_0+ USBP_0R886 0 R889 0 32 34 R504 15K R505 15K 50 USBP0+ 1 4

L509 600Z/100M 2 3

P2
3

2 4 GND

U14 MuTIOL Media I/O Controller SiS961

USBP0_P USBP0_N C86 100P C87 22P

USBP0+ USBP0-

R148 22 R75 22

+5V
USB0VCC5 USBP_1+ USBP_13 26 28 C8 1 4 C10 1 -USBOC1 VIN1 VIN0 GND_USB L516 120Z/100M 1

USBP1_P USBP1_N C122 100P C121 22P

USBP1+ USBP1-

P2

VOUT1

U3

VOUT0

R158 22

R887 0

R3 33K

C517 0.1

USBP3_P USBP3_N C83 100P C84 22P

R142 22

USBP3+ USBP3-

R893 0

J7
USBP_3+ USBP_316 USBP1+ 1 USBP1USBP_5+ USBP_51 3 R508 15K R509 15K JO512 GND 4 2 3 C9 1000P 14 L518 600Z/100M 3 R5 47K 1

P2

R143 22 R161 22

R891 0 R892 0

2 4

USBP5_P USBP5_N C126 100P C125 22P

USBP5+ USBP5-

R163 22

R890 0 GND_USB

146

8575A N/B Maintenance


8.9 USB Test Error - 2
An error occurs when a USB I/O device is installed.
DC Power Board
+3V
L523 120Z/100M USBVDD

USBCLK_SB From U508 clock generator

+3V P27

USB5VC5 D3 BAW56 R10 10K -USBOC3 2 3 1 -USBOC5 C11 1000P R8 47K R7 33K

L520 120Z/100M

J7 PJ2 P2
-USBOC3_5

P16
USBVSS

C744 0.1

C745 1

C743 10

C525 0.1

J8
1

USB_OC0_1# OC0,1# USB_OC3_5# OC3,5# R147 22 R888 0 48 USBP5USBP_0+ 32 USBP0_N C86 100P C87 22P R148 22 R75 22 USBP0R886 0 R889 0 USBP_034 R513 15K R514 15K 50 USBP5+ 1 4

L522 600Z/100M 2 3

P3
3

2 4 GND

USBP0_P

USBP0+

U14 MuTIOL Media I/O Controller SiS961

+5V
USB5VCC5 USBP_1+ 26 USBP_128 3 VIN0 GND_USB L504 120Z/100M 1

USBP1_P USBP1_N C122 100P C121 22P

USBP1+ USBP1-

P3

VOUT1

4 C3 1 C509 1

VIN1

U1

VOUT0

R158 22

R887 0

R2 33K -USBOC3

C504 0.1

USBP3_P USBP3_N C83 100P C84 22P

R142 22

USBP3+ USBP3-

R893 0

J4
USBP_3+ USBP_314 16 USBP3+ 1 USBP3USBP_5+ USBP_51 3 R503 15K R502 15K JO501 GND 4 L508 600Z/100M 3 2 3 C1 1000P R4 47K 1

P3

R143 22 R161 22

R891 0 R892 0

2 4

USBP5_P USBP5_N C126 100P C125 22P

USBP5+ USBP5-

R163 22

R890 0 GND_USB

147

8575A N/B Maintenance


8.10 PIO Port Test Error
When a print command is issued, printer prints nothing or garbage.

PIO Port Test Error

1. Check if PIO device is installed properly. (J504) 2. Check CMOS LPT port setting properly.

Board-level Troubleshooting

One of the following parts or signals on the motherboard may be defective, use an oscilloscope to check the signals or replace the parts one at a time and test after each replacement. Parts: M/B
U511 J7 RP501 RP503 RP504 RP505 R501 CP503 CP504 CP505 CP506 C504

Test OK? No Try another known good PIO device. No

Yes

Correct it

Signals: D/D
PJ2 U501 U502 J3 RP1 RP2 R1 RP3 RP4 D1 +5VS P_LPD0 P_LPD1 P_LPD2 P_LPD3 P_LPD4 P_LPD5 P_LPD6 P_LPD7 -P_STB -P_AFD -P_ERR -P_INIT -P_SLIN -P_ACK P_BUSY P_PE P_SLCT

Yes

Replace the faulty parts.

Replace Motherboard

Re - Test OK? No

Yes

End

148

8575A N/B Maintenance


8.10 PIO Port Test Error
When a print command is issued, printer prints nothing or garbage.
+5VS P3

U501
13 14 15 16 17 18 19 20 21 22 23 24

PJ2 P2

PAC128401Q
RP1 0*4 8 7 6 5 1 2 3 4 1 2 3 4 -PP_STB -PP_AFD P_LPD0 -PP_ERR PP_LPD1 -PP_INIT PP_LPD2 -PP_SLIN PP_LPD3 12 11 10 9 8 7 6 5 4 3 2 1

D501
BAS32L

J3
STB# AFD# LPD0 ERR# LPD1 INIT# LPD2 SLIN# LPD3 1 14 2 15 3 16 4 17

Mother Board
RP501 0*4

P27

J7

-P_STB 25 -P_AFD 23 P_LPD0 43 -P_ERR 21

P3

P_LPD [0:3]

DP_LPD [0:3] 41

P_LPD1 -P_INIT

RP2
0*4

8 7 6 5

P21
P_LPD [4:7]

RP503 0*4

19 DP_LPD [4:7] P_LPD2 39 -P_SLIN 17

U511

P_SLCT, -P_STB -P_AFD, -P_ERR

RP504 0*4

P_LPD3 DP_SLCT, -DP_STB -DP_AFD, -DP_ERR 37

Parallel Port Connector

5 18-27

R1 0

LPC Super I/O PC87393

-P_INIT, -P_SLIN -P_ACK, P_BUSY

RP505 0*4

-DP_INIT, -DP_SLIN -DP_ACK, DP_BUSY

P3
RP3
0*4 12 1 2 3 4 1 2 3 4 PP_LPD4 PP_LPD5 PP_LPD6 PP_LPD7 -PP_ACK PP_BUSY PP_PE PP_SLCT 11 10 9 8 7 6 5 4 X 3 2 1

U502
GND_IO2 13 14 15 16 17 18 19 20 21 22 X 23 24 LPD4 LPD5 LPD6 LPD7 ACK# BUSY PE SLCT 6 7 8 9 10 11 12 13

PAC128401Q
35 P_LPD4 P_LPD5 33 P_LPD6 31 P_LPD7 8 7 6 5 8 7 6 5

P_PE

R501 0

DP_PE

VDD[0:3]

+3VS

CP503 22P*4

C504 22P

29 -P_ACK 36 P_BUSY 34 P_PE

CP504 22P*4

CP505 22P*4

CP506 22P*4

32 P_SLCT 27

RP4
0*4

GND_IO2

GND_IO2

149

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8.11 Audio Failure
No sound from speaker after audio driver is installed.

Audio Failure

1. Check if speaker cables are connected properly. 2. Make sure all the drivers are installed properly.

Board-level Troubleshooting

Check the following parts for cold solder or one of the following parts on the motherboard may be defective,use an oscilloscope to check the following signal or replace parts one at a time and test after each replacement. 1.If no sound cause of line out, check the following parts & signals: Parts: Signals:
AOUT_R AOUT_L +3VS 5V_AMP +3VS_SPD SPK_OFF SPDIFOUT

Test OK? No

Yes Correct it.

2. If no sound cause of MIC, check the following parts & signals: Parts:
U14 U15 J21 J28 C272 L531 L532

3. If no sound cause of CD-ROM, check the following parts & signals: Parts:
U14 U15 J12 R187 R185 R186

Signals:
+5VS AVDDAD MIC1

Signals:
CDROM_LEFT CDROM_RIGHT CDROM_COMM

1.Try another known good speaker, CD-ROM. 2. Exchange another known good charger board.

Replace Motherboard

Re-test OK? No

Yes Correct it.

U14 U15 U16 VR1 L529 L28 L530 Q528 Q529 J24

150

8575A N/B Maintenance


8.11 Audio Failure
No sound from speaker after audio driver is installed.
AVDDAD
L532 600Z/100M R728 2.7K DVDD1,2 C801 1 C788 2.2 R739 2.7K C118 47P AGND AGND 3 L531 600Z/100M MIC C798 220P AGND 8 5 20 AC97_SYNC R764 22 10 11 R699 22 6 C271 1 C269 1 R187 6.8K AGND 5 MIC_3 MIC_2 4 2 1 MIC_VREF R727 2.2K 1 2

AUDIO IN
+3VS

J21
Internal MIC

L553 120Z/100M 1,9 C88 10 C116 0.1

+5VS
JS505 L554 120Z/100M

AVDDAD
AGND 25,38 C784 10 AGND C117 0.1 AGND R154 22 C120 0.1 AGND AVDD1,2 21 MIC1 C272 1 AGND AGND

J28

P20
22 MIC2

C264 0.1

L535 600Z/100M CAGND

External MIC

AC97_SDIN

P15

AC97_SDOUT

CDROM_RIGHT

U14 MuTIOL Media I/O Controller SiS961


SB_SPKR R703 10K

U15
18

AC97_RST# AC97_BITCLK

R185 6.8K

P17
CDROM_LEFT 1

J12
CDROM CONN

Audio Codec
SPK_OFF#

19

C270 1

R186 6.8K

CDROM_COMM

To next page

C227 10P 2

ALC201
R150 1M 3 LINE/IN/L 23

R193 100K

R191 100K

R192 100K

R141 0

AGND X3 24.576MHZ

AGND

AGND

AGND

AVDDAD
C771 0.1 C246 10P

C274 0.1

R173 0

LINE/IN/R

24

C260 0.1

R165 0

L34 L35 L40

120Z/100M 120Z/100M 120Z/100M 120Z/100M 120Z/100M 120Z/100M

R697 470K 4

C777 0.1

48 12 PC_BEEP

SPDIFOUT

L545 L546

P18

U6

-CARDSPK

36

AOUT_R

PCI1410GU

R700 10K

U513

To next page
AOUT_L

L547

R698 20K

35

AGND

151

8575A N/B Maintenance


8.11 Audio Failure
No sound from speaker after audio driver is installed.
AUDIO OUT
-DEVICE_DECT C803 2.2 R731 10K R719 20K 0 0 1 1 C804 2.2 VR1_5 L39 600Z/100M 21 20 22 RLINE IN RHP IN 15 SPKROUTL43 600Z/100M AMP_MUTE 11 C286 4.7 4 From last page 1 AOUT_L C287 4.7 2 -DEVICE_DECT VR1 10K 7 6 3 R159 47K MUTE IN L44 600Z/100M 1 2 L45 600Z/100M 2 SPKROUT+ 1 R732 10K R720 10K -DECT_HP/OPT 0 1 0 1 HP OPT No this condition No device

5V_AMP

+3VS
Q529 DTA144WK

+3VS_SPD

J25
R
AMP_MUTE R96 4.7K

Internal Speaker CONN L

AOUT_R

5V_AMP

C201 0.1

P20

3 10

SPKLOUT+ SPKLOUT-

Q10 DTC144TKA SPK_OFF

R1

U16
R168 100K 14 16 SE/BTL# HP/LINE#

J23

Q528 DTC144TKA From last page

R1

-DECT_HP/OPT

5V_AMP
R713 10K -DECT_HP/OPT -DEVICE_DECT

R1

Q523 DTC144TKA

R762 4.7K

Amplifier
+5V
JS3

5V_AMP
C289 100 R710 22 L529 3 R714 22 C280 100 2

J24
LINE OUT

5V_AMP
L27 120Z/100M 7,18

5 4 1 4 3 2 1

TPA0202
LVDD/RVDD C284 0.1 C247 0.1

C245 100

R194 1K

C791 100P

R174 1K

C789 100P L28 600Z/100M

5 4 C805 2.2 R733 10K R721 20K

L534 600Z/100M LED Drive IC

LHP IN LLINE IN CAGND L536 120Z/100M AGND SPDIFOUT From last page

+3VS_SPD
C806 2.2 R734 10K R722 10K

7 8 9 2 3 1 4 L530

VR1_2

L552 120Z/100M

152

8575A N/B Maintenance


8.12 LAN Test Error
An error occurs when a LAN device is installed.

LAN Test Error

1.Check if the driver is installed properly. 2.Check if the notebook connect with the LAN properly.
Board-level Troubleshooting Test OK? No Yes Correct it.

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Parts:
U14 U5 U3 J9 L5 R171 R177 R166 R167 R172 R178 R72 R69 R67 RP6 RP5 X4 L6 L8 R32 L4 R31 R538 R35 R537 X1

Signals:
MIIAVDD +3V_LAN LAN_DATAIO LAN_DCLK LAN_MTXD[0:3] LAN_MTXE LAN_MTXC LAN_COL LAN_CRS LAN_MRXDV LAN_MRXER LAN_MRXC LAN_MRXD[0:3] OSC25MHI OSC25MHO RXIN+ RXINLAN_CT TXD+ TXDPJRX+ PJRXPJTX+ PJTXPJ8 PJ7 PJ5 PJ4

Check if BIOS setup is ok. Replace Motherboard Re-test OK?


No

Yes

Correct it.

153

8575A N/B Maintenance


8.12 LAN Test Error
An error occurs when a LAN device is installed.
+3V
L5 120Z/100M MIIAVDD VDD[0:6] C232 0.01 MIIAVSS C230 0.1 JL522 C754 10 7,8,15,16,25,54,63 37 51 55 18 C57 1 R595 10K R609 R66 R61 R49 0 0 10K 22K C44 0.1 C45 0.1 C48 0.1 C62 0.1 C59 0.1 C64 0.1

+3V_LAN +3V_LAN
L8 120Z/100M

+3V

+3V_LAN
R64 1.5K

VDD_IO0 VDD_IO1 P0AC RESETN

R171 R177

33 33

LAN_DATAIO LAN_DCLK

30 31

P15 P16

C54 0.1 C41 10P R41 56 R46 56 L6 2 1 3 4 C310 0.1 R32 0 2 1

P19
R166 R167 R172 R178 33 33 33 33 LAN_MTXD0 LAN_MTXD1 LAN_MTXD2 LAN_MTXD3 45 46 47 48 14 RXIN+

J9
RD+ RX+ RDC RXRD16 15 10 9 PJRX+ PJRXPJTX+ PJTX6 3 8 7

U14 MuTIOL Media I/O Controller SiS961

LAN_MTXE LAN_MTXC LAN_COL LAN_CRS R72 R69 R67 22 22 22 RP6 22*4

43 44 49 50

U5

13

RXIN-

P19

P19
RJ45 LAN Connector

TX+ TX-

U3
C37 100P L4 2 1 6 4

ISC1893Y
36 39 38

LAN_CT

LAN_MRXDV LAN_MRXER LAN_MRXC

1 2 3 4

8 7 6 5

LF-H80P
TXC 11 7 TD+ TDC RXC TD14

R31 75

R538 75

PJ7

1,2

TXD+

R35 75

R537 75

PJ4

LAN_MRXD0 LAN_MRXD1 LAN_MRXD2 LAN_MRXD3

1 2 3 4

8 7 6 5

RP5 22*4

6 35 34 33 32 52

TXDR30 61.9 R27 61.9

4,5

C577 1000P

L5 120Z/100M 1 3 2 4 X1 25MHZ C68 27P

GND_45 C311 0.1

OSC25MHI OSC25MHO 3 2 4 1

53

R260 R261

0 0 0 0 JS502

C65 27P C306 10P

LAN_GND R262 R263

C305 10P

X4 25MHZ

LAN_GND

GND_45

154

8575A N/B Maintenance


8.13 PC Card Socket Failure
An error occurs when a PC card device is installed.

PC Card Socket Failure

1. Check if the PC CARD device is installed properly. 2. Confirm PC card driver is installed ok.

Board-level Troubleshooting

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Parts: Signals
PCI_AD[0:31] PCI_C/BE# [0:3] PCI_REQ0# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_INTC# -PCIRST# PCI_GNT0# PCI_PAR PCI_PERR# PCI_SERR# CARD_PME# SERIRQ -CARD_RI CLK_CARDPCI -VCCEN0 -VCCEN1 -VPPEN0 -VPPEN1 +3VS VCCA VPPA

Test OK? No

Yes

Correct it
U14 U508 U513 U505 J11 R249 R785 Q20 R789 R793 R219 R220 R218

Try another known good PC card device.

Replace Motherboard

Re-test OK? No

Yes

Change the faulty part then end.

155

8575A N/B Maintenance


8.13 PC Card Socket Failure
An error occurs when a PC card device is installed.

R249 10K

+5VS
SUSPEND#

+3VS
R785 0

+3VS
3,4 -VCCEN0 -VCCEN1 VPPEN0 1 2 15 14 5,6 9

+12VS

VCCA VPPA
17,51 18,52

J11

AUX_VCC PCI_VCC[0:3] CORE_VCC[0:5]

11~13

U505 TPS2211

10

VCCA +3VS
C203 0.1

SKT_VCC0,1 VPPEN1

C684 0.1

C662 0.1

C650 0.1

C661 0.1

P18

P18

R223 10K -CARD_RI To H8

C217 0.1

U513
CAD[0:31]

Q20 DTC144WK CLK_CARDPCI From U508 Clock Generator

PCMCIA Controller
-CCBE[0:3]

CAD9

R219

Card Bus Socket

CAD12

R220

PCI_AD[0:31]

P14 P15
PCI_AD20

R789 100

PCI1410
IDSEL

-CFRAME, -CIRDY, -CTRDY -CDEVSEL, -CSTOP, CPAR -CPERR, -CBLOCK, CVS1,2 -CSERR, -CREQ, -CINT CAUDIO, CSTSCHG, -CCD1,2 R2_D2, R2_D14, R2_A18 -CGNT

U14
PCI_C/BE#[0:3]

MuTIOL Media I/O Controller SiS961

PCI_DEVSEL, PCI_FRAME#, PCI_IRDY#

PCI_TRDY#, PCI_STOP#, PCI_PAR, PCI_PERR#

PCI_SERR#, PCI_REQ0#, CARD_PME#, SERIRQ

-PCIRST, PCI_GNT0# R793 0

PCI_INTB#

CCLK

R218

156

8575A N/B Maintenance


8.14 IEEE 1394 Failure
An error occurs when a IEEE 1394 device is installed.

IEEE1394 Fail

1. Check if the 1394 device is installed properly. 2. Confirm 1394 driver is installed ok. Board-level Troubleshooting Test OK? No Yes Correct it.

Check the following parts for cold solder or one of the following parts on the mother-board may be defective, use an oscilloscope to check the following signal or replace the parts one at a time and test after each replacement. Parts:
U14 U508 U18 U7 J27 L543 L544 R231 R224 R198 R197 R196 R195 R225 X6

Signals
PCI_AD[0:31] PCI_C/BE# [0:3] PCI_REQ1# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_DEVSEL# PCI_STOP# PCI_INTC# -PCIRST# PCI_GNT1# PCI_PAR PCI_PERR# PCI_SERR# 1394_PME# CLK_1394PCI SDATA SCLK TPA+ TPATPB+ TPBTPBIAS1 +3VS +PHYVDD +PHYAVDD

Check if BIOS setup is ok. Replace Motherboard Re-test OK?


No Yes

Correct it.

157

8575A N/B Maintenance


8.14 IEEE 1394 Failure
An error occurs when a IEEE 1394 device is installed.

+3VS +3VS
L543 SDATA SCLK

+PHYVDD
R86 2.7K 116 C857 4.7 C231 0.1 C859 0.1 C233 0.1 117 R87 2.7K R236 0 5 6 7 8 87 R242 0 R225 1M C93 0.1

P29 +3VS
L544

U7 NM24C02N

+PHYAVDD

U18
C861 4.7 C235 0.1 C863 0.1 C239 0.1 C241 0.1 C252 0.1

88

IEEE 1394
CLK_1394PCI From U508 Clock Gen. 6

3 2 4 C300 22P

C299 22P

X6 24.576MHZ

Controller J27 uPD72872


101 100 IDSEL 99 98 TPA+ TPATPB+ TPBR198 R197 R196 R195 0 0 0 0 4 3 2 1

PCI_AD[0:31]

P29

P14 P15
PCI_AD22

R231 100

U14
PCI_C/BE#[0:3]

1394 Socket

MuTIOL Media I/O Controller SiS961

PCI_DEVSEL, PCI_FRAME#, PCI_IRDY# R241 56 96 PCI_SERR#, PCI_REQ1#, 1394_PME#, C303 0.01 R224 0 C304 0.01 C302 270P R239 5.1K TPBIAS1 R243 56 R238 56 R240 56

PCI_TRDY#, PCI_STOP#, PCI_PAR, PCI_PERR#

JS506

GND1,2

-PCIRST, PCI_GNT1#

1394_GND

PCI_INTC#

158

8575A N/B Maintenance


9. Spare Parts List - 1
8575A ID3 14
Part Number
541667170052 346600000186 343671600014 441999900065 442671700003 441503900201 541350390201 344671720019 221671640001 344600000544 342671600007 342671600005 221600020123 221671220002 451671720091 331810006014 346600000059 340671720008 340671720001 340671720004 340671720010 344671720017 344671720002 344671720013 344671720023

8575A ID3 14
Location(S) Part Number
344670500042 523499999054 523467172012 523467120038 227671600001 227671600008 227671600009 345671600018 344670500024 451671720071 340671600020 340671600018 340671720011 340671720007 340671720003 451671750001 344671720018 346671720002 451671720032 242671720002 242671720001 242669900009 441671720031 451671720052 413000020289

Description
AK;19-UN,BOX,8575A AL-FOIL/CONDUCTIVE ADHESIVE;T=0. AL-FOIL;HST-PANEL_15"-XGA,8175 BATT ASSY OPTION;LI-ION,2000mAH BATT ASSY;11.1V/6AH,LI,ID3,MSL,8 BATT ASSY;LI,9CELLS/6AH,8575ID3 BATT KIT;8575ID3/11.1V,6AH,LI BEZEL;BATTERY,ID3,8575 BOX;AK,8175 BOX;PVC,0.5*218*240MM,T/P BUTTON BRACKET;LCD,14",8175 BRACKET;LCD,R,14",8175 CARTON;330*535*373MM,HOUSING CAS CARTON;NON-BRAND,MSL,8170 CD-ROM ME KIT;TEAC,ID3,8575 CON;MODULAR JACK,FM,6P4C,R/A,UK CONDUCTIVE TAPE;15MM,UCTP,PRC COVER ASSY;DIMM,ID3,8575 COVER ASSY;ID3,8575 COVER ASSY;KB,ID3,8575 COVER ASSY;LCD,14",ID3,8575 COVER;BATTERY,ID3,8575 COVER;DUMMY,ID3,8575 COVER;HDD,ID3,8575 COVER;HINGE,ID3,8575

Description
DUMMY CARD;PCMCIA,TETRA DVD COMBO ASSY OPTION;8575,ID3 DVD COMBO ASSY;MATSUSHITA,ID3,85 DVD-COMBO DRIVE;UJDA720,8170 END CAP;14.1",8175 END CAP;BATTERY,AK BOX,8175 END CAP;FDD,AK BOX,8175 GASKET;HEATSINK,K/B_PLATE,8175 GRAIN;PLASTIC,ABS+PC,BLACK,TETRA HDD ME KIT;ID3,8575 HINGE;L,14",8175 HINGE;R,14",8175 HOUSING ASSY;CDROM,ID3,8575 HOUSING ASSY;ID3,8575 HOUSING ASSY;LCD,14",ID3,8575 HOUSING KIT;ID3,8575A HOUSING;BATTERY,ID3,8575 INSULATOR;REAR,SCREW,ID3,8575 LABEL KIT;N-B,8575 ID3 LABEL;AGENCY-GLOBAL,ID3,8575 LABEL;BATT 11.1V/6AH,LI,MSL,ID3, LABEL;BLANK,60*80MM,7170 LCD ASSY;UNIPAC,XGA,14.1",ID3,85 LCD ME KIT;UNIPAC,XGA,14.1",ID3, LCD;UB141X01,TFT,14.1",XGA,UNIPA

Location(S)

159

8575A N/B Maintenance


9. Spare Parts List - 2
8575A ID3 14
Part Number
416267175001 526267175010 561567175001 561567175013 416267175901 461503900201 461671600002 221671650014 221671650004 222668820001 411503900203 411503900201 411503900202 345671720005 565180626001 565167000013 370102610401 370102610405 370102610805 370102010302 421671600006

8575A ID3 15
Location(S) Part Number
541667170052 346600000364 346671600021 441999900065 442671700003 441503900201 541350390201 344671720019 221671640001 344600000544 342671600006 342671600004 221600020123 221671220001 451671720091 346600000177 340671720008 340671720001 340671720004 340671720009 344671720017 344671720002 344671720013 344671720023

Description
LT PF;UNIPAC,XGA,14.1",ID3,8575A LTXNX;8575A/T4XX/XXK/3XX1/L9D3C/ MANUAL KIT;EN,8575A,N-B MANUAL;USER'S,EN,8575A,N-B NB PF OPTION;XGA,14.1",ID3,8575A PACKING KIT;8575ID3,BATT,LI PACKING KIT;N-B,14.1",8175 PARTITION;AK BOX,8175 PARTITION;FDD,AK BOX,8175 PE BAG;ANTI-STATIC,170x270MM,ORC PWA;PWA-8575ID3/BATT GAUGE BD,LI PWA;PWA-8575ID3/BATT PROTECTION PWA;PWA-8575ID3/BATT PROTECTION RUBBER;BTM SCREW,ESD,ID3,8575 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO S/W;CD-ROM,B'S RECORDER GOLD2.0 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8, SPC-SCREW;M2.6L8,K-HD,NIW/NLK SPC-SCREW;M2L3,NIW,K-HD,736 WIRE ASSY;LCD,UNIPAC,14",XGA,817

Description
AK;19-UN,BOX,8575A AL-FOIL/CONDUCTIVE ADHESIVE;T=0. AL-FOIL;CONDUCTIVE,LCD-SAM_XGA,8 BATT ASSY OPTION;LI-ION,2000mAH BATT ASSY;11.1V/6AH,LI,ID3,MSL,8 BATT ASSY;LI,9CELLS/6AH,8575ID3 BATT KIT;8575ID3/11.1V,6AH,LI BEZEL;BATTERY,ID3,8575 BOX;AK,8175 BOX;PVC,0.5*218*240MM,T/P BUTTON BRACKET;LCD,L,15",8175 BRACKET;LCD,R,15",8175 CARTON;330*535*373MM,HOUSING CAS CARTON;MITAC,MSL,8170 CD-ROM ME KIT;TEAC,ID3,8575 CONDUCTIVE TAPE;UCTP,W=30MM,PRC COVER ASSY;DIMM,ID3,8575 COVER ASSY;ID3,8575 COVER ASSY;KB,ID3,8575 COVER ASSY;LCD,15",ID3,8575 COVER;BATTERY,ID3,8575 COVER;DUMMY,ID3,8575 COVER;HDD,ID3,8575 COVER;HINGE,ID3,8575 DUMMY CARD;PCMCIA,TETRA

Location(S)

P/N:526267175010

344670500042

160

8575A N/B Maintenance


9. Spare Parts List - 3
8575A ID3 15
Part Number
523499999054 523467172012 523467120038 227671600002 227671600008 227671600009 345671600018 344670500024 451671720071 340671600019 340671600017 340671720011 340671720007 340671720002 451671750001 344671720018 346671720002 531099990213 531020237355 451671720031 242671720002 242671720001 242669900009 441671720034 451671720053

8575A ID3 15
Location(S) Part Number
413000020265 416267175902 416267175003 526267175011 561567175001 561567175013 242670000005 461503900201 461671600009 221671650014 221671650004 222668820001 411503900203 411503900201 411503900202 345671720005 565180626001 565167000013 370102610405 370102610805 370102010302 225600000029 421671600002

Description
DVD COMBO ASSY OPTION;8575,ID3 DVD COMBO ASSY;MATSUSHITA,ID3,85 DVD-COMBO DRIVE;UJDA720,8170 END CAP;15.1",8175 END CAP;BATTERY,AK BOX,8175 END CAP;FDD,AK BOX,8175 GASKET;HEATSINK,K/B_PLATE,8175 GRAIN;PLASTIC,ABS+PC,BLACK,TETRA HDD ME KIT;ID3,8575 HINGE;L,15",8175 HINGE;R,15",8175 HOUSING ASSY;CDROM,ID3,8575 HOUSING ASSY;ID3,8575 HOUSING ASSY;LCD,15",ID3,8575 HOUSING KIT;ID3,8575A HOUSING;BATTERY,ID3,8575 INSULATOR;REAR,SCREW,ID3,8575 KBD OPTION;87,RU,8575 KBD;87,RU,K000918J1,8175 LABEL KIT;MITAC,8575 ID3 LABEL;AGENCY-GLOBAL,ID3,8575 LABEL;BATT 11.1V/6AH,LI,MSL,ID3, LABEL;BLANK,60*80MM,7170 LCD ASSY;SAMSUNG,XGA,15.1",ID3,8 LCD ME KIT;SAMSUNG,XGA,15.1",ID3

Description
LCD;LT150X3-124,TFT,15",LVDS,XGA LT PF OPTION;XGA,15",ID3,8575A LT PF;SAMSUNG,XGA,15.1",ID3,8575 LTXMX;8575A/T5XX/XXK/3RU1/L9B2C/ MANUAL KIT;EN,8575A,N-B MANUAL;USER'S,EN,8575A,N-B NAMEPLATE;LOGO,MITAC,7521 PACKING KIT;8575ID3,BATT,LI PACKING KIT;MITAC,15",8175 PARTITION;AK BOX,8175 PARTITION;FDD,AK BOX,8175 PE BAG;ANTI-STATIC,170x270MM,ORC PWA;PWA-8575ID3/BATT GAUGE BD,LI PWA;PWA-8575ID3/BATT PROTECTION PWA;PWA-8575ID3/BATT PROTECTION RUBBER;BTM SCREW,ESD,ID3,8575 S/W;CD*1,DVD,WIN-DVD,INTERVIDEO S/W;CD-ROM,B'S RECORDER GOLD2.0 SPC-SCREW;M2.6L4,NIW,K-HD,t=0.8, SPC-SCREW;M2.6L8,K-HD,NIW/NLK SPC-SCREW;M2L3,NIW,K-HD,736 TAPE;ACETUM ADHESIVE,W=20mm,BLK, WIRE ASSY;LCD,SAM,15",XGA,8175

Location(S)

P/N:526267175011

161

8575A N/B Maintenance


9. Spare Parts List - 4
8575A ID4 14
Part Number
541667170038 441999900062 442671700002 441503900001 541350390001 344671600020 342671600007 342671600005 220671600002 221671720004 431671760001 451671600031 346600000059 340671700001 340671600012 340671600029 340671600022 344671600018 344671600010 344671600016 344671600011 344671600043 227671600001 227669900007 345671600018

8575A ID4 14
Location(S) Part Number
451671600051 340671600020 340671600018 340671700002 340671600039 340671730002 451671760001 344671600019 346671700021 531099990215 531020237362 340671700015 451671700032 242671700001 242671700002 441671730003 451671730003 413000020289 416267176001 526267176006 561567175003 561567175013 561567175015 242671730004 416267176901 HINGE;L,14",8175 HINGE;R,14",8175 HOUSING ASSY;8575 HOUSING ASSY;CDROM,8175 HOUSING ASSY;LCD,14",ID4,8575 HOUSING KIT;ID4,8575A HOUSING;BATTERY,8175 INSULATOR;REAR,SCREW,8575 KBD OPTION;87,SP,8575 KBD;87,SP,K000918J1,8175 KEYBOARD COVER;ASSY-B,8575 LABEL KIT;N-B,8575 LABEL;AGENCY-GLOBAL,8575 LABEL;BATT 11.1V/6AH,LI,PANASONI LCD ASSY;UNIPAC,XGA,14.1",ID4,8 LCD ME KIT;UNIPAC,XGA,14.1",ID4 LCD;UB141X01,TFT,14.1",XGA,UNIPA LT PF;UNIPAC,XGA,14.1",ID4,8575A LTXNX;8575A/T4XX/XXX/3SP9/L9S4D/ MANUAL KIT;EU,8575A,N-B MANUAL;USER'S,EN,8575A,N-B MANUAL;USER'S,EU,8575A,N-B NAMEPLATE;NEOBOOK,8575 NB PF OPTION;XGA,14.1",ID4,8575A

Description
AK;05-EU,BAG,8575A BATT ASSY OPTION;LI,9-CELL,8575 BATT ASSY;11.1V/6AH,LI,MSL,8575 BATT ASSY;Li,9CELLS/6AH,8575 BATT KIT;8575/11.1V,6AH,Li BEZEL;BATTERY,8175 BRACKET;LCD,14",8175 BRACKET;LCD,R,14",8175 CARRY BAG;N-B,8175 CARTON;NEOBOOK,8575 CASE KIT;ID4,8575A CD ROM ME KIT;8175 CONDUCTIVE TAPE;15MM,UCTP,PRC COVER ASSY;8575 COVER ASSY;DIMM,8175 COVER ASSY;HDD,8175 COVER ASSY;LCD,14",8175 COVER;BATTERY,8175 COVER;DUMMY,8175 COVER;HDD,8175 COVER;HINGE,8175 DUMMY CARD;PCMCIA,8175 END CAP;14.1",8175 END CAP;IN BAG,7170 GASKET;HEATSINK,K/B_PLATE,8175

Description
HDD ME KIT;8175

Location(S)

162

8575A N/B Maintenance


9. Spare Parts List - 5
8575A ID4 14
Part Number
461503900001 461671700003 221671250002 221671250001 222668820004 411503900003 411503900001 411503900002 345671700034 370102610401 370102610401 370102610801 421671600006

8575A ID4 15
Location(S) Part Number
541667170038 346600000364 346671600021 441999900062 442671700002 441503900001 541350390001 344671600020 342671600006 342671600004 220671600002 221671720004 431671760001 451671600031 346600000177 340671700001 340671600012 340671600029 340671600021 344671600018 344671600010 344671600016 344671600011 344671600043

Description
PACKING KIT;8575,BATT,Li PACKING KIT;CALSA CARTON,N-B,14" PARTITION;CARRY BAG,8170 PARTITION;IN BAG,8170 PE BUBBLE BAG;190X190MM,ANTI-STA PWA;PWA-8575/BATT GAUGE BD,LI PWA;PWA-8575/BATT PROTECTION BD, PWA;PWA-8575/BATT PROTECTION BD, RUBBER;BTM SCREW,ESD,8575 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1, WIRE ASSY;LCD,UNIPAC,14",XGA,817

Description
AK;05-EU,BAG,8575A AL-FOIL/CONDUCTIVE ADHESIVE;T=0. AL-FOIL;CONDUCTIVE,LCD-SAM_XGA,8 BATT ASSY OPTION;LI,9-CELL,8575 BATT ASSY;11.1V/6AH,LI,MSL,8575 BATT ASSY;Li,9CELLS/6AH,8575 BATT KIT;8575/11.1V,6AH,Li BEZEL;BATTERY,8175 BRACKET;LCD,L,15",8175 BRACKET;LCD,R,15",8175 CARRY BAG;N-B,8175 CARTON;NEOBOOK,8575 CASE KIT;ID4,8575A CD ROM ME KIT;8175 CONDUCTIVE TAPE;UCTP,W=30MM,PRC COVER ASSY;8575 COVER ASSY;DIMM,8175 COVER ASSY;HDD,8175 COVER ASSY;LCD,15",8175 COVER;BATTERY,8175 COVER;DUMMY,8175 COVER;HDD,8175 COVER;HINGE,8175 DUMMY CARD;PCMCIA,8175 END CAP;15.1",8175

Location(S)

P/N:526267176006

227671600002

163

8575A N/B Maintenance


9. Spare Parts List - 6
8575A ID4 15
Part Number
227669900007 345671600018 451671600051 340671600019 340671600017 340671700002 340671600039 340671730001 451671760001 344671600019 346671700021 531099990215 531020237362 340671700015 451671700032 242671700001 242671700002 441671730001 451671730001 413000020265 416267176902 416267176003 526267176007 561567175003 561567175013

8575A ID4 15
Location(S) Part Number
561567175015 242671730004 461503900001 461671700002 221671250002 221671250001 222668820004 411503900003 411503900001 411503900002 345671700034 370102610401 370102610801 225600000029 421671600002

Description
END CAP;IN BAG,7170 GASKET;HEATSINK,K/B_PLATE,8175 HDD ME KIT;8175 HINGE;L,15",8175 HINGE;R,15",8175 HOUSING ASSY;8575 HOUSING ASSY;CDROM,8175 HOUSING ASSY;LCD,15",ID4,8575 HOUSING KIT;ID4,8575A HOUSING;BATTERY,8175 INSULATOR;REAR,SCREW,8575 KBD OPTION;87,SP,8575 KBD;87,SP,K000918J1,8175 KEYBOARD COVER;ASSY-B,8575 LABEL KIT;N-B,8575 LABEL;AGENCY-GLOBAL,8575 LABEL;BATT 11.1V/6AH,LI,PANASONI LCD ASSY;SAMSUNG,XGA,15",ID4,85 LCD ME KIT;SAMSUNG,XGA,15",ID4, LCD;LT150X3-124,TFT,15",LVDS,XGA LT PF OPTION;XGA,15",ID4,8575A LT PF;SAMSUNG,XGA,15.1",ID4,8575 LTXNX;8575A/T5XX/XXX/3SP9/L9S4D/ MANUAL KIT;EU,8575A,N-B MANUAL;USER'S,EN,8575A,N-B

Description
MANUAL;USER'S,EU,8575A,N-B NAMEPLATE;NEOBOOK,8575 PACKING KIT;8575,BATT,Li PACKING KIT;CALSA CARTON,N-B,15" PARTITION;CARRY BAG,8170 PARTITION;IN BAG,8170 PE BUBBLE BAG;190X190MM,ANTI-STA PWA;PWA-8575/BATT GAUGE BD,LI PWA;PWA-8575/BATT PROTECTION BD, PWA;PWA-8575/BATT PROTECTION BD, RUBBER;BTM SCREW,ESD,8575 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1, TAPE;ACETUM ADHESIVE,W=20mm,BLK, WIRE ASSY;LCD,SAM,15",XGA,8175

Location(S)

P/N:526267176007

164

8575A N/B Maintenance


9. Spare Parts List - 7
8575A ID5 14
Part Number
541667170040 346600000186 343671600014 441999900062 442671700002 441503900001 541350390001 344671600020 221671640001 342671600007 342671600005 221671220002 431671770001 451671600031 331810006010 346600000059 340671600012 340671600029 340671740006 340671740005 340671740004 344671600018 344671740107 344671600016 344671740106

8575A ID5 14
Location(S) Part Number
344671600043 227671600001 227671600008 227671600009 451671600051 340671600020 340671600018 340671700002 340671600039 340671740002 451671770001 344671600019 346671700021 531099990211 531020237349 451671700032 242671700001 242671700002 242669900009 441671740003 451671740003 413000020289 416267177901 416267177001 526267177015

Description
AK;07-GR,BOX,8575A AL-FOIL/CONDUCTIVE ADHESIVE;T=0. AL-FOIL;HST-PANEL_15"-XGA,8175 BATT ASSY OPTION;LI,9-CELL,8575 BATT ASSY;11.1V/6AH,LI,MSL,8575 BATT ASSY;Li,9CELLS/6AH,8575 BATT KIT;8575/11.1V,6AH,Li BEZEL;BATTERY,8175 BOX;AK,8175 BRACKET;LCD,14",8175 BRACKET;LCD,R,14",8175 CARTON;NON-BRAND,MSL,8170 CASE KIT;ID5,8575A CD ROM ME KIT;8175 CON;MODULAR JACK,FM,6P4C,R/A,GR CONDUCTIVE TAPE;15MM,UCTP,PRC COVER ASSY;DIMM,8175 COVER ASSY;HDD,8175 COVER ASSY;ID5,8575 COVER ASSY;KB,ID5,8575 COVER ASSY;LCD,14",ID5,8575 COVER;BATTERY,8175 COVER;DUMMY,ID5,8575 COVER;HDD,8175 COVER;HINGE,ID5,8575

Description
DUMMY CARD;PCMCIA,8175 END CAP;14.1",8175 END CAP;BATTERY,AK BOX,8175 END CAP;FDD,AK BOX,8175 HDD ME KIT;8175 HINGE;L,14",8175 HINGE;R,14",8175 HOUSING ASSY;8575 HOUSING ASSY;CDROM,8175 HOUSING ASSY;LCD,14",ID5,8575 HOUSING KIT;ID5,8575A HOUSING;BATTERY,8175 INSULATOR;REAR,SCREW,8575 KBD OPTION;87,GR,8575 KBD;87,GR,K000918J1,8175 LABEL KIT;N-B,8575 LABEL;AGENCY-GLOBAL,8575 LABEL;BATT 11.1V/6AH,LI,PANASONI LABEL;BLANK,60*80MM,7170 LCD ASSY;UNIPAC,XGA,14.1",ID5,85 LCD ME KIT;UNIPAC,XGA,14.1",ID5, LCD;UB141X01,TFT,14.1",XGA,UNIPA LT PF OPTION;XGA,14.1",ID5,8575A LT PF;UNIPAC,XGA,14.1",ID5,8575A LTXNX;8575A/T4XX/XXX/3GR4/L9D3E/

Location(S)

165

8575A N/B Maintenance


9. Spare Parts List - 8
8575A ID5 14
Part Number
561567175005 561567175017 461503900001 461671600002 221671650014 221671650004 222668820001 411503900003 411503900001 411503900002 345671700034 370102610401 370102610401 370102610801 421671600006

8575A ID5 15
Location(S) Part Number
541667170040 346600000364 346671600021 441999900062 442671700002 441503900001 541350390001 344671600020 221671640001 342671600006 342671600004 221671220002 431671770001 451671600031 331810006010 346600000177 340671600012 340671600029 340671740006 340671740005 340671740003 344671600018 344671740107 344671600016

Description
MANUAL KIT;GR,8575A,N-B MANUAL;USER'S,GR,8575A,N-B PACKING KIT;8575,BATT,Li PACKING KIT;N-B,14.1",8175 PARTITION;AK BOX,8175 PARTITION;FDD,AK BOX,8175 PE BAG;ANTI-STATIC,170x270MM,ORC PWA;PWA-8575/BATT GAUGE BD,LI PWA;PWA-8575/BATT PROTECTION BD, PWA;PWA-8575/BATT PROTECTION BD, RUBBER;BTM SCREW,ESD,8575 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1, WIRE ASSY;LCD,UNIPAC,14",XGA,817

Description
AK;07-GR,BOX,8575A AL-FOIL/CONDUCTIVE ADHESIVE;T=0. AL-FOIL;CONDUCTIVE,LCD-SAM_XGA,8 BATT ASSY OPTION;LI,9-CELL,8575 BATT ASSY;11.1V/6AH,LI,MSL,8575 BATT ASSY;Li,9CELLS/6AH,8575 BATT KIT;8575/11.1V,6AH,Li BEZEL;BATTERY,8175 BOX;AK,8175 BRACKET;LCD,L,15",8175 BRACKET;LCD,R,15",8175 CARTON;NON-BRAND,MSL,8170 CASE KIT;ID5,8575A CD ROM ME KIT;8175 CON;MODULAR JACK,FM,6P4C,R/A,GR CONDUCTIVE TAPE;UCTP,W=30MM,PRC COVER ASSY;DIMM,8175 COVER ASSY;HDD,8175 COVER ASSY;ID5,8575 COVER ASSY;KB,ID5,8575 COVER ASSY;LCD,15",ID5,8575 COVER;BATTERY,8175 COVER;DUMMY,ID5,8575 COVER;HDD,8175 COVER;HINGE,ID5,8575

Location(S)

P/N:526267177015

344671740106

166

8575A N/B Maintenance


9. Spare Parts List - 9
8575A ID5 15
Part Number
344671600043 227671600002 227671600008 227671600009 451671600051 340671600019 340671600017 340671700002 340671600039 340671740001 451671770001 344671600019 346671700021 531099990211 531020237349 451671700032 242671700001 242671700002 242669900009 441671740001 451671740001 413000020265 416267177902 416267177003 526267177014

8575A ID5 15
Location(S) Part Number
561567175005 561567175017 461503900001 461671600010 221671650014 221671650004 222668820001 411503900003 411503900001 411503900002 345671700034 370102610401 370102610801 225600000029 421671600002

Description
DUMMY CARD;PCMCIA,8175 END CAP;15.1",8175 END CAP;BATTERY,AK BOX,8175 END CAP;FDD,AK BOX,8175 HDD ME KIT;8175 HINGE;L,15",8175 HINGE;R,15",8175 HOUSING ASSY;8575 HOUSING ASSY;CDROM,8175 HOUSING ASSY;LCD 15",ID5,8575 HOUSING KIT;ID5,8575A HOUSING;BATTERY,8175 INSULATOR;REAR,SCREW,8575 KBD OPTION;87,GR,8575 KBD;87,GR,K000918J1,8175 LABEL KIT;N-B,8575 LABEL;AGENCY-GLOBAL,8575 LABEL;BATT 11.1V/6AH,LI,PANASONI LABEL;BLANK,60*80MM,7170 LCD ASSY;SAMSUNG,XGA,15.1",ID5,8 LCD ME KIT;SAMSUNG,XGA,15.1",ID5 LCD;LT150X3-124,TFT,15",LVDS,XGA LT PF OPTION;XGA,15",ID5,8575A LT PF;SAMSUNG,XGA,15.1",ID5,8575 LTXNX;8575A/T5XX/XXX/3GR4/L9D3E/

Description
MANUAL KIT;GR,8575A,N-B MANUAL;USER'S,GR,8575A,N-B PACKING KIT;8575,BATT,Li PACKING KIT;N-B,15",8175 PARTITION;AK BOX,8175 PARTITION;FDD,AK BOX,8175 PE BAG;ANTI-STATIC,170x270MM,ORC PWA;PWA-8575/BATT GAUGE BD,LI PWA;PWA-8575/BATT PROTECTION BD, PWA;PWA-8575/BATT PROTECTION BD, RUBBER;BTM SCREW,ESD,8575 SPC-SCREW;M2.6L4,K-HD,t0.8,NIB/N SPC-SCREW;M2.6L8,NIB,K-HD,t=1.1, TAPE;ACETUM ADHESIVE,W=20mm,BLK, WIRE ASSY;LCD,SAM,15",XGA,8175

Location(S)

P/N:526267177014

167

8575A N/B Maintenance


9. Spare Parts List - 10
8575A-ID3/ID4/ID5 Common Spare Parts
Part Number
441999900205 442671200004 361400003030 361400003005 541667170065 346600000531 346671700016 338536010006 242670800113 340671600010 340671600028 342671600003 421015560001 272072153401 272075103403 272075103702 272075103401 272075103401 272005103401 272005103401 272073223401 272072473401 272072104702 272073104703 272073104701

Description
AC ADPT ASSY OPTION;8575 AC ADPT ASSY;19V/4.74A,DELTA,817 ADHESIVE;ABS+PC PACK,G485,CEMIDA ADHESIVE;HEAT,TRANSFER,HTA-48(W) AK;EN,8575A,UTILITY ONLY AL-FOIL/ADHESIVE;T=0.1,W=220,PRC AL-FOIL;HDD,M/B,8575 BATTERY;LI,3.6V/2.0AH,18650,PANA BFM-WORLD MARK;WINXP,7521N BRACKET ASSY;T/P,8175 BRACKET ASSY;T/P,INSULATOR,8175 BRACKET;HDD,8175 CABLE ASSY;PHONE LINE,6P2C,W/Z C CAP;.015U ,CR,16V,10%,0603,X7R,S CAP;.01U ,50V,10%,0603,X7R,SMT CAP;.01U ,50V,+80-20%,0603,Y5V,S CAP;.01U ,CR,50V ,10%,0603,X7R,S CAP;.01U ,CR,50V ,10%,0603,X7R,S CAP;.01U ,CR,50V,10%,0805,X7R CAP;.01U ,CR,50V,10%,0805,X7R CAP;.022U,CR,25V ,10%,0603,X7R,S CAP;.047U,16V ,10%,0603,X7R,SMT CAP;.1U ,16V,+80-20%,0603,Y5V,S CAP;.1U ,25V,+80-20%,0603,X7R,S CAP;.1U ,25V,+80-20%,0603,Y5V,S

Location(S)

Part Number
272075104701 272075104701 272075104703 272075104703 272072104402 272003104701 272005104404 272072334701 272072474701 272072474701 272002474401 272075102701 627207510241

Description
CAP;.1U ,50V,+80-20%,0603,Y5V,S CAP;.1U ,50V,+80-20%,0603,Y5V,S CAP;.1U ,50V,+80-20%,0603,Y5V,S CAP;.1U ,50V,+80-20%,0603,Y5V,S CAP;.1U ,CR,16V,10%,0603,X7R,SM CAP;.1U ,CR,25V ,+80-20%,0805,Y CAP;.1U,CR,50V,10%,0805,SMT CAP;.33U ,CR,16V ,+80-20%,0603,Y CAP;.47U ,16V,+80-20%,0603,Y5V,S CAP;.47U ,16V,+80-20%,0603,Y5V,S CAP;.47U ,CR,16V ,10%,0805,X7R,S CAP;1000P,50V ,+/-20%,0603,X7R,S CAP;1000P,50V ,10%,0603,X7R,SMT CAP;1000P,CR,3KV,10%,1808,X7R,TU CAP;1000P,CR,50V,10%,0603,X7R,SM CAP;1000P,CR,50V,10%,0603,X7R,SM CAP;100P ,50V ,+ -10%,0603,NPO,S CAP;100P ,50V ,10%,0603,COG,SMT CAP;100P ,50V ,10%,0603,COG,SMT CAP;10P ,50V ,+-10%,0603,NPO,SM CAP;10P ,CR,50V ,5%,0603,NPO,SM CAP;10U ,10V ,20%,1210,X7R,SMT CAP;10U ,10V ,20%,1210,X7R,SMT CAP;10U ,10V,+80-20%,1206,Y5V,S CAP;10U ,16V ,+80-20%,1206,Y5U,

Location(S)
C106,C107,C108,C110,C111 C504,C506,C512,C513,C517

PC542,PC572 C803,C805,PC22,PC23,PC25 PC529,PC538,PC545,PC557

C101,C130,C151,C153,C155 C501,C502,C577 C1,C11,C534,C9,PC13,PC23 PC28,PC29,PC521,PC527,PC PC22 C1,C37,C579,C789,C791 C4,C7 C196,C291,C41,C43,C732 C701,C702 C100,C132,C133 PC31 C10,C12,C14,C15,C16,C18,C C531,PC21

C152,C154,C172,C192 C212,C213,C232,C26,C265,C PC16,PC20,PC27,PC541 PC525,PC551 PC501,PC583 PC519 PC10 C143,C144,C145,C146,C147 PC4,PC502

272030102405 272075102403 272075102403 272075101701 272075101401 272075101401 272075100701 272075100302 272021106501 272021106501 272011106701 272012106701

168

8575A N/B Maintenance


9. Spare Parts List - 11
Part Number
272012106701 272022106701 272023106501 272073151301 272073151301 272431157507 272431157507 272071105701 272071105701 272001105402 272001105402 272002105403 272003105701 272003105701 272002105701 272001225401 272002225701 272012225702 272012225702 272075200302 272075222701 272075221302 272075221302 272431225501 272431227001

Description
CAP;10U ,16V ,+80-20%,1206,Y5U, CAP;10U ,16V,+80-20%,1210,Y5V,S CAP;10U ,25V ,20%,1210,Y5U,SMT CAP;150P ,CR,25V,5% ,0603,NPO,SM CAP;150P ,CR,25V,5% ,0603,NPO,SM CAP;150U ,TPC,6.3V,20%,H1.9,7343 CAP;150U ,TPC,6.3V,20%,H1.9,7343 CAP;1U ,CR,10V ,80-20%,0603,Y5 CAP;1U ,CR,10V ,80-20%,0603,Y5 CAP;1U ,CR,10V,10%,0805,X5R,SM CAP;1U ,CR,10V,10%,0805,X5R,SM CAP;1U ,CR,16V,10%,0805,X7R,SM CAP;1U ,CR,25V ,+80%-20%,0805, CAP;1U ,CR,25V ,+80%-20%,0805, CAP;1U ,CR,16V ,-20+80%,0805,Y5 CAP;2.2U ,CR,10V ,10%,0805,X7R,S CAP;2.2U ,CR,16V ,+80-20%,0805,Y CAP;2.2U ,CR,16V ,+80-20%,1206,Y CAP;2.2U ,CR,16V ,+80-20%,1206,Y CAP;20P ,CR,50V ,5% ,0603,NPO,S CAP;2200P,50V ,+/-20%,0603,X7R,S CAP;220P ,50V ,5% ,0603,NPO,SMT CAP;220P ,50V ,5% ,0603,NPO,SMT CAP;220U ,TT,4V,20%,7243,OS-CON, CAP;220U, 2.5V,TPE, 7343,18MR

Location(S)
C698,PC24,PC27,PC533,PC5 PC1,PC2 PC546,PC577 PC573 PC9 C17,C9,PC524,PC531,PC547 PC12,PC29,PC30 C10,C3,C509,C8 C136,C137,C138,C139,C140 PC5 PC532 PC550 PC580 C521,C546,PC566 C283,C788,C804,C806 C522 C714 C290 C23,PC548,PC562 C519,C520,C549,C550,C798 PC18,PC28 PC20 PC591,PC592,PC6,PC8

Part Number
272075220701 272075220701 272075220301 272021226701 272075271401 272075271401 272075270302 272075209001 272073330701 272001475701 272002475701 272012475701 272012475502 272013475701 272075471401 272075471401 272072471301 272075470701 272431476502 272431476502 272075681401 272030680402 272075680302 221669950008 221669950006

Description
CAP;22P ,50V ,+ -10%,0603,NPO,S CAP;22P ,50V ,+ -10%,0603,NPO,S CAP;22P ,50V ,5% ,0603,COG,SMT CAP;22U ,10V,+80-20%,1210,Y5V,S CAP;270P ,50V,+-10%,0603,X7R,SMT CAP;270P ,50V,+-10%,0603,X7R,SMT CAP;27P ,50V ,5%,0603,COG,SMT CAP;2P ,CR,50V ,+-0.25PF,0603, CAP;33P ,25V ,+/-10%,0603,NPO,S CAP;4.7U ,CR,10V ,+80-20%,0805,Y CAP;4.7U ,CR,16V ,+80-20%,0805,Y CAP;4.7U ,CR,16V ,+80-20%,1206,Y CAP;4.7U ,CR,16V,20%,1206,Y5U,SM CAP;4.7U ,CR,25V ,+80-20%,1206,Y CAP;470P ,50V,10%,0603,X7R,SMT CAP;470P ,50V,10%,0603,X7R,SMT CAP;470P ,CR,16V ,5% ,0603,NPO,P CAP;47P ,50V ,+ -10%,0603,NPO,S CAP;47U ,6.3V,20%,SP-CON,7343,S CAP;47U ,6.3V,20%,SP-CON,7343,S CAP;680P ,50V ,10%,0603,X7R,SMT CAP;68P ,3KV,10%,1808,NPO,SMT,P CAP;68P ,50V ,5% ,0603,NPO,SMT CARD BOARD;FRAME,PALLET,7170 CARD BOARD;TOP,PALLET,7170

Location(S)
C299,C300,C504 C610,C651 C109,C11,C21,C22,C255,C51 C2,C5 C302,C38,C81 C65,C68 C12,C13 C756,C857,C861 C286,C287 C273,C648,C699

PC19 PC541,PC556,PC563 C118,C121,C122,C125,C126 PC11 PC596 C707,C710

169

8575A N/B Maintenance


9. Spare Parts List - 12
Part Number
221671620001 431671750001 335152000044 313000020360 273000111002 273000111002 331000008038 291000001001 331000007015 331720015006 331720025005 291000153006 291000142404 291000150804 291000144004 331040020004 331030044013 331040050013 291000011024 331040020005 291000021101 291000011209 291000024409 331040050012 291000020202

Description
CARTION;BATTERY,20IN1 CASE KIT;ID3,8575A CFM-BAT;FUSE THERMAL 98'C CHOKE COIL;1.25uH,+30-0%,4.5Ts,D CHOKE COIL;120OHM/100MHZ,20%,321 CHOKE COIL;120OHM/100MHZ,20%,321 CON;BAT,8P,2.5MM,SUYIN CON;BATTERY,10P,FM,2MM,R/A,SMT CON;BATTERY,FM,7P,R/A,8175,PRC CON;D,FM,15P,2.29,R/A,3ROW CON;D,FM,25P,2.775,R/A CON;FPC/FFC,15P*2,.8MM,BD/BD,ST, CON;FPC/FFC,24P,1MM,H8.2,ST,ACES CON;FPC/FFC,8P,1MM,R/A,2CONTAC,E CON;HDR,20P*2,1.0MM,H=4.6,ST,SMT CON;HDR,FM,10P*2,2.54MM,R/A,H8,4 CON;HDR,FM,22*2,2MM,ST,C16805 CON;HDR,FM,25P*2,1.27X1.27MM,D/R CON;HDR,FM,5P*2,1.27MM,ST,H4.5,S CON;HDR,MA,10P*2,2.54MM,R/A,H8.4 CON;HDR,MA,11P*1,1.25,R/A,DF13-1 CON;HDR,MA,12P*1,1.25,ST,SMT CON;HDR,MA,22P*2,2MM,R/A,SMT,ALL CON;HDR,MA,25P*2,1.27X1.27MM,D/R CON;HDR,MA,2P*1,1.25,R/A,SMT,HIR

Location(S)

Part Number
291000020204 331040050010 291000011030

Description
CON;HDR,MA,2P*1,3.5MM,R/A,SMT,SM CON;HDR,MA,50P,0.8MM,R/A,H1.1 CON;HDR,MA,5P*2,1.27MM,ST,H17,85 CON;HDR,SHROUD,MA,3P,1.25MM,R/A, CON;IC CARD PART;68P,0.635,H5,SM CON;IEEE1394,MA,4P,.8MM,R/A,LINK CON;MINI DIN,4P,R/A,W/GROND,C108 CON;PHONE JACK,2P,H=8.4,R/A,SMT CON;PHONE JACK,8P,H=12.59,R/A,RJ CON;POF MINI JACK,10P,W/SPDIF,2F CON;POWER JACK,2P,20VDC,5A,DIP CON;STEREO JACK,5P,R/A,28MF60-07 CON;USB,MA,R/A,4P*1,2551A-04G5TCON;WFR,MA,2P,1.25,ST,SMT/MB CON;WFR,MA,3P,1.25,ST,SMT/MB CON;WFR,MA,4P,1.25MM,ST,SMT CON;WFR,MA,8P*1,1.25MM,ST,SMT CONDUCTIVE TAPE;10MM,UCTP,PRC CONDUCTIVE TAPE;25MM,UCTP,PRC CONDUCTIVE TAPE;5MM,UCTP/8269H,P CONDUCTIVE TAPE;U-TEK/UCTP,W=10M CONDUCTIVE TAPE;U-TEK/UCTP,W=20M CONTACT PLATE;W5L135T0.13,8170LI CONTACT PLATE;W5L24T0.13,7170LI, CONTACT PLATE;W5L45T0.13,7170LI,

Location(S)
J12 J6 J503 J11 J27 J1 J1 J9 J24 J2 J28 J4,J5,J7,J8 J21,J23,J25,J5 J8 J502 J20

PL1,PL2 L1,L4,L529,L530,L6 L508,L509,L518,L522 J14

291000020303 291000256823 331000004018 331870004017 291000810205 291000810808

J2 J3 J18 J13 J501 J3 J4 J7 J501 PJ1 J6 J19 PJ2 J508

331840010005 331910002006 331840005013 331000004029 291000410201 291000410301 291000410401 291000410801 346600000040 346600000060 346600000039 225600000290 225600000292 342503400302 342503400005 342503400004

170

8575A N/B Maintenance


9. Spare Parts List - 13
Part Number
342503400006 342503400303 342503400301 342503400002 342503400003 313000150093 272625220401 346600000142 331660020004 331660020005 288100032013 288100032013 288100054001 288100701002 288100099001 288100099001 288100099001 288100056003 288100056003 288100084002 288101004024 288101004024 288100112003 288100112003 288103104001

Description
CONTACT PLATE;W5L45T0.13,7170LI, CONTACT PLATE;W5L75T0.13,8170LI, CONTACT PLATE;W5L92T0.15,8170LI, CONTACT PLATE;W5L9T0.13,7170LI,P CONTACT PLATE;W7L7T0.13,7170LI,P CORE;LAN CORE,230OHM/100MHZ,LF-1 CP;22P*4 ,8P,50V ,10%,1206,NPO,S DIALAMY;T=0.1,W=113,WHITE,PRC DIMM SOCKET;DDR SODIMM 200P, CA0 DIMM SOCKET;DDR SODIMM 200P, CA0 DIODE;BAS32L,VRRM75V,MELF,SOD-80 DIODE;BAS32L,VRRM75V,MELF,SOD-80 DIODE;BAT54,30V,200mA,SOT-23 DIODE;BAV70LT1,70V,225MW,SOT-23 DIODE;BAV99,70V,450MA,SOT-23 DIODE;BAV99,70V,450MA,SOT-23 DIODE;BAV99,70V,450MA,SOT-23 DIODE;BAW56,70V,215mA,SOT-23 DIODE;BAW56,70V,215mA,SOT-23 DIODE;BZX84C5V6,5.2~6V,350mA,SOT DIODE;EC10QS04,RECT,40V,1A,CHIP, DIODE;EC10QS04,RECT,40V,1A,CHIP, DIODE;EC11FS2-TE12L,SCHOTTKY,200 DIODE;EC11FS2-TE12L,SCHOTTKY,200 DIODE;EC31QS04-TE12L,40V,3A,SMT

Location(S)

Part Number
288103104001 288104148001 288100020001 288100024002 288100056001 288100056005

Description
DIODE;EC31QS04-TE12L,40V,3A,SMT DIODE;RLS4148,200MA,500MW,MELF,S DIODE;RLZ20C,ZENER,19.23V,5%,SMT DIODE;RLZ24D,ZENER,23.63V,5%,SMT DIODE;RLZ5.6B,ZENER,5.6V,5%,LL34 DIODE;UDZ5.6B,ZENER,5.6V,UMD2,SM DIODE;UDZS18B,ZENER,18V,SOD-323, EC;100U,16V,M,6.3*5.5,-55+85'C,S EC;100U,25V,RA,M,D6.3*7,SGX,SANY EC;100U,25V,RA,M,D6.3*7,SGX,SANY EC;10U,25V,20%,RA,6.3*6.8,+105! EC;10U,25V,20%,RA,6.3*6.8,+105! EC;330U ,6.3V ,RA,M,6.3*7,+105C EC;47U,25V,20%,D10X10.5,105'C,SY EC;47U,25V,20%,D10X10.5,85!,SYO EC;820U ,4V,+-20%,10X10.5,FPCAP F/W ASSY;KBD CTRL,SCORPIO F/W ASSY;SYS/VGA BIOS,8575A F/W ASSY;SYS/VGA BIOS,SCORPIO FAN ASSY;8170 FERRITE ARRAY;130OHM/100MHZ,3216 FERRITE ARRAY;130OHM/100MHZ,3216 FERRITE CHIP;120OHM/100MHZ,2012, FERRITE CHIP;120OHM/100MHZ,2012, FERRITE CHIP;130OHM/100MHZ,1608,

Location(S)
PD505,PD506,PD514 D11,D14,D15,D16,D17,D513 PD511 PD501 D10,D5,D508 D516 C245,C280,C289 PC15,PC17,PC18 PC25 PC11,PC12,PC14 PC2,PC3 PC1,PC6 PC31,PC32,PC33 PC3,PC5,PC7,PC9 U509 U10 U10 FA501 FA501 L27,L504,L523,L554,PL5,PL L504,L512,L514,L516,L520,L L1,L4,L513,L515

CP501,CP502,CP503,CP504, J505 J506 D501,PD2,PD3,PD515,PD51 PD506,PD507,PD510,PD517 D509,D510 D511 D1,D3,D4,D6 PD5,PD8 D3,D504 D514 PD1,PD2 PD1,PD4 PD503,PD504,PD511 PD504,PD505 PD3,PD4,PD501,PD502,PD5

288100018003 272602107501 312271006358 312271006358 312271005357 312271005357 312273361501 312304705351 312374705351 312278206152 481672400002 481671750001 481672400001 340671200020 273000610019 273000610019 273000150013 273000150013 273000130039

171

8575A N/B Maintenance


9. Spare Parts List - 14
Part Number
273000130039 273000150001 273000150036 273000130038 422665400002 341671200010 341671200010 342671700001 342672400007 288003600001 295000010105 295000010057 295000010116 295000010116 295000010029 295000010114 335152000062 345671700009 345671700033 345671700032 345671700029 345671700011 345671700031 345671600016 345671700019

Description
FERRITE CHIP;130OHM/100MHZ,1608, FERRITE CHIP;220OHM/100MHZ,2012, FERRITE CHIP;32OHM/100MHZ,2012,S FERRITE CHIP;600OHM/100MHZ,1608, FFC ASSY;TOUCH PAD,CASE KIT,VENU FINGER;EMI GROUND SMD FINGER,H=4 FINGER;EMI GROUND SMD FINGER,H=4 FINGER;EMI GROUNDING SMD FINGER FINGER;EMI GROUNDING SMD FINGER FIR;HSDL3600#007,FRONT VIEW,10P, FUSE;1A,NORMAL,1206,SMT FUSE;228R,139C',5A/250V,SMT,PRC FUSE;FAST, 10A, 86VDC, 6125,SMT FUSE;FAST, 10A, 86VDC, 6125,SMT FUSE;FAST,.75A,63V,1206,THIN FIL FUSE;FAST,1.75A,63VDC,1206,SMT,P FUSE;LR4-730,POLY SWITCH,PRC GASKET;BRACKET T/P,8575 GASKET;BTM SHD,ESD,8575 GASKET;HEATSINK,ESD,8575 GASKET;HOUSING,ESD,8575 GASKET;KB PLATE-1,8575 GASKET;LAN,ESD,8575 GASKET;LCD-HINGE,8175 GASKET;MIC,8575

Location(S)
L16,L17,L18,L19,L20,L21,L2 L34,L35,L40,L545,L546,L547 L28,L39,L43,L44,L45,L531,L E501,E502 E511,E518,E519 E1,E10,E2,E4,E5,E7,E8,E9 E501,E502,E503,E507,E520 U2 F1,F501,F503,F504 PF501 PF502 PF501

Part Number
345671700030 345671700004 230000010004 230000010003 340671700006 340671750001 344600000425 344600000842 344600000843 344600000889 344600000577 344600000863 344600000824 291000614793 282574373004 282574186002 282074338402 282574164002 284501032001 284500202003 286308800006 286308801002 286002040001 284508500002 283400000003

Description
GASKET;PHONE JACK,ESD,8575 GASKET;USB,8575 GLUE;9001B,BLACK,PRC GULE;9001A,BLACK,PRC HEATSINK ASSY;N/B,8575 HEATSINK ASSY;P4,CPU,ID3,8575A HOUSING;HIROSE/DF13-4S-1.25C,PRC HOUSING;HRS/DF13-11S-1.25C,PRC HOUSING;HRS/DF13-12S-1.25C,PRC HOUSING;HRS/DF13-8S-1.25C,PRC HOUSING;JAE/F1-S20S,PRC HOUSING;JST//SHDR-40V-S-B,PRC IC CARD CON PART;68P,IC11SA-BD-P IC SOCKET;UPGA479M,479P,MOLEX IC;74AHC373,OCT D-TRAN,TSSOP,20P IC;74AHCT1G86,SINGLE,XOR,SOT23,S IC;74CBTD3384,10 BIT BUS SW,TSOP IC;74VHC164,SIPO REGISTER,TSSOP, IC;ADM1032,TEMPERATURE MTR,SO8 IC;ALC202,AUDIO CODEC,TQFP,48P IC;AME8800AEEV,VOL REG.,SOT23-5, IC;AME8801MEEV,VOL REG.,SOT23-5, IC;BQ2040,GAS GAUGE,SO,16P,SMT IC;CM8500,3A BUS TERMINATOR,PTSS IC;EEPROM,NM24C02N,2K,SO,8P

Location(S)

U1 U8 U513 U11 U517 U2 U15 U17 U512 PU10 U7

172

8575A N/B Maintenance


9. Spare Parts List - 15
Part Number
283400000003 283450083001 283450083001 284583437003 284583437003 286317812001 284501893001 284593722001 284595200101 286300811002 286100393004 286302951015 286303707001 286303707001 286303716001 286104173001 286300809002 286305258001 286301414001 286300965001 284501284001 284587393002 284501410008 286309701001 286381250001

Description
IC;EEPROM,NM24C02N,2K,SO,8P IC;FLASH,256K*8-70,PLCC32,ST39SF IC;FLASH,256K*8-70,PLCC32,ST39SF IC;H8/F3437S,KBD CTRL,TQFP,100P, IC;H8/F3437S,KBD CTRL,TQFP,100P, IC;HA178L12UA,VOLT REGULATOR,SCIC;ICS-1893,LAN-PHY,TQFP,64P,SMT IC;ICS93722,DDR ZERO DELAY CLOCK IC;ICS952001,TIMING CTL HUB FOR IC;IMP811,RESET CIRCUIT,4.38,SOT IC;LMV393,DUAL COMPARTOR,SSOP,8P IC;LP2951ACM,VOLTAGE REGULATOR,S IC;LTC3707,PWM SWITCH REG,SOOP,2 IC;LTC3707,PWM SWITCH REG,SOOP,2 IC;LTC3716,PWM,QSOP,36P IC;MAX4173F,I-SENSE AMP,SOT23,6P IC;MAX809S,RESET CIRCUIT,2.9V,SO IC;MIC 5258-1.2BM5,LV12,LDO REG, IC;MM1414,PROTECTION,TSOP-20A,PR IC;OZ965R,CCFL CTRL,TSSOP16,O2 IC;PAC1284-01Q,TERMIN. NETWK,QSO IC;PC87393F,TQFP,100P IC;PCI1410AGGU,BGA144P IC;RT9701,POWER DISTRI SW,SOT23IC;S-81250,DECECTOR,SOT-89,PRC

Location(S)

Part Number
286300431014 284500301004 284500650002

Description
IC;SC431LCSK-.5,.5%,ADJ REG,SOT2 IC;SIS301LV,TV ENCODER/LVDS,128P IC;SIS650,N.B.,BGA702 IC;SIS961 HM-I/O,S.B.,BGA371 IC;TL594C,PWM CONTROL,SO,16P IC;TPA0202,AUDIO AMP,2W,TSSOP,24 IC;TPS2211,POWER DISTRI SW,SSOP1 IC;UPD72872;IEEE1394;PQFP120,2PO INDUCTOR;10UH,CDRH127,SUMIDA,SMT INDUCTOR;10UH,CDRH127,SUMIDA,SMT INDUCTOR;10UH,CDRH127B,SUMIDA,SM INDUCTOR;10UH,D124C,+/-20%,TOKO, INDUCTOR;3.3uH,3A,CSS054D,SMT INDUCTOR;33uH,CDRH124,SUMIDA,SMT INDUCTOR;4.7UH,10%,2012,30mA,SMT INSULATOR,MDC,8170 INSULATOR/2ADHESIVE;FIBER/W204,T INSULATOR/2ADHESIVE;FIBER/W204,T INSULATOR/2ADHESIVE;FIBER/W204,T INSULATOR/ADHESIVE;FIBER/W204,T= INSULATOR/ADHESIVE;FIBER/W204,T= INSULATOR/ADHESIVE;FIBER/W204,T= INSULATOR;5,BATTERY ASSY,7521Li INSULATOR;AL-FOIL,M/B BOTTOM,857 INSULATOR;BATT ASSY,L125,8175

Location(S)
PQ510 U504 U4 U14 PU511 U16 U505 U18 PL2 PL4 PL3 PL3 PL8 PL6 L2,L3

U509 PU507 U5 U9 U508 U515 PU514 U506 PU4 PU510 PU508 PU1 U12 U502

284500961003 286300594001 286100202001 286302211001 284572872001 273000990012 273000990012 273000990031 273000990054 273000990115 273000990021 273000150106 346671200036 346600000464 346600000481 346600000517 346600000414

U501,U502 U511 U6 U1,U3

346600000463 346600000515 346503100005 346671700001 346503400504

173

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9. Spare Parts List - 16
Part Number
346503400502 346503200006 346503400503 346671700006 346503400301 346503400501 346503200002 346669900004 346671700023 346671750002 346503400203 346503900001 346671600015 346671700022 346671600009 346600000403 346503400303 242600000145 242600000145 242600000145 242600000457 242662300009 242662300009 242662300009 242600000434

Description
INSULATOR;BATT ASSY,L22R9.2,8175 INSULATOR;BATT ASSY,ONE ROUND,GR INSULATOR;BATT ASSY,W7L13,8175 INSULATOR;CD-ROM,M-B,8575 INSULATOR;FOR 3 CELLS,DOUBLE-FA, INSULATOR;FOR 4 CELL,DOUBLE-FACE INSULATOR;FOR 4 CELLS,GRAMPUS INSULATOR;INVERTER,7170 INSULATOR;M/B,ESD,8575 INSULATOR;MINIPCI,ID3,8575A INSULATOR;ONE ROUND,STINGRAY INSULATOR;PCB ASSY,W15L52,8575 INSULATOR;PCMCIA,8175 INSULATOR;PHONE JACK,8575 INSULATOR;T/P,BRACKET,8175 INSULATOR;TWO DIALAMY,T=0.1,W=60 INSULATOR;W13MML52MM,8170Li,PRC LABEL;10*10,BLANK,COMMON LABEL;10*10,BLANK,COMMON LABEL;10*10,BLANK,COMMON LABEL;20*7MM,COMMON,PRC LABEL;25*10MM,3020F LABEL;25*10MM,3020F LABEL;25*10MM,3020F LABEL;25*6MM,COMMON

Location(S)

Part Number
242668300017 242668300017 624200010140 242600000157 242600000364 242600000452 242600000452 242664800013 242600000315 242600000195 294011200069 294011200001 294011200070 421671600051 291000001203 346600000446 346600000465 346600000074 346600000226 346600000574 346600000321 375102030010 375120262008 227671600003 224670830002

Description
LABEL;4*3MM,HI-TE LABEL;4*3MM,HI-TE LABEL;5*20,BLANK,COMMON LABEL;BAR CODE & S/N,13.5*75,COM LABEL;BLANK,6*6MM,HI-TEMP LABEL;BLANK,7MM*7MM,PRC LABEL;BLANK,7MM*7MM,PRC LABEL;CAUTION,INVERT BD,PITCHING LABEL;RED ARROW HEAD,PRC LABEL;SOFTWARE,INSYDE BIOS-M LED;GREEN,19-21VGC/TR8,LED_CL190 LED;GRN,H1.5,0805,PG1102W,SMT LED;RED/GREEN,19-22SRVGC/TR8,LED MICROPHONE ASSY;8175 MINIPCI SOCKET;124P,0.8MM,H=6,SM MYLAR/3M-467;T=0.1,W=46,BLACK,PR MYLAR/ADHESVIE;MYLAR/W204,T=0.1, MYLAR;T=0.1,W=110,BLACK,PRC MYLAR;T=0.1,W=113,BLACK,PRC MYLAR;T=0.1,W=220,BLACK,PRC MYLAR;T=0.2,W=72.4,BLACK,PRC NUT-HEX;M2,2,NIW NUT-HEX;M2.6,NCG PAD;LCD/KB,ANIT-STATIC,8175 PALLET;1250*1080*130,7521N

Location(S)

D18,D19,D20,D21,D22,D23

J509

174

8575A N/B Maintenance


9. Spare Parts List - 17
Part Number
221671650009 221671250005 221671250003 221671650010 412155600047 316671200005 316503400501 316503400502 316671700002 316671700003 316671750001 316503400101 222600020049 222600020310 222667220003 222670000001 222503220001 222671620001 230000000003 273000150033 343671600006 411671200007 411671700007 411671700006 411671700009

Description
PARTITION;BATTERY,8575N PARTITION;HDD CASE,8170 PARTITION;PALLET,8170 PARTITION;TOP/BTM,8575N PCB ASSY;MDM,56K,UNIV,F-PACK,WO/ PCB;PWA-8170/ESB BD PCB;PWA-8175/BATT GAUGE BD PCB;PWA-8175/BATT PROTECTION BD PCB;PWA-8575/DD BD PCB;PWA-8575/TOUCHPAD BD PCB;PWA-8575A/MOTHER BD PCB;PWA-STINGRAY/INVERTER BD PE BAG;50*70MM,W/SEAL,COMMON PE BAG;70X100MM,W/SEAL,COMMON PE BAG;L560XW345,CERES PE BUBBLE BAG;BATTERY,7521 PE BUBBLE BAG;BATTERY,GRAMPUS PE BUBBLE BAG;CD-ROM HOUSING,817 PEN;OIL,BLUE,PRC PHASEOUT;FERRITE CHIP,120OHM/100 PLATE;KB,8175 PWA;PWA-8170,ESB BD PWA;PWA-8575,D/D BD R0A,SMT PWA;PWA-8575,D/D BD R0A,T/U PWA;PWA-8575,T/P BD

Location(S)

Part Number
411671750010 411671750012 411671750011 411503400201 411503400202

Description
PWA;PWA-8575A,MOTHER R00 BD PWA;PWA-8575A,MOTHER R00 BD,SMT PWA;PWA-8575A,MOTHER R00 BD,T/U PWA;PWA-STINGRAY/INVERTER BD PWA;PWA-STINGRAY/INVERTER BD,SMT PWR CORD;250V/2.5A,2P,BLK,EU,175 RES;.003,1.5W,1%,2512,SMT RES;.005,1.5W,1%,2512,SMT RES;.008 ,1W ,1% ,2512,SMT RES;.01 ,1W ,1% ,2512,SMT RES;.01 ,1W ,1% ,2512,SMT RES;.015 ,1W ,1% ,2512,SMT RES;.02 ,2W,1%,2512,SMT RES;.025 ,2W ,1% ,2512,SMT,PRC RES;0 RES;0 RES;0 RES;0 ,1/10W,5% ,0805,SMT ,1/10W,5% ,0805,SMT ,1/16W,5% ,0603,SMT ,1/16W,5% ,0603,SMT

Location(S)

R01

332810000034 271046037103 271046057102

PR501,PR503 PR502,PR504 PR16 PR4,PR506 PR525 PR515 PR13 L2 L513 C305,C723,L538,PR32,PR52 PR17,PR522,PR523,R1,R511 R579 R64 PR1,PR2,PR521,R100,R101, PR3

R0B R00 R01

271045087101 271045107101 271045107101 271045157101 271586026101 271046257101 271002000301 271002000301 271071000002 271071000002 271071152101

RES;1.5K ,1/16W,1% ,0603,SMT RES;1.5K ,1/16W,1% ,0603,SMT RES;1.5K ,1/16W,5% ,0603,SMT RES;10 ,1/16W,5% ,0603,SMT RES;10 ,1/16W,5% ,0603,SMT RES;10 ,1/16W,5% ,0603,SMT RES;10.2K,1/16W,1% ,0603,SMT

L12,L13,L14,L15,L22,L24,L2

271071152101 271071152302 271071100302 271071100302 271071100302 271071102211

175

8575A N/B Maintenance


9. Spare Parts List - 18
Part Number
271071101101 271071101301 271071101301 271071101301 271071104101 271071104101 271071104101 271071104101 271071104302 271071104302 271071104302 271071104302 271071103101 271071103101 271071103101 271071103302 271071103302 271071103302 271071106301 271071111101 271071113101 271071113101 271071121211 271071127211 271071137271

Description
RES;100 ,1/16W,1% ,0603,SMT RES;100 ,1/16W,5% ,0603,SMT RES;100 ,1/16W,5% ,0603,SMT RES;100 ,1/16W,5% ,0603,SMT RES;100K ,1/16W,1% ,0603,SMT RES;100K ,1/16W,1% ,0603,SMT RES;100K ,1/16W,1% ,0603,SMT RES;100K ,1/16W,1% ,0603,SMT RES;100K ,1/16W,5% ,0603,SMT RES;100K ,1/16W,5% ,0603,SMT RES;100K ,1/16W,5% ,0603,SMT RES;100K ,1/16W,5% ,0603,SMT RES;10K ,1/16W,1% ,0603,SMT RES;10K ,1/16W,1% ,0603,SMT RES;10K ,1/16W,1% ,0603,SMT RES;10K ,1/16W,5% ,0603,SMT RES;10K ,1/16W,5% ,0603,SMT RES;10K ,1/16W,5% ,0603,SMT RES;10M ,1/16W,5% ,0603,SMT RES;110 ,1/16W,1% ,0603,SMT RES;11K ,1/16W,1% ,0603,SMT RES;11K ,1/16W,1% ,0603,SMT RES;12.1K,1/16W,1% ,0603,SMT RES;12.7K,1/16W,1%,0603,SMT RES;13.7K,1/16W,.1%,0603,SMT

Location(S)
R522,R536 R231,R548,R566,R74,R789,R

Part Number
271071131101 271071134701 271071134101 271071147011

Description
RES;130 ,1/16W,1% ,0603,SMT RES;130K ,1/16W,0.1% ,0603,SMT RES;130K ,1/16W,1% ,0603,SMT RES;147 ,1/16W,1% ,0603,SMT RES;150 ,1/16W,1% ,0603,SMT RES;150 ,1/16W,5% ,0603,SMT RES;150K ,1/16W,1% ,0603,SMT RES;15K ,1/16W,1% ,0603,SMT RES;15K ,1/16W,1% ,0603,SMT RES;15K ,1/16W,1% ,0603,SMT RES;15K ,1/16W,5% ,0603,SMT RES;15K ,1/16W,5% ,0603,SMT RES;160K ,1/16W,5% ,0603,SMT RES;18.2K,1/16W,1%,0603,SMT RES;187K ,1/16W,1% ,0603,SMT RES;1K ,1/16W,1% ,0603,SMT RES;1K ,1/16W,1% ,0603,SMT RES;1K ,1/16W,5% ,0603,SMT RES;1K ,1/16W,5% ,0603,SMT RES;1M ,1/16W,1% ,0603,SMT RES;1M ,1/16W,1% ,0603,SMT RES;1M ,1/16W,5% ,0603,SMT RES;1M ,1/16W,5% ,0603,SMT RES;2.2K ,1/16W,1% ,0603,SMT RES;2.2K ,1/16W,5% ,0603,SMT

Location(S)
R545 PR560 PR575 R549 R109,R116,R21,R508,R553,R R503 PR13,PR14 PR528,PR532,R720,R722 R107,R114,R269,R270 R502,R503,R504,R505,R508 PR519 PR20 PR19,R556,R95 PR517 PR537,R1,R174,R194,R43,R5 PR550 PR5,PR539,PR545,PR6,PR60 PR509,PR521,PR6,PR7,R528 PR511 R552,R558,R672,R674

PR557,PR563

271071151101 271071151302 271071154101 271071153101

PR15,PR27,PR28,PR3,PR538 PR508,PR518

271071153101 271071153101 271071153301 271071153301

PR12,PR19 PR507,PR513,PR527,PR540, PR574,R125,R138,R149,R15 R10,R516 R189 R20 PR530 PR8 R578,R731,R732,R733,R734 PR508 PR10,PR558

271071164301 271071182214 271071187311 271071102102 271071102102 271071102302 271071102302 271071105101 271071105101 271071105301 271071105301 271071222102 271071222302

176

8575A N/B Maintenance


9. Spare Parts List - 19
Part Number
271071225301 271071249111 271012278101 271071272101 271071272101 271071272301 271071200101 271072201101 271071201301 271071201301 271071204101 271071203701 271071203101 271071203101 271071203302 271071215211 271071221302 271071226311 271071223302 271071244301 271071249311 271071267211 271071270301 271071202301 271071205101

Description
RES;2.2M,1/16W,5% ,0603,SMT RES;2.49K,1/16W,1% ,0603,SMT RES;2.7 ,1/8W,1% ,1206,SMT RES;2.7K ,1/16W,1% ,0603,SMT RES;2.7K ,1/16W,1% ,0603,SMT RES;2.7K ,1/16W,5% ,0603,SMT RES;20 ,1/16W,1% ,0603,SMT RES;200 ,1/10W,1% ,0603,SMT RES;200 ,1/16W,5% ,0603,SMT RES;200 ,1/16W,5% ,0603,SMT RES;200K ,1/16W,1% ,0603,SMT RES;20K ,1/16W,.1%,0603,SMT RES;20K ,1/16W,1% ,0603,SMT RES;20K ,1/16W,1% ,0603,SMT RES;20K ,1/16W,5% ,0603,SMT RES;21.5K,1/16W,1% ,0603,SMT RES;22 ,1/16W,5% ,0603,SMT RES;226K ,1/16W,1% ,0603,SMT RES;22K ,1/16W,5% ,0603,SMT RES;240K ,1/16W,5% ,0603,SMT RES;249K ,1/16W,1% ,0603,SMT RES;26.7K,1/16W,1% ,0603,SMT RES;27 ,1/16W,5% ,0603,SMT RES;2K ,1/16W,5% ,0603,SMT RES;2M ,1/16W,1% ,0603,SMT

Location(S)
PR546 R14 PR531 PR9 R86,R87 R544 R57 R246,R524,R63,R748,R749,R PR18 PR7 PR12,PR21,PR581 R679,R719,R721 PR526 R117,R118,R119,R129,R130 PR551 PR522,R49 PR547 PR29 R509 PR573,R577,R727,R728,R83

Part Number
271071205301 271071301301 271071301011 271071301311 271071324211 271071330302 271071330302 271071333301 271071333301 271071390302 271072302301 271002472301 271071472302 271071499111 271071412311 271071432211 271071471101 271071471302 271071474301 271071474301 271071475011 271071473301 271071473301 271071487211 271071487311

Description
RES;2M ,1/16W,5% ,0603,SMT RES;300 ,1/16W,5% ,0603,SMT RES;301 ,1/16W,1% ,0603,SMT RES;301K ,1/16W,1% ,0603,SMT RES;32.4K,1/16W,1% ,0603,SMT RES;33 ,1/16W,5% ,0603,SMT RES;33 ,1/16W,5% ,0603,SMT RES;33K ,1/16W,5% ,0603,SMT RES;33K ,1/16W,5% ,0603,SMT RES;39 ,1/16W,5% ,0603,SMT RES;3K ,1/10W,5% ,0603,SMT RES;4.7K ,1/10W,5% ,0805,SMT RES;4.7K ,1/16W,5% ,0603,SMT RES;4.99K,1/16W,1% ,0603,SMT RES;412K ,1/16W,1% ,0603,SMT RES;43.2K,1/16W,1% ,0603,SMT RES;470 ,1/16W,1% ,0603,SMT RES;470 ,1/16W,5% ,0603,SMT RES;470K ,1/16W,5% ,0603,SMT RES;470K ,1/16W,5% ,0603,SMT RES;475 ,1/16W,1% ,0603,SMT RES;47K ,1/16W,5% ,0603,SMT RES;47K ,1/16W,5% ,0603,SMT RES;48.7K,1/16W,1% ,0603,SMT RES;487K ,1/16W,1% ,0603,SMT

Location(S)
PR26,PR34,PR35 R267 R12,R62 PR564 PR5 R16,R166,R167,R171,R172,R R9 PR16,PR552,R697 R2,R3,R506,R7 R532 R739 PR516 PR14,PR4,PR561,R120,R144 PR11 PR22 PR518 R137,R156,R157,R200,R201 PR507,PR510 R505,R683,R7 R85 PR544,R134,R159 R4,R5,R518,R8 PR9

177

8575A N/B Maintenance


9. Spare Parts List - 20
Part Number
271071499811 271071518301 271071512101 271002515302 271071562301 271071510301 271071511812 271071513301 271071536211 271071560101 271071560301 271071561101 271071576311 271071604111 271071619111 271071682301 271071604811 271071619811 271071620102 271071681101 271071683101 271071698311 271071750101 271071750302 271071754301

Description
RES;49.9 ,1/16W,1% ,0603,SMT RES;5.1 ,1/16W,5% ,0603,SMT RES;5.1K ,1/16W,1% ,0603,SMT RES;5.1M ,1/8W ,5% ,0805,SMT,PRC RES;5.6K ,1/16W,5% ,0603,SMT RES;51 ,1/16W,5% ,0603,SMT RES;51.1,1/16W,1% 0603,SMT RES;51K ,1/16W,5% ,0603,SMT RES;53.6K,1/16W,1% ,0603,SMT RES;56 ,1/16W,1% ,0603,SMT RES;56 ,1/16W,5% ,0603,SMT RES;560 ,1/16W,1% ,0603,SMT RES;576K ,1/16W,1% ,0603,SMT RES;6.04K,1/16W,1% ,0603,SMT RES;6.19K,1/16W,1% ,0603,SMT RES;6.8K ,1/16W,5% ,0603,SMT RES;60.4 ,1/16W,1% ,0603,SMT RES;61.9 ,1/16W,1% ,0603,SMT RES;62,1/16W,1% 0603,SMT RES;680 ,1/16W,1% ,0603,SMT RES;68K ,1/16W,1% ,0603,SMT RES;698K ,1/16W,1% ,0603,SMT RES;75 ,1/16W,1% ,0603,SMT RES;75 ,1/16W,5% ,0603,SMT RES;750K ,1/16W,5% ,0603,SMT

Location(S)
R533,R535,R636,R640,R645 PR17,PR514 R239 R131,R140 R512,R513,R514,R515,R516 R14,R521 R184 PR18 R276,R41,R46,R605,R676 R238,R240,R241,R243,R587 PR556 R550 PR543 R185,R186,R187 R50 R27,R30 R10,R11,R528 R534

Part Number
271071822301 271071866111 271071820301 271071887211 271071909101 271071909011 271071976311 271611000301 271611000301 271571000301 271611100301 271571100301 271611103301 271611102301 271621102302 271611220301 271611330301 271571330301 271611472301 271621472303 271621471301 271621473301

Description
RES;8.2K ,1/16W,5% ,0603,SMT RES;8.66K,1/16W,1% ,0603,SMT RES;82 ,1/16W,5% ,0603,SMT RES;88.7K,1/16W,1% ,0603,SMT RES;9.09K,1/16W,1% ,0603,SMT RES;909 ,1/16W,1% ,0603,SMT RES;976K ,1/16W,1% ,0603,SMT RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP;0*4 ,8P ,1/16W,5% ,0612,SMT RP;0*8 ,16P ,1/16W,5% ,1606,SM RP;10*4 ,8P ,1/16W,5% ,0612,SMT RP;10*8 ,16P ,1/16W,5% ,1606,SM RP;10K*4 ,8P ,1/16W,5% ,0612,SMT RP;1K*4 ,8P ,1/16W,5% ,0612,SMT RP;1K*8 ,10P,1/32W,5% ,1206,SMT RP;22*4 ,8P ,1/16W,5% ,0612,SMT RP;33*4 ,8P ,1/16W,5% ,0612,SMT RP;33*8 ,16P ,1/16W,5% ,1606,SM RP;4.7K*4,8P ,1/16W,5% ,0612,SMT RP;4.7K*8,10P,1/16W,5% ,1206,SMT RP;470*4,8P,1/16W,5%,1206,SMT RP;47K*8 ,10P,1/16W,5% ,1206,SMT RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP;75*4 ,8P ,1/16W,5% ,0612,SMT RP;8.2K*8,10P,1/32W,5% ,1206,SMT

Location(S)
R190 PR549 R205,R207,R210,R777 R228 PR8 RP1,RP2,RP3,RP4 RP48,RP501,RP503,RP504,R RP13,RP14,RP15 FA502,FA503,FA504,FA505,F RP10,RP11,RP12,RP16,RP17 RP3,RP4,RP40,RP518,RP529 RP1 RP2,RP507 RP5,RP512,RP6 RP43,RP528 RP21,RP22,RP23,RP24,RP25 RP36,RP46,RP47,RP511,RP5 RP514,RP519 RP7 RP513,RP517 RP5 RP502 RP37,RP38,RP39

R25,R562 R31,R35,R525,R537,R538,R5 PR23

271611750301 271611750301 271621822302

178

8575A N/B Maintenance


9. Spare Parts List - 21
Part Number
345671600002 345671600001 345503400001 565167170001 340671200013 340671200014 371102011502 340671750002 341671700001 333050000119 333050000120 333050000107 333050000117 333050000116 333050000098 561860000022 361400003021 370102610302 370102610603 370102610603 370102030301 370102030301 370102030301 370102010309 370102010407

Description
RUBBER PAD;LCD,LOWER,8175 RUBBER PAD;LCD,UPPER,8175 RUBBER;2MM,ROUND,STINGRAY S/W;CD ROM,SYSTEM DRIVER,8575 SCREW ASSY;CPU,8170 SCREW ASSY;IC,82845,8170 SCREW;M2L15,FLT(+),NIW/NLK SHIELDING ASSY;TOP,ID3,8575A SHIELDING;AUDIO,8575 SHRINK TUBE;600V,105'C,D0.8*6MM, SHRINK TUBE;600V,105'C,D0.8*9MM, SHRINK TUBE;UL,600V,105'C,ID2.5* SHRINK TUBE;UL,600V,105'C,ID2.5* SHRINK TUBE;UL,600V,105'C,ID3.5* SHRINK TUBE;ULCSA,125'C,D0.7MM,B SINGLE PAGE;GN,NOTE FOR BATTERY& SOLDER CREAM;NOCLEAN,P4020870980 SPC-SCREW;M2.6L3,NIB,K-HD,NYLOK SPC-SCREW;M2.6L6,K-HD,NIB/NLK SPC-SCREW;M2.6L6,K-HD,NIB/NLK SPC-SCREW;M2L3,K-HD,1,NIB/NLK SPC-SCREW;M2L3,K-HD,1,NIB/NLK SPC-SCREW;M2L3,K-HD,1,NIB/NLK SPC-SCREW;M2L3.0,NIW/NLK,HD07 SPC-SCREW;M2L4,K-HD,NIB/NLK

Location(S)

Part Number
370102010407 370102010401 370102010606 370103010405 370103010604 340671700003 340671700008 226600030149 226600030058 377244010002 341668300008 297120101007 297120100008 297040105012 297040105012 297040105010 297030102001 225600000309 225600000032 225600000032 225600000034 225600000061 225600000310 622200000008 225671700006

Description
SPC-SCREW;M2L4,K-HD,NIB/NLK SPC-SCREW;M2L4,NIB,FLT(+),NL,731 SPC-SCREW;M2L6,K-HD(t0.2),NIB/NL SPC-SCREW;M3L4,NIW,K-HD,T0.3 SPC-SCREW;M3L6,NIB,K-HD,t0.8,NYL SPEAKER ASSY,L,8575 SPEAKER ASSY;R,8575 SPONGE/2ADHESIVE;CR-RUBBER/G9000 SPONGE;CR,T=1.5MM,W=8MM,PRC STANDOFF;#4-40DP3.5H5L5.5,NIW STANDOFF;MDC MODEM,NLK,HOPE SW;DIP,SPST,4P,24VDC,.025A,SMT SW;DIP;SPST,8P,24VDC,25MA,SMT,FH SW;PUSH BUTTOM,4P,SP,12V/50MA,H2 SW;PUSH BUTTOM,4P,SP,12V/50MA,H2 SW;PUSH BUTTOM,5P,SPST,12V/50MA, SW;TOGGLE,SPST,5V/0.2mA,H10.7MM, TAPE;3M-467/DOUBLE RELEASE PAPER TAPE;ACETURM ADHESTIVE,W=4mm,BLK TAPE;ACETURM ADHESTIVE,W=4mm,BLK TAPE;ACETURN ADHESI,W=10mm,PRC TAPE;ADHENSIVE,DOUBLE-FACE,W20,U TAPE;ADHENSIVE,DOUBLE-FACE,W8,UL TAPE;CARTON,2.5"W,30M/RL,PRC TAPE;CONDUCTIVE,20X20,PLATE,KB

Location(S)

SW503 SW6 SW1,SW2,SW3,SW4,SW5,SW SW502 SW1,SW2,SW3,SW4 SW1

179

8575A N/B Maintenance


9. Spare Parts List - 22
Part Number
225671700009 225671700008 225671700007 225600000375 225600000004 225600000237 225600000312 225600000344 225600000268 225600000054 225600000027 225600000143 225600000177 333334000046 333334000046 333334000084 333334000099 346671750001 345671700003 310111103013 442164900010 288227002006 288227002001 288227002001 628820014401

Description
TAPE;CONDUCTIVE,BTM SHD,ESD,8575 TAPE;CONDUCTIVE,KB COVER,ESD,857 TAPE;CONDUCTIVE,KB,ESD,8575 TAPE;CONDUCTIVE/DOUBLE RELEASE P TAPE;DOUBLE SIDE,12MM*15M TAPE;G9000,W=110,PRC TAPE;G9000,W=113,PRC TAPE;G9000,W=220,PRC TAPE;G9000,W=72,PRC TAPE;INSULATING,POLYESTER FILM,1 TAPE;INSULATOR,W10T0.06,UL-510 TAPE;SONY G9000,W=10,T=0.15,PRC TAPE;T=0.05MM,W=7MM,KAPTON/ADHES TERMINAL;HRS/DF13-2630SCF,PRC TERMINAL;HRS/DF13-2630SCF,PRC TERMINAL;JAE/FI-C3-A1-15000,PRC TERMINAL;JST/SSH-003T-P0.2,PRC THERMAL PAD;MOS,ID3,8575A THERMAL PAD;SIS301,8575 THERMISTOR;10K,1%,RA,DISK,103ATTOUCH PAD MODULE;TM41PD-350 TRANS;2N7002LT1,N-CHANNEL FET,ES TRANS;2N7002LT1,N-CHANNEL FET,SO TRANS;2N7002LT1,N-CHANNEL FET,SO TRANS;DTA144EKA,PNP,100MA,50V,SO

Location(S)

Part Number
288200144002 288200114001 288200144003 288200144001 288206612003 288206676004 288202222001 288203904010 288203906002 288203906018 288207002001 288202301001 288202301001 288202302001 288204416001 288204416001 288204425002 288204425002 288204425002 288204532001 288204788001

Description
TRANS;DTA144WK,PNP,SMT TRANS;DTC114TKA,10K,N-MOSFET,SOT TRANS;DTC144TKA,N-MOSFET,SOT-23 TRANS;DTC144WK,NPN,SOT-23,SMT TRANS;FDD6612A,30V,30A,.028hm,NTRANS;FDD6676,30V,78A,.0085hm,NTRANS;MMBT2222AL,NPN,TO236AB TRANS;MMBT3904L,NPN,Tr35NS,TO236 TRANS;MMBT3906L,40V,200mA,SOT23, TRANS;MMBT3906L,PNP,Tr35NS,TO236 TRANS;NDC7002N,N-MOSFET,SSOT-6 TRANS;SI2301DS,P-MOSFET,SOT-23 TRANS;SI2301DS,P-MOSFET,SOT-23 TRANS;SI2302DS,N-MOSFET,SOT-23 TRANS;Si4416DY,N-MOSFET,.028OHM, TRANS;Si4416DY,N-MOSFET,.028OHM, TRANS;SI4425DY,PMOS,8.5A/30V,0.0 TRANS;SI4425DY,PMOS,8.5A/30V,0.0 TRANS;SI4425DY,PMOS,8.5A/30V,0.0 TRANS;SI4532DY,N&P-MOSFET,SO8,PR TRANS;SI4788CY,P-MOS,5A1.8~5.5V, TRANS;SI4810DY,N-MOS,.0155OHM,SO TRANS;SI4810DY,N-MOS,.0155OHM,SO TRANS;SI4835DY,PMOS,6A/30V,.035, TRANS;SI4925DY,P-MOSFET,SO-8

Location(S)
PQ506,Q529 Q13 Q10,Q11,Q17,Q18,Q19,Q2,Q PQ509,Q20,Q5,Q510,Q9 PU501,PU502,PU515,PU516 PU1,PU2,PU3,PU4,PU5,PU6 PQ3 PQ511,Q12,Q15,Q516,Q517, Q14 PQ2 PQ1 Q1,Q509,Q511,Q6,Q8 Q534 PU2,PU5 PU507,PU509 PU502 PU512,PU513

PU504,PU505 PU3,PU6 PU7,PU8 PQ1 PU9

PQ10,PQ4,PQ504,PQ505,PQ PQ2,PQ501,PQ502,PQ503 Q3,Q4,Q501,Q502,Q505,Q50

288204810001 288204810001 288204835001 288204925001

180

8575A N/B Maintenance


9. Spare Parts List - 23
Part Number
288209410001 273001050039 271911103906 421671700002 421668300005 421671600010 421671700004 421671700001 332110020057 332110020028 332110020050 332110020020 332110020019 332110020019 332110026096 332110026097 332110026099 332110026008 332110026016 332110026013 332110030058 332110030052 332110030059 332110030055 332110030050

Description
TRANS;SI9410DY,N-MOSFET,.04OHM,S TRANSFORMER;10/100 BASE,LF-H80P, VR;10K,20%,0.05W,RN101GAC10KPGJWIRE ASSY;ANTENNA,8575 WIRE ASSY;BIOS,BATTERY,HOPE WIRE ASSY;INVERT,8175 WIRE ASSY;MDC,EMI,8575 WIRE ASSY;TOUCHPAD,8575 WIRE;#20,UL1007,122MM,RED,PRC WIRE;#20,UL1007,50MM,RED,PRC WIRE;#20,UL1007,55MM,BLK,PRC WIRE;#20,UL1007,BLK,PRC WIRE;#20,UL1007,RED,PRC WIRE;#20,UL1007,RED,PRC WIRE;#26,UL1007,165MM,WHITE,PRC WIRE;#26,UL1007,55MM,BLACK,PRC WIRE;#26,UL1007,93MM,YELLOW,PRC WIRE;#26,UL1007,BLACK,PRC WIRE;#26,UL1007,WHITE,PRC WIRE;#26,UL1007,YELLOW,PRC WIRE;#30,UL1571,OD0.6mm,BLACK,PR WIRE;#30,UL1571,OD0.6mm,BLUE,PRC WIRE;#30,UL1571,OD0.6mm,BROWN,PR WIRE;#30,UL1571,OD0.6mm,GREEN,PR WIRE;#30,UL1571,OD0.6mm,GREY,PRC

Location(S)
Q503 U3 VR1 J508

Part Number
332110030057 332110030060 332110030053 332110030056 332110030051 332110030054 332110032036 332110032014 332110032006 332110032005 332110032002 332110032003 332110032004 332110032001 273001050062 274011431408 274011431422 274011600408 274012457405 274012500401 274013276103

Description
WIRE;#30,UL1571,OD0.6mm,ORANGE,P WIRE;#30,UL1571,OD0.6mm,ORANGE/B WIRE;#30,UL1571,OD0.6mm,PURPLE,P WIRE;#30,UL1571,OD0.6mm,RED,PRC WIRE;#30,UL1571,OD0.6mm,WHITE,PR WIRE;#30,UL1571,OD0.6mm,YELLOW,P WIRE;#32,1571,BLACK/RED/#28,DRAI WIRE;#32,UL1571,BLK,PRC WIRE;#32,UL1571,BLK/WHT,PRC WIRE;#32,UL1571,BROWN/WHT,PRC WIRE;#32,UL1571,GRAY,PRC WIRE;#32,UL1571,ORANGE/BLK,PRC WIRE;#32,UL1571,RED/WHT,PRC WIRE;#32,UL1571,WHT,PRC XSFORMER;CI8.5,SIT16260,16/2600T XTAL;14.318M,50PPM,32PF,7*5,4P,S XTAL;14.318MHZ,16PF,20PPM,8*4.25 XTAL;16MHZ,16PF,50PPM,8*4.5,2P XTAL;24.576M,50PPM,16PF,7*5,4P,S XTAL;25MHZ,30PPM,18PF,4P,SMT XTAL;32.768KHZ,20PPM,12.5PF,CM20

Location(S)

X502 X501 X503 X6 X1,X4 X5

181

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MODEL : 8575 A
Contexts
Title
COVER SHEET & SCREW HOLE System Block Diagram Power Block Diagram P4-CPU (1/2) P4-CPU (2/2) SIS650(1/3) SIS650(2/3) SIS650(3/3) TV/LVDS ENCODER(SiS301LV) LCD/VGA INTERFACE & LEDs MAIN CLOCK & CLOCK BUFFER DDR SODIMMs DDR TERMINATION SIS961(1/3) SIS961(2/3) SIS961(3/3) IDE INETRFACE PCI 1410 / PU2211 LAN PHY (ICS 1893) & MDC AUDIO CODEC & AUDIO AMP SUPER I/O, T/P & BUTTON MICROCONTROLLER (H8) BATTERY CONNECT AND +1.25V 2.5v_DDR / +1.8VS CHARGER CPU CORE D/D CONNECTOR MINI PCI SLOT NEC UPD72872 IEEE1394 Revision 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

Revision 01
Page
TP514 TP507 TP505 TOUCHPAD_METAL8 TOUCHPAD_METAL8 TOUCHPAD_METAL8 1 1 1

MTG7 ID3.2/OD6.0

MTG8 ID3.2/OD6.0

MTG9 ID3.2/OD6.0

MTG10 ID3.0/OD6.0

MTG11 ID3.0/OD6.0

MTG13 ID3.0/OD6.0

FD1 FIDUCIAL-MARK

FD2 FIDUCIAL-MARK

FD3 FIDUCIAL-MARK

FD4 FIDUCIAL-MARK

FD504 FIDUCIAL-MARK

FD503 FIDUCIAL-MARK

FD502 FIDUCIAL-MARK

FD501 FIDUCIAL-MARK

E501 TOUCHPAD_METAL10

E502 TOUCHPAD_METAL10

E503 TOUCHPAD_METAL10

E507 TOUCHPAD_METAL10 MTG6 ID3.0/OD4.0 MTG12 ID3.0/OD4.0 MTG32 ID3.0/OD4.0

E511 TOUCHPAD_METAL10

E518 TOUCHPAD_METAL10

E519 TOUCHPAD_METAL10

E520 TOUCHPAD_METAL10

E521 TOUCHPAD_METAL10

E522 TOUCHPAD_METAL10

3 2 1

3 2 1

E1 E2 TOUCHPAD_METAL10 TOUCHPAD_METAL10

E4 TOUCHPAD_METAL10

E5 TOUCHPAD_METAL10

E7 TOUCHPAD_METAL10

4 5 6 7 8 9

12 11 10

4 5 6 7 8 9

12 11 10

4 5 6 7 8 9

3 2 1

MTG3 ID2.8/OD7.6

MTG4 ID2.8/OD6.5

MTG5 ID2.8/OD7.6 12 11 10

E8 TOUCHPAD_METAL10

E9 E10 TOUCHPAD_METAL10 TOUCHPAD_METAL10 3 2 1

3 2 1

MTG14 ID2.8/OD7.6 12 11 10 4 5 6

MTG15 ID2.8/OD6.0 13 12 11 10 MTG16 ID2.8/OD6 8 7 5 6

4 5 6 MTG17 ID2.8/OD6.0 3 2 1 4 5 6 7 8 9 13 12 11 10 3 2 1 4 5 6 7 8 9 7 8 9

2 3 4 MTG22 ID2.8/OD7.6

3 2 1

MTG21 ID2.8/OD7.6 12 11 10 4 5 6

7 8 9

+5VS

+3V

+1.8VS

12 11 10 7 8 9

MTG20 ID4.9/OD7.6

AGND

EC501 0.1U/NA 0603 50V

EC502 0.1U/NA 0603 50V

EC2 0.1U/NA 0603 50V

+3V

+3VS

+3VS

POWER STATES
STATE SIGNAL -SUSB -SUSC ADP BATTERY +VCC_RTC +VCC_CORE VOTAGE +19V +12V +3.3V +1.75V +1.8V +1.8V +2.5V +3.3V +3.3V +3.3V +5V +5V +5V +12V +12V FULL ON HIGH HIGH O O O O O O O O O O O O O O O STR LOW HIGH O O O O X O O X O O X O O X O STD LOW LOW O O O X X X X X X O X X 0 X X MEC-OFF LOW LOW O O O X X X X X X 0 X X 0 X X REMARK

IDSEL
IDSEL AD20 AD22

CHIP TI1410 1394 (UPD72872)

BUS MASTER
REQ/GNT -REQ0/-GNT0 -REQ1/-GNT1

CHIP TI1410 1394 (UPD72872)

PCIINT
PCIINT INTA# INTB# INTC#

CHIP SIS 650 PCMCIA (TI1410) 1394 (UPD72872)


1

+1.8VS +1.8V +2.5V_DDR

DRAW

DESIGN

CHECK

ISSUED

+3VS +3V +3VA +5VS +5V +5VA +12VS +12V

Title Size C Date:


A B

8575A COVER SHEET & SCREW HOLE Document Number BD 311671750001 & TU 411671750012 Sheet 1 of 30 Rev 01

Monday, June 17, 2002

8575 A System Block Diagram


Speed Step! D/D Power Components VID

Pentiun 4 Processor-M Willamette/Northwood


C.P.U.
Micro-FCPGA 479 pin

Pentium 4

ADM 1032
Thermal Recorder

H8-3437

-HD[0..63]

NM24C02N

SSOP 16

A[0..25]

Control

D[0..15]

TV

TV

SIS301LV
128-pin LQFP AGP

HOST

Control

MINI 1394 CONNECTOR

Power Switch

-HA3..31]

EEPROM

IC CARD Socket

TPS211

MINI PCI SLOT

IEEE 1394
NEC UPD72872 PQFP120

PCI 1410
PCMCIA CONTROLLER uBGA 144

200 Pin DDR SO-DIMM Socket*2

SO-DIMM

Pannel

LVDS

Sis 650
702-Balls BGA
Local
Memory

DDR SDRAM PC2100/PC1600 Memory Bus / 266MHz


SDRAM

CRT

Clock Generator
ICS952001

Hyper Zip HyperZip Data Bus 266MHz 512MB/sec

DDRAM Slot * 2 (200Pins SO-DIMM)

AD[0..31]

AD[0..31]

AD[0..31]

Control

Control

Control

DDR Clock Generator


ICS93722

PCI BUS
HUB[0..11] AD[0..31] Control Control

13

RJ-45 Connector

LAN PHY 10/100 M


ICS1893

DUAL USB

MII LAN PCI

USB Cover Switch

External Microphone Internal Microphone Internal Speaker SPDIF JACK RJ-11 Connect
Mic-in Connector

HyperZip USB

Ultra DMA 33/66/100

SiS 961
IDE 371-Balls BGA LPC
AC'97

1
AC Link

Primary EIDE (HDD)

Realtek ALC201
Audio Codec PQFP 48

TPA 0202
Amplifier

Ultra DMA 33/66/100

Secondary EIDE (CDROM/DVD)

FWH

5 LPC
FWH 82802

(30 pin)

M.D.C.

IR Module HP-3600
PRINTER PORT

PC87393
Super I/O TQFP 100PIN

ISA BUS

H8-3437S
Micro Controller
PQFP 100

Keyboard Touch PAD

Internal Keyboard

Touch Pad

HDD CD-ROM DVD-ROM CD-RW Combo

Flash ROM
512KB PLCC 32 16MHz

Power Button

FAN1 For CPU

Fan 1

FAN2 For D/D


A

Fan 2

Title Size Date:


B

8575A SYSTEM BLOCK DIAGRAM Document Number BD 311671700001 & TU 411671700011 Sheet 2 of 30 Rev 01

Monday, June 17, 2002

POWER DIAGRAM OF THE PROJECT 8575

-POWERBTN

2
SIS_PWRBTN

3
S3AUXSW#

LEVEL SHIFT
-SUSC PSON

-SUSB

DTC 144WK
ALWAYS H8_AVREF1 +5VA

SW_+5VA

LP2951

SI 2301DS

SI 2301DS

H8_PWRON

H8 F3437
H8_PWROK

SIS_PWRBTN#

SIS 961

PSON#

BATOK AUXOK

+5V

+5VS

SI4788
PSON +12V
C

5
+12VS PWROK
C

MAX 1632
+3V PWR_ON

SI2301
PSON +3VS

SI4788
PSON

MAX 809
AUXOK

SIS 650 CPU

CPUPWRGD

AUXOK circuit
+1.8VS +3VS VMAIN
B

PWR JACK

SI 4835DY
LEARNING

PWR_ON

+5VS

LTC 1628CG
-SUSC +VCC_CORE

+2.5V_DDR

2N7002

MIC 5248
+VCC_RTC

4
CPU_CORE_EN

LTC 1709EG

H_PWRGD

+VCC_RTC

RTC BAT

MAX 4173FEUT

+5VAS

+VCC_RTC circuit

BATOK circuit

BATOK


5 4 3 2

Title 8575A POWER BLOCK DIAGRAM Size Date: Document Number Rev 01 of 30

BD 311671700001 & TU 411671700011 Sheet


1

Monday, June 17, 2002

TP503 TP501 6 HA#[3..31] HA#[3..31] HA#3 HA#4 HA#5 HA#6 HA#7 HA#8 HA#9 HA#10 HA#11 HA#12 HA#13 HA#14 HA#15 HA#16 HA#17 HA#18 HA#19 HA#20 HA#21 HA#22 HA#23 HA#24 HA#25 HA#26 HA#27 HA#28 HA#29 HA#30 HA#31 H_ADSTB#1 H_ADSTB#0 H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 H_REQ#[0..4] K2 K4 L6 K1 L3 M6 L2 M3 M4 N1 M1 N2 N4 N5 T1 R2 P3 P4 R3 T2 U1 P6 U3 T4 V2 R6 W1 T5 U4 R5 L5 H3 J3 J4 K5 J1 AB1 Y1 W2 V3 U1A A#3 A#4 A#5 A#6 A#7 A#8 A#9 A#10 A#11 A#12 A#13 A#14 A#15 A#16 A#17 A#18 A#19 A#20 A#21 A#22 A#23 A#24 A#25 A#26 A#27 A#28 A#29 A#30 A#31 ADSTB#1 ADSTB#0 REQ#4 REQ#3 REQ#2 REQ#1 REQ#0 A#35 A#34 A#33 A#32 ADS# AP#0 AP#1 BINIT# BNR# DP#3 DP#2 DP#1 DP#0 TESTHI8 TESTHI9 TESTHI10 BR#0 BPRI# DBSY# DEFER# DRDY# HIT# HITM# IERR# INIT# LOCK# MCERR# RESET# RS#2 RS#1 RS#0 RSP# TRDY# G1 AC1 V5 AA3 G2 L25 K26 K25 J26 U6 W4 Y3 H6 D2 H5 E2 H2 F3 E3 AC3 W5 G4 V6 AB25 F4 G5 F1 AB2 J6 CPURST# H_RS#2 H_RS#1 H_RS#0 H_TRDY# CPURST# 6 6 DBI#[0..3] DBI#[0..3] TESTHI8 TESTHI9 TESTHI10 H_BR#0 H_BPRI# H_DBSY# H_DEFER# H_DRDY# H_HIT# H_HITM# 1 R520 2 1K 0603 H_INIT# H_LOCK# H_ADS# 1 H_ADS# 6

TP504

U1B HD#31 HD#30 HD#29 HD#28 HD#27 HD#26 HD#25 HD#24 HD#23 HD#22 HD#21 HD#20 HD#19 HD#18 HD#17 HD#16 HD#15 HD#14 HD#13 HD#12 HD#11 HD#10 HD#9 HD#8 HD#7 HD#6 HD#5 HD#4 HD#3 HD#2 HD#1 HD#0 DBI#0 DBI#1 DBI#2 DBI#3 DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3 6 DSTBN#[0..3] DSTBN#[0..3] H25 K23 J24 L22 M21 H24 G26 L21 D26 F26 E25 F24 F23 G23 E24 H22 D25 J21 D23 C26 H21 G22 B25 C24 C23 B24 D22 C21 A25 A23 B22 B21 E21 G25 P26 V21 E22 K22 R22 W22 D#31 D#30 D#29 D#28 D#27 D#26 D#25 D#24 D#23 D#22 D#21 D#20 D#19 D#18 D#17 D#16 D#15 D#14 D#13 D#12 D#11 D#10 D#9 D#8 D#7 D#6 D#5 D#4 D#3 D#2 D#1 D#0 DBI#0 DBI#1 DBI#2 DBI#3 DSTBN#0 DSTBN#1 DSTBN#2 DSTBN#3 WMT478/NWD_14 BGA_PGA479_SKT D#32 D#33 D#34 D#35 D#36 D#37 D#38 D#39 D#40 D#41 D#42 D#43 D#44 D#45 D#46 D#47 D#48 D#49 D#50 D#51 D#52 D#53 D#54 D#55 D#56 D#57 D#58 D#59 D#60 D#61 D#62 D#63 M23 N22 P21 M24 N23 M26 N26 N25 R21 P24 R25 R24 T26 T25 T22 T23 U26 U24 U23 V25 U21 V22 V24 W26 Y26 W25 Y23 Y24 Y21 AA25 AA22 AA24 HD#32 HD#33 HD#34 HD#35 HD#36 HD#37 HD#38 HD#39 HD#40 HD#41 HD#42 HD#43 HD#44 HD#45 HD#46 HD#47 HD#48 HD#49 HD#50 HD#51 HD#52 HD#53 HD#54 HD#55 HD#56 HD#57 HD#58 HD#59 HD#60 HD#61 HD#62 HD#63 DSTBP#[0..3] DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3 F21 J23 P23 W23 DSTBP#0 DSTBP#1 DSTBP#2 DSTBP#3 DSTBP#[0..3] 6 22 -THRMTRIP 11 11 HCLK_CPU HCLK_CPU# HCLK_CPU HCLK_CPU#

HD#[0..63]

HD#[0..63] U1C AF22 AF23 AC26 AD26 C6 B6 B2 D1 E5 B5 Y4 AE1 AE2 AE3 AE4 AE5 AF2 AF3 AF4 AD20 A5 AE23 AD22 A4 AE21 A22 A7 B3 C4 A2 AD3 AF25 AD2 AF24 BCLK0 BCLK1 ITP_CLK0 ITP_CLK1 A20M# FERR# IGNNE# LINT0 LINT1 SMI# STPCLK# VID4 VID3 VID2 VID1 VID0 VCC RSVD VCCVID VCCA VCCSENSE VCCIOPLL VSSA VSSSENSE RSVD RSVD RSVD THRMDA THRMDC THRMTRIP# RSVD RSVD RSVD RSVD WMT478/NWD_14 BGA_PGA479_SKT BSEL0 BSEL1 TESTHI11 COMP0 COMP1 BPM#5 BPM#4 BPM#3 BPM#2 BPM#1 BPM#0 TESTHI0 DBR# TESTHI12 GTLREF3 GTLREF2 GTLREF1 GTLREF0 TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI7 TESTHI6 SKTOCC# TESTHI1 PWRGOOD PROCHOT# SLP# TCK TDI TDO TMS TRST# AD6 AD5 A6 L24 P1 AB4 AA5 Y6 AC4 AB5 AC6 AD24 AE25 AD25 AA6 F6 AA21 F20 AC23 AC24 AC20 AC21 AB22 AA20 AF26 AA2 AB23 C3 AB26 D4 C1 D5 F7 E6 1 1 H_COMP0 H_COMP1 -H_BPM5_PREQ -H_BPM4_PRDY -H_BMP1_ITP -H_BMP0_ITP TESTHI0 DBR# H_DPSLP# H_GTLREF2_3 CPU_GTLREF TESTHI5 TESTHI4 TESTHI3 TESTHI2 TESTHI7 TESTHI6 TESTHI1 CPUPWRGD -H_PROCHOT SLP# ITP_TCK ITP_TDI ITP_TDO ITP_TMS -ITP_TRST TP1 TP2 G_LO/HI# 15

ITP_CLK0 ITP_CLK1 H_A20M# H_FERR# H_IGNNE# H_INTR H_NMI H_SMI# H_STPCLK# VID4_R VID3_R VID2_R VID1_R VID0_R

H_BNR#

H_BNR#

15 15 15 15 15 15

H_A20M# H_FERR# H_IGNNE# H_INTR H_NMI H_SMI# H_STPCLK#

+VCC_CORE H_A20M# H_STPCLK# H_SLP# H_SMI# H_IGNNE# H_NMI H_INTR G_LO/HI# H_DPSLP# 200 200 200 200 200 200 200 200 200 1 1 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 2 0603 0603 0603 0603 0603 0603 0603 0603 0603 R748 R749 R750 R751 R752 R753 R754 R63 R246

H_BR#0 H_BPRI#

6 6

R60 2 0 0603

CPU_DPSLP# 15

H_DBSY# 6 H_DEFER# 6 H_DRDY# 6 H_HIT# 6 H_HITM# 6 TP520 1 H_INIT# 15

+VCC_CORE 5 26 26 VCC_SENSE VSS_SENSE VCCPVID 1 R247 2 10 0603 1 R248 2 10 0603 PLL_VCCA VCCIO_PLL PLL_VSSA

SKTOCC# GND

TP512 TP502

1 6 6 1

H_LOCK# 6

H_ADSTB#1 H_ADSTB#0

CPUPWRGD 6 H_SLP# 15

CPU_THERMDA CPU_THERMDC -THRMTRIP

H_RS#[0..2]

H_REQ#[0..4]

H_RS#[0..2] 6 H_TRDY# 6

WMT478/NWD_14 BGA_PGA479_SKT

+VCC_CORE

PRECISION FSB COMPENSATION RESISTORS


2 1 R14 51.1 1% 51.1 1% 1 R521 1 2 0603 2 0603 H_COMP0 H_COMP1 1 R524 200 0603 2 R11 62 0603 2 1 R10 62 0603 -THRMTRIP -H_PROCHOT H_INIT# 26 VID[0..4] VID[0..4]

RP506 VID0 VID1 VID2 VID3 VID4 1 2 3 4 0*4 0 1 R507 VID0_R VID1_R VID2_R VID3_R 1206 VID4_R 2 0603 8 7 6 5 +VCC_CORE +3VS 1 1 1 1 1 1 1 1 1 1 R514 51 0603 2 2 R513 51 0603

PLACE THESE INSIDE SOCKET CAVITY REQUEST NEW PART NUMBER FOR 51.1 Ohm, 1%

DESIGN GUIDE PAGE 236 DESCRIPTION(NO extra pull-up resistors required)


+VCC_CORE

R267 300 0603D 2 15 H_961_FERR# 1 1 1 1 1 2

R275 470 0603D

+VCC_CORE 2 ITP_TDO CPURST# DBR# ITP_TMS -H_BMP0_ITP -H_BMP1_ITP -H_BPM4_PRDY -H_BPM5_PREQ ITP_TCK

R506 R525 1.5K/NA 75 0603 0603 1% 2 2 2

R512 R504 51 150/NA 0603 0603 2 2

R503 150 0603 2

R532 39 0603 2

R516 51 0603 2

R515 51 0603

R508 150 0603 2 2 TESTHI0 TESTHI1 TESTHI2 TESTHI3

R529 51 0603 2

R526 51 0603 2

R530 51 0603 2

R527 51 0603 -H_BPM5_PREQ -H_BPM4_PRDY -H_BMP1_ITP -H_BMP0_ITP ITP_TDI

+VCC_CORE

Q7 MMBT3904L E

B R277 B 1 Q12 MMBT3904L E 1 2 470 0603D

R276 56 1% 0603D H_FERR#

TESTHI4 TESTHI5 TESTHI6 TESTHI7

RP2 1 2 3 4 5 1K*8 RP507 1 2 3 4 5 1K*8 1206 10 9 8 7 6 TESTHI8 TESTHI9 TESTHI10 1 R534 680 0603 1206 10 9 8 7 6

1 GND

PLACE CLOSE TO J515


2

R509 27 0603 1%

ITP_CLK0 ITP_CLK1

GND
B

-ITP_TRST

PLACE CLOSE TO CPU SOCKET

+3VS

VID4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

VID3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

VID2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1

VID1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1

VID0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

VOLT. 1.75 1.70 1.65 1.60 1.55 1.50 1.45 1.40 1.35 1.30 1.25 1.200 1.15 1.100 1.050 1.000 0.975 0.950 0.925 0.9 0.875 0.85 0.825 0.8 0.775 0.75 0.725 0.7 0.675 0.65 0.625 0.6

Close to CPU socket

4 3 2 1 RP3 10K*4 1206 CPU_THERMDA +VCC_CORE H_GTLREF2_3 +VCC_CORE

One 220PF for each GTL REF Pin


+VCC_CORE 49.9 1% 1

R533 1 1 1 2 0603

PLACE AT CPU END

1.5" MAX.
1 1 1

C23 2200P 0603D 2 3 1 5 1 C24 0.1U 0603 50V

U2 D+ DVDD GND ADM1032 SO8 SCLK SDATA ALERT THEPM 8 7 6 4 SCL_THRM 22 SDA_THRM 22 -THERM_ERR 22

CPU_THERMDC 1 1 1 1 L3 4.7UH 2012 R13 51/NA 0603 2 2 R523 51 0603 2 R12 301 0603 2 R528 62 0603 1% H_FERR# PLL_VCCA CPUPWRGD H_BR#0 PLL_VSSA CPURST# +3VS

R522 100 0603 1% R531 0/NA 0603 2

C521 1U 0805 5%

220P 0603 5%

C519 220P 0603 5%

C520

L2 4.7UH 2012 2 2

+VCC_CORE 49.9 1%
A

R535 1 1 2 0603

PLACE AT CPU END


CPU_GTLREF 1 1 R536 100 0603 1% 2 1

7343 C21 2 1 20% 16V 33U +

GND

C546 1U 0805 5%

C549 220P 0603 5%

C550 220P 0603 5% 7343 C22 2 1 20% 16V 33U +

5 6 7 8

VCCIO_PLL

CPU SIGNAL TERMINATION

CP1812_7243 SHAPE

GTL Reference CKT PLL SUPPLY FILTER


5 4 3 2

Title 8575A PENTIUM4 (1/2) Size Date: Document Number Rev 01 of 30

BD 311671700001 & TU 411671700011 Sheet 4


1

Monday, June 17, 2002

+VCC_CORE

Place these caps at CPU solder side


+VCC_CORE +VCC_CORE

N6 N3 N24 N21 P5 P2 P25 P22 R26 R4 R1 R23 T6 T3 T24 T21 U5 U2 U25 U22 V26 G21 H26 H4 H1 H23 J5 J2 J25 J22 K6 K3 K24 K21 L26 L4 L1 L23 M5 M2 M25 M22 E11 E9 E26 E7 E4 E1 E23 E19 F18 F16 F14 F12 F10 F8 F5 F2 F25 F22 G6 G3 G24

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS

AE7 AE24 AE22 AE19 AD14 AD12 AD10 AD8 AD4 AD1 AD23 AD21 AE17 AE15 AE13 AE11 AE9 AE26 AB20 AC17 AC15 AC13 AC11 AC9 AC7 AC5 AC2 AC25 AC22 AC19 AD18 AD16 AA4 AA1 AA23 AA19 AB18 AB16 AB14 AB12 AB10 AB8 AB6 AB3 AB24 AB21 V4 V1 V23 W6 W3 W24 W21 Y5 Y2 Y25 Y22 AA17 AA15 AA11 AA9 AA26 AA7

C527 10U 1206 10V

C524 10U 1206 10V

C10 10U 1206 10V

C20 10U 1206 10V

U1D

A8 A10 A12 A14 A16 A18 A20 B7 B9 B11 B13 B15 B17 B19 C8 C10 C12 C14 C16 C18 C20 D7 D9 D11 D13 D15 D17 D19 E8 E10 E12 E14 E16 E18 E20 F9 F11 F13 F15 F17 F19 AA8 AA10 AA12 AA14 AA16 AA18 AB7 AB9 AB11 AB13 AB15 AB17 AB19 AC8 AC10 AC12 AC14 AC16 AC18 AD7 AD9 AD11 AD13 AD15 AD17 AD19 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AF5 AF7 AF9 AF11 AF13 AF15 AF17 AF19 AF21

C517 10U 1206 10V +VCC_CORE C18 10U 1206 10V 1 1

C6 22U 1210 10V

C511 22U 1210 10V

C11 22U 1210 10V

C555 + 22U 1210 10V 2

C9 150U 7343 10V

1 + 2

C17 150U 7343 10V

VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC

C515 10U 1206 10V

C12 10U 1206 10V

C14 10U 1206 10V

C15 10U 1206 10V

2 1

C531 0.1U 0603 50V

C547 0.1U 0603 50V

C538 0.1U 0603 50V

C13 0.1U 0603 50V

C540 0.1U 0603 50V

C536 0.1U 0603 50V

C530 0.1U 0603 50V

C552 0.1U 0603 50V

C532 0.1U 0603 50V

1 2

C548 0.1U 0603 50V

Place these caps at CPU north side


1 1 1 1

+VCC_CORE

Place these caps at CPU south side


1 1 1 1 2

+VCC_CORE

C541 10U 1206 10V

C533 10U 1206 10V

C526 10U 1206 10V

C554 10U 1206 10V

C16 10U 1206 10V

C19 10U 1206 10V

C545 10U 1206 10V

C8 10U 1206 10V


C

C528 10U 1206 10V

C537 10U 1206 10V

C535 10U 1206 10V

C556 10U 1206 10V

C516 10U 1206 10V

C5 10U 1206 10V

C553 10U 1206 10V

C542 10U 1206 10V

C539 10U 1206 10V

1 1 2 2

C534 10U 1206 10V

C529 10U 1206 10V

C544 10U 1206 10V

C543 10U 1206 10V

C557 10U 1206 10V

C551 10U 1206 10V

C525 10U 1206 10V

C523 10U 1206 10V

C518 10U 1206 10V

C512 10U 1206 10V

C7 10U 1206 10V

C5 VSS C2 VSS C25 VSS C22 VSS C19 VSS D18 VSS D16 VSS D14 VSS D12 VSS D10 VSS D8 VSS D6 VSS D3 VSS D24 VSS D21 VSS D20 VSS E17 VSS E15 VSS E13 VSS A3 VSS A24 VSS A21 VSS A19 VSS B18 VSS B16 VSS B12 VSS B10 VSS B26 VSS B8 VSS B4 VSS B23 VSS B20 VSS C17 VSS C15 VSS C13 VSS C11 VSS C9 VSS C7 VSS AF18 VSS AF16 VSS AF14 VSS AF12 VSS AF10 VSS

AF8 VSS AF6 VSS AF1 VSS AF20 VSS A17 VSS A15 VSS A13 VSS A11 VSS A9 VSS A26 VSS AA13VSS B14 VSS

+5VS

+5VS

+5VS 1

WMT478/NWD_14 BGA_PGA479_SKT

R894 0 0603 2

0603/0805 CO-LAYOUT U502 1 3 2 C514 0.1U 0603 50V IN EN GND MIC5248 SOT25 PG OUT 4 5 1 2

R517 10K 0603

CPU_CORE_EN 26 VCCPVID C513 1U 0603


B

VCCPVID 4

C601 0.1U/NA 0603 50V

Title 8575A PENTIUM4 (2/2) Size Date:


5 4 3 2

Document Number

BD 311671700001 & TU 411671700011 Sheet 5 of 30


1

Rev 01

Monday, June 17, 2002

SIS650(1/3)
A

AHSYNC VBD11 VBD10 VBD9 VBD8 FA502 10*4 1 2 3 4 FA504 10*4 1 2 3 4 FA506 10*4 1 2 3 4 1206 8 7 6 5 1206 8 7 6 5 1206 8 7 6 5 4 3 2 1 4 3 2 1 4 3 2 1 FC_VBD11 FC_VBD10 FC_VBD9 FC_VBD8 FC_VBD[0..11] VAD11 VAD10 VAD9 VAD8 9 FA503 10*4 1 2 3 4 FA505 10*4 1 2 3 4 FA507 10*4 1 2 3 4 1206 8 7 6 5 1206 8 7 6 5 1206 8 7 6 5 4 3 2 1 4 3 2 1 4 3 2 1 FC_VAD11 FC_VAD10 FC_VAD9 FC_VAD8 FC_VAD[0..11] 9

R36

2 22

VAHSYNC

VAHSYNC 9

VBD7 VBD6 VBD5 VBD4

FC_VBD7 FC_VBD6 FC_VBD5 FC_VBD4

VAD7 VAD6 VAD5 VAD4

FC_VAD7 FC_VAD6 FC_VAD5 FC_VAD4

AVSYNC

R37

2 22

VAVSYNC

VAVSYNC 9

L14 CPUAVDD 1 120Z/100M 2012 C78 0.1U 0603 50V JL500 1 2 JP_NET20 2

+3VS

VBD3 VBD2 VBD1 VBD0 C82 10U 1206 10V

FC_VBD3 FC_VBD2 FC_VBD1 FC_VBD0

C76 0.01U 0603

VAD3 VAD2 VAD1 VAD0

FC_VAD3 FC_VAD2 FC_VAD1 FC_VAD0

CP507 22P*4/NA 1206

CP508 22P*4/NA 1206

CP509 22P*4/NA 1206

CPUAVSS

CP510 22P*4/NA 1206

CP511 22P*4/NA 1206

CP512 22P*4/NA 1206

BHSYNC

R29

2 22

VBHSYNC

VBHSYNC 9

5 6 7 8

5 6 7 8

GND 5 6 7 8 5 6 7 8 L15 PHYAVDD 1 120Z/100M 2012 C79 0.1U 0603 50V JL502 1 2 JP_NET20 2 +3VS GND GND GND GND 1 C80 10U 1206 10V CPUAVSS CPUAVDD HPCOMP HNCOMP HNCVREF PHYAVSS PHYAVDD HVREF VBD7 VBD6 VBD5 VBD4 VBD3 VBD2 VBD1 VBD0 VAD6 VAD5 VAD4 VAD7 VAD8 VAD9 VAD10 VAD11 VADE AVSYNC AHSYNC VBD11 VBD10 VBD8 VBD9 VAD1 VAD0 VAD2 VAD3 VBDE VBCTL0 VBCTL1 BHSYNC BVSYNC GND GND BVSYNC R24 1 2 22 VBVSYNC VBVSYNC 9 5 6 7 8

C77 0.01U 0603

PHYAVSS

5 6 7 8

GND

AH25 AJ25

AH27 AJ27

U21 T21 P21 N21 J17

A7 F9 B7 M6 M5 M4 L3 L6 L4 K6 L2 K3 J3 K4 J2 J6 J4 J1 H6 F4 F1 G6 E3 F5 E2 E4 E1 D3 D4 C2 F7 C3 E6 B2 D5

D6 A3 D7 C5 A5 C6 D8 C7

U4A
B

B20 B19 A19

BCLK

+VCC_CORE 11 HCLK_SIS650 11 HCLK_SIS650# 4 4 4 4 4 4 4 H_RS#[0..2] H_LOCK# H_DEFER# H_TRDY# CPURST# CPUPWRGD H_BPRI# H_BR#0 H_LOCK# H_DEFER# H_TRDY# CPURST# CPUPWRGD H_BPRI# H_BR#0 H_RS#2 H_RS#1 H_RS#0 4 4 4 4 4 4 H_REQ#[0..4] H_ADS# H_HITM# H_HIT# H_DRDY# H_DBSY# H_BNR# H_ADS# H_HITM# H_HIT# H_DRDY# H_DBSY# H_BNR# H_REQ#4 H_REQ#3 H_REQ#2 H_REQ#1 H_REQ#0 H_ADSTB#1 H_ADSTB#0 H_ADSTB#1 H_ADSTB#0 HA#31 HA#30 HA#29 HA#28 HA#27 HA#26 HA#25 HA#24 HA#23 HA#22 HA#21 HA#20 HA#19 HA#18 HA#17 HA#16 HA#15 HA#14 HA#13 HA#12 HA#11 HA#10 HA#9 HA#8 HA#7 HA#6 HA#5 HA#4 HA#3 1 1 AJ26 AH26 U24 U26 V26 C20 D19 T27 U25 T24 T26 U29 V28 T28 U28 W26 V24 V27 W28 W29 W24 W25 Y27 AD24 AA24 AF26 AE25 AH28 AD26 AG29 AE26 AF28 AC24 AG28 AE29 AD28 AC25 AD27 AE28 AF27 AB24 AB26 AC28 AC26 AC29 AA26 AB28 AB27 AA25 AA29 AA28 Y26 Y24 Y28 CPUCLK CPUCLK# HLOCK# DEFER# HTRDY# CPURST# CPUPWRGD BPRI# BREQ0# RS2# RS1# RS0# ADS# HITM# HIT# DRDY# DBSY# BNR# HREQ4# HREQ3# HREQ2# HREQ1# HREQ0# ADSTB1# ADSTB0# HA31# HA30# HA29# HA28# HA27# HA26# HA25# HA24# HA23# HA22# HA21# HA20# HA19# HA18# HA17# HA16# HA15# HA14# HA13# HA12# HA11# HA10# HA9# HA8# HA7# HA6# HA5# HA4# HA3#

BCLK AC/BE3# AC/BE2# AC/BE1# AC/BE0# AREQ#/VBCAD AGNT# AFRAME# AIRDY# ATRDY# ADEVSEL# ASERR# ASTOP# APAR RBF#/VBHCLK WBF#/VGPIO2 PIPE#/VGPIO3 AGP8XDET ADBIH ADBIL SB_STB SB_STB# AD_STB0/VAGCLK AD_STB0#/VAGCLK# AD_STB1/VBGCLK AD_STB1#/VBGCLK# AGPCLK AGPRCOMP AGPAVDD1 AGPVSS1 AGPVDD2 AGPVSS2 AGPVERF AGPVSSREF DSTBN3# DSTBN2# DSTBN1# DSTBN0# DSTBP3# DSTBP2# DSTBP1# DSTBP0# F6 F3 H4 K5 C9 A6 G2 G1 G3 G4 H5 H1 H3 E8 F8 D9 D10 B3 C4 B5 A4 K1 L1 C1 D1 B10 M1 B9 A9 B8 A8 M3 M2 F20 F23 K24 P24 F21 F24 L24 N25 AGCLK AGCLK# BGCLK BGCLK# AGP_CLK AGPRCOMP AGPAVDD1 AGPAVSS1 AGPAVDD2 AGPAVSS2 AGPVREF GND DSTBN#3 DSTBN#2 DSTBN#1 DSTBN#0 DSTBP#3 DSTBP#2 DSTBP#1 DSTBP#0 DSTBN#[0..3] AGP_CLK 11 BGCLK# R34 1 BHCLK BCAD R22 1 R108 1 R110 1 2 0 2 0/NA 2 0/NA VBHCLK VBCAD R19 1 2 0 VBCAD 9

R23

ST0 ST1 ST2 AD0/VBD7 AD1/VBD6 AD2/VBD5 AD3/VBD4 AD4/VBD3 AD5/VBD2 AD6/VBD1 AD7/VBD0 AD8/VAD6 AD9VAD5 AD10/VAD4 AD11/VAD7 AD12/VAD8 AD13/VAD9 AD14/VAD10 AD15/VAD11 AD16/VADE AD17/VAVSYN AD18/VAHSYNC AD19/VBD11 AD20/VBD10 AD21/VBD8 AD22/VBD9 AD23/VAD1 AD24/VAD0 AD25/VAD2 AD26/VAD3 AD27/VBDE AD28/VBCTL0 AD29/VBCTL1 AD30/VBHSYNC AD31/VBVSYNC

CPUAVSS CPUAVDD

PHYAVSS PHYAVDD

HPCOMP HNCOMP HCOMPVREF

HVREF0 HVREF1 HVREF2 HVREF3 HVREF4

R562 75 0603D 1% 2

C638 0.01U 0603 HVREF

H_RS#[0..2]

R563 150 0603D 1% 2

C628 0.01U 0603

C597 0.1U 0603 50V

Place this cap under 650 solder side

SBA7 SBA6 SBA5 SBA4 SBA3 SBA2 SBA1 SBA0

2 22

VBCLK

VBCLK

VBHCLK VBCAD

9 9

GND

H_REQ#[0..4]

BGCLK

R33

2 22

VBGCLK

VBGCLK

+VCC_CORE 4 4 HA#[3..31]

R21 150 0603D 1%


C

C26 0.01U 0603 HNCVREF

HA#[3..31]

2 22/NA VBGCLK#

VBGCLK# 9
C

1 R62 301 0603 1% AGPVREF 1 1 C56 0.1U 0603 50V 2 R57 200 0603 1% 2

R25 75 0603D 1%

C27 0.01U 0603

+3VS

GND

DSTBN#[0..3] 4

R50 AGPRCOMP 1 60.4 1% 2 0603D

+3VS

DSTBP#[0..3]

DSTBP#[0..3] 4

60 OHM 1%
L507 +3VS 2

+VCC_CORE 1 20

R544 2 1% 0603D HNCOMP

AGPAVDD1 HD63# HD62# HD61# HD60# HD59# HD58# HD57# HD56# HD55# HD54# HD53# HD52# HD51# HD50# HD49# HD48# HD47# HD46# HD45# HD44# HD43# HD42# HD41# HD40# HD39# HD38# HD37# HD36# HD35# HD34# HD33# HD32# HD31# HD30# HD29# HD28# HD27# HD26# HD25# HD24# HD23# HD22# HD21# HD20# HD19# HD18# HD17# HD16# HD15# HD14# HD13# HD12# HD11# HD10# HD9# HD8# HD7# HD6# HD5# HD4# HD3# HD2# HD1# HD0# DBI3# DBI2# DBI1# DBI0#

1 120Z/100M 2012 C29 0.1U 0603 50V JL503 1 2

B21 F19 A21 E19 D22 D20 B22 C22 B23 A23 D21 F22 D24 D23 C24 B24 E25 E23 D25 A25 C26 B26 B27 D26 B28 E26 F28 G25 F27 F26 G24 H24 G29 J26 G26 J25 H26 G28 H28 J24 K28 J29 K27 J28 M24 L26 K26 L25 L28 M26 P26 L29 N24 N26 M27 N28 P27 N29 R24 R28 M28 P28 R26 R29

E21 A27 H27 R25

R20 1 GND 110 1% 2 0603D HPCOMP

SIS650 BGA540_77_85 AGPAVSS1

C34 0.01U 0603

1 2

GND

C559 10U 1206 10V

HD#63 HD#62 HD#61 HD#60 HD#59 HD#58 HD#57 HD#56 HD#55 HD#54 HD#53 HD#52 HD#51 HD#50 HD#49 HD#48 HD#47 HD#46 HD#45 HD#44 HD#43 HD#42 HD#41 HD#40 HD#39 HD#38 HD#37 HD#36 HD#35 HD#34 HD#33 HD#32 HD#31 HD#30 HD#29 HD#28 HD#27 HD#26 HD#25 HD#24 HD#23 HD#22 HD#21 HD#20 HD#19 HD#18 HD#17 HD#16 HD#15 HD#14 HD#13 HD#12 HD#11 HD#10 HD#9 HD#8 HD#7 HD#6 HD#5 HD#4 HD#3 HD#2 HD#1 HD#0

L511 AGPAVDD2
D

+3VS 2 4 HD#[0..63]

DBI#3 DBI#2 DBI#1 DBI#0

112 OHM 1%
HD#[0..63]

JP_NET20 GND DBI#[0..3] 4


D

DBI#[0..3]

1 120Z/100M 2012 C28 0.1U 0603 50V JL504 1 2

C33 0.01U 0603

C563 10U 1206 10V

AGCLK

R42

2 22 1

VAGCLK C43 10P 0603 10% GND

VAGCLK

AGCLK#

R45

2 22/NA 1

VAGCLK# C50 10P/NA 0603 10% GND

VAGCLK# 9

AGPAVSS2

VADE VBDE

VADE VBDE

9 9

JP_NET20 2 GND

VBCTL0 VBCTL1

VBCTL0 VBCTL1

9 9

Title Size C Date:

8575A SIS650 (1/3) Document Number Rev 01 of


8

BD 311671700001 & TU 411671700011 Sheet 6 30

Monday, June 17, 2002

SIS650(2/3)
12 DDR_MD[0..63] U4B DDR_MD0 DDR_MD1 DDR_MD2 DDR_MD3 DDR_MD4 DDR_MD5 DDR_MD6 DDR_MD7 DDR_DQM0 DDR_MD8 DDR_MD9 DDR_MD10 DDR_MD11 DDR_MD12 DDR_MD13 DDR_MD14 DDR_MD15 DDR_MD16 DDR_MD17 DDR_MD18 DDR_MD19 DDR_MD20 DDR_MD21 DDR_MD22 DDR_MD23 DDR_MD24 DDR_MD25 DDR_MD26 DDR_MD27 DDR_MD28 DDR_MD29 DDR_MD30 DDR_MD31 DDR_MD32 DDR_MD33 DDR_MD34 DDR_MD35 DDR_MD36 DDR_MD37 DDR_MD38 DDR_MD39 DDR_MD40 DDR_MD41 DDR_MD42 DDR_MD43 DDR_MD44 DDR_MD45 DDR_MD46 DDR_MD47 DDR_MD48 DDR_MD49 DDR_MD50 DDR_MD51 DDR_MD52 DDR_MD53 DDR_MD54 DDR_MD55 DDR_MD56 DDR_MD57 DDR_MD58 DDR_MD59 DDR_MD60 DDR_MD61 DDR_MD62 DDR_MD63 DDR_DQS0 AJ23 AG22 AH21 AJ21 AD23 AE23 AF22 AF21 AD22 AH22 AD21 AG20 AE19 AF19 AE21 AD20 AD19 AH19 AF20 AH20 AF18 AG18 AH17 AD16 AD18 AD17 AF17 AJ17 AE17 AH18 AD14 AG14 AJ13 AE13 AJ15 AF14 AD13 AF13 AH13 AH14 AD10 AH10 AE9 AD8 AG10 AF10 AH9 AF9 AD9 AJ9 AH5 AG4 AE5 AH3 AG6 AF6 AF5 AF4 AH4 AJ3 AE4 AD6 AE2 AC5 AG2 AG1 AF3 AC6 AD4 AF2 AB6 AD3 AA6 AB3 AC4 AE1 AD2 AC1 AB4 AC2 MD0/SMD63 MD1/SMD30 MD2/SMD29 MD3/SMD59 MD4/SMD31 MD5/SMD62 MD6/SMD60 MD7/SMD28 DQM0/SMD61 DQS0/CSB0# MD8/SMD27 MD9/SMD58 MD10/SMD55 MD11/SMD23 MD12/SMD26 MD13/SMD57 MD14/SMD56 MD15/SMD24 DQM1/SMD25 DQS1/CSB1# MD16/SMD22 MD17/SMD53 MD18/SMD20 MD19SMD19 MD20/SMD54 MD21/SMD21 MD22/SMD51 MD23/SMD50 DQM2/SMD52 DQS2/CSB2# MD24/SMD18 MD25/SMD17 MD26/SDQM7 MD27/SDQM6 MD28/SMD49 MD29/SMD48 MD30/SDQM3 MD31/SDQM2 DQM3/SMD16 DQS3/CSB3# MD32/SDQM5 MD33/SDQM4 MD34/SMD47 MD35/SMD45 MD36/SDQM1 MD37/SDQM0 MD38/SMD46 MD39/SMD14 DQM4/SMD15 DQS4/CSB4# MD40/SMD13 MD41/SMD43 MD42/SMD42 MD43/SMD10 MD44/SMD44 MD45/SMD12 MD46/SMD41 MD47/SMD9 DQM5/SMD11 DQS5/CSB5# MD48/SMD40 MD49/SMD8 MD50/SMD37 MD51/SMD36 MD52/SMD39 MD53/SMD7 MD54/SMD6 MD55/SMD5 DQM6//SMD38 DQS6/CSB6# MD56/SMD35 MD57/SMD34 MD58/SMD1 MD59/SMD0 MD60/SMD4 MD61/SMD3 MD62/SMD33 MD63/SMD32 DQM7/SMD2 DQS7/CSB7# SIS650 BGA540_77_85
A

U4C MA0 MA1 MA2 MA3 MA4 MA5 MA6 MA7 MA8 MA9 MA10 MA11 MA12 MA13 MA14 SRAS# SCAS# SWE# AH11 AF12 AH12 AG12 AD12 AH15 AF15 AH16 AE15 AD15 AF11 AG8 AJ11 AG16 AF16 AH8 AJ7 AH7 DDR_MA0 DDR_MA1 DDR_MA2 DDR_MA3 DDR_MA4 DDR_MA5 DDR_MA6 DDR_MA7 DDR_MA8 DDR_MA9 DDR_MA10 DDR_MA11 DDR_MA12 DDR_BA0 12 DDR_BA1 12 DDR_MA[0..12] 12 11 14 14 14 14 14 14 14 MA11 --> BANK SELECT 0 MA12 --> BANK SELECT 1 MA13 --> MEM_MA11 MA14 --> MEM_MA12 ZCLK0 ZUREQ ZDREQ ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZAD[0..15] V3 U6 U1 T3 T1 P1 P3 ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZVREF 8 7 6 5 470*4 1206 VDDZCMP ZCMP_N ZCMP_P VSSZCMP Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS T4 R3 T5 T6 R2 R6 R1 R4 P4 N3 P5 P6 N1 N6 N2 N4 U3 V5 U4 U2 V6 W1 W2 V2 V1 ZCLK ZUREQ ZDREQ ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZVREF VDDZCMP ZCMP_N ZCMP_P VSSZCMP A10 TESTMODE2 F11 TESTMODE1 C11 TESTMODE0 Z1XAVDD Z1XAVSS Y3 PCIRST# W4 PWROK W6 AUXOK D11 TRAP1 E10 TRAP0 Z4XAVDD Z4XAVSS VOSCI C15 REFCLK0 11

12 DDR_DQS[0..7]

ROUT GOUT BOUT HSYNC VSYNC VGPIO0 VGPIO1 INTA# CSYNC RSYNC LSYNC VCOMP VRSET VVBWN DACAVDD1 DACAVSS1 DACAVDD2 DACAVSS2 DCLKAVDD DCLKAVSS E11 DLLEN# F10 ENTEST ECLKAVDD ECLKAVSS

A12 B13 A13 F13 E13 D13 D12 B11 E12 A11 F12 E14 D14 F14 B12 C12 C13 C14 B15 A15 B14 A14 PID1 RSYNC PID2 VCOMP VRSET VVBWN DACAVDD1 DACAVSS1 DACAVDD2 DACAVSS2 DCLKAVDD DCLKAVSS ECLKAVDD ECLKAVSS R546 1 R547 1 R548 1 R566 1 2 33 2 33 2 100 2 100

CRT_RED 10 CRT_GREEN 10 CRT_BLUE 10 CRT_HSYNC 10 CRT_VSYNC 10 CRT_DDCK 10 CRT_DDDA 10 PCI_INTA# 9,14,17

ZAD[0..15]

DDR_DQM1 DDR_DQS1

DDR_RAS# 12 DDR_CAS# 12 DDR_WE# 12

DDR_DQM2 DDR_DQS2

CS0# CS1# CS2# CS3# CS4# CS5#

AE7 AF7 AH6 AJ5 AF8 AD7

1 1

DDR_CS0# DDR_CS1# DDR_CS2# DDR_CS3# TP513 TP511

12 12 12 12 CKE3 CKE2 CKE0 CKE1 1 2 3 4

+2.5V_DDR RP7

DDR_DQM3 DDR_DQS3

CKE0 CKE1 CKE2 CKE3 CKE4 CKE5 S3AUXSW# SDCLK FWDSDCLKO SDRCLKI

AB2 AA4 AB1 Y6 AA5 Y5 Y4 AA3 AD11 AE11

1 1 S3AUXSW#

TP510 TP509

CKE0 CKE1 CKE2 CKE3

12 12 12 12

S3AUXSW# 15,22 SDRAMCLK 11 C691 FWDSDCLKO 1 2 10P/NA 0603 GND

DDR_DQM4 DDR_DQS4

R614 1

2 22

SIS650 BGA540_77_85

FWDSDCLKO 11

DDR_DQM5 DDR_DQS5

SDAVDD SDAVSS

Y1 Y2

SDAVDD SDAVSS

GND

9,14,17,18,21,28,29 -PCIRST 15 PWROK 15 AUXOK TP6 TP508 TP7 1 1 1

PID0 TRAP0

1 R554 4.7K 0603D 2 GND +3VS 2

C654 1 0.1U C667 1 0.1U GND

2 50V 0603 2 50V 0603

PWROK AUXOK

DLLEN#

DDRAVDD DDRAVSS

AA1 AA2

DDRAVDD DDRAVSS

DDR_DQM6 DDR_DQS6

DDRVREFA DDRVREFB DRAM_SEL

AJ19 AH2 W3

DDRVREFA DDRVREFB DRAM_SEL ECLKAVDD

L506 1 120Z/100M 2012 C30 0.1U 0603 50V JL505 1 2 JP_NET20 A RLS4148 D15 2

+3VS DCLKAVDD 1

L505

DDR_DQM7 DDR_DQS7
C

C35 0.01U 0603

C562 10U 1206 10V DCLKAVSS GND

C36 0.01U 0603

ECLKAVSS D14 22 H8_PWROK K

120Z/100M 2012 C31 0.1U 0603 50V JL506 1 2 JP_NET20

C561 10U 1206 10V DLLEN# DRAM_SEL TRAP0 GND TRAP1 CSYNC RSYNC LSYNC

NB Hardwre Trap Table


0
Enable PLL SDR PANEL ID0
Video Bridge Disable/Enable (0/1)

1
Disable PLL DDR

Default 0 1(DDR) 0 0 0 1 0

650 Debug Mode Disable/Enable (0/1)

embedded pull-low (3050K Ohm) Yes Yes Yes

12 DDR_DQM[0..7]

DDR_DQM0 DDR_DQM1 DDR_DQM2 DDR_DQM3 DDR_DQM4 DDR_DQM5 DDR_DQM6 DDR_DQM7 DDRVREFA L516

+2.5V_DDR

+1.8VS

PANEL ID1 PANEL ID2

C600 VVBWN 1 2 0.1U C593 VCOMP 3 0603D 1 DACAVDD1 C223 0.1U 0603 50V DACAVDD2 1 120Z/100M 2012 C584 1U 0603 1 JL509 2 JP_NET20 GND 1 2 0.1U 50V L514 2 1 +1.8VS VRSET 50V DLLEN# DRAM_SEL TRAP0 RSYNC R570 R599 R571 R18 1 1 1 1 2 2 2 2 4.7K/NA 4.7K 4.7K/NA 4.7K +3VS

C689 0.01U 0603D 2

R613 150 0603D 1% 2

R557 150 0603D 1%

C595 0.1U 0603D 50V ZVREF

26

H_PWRGD

A +3VS RLS4148 U12 MAX809 2 RESET# GND

0603D

SOT23N VCC

15

PWROK

PWROK

DDRAVDD

1 120Z/100M 2012 C624 0.1U 0603 50V JL507 1 2

2 2

C688 0.01U 0603D

+3VS

C623 0.01U 0603

C632 10U 1206 10V

GND

GND GND

GND

GND 2 DACAVSS2 DACAVSS1

C583 0.1U 0603D 50V

R612 150 0603D 1% 2 2

R553 150 0603D 1%

C589 0.1U 0603D 50V

1 R145 100K 0603 2

C580 10U 1206 10V 2

R545 130 1% 0603D

DDRAVSS

JP_NET20

GND

+2.5V_DDR

PID0 PID1

R828 1 0 R829 1 0 R830 1 0

0603D_DFS 2 0603 2 0603D_DFS 2 0603D_DFS

LCD_ID0 LCD_ID1 LCD_ID2

LCD_ID0 LCD_ID1 LCD_ID2

10 10 10
D

L13 SDAVDD 1 120Z/100M C692012 0.1U 0603 50V JL510 1 2 JP_NET20 2

+3VS

C692 0.01U 0603D 2

R616 150 0603D 1% VDDZCMP ZCMP_N R615 150 0603D 1% 2 ZCMP_P VSSZCMP R587 1 R596 1 2 56 2 56 2 1

PID2 L518 2 +1.8VS Z4XAVDD 1 120Z/100M 2012 C66 0.1U 0603 50V JL512 1 2 JP_NET20 GND
3 4 5

L12 2

+3VS Z1XAVDD 1

L515 2

+3VS

DDRVREFB C71 10U 1206 10V 1 1 1 1 C693 0.01U 0603D C641 0.01U 0603

C70 0.01U 0603

SDAVSS

GND GND

120Z/100M 2012 C637 0.1U 0603 50V JL511 1 2 JP_NET20

C630 10U 1206 10V Z4XAVSS

C67 0.01U 0603

C63 10U 1206 10V Z1XAVSS GND

C606 0.01U 0603

120Z/100M 2012 C607 0.1U 0603 50V JL513 1 2 JP_NET20

1 2

C599 10U 1206 10V Title Size C Date:


7

8575A SIS650 (2/3) Document Number Rev 01 of


8

GND
6

BD 311671700001 & TU 411671700011 Sheet 7 30

Monday, June 17, 2002

SIS650(3/3)
+1.8VS
A

+3VS

+3V
A

+VCC_CORE

+3VS +3V +1.8V C635 +1.8V H21 H22 J16 J20 J21 J22 K16 K17 K18 K19 K20 K21 L20 M20 N20 P20 R20 R21 T20 U20 V20 W20 Y20 Y21 AA20 AA21 AA22 AB21 AB22 L12 L14 L15 L16 L18 M11 M19 N11 P19 R11 T19 U11 V19 W11 W13 W15 W17 +VCC_CORE A16 A17 A18 B16 B17 B18 C16 C17 C18 D15 D16 D17 D18 E15 E16 E17 E18 F15 F16 F17 F18 AB5 AD5 AE6 AE8 AE10 AE12 AE14 AE16 AE18 AE20 AE22 V10 V11 W18 Y9 Y10 Y12 Y14 Y16 Y18 Y19 AA8 AA9 AA10 AA13 AA14 AA15 AA16 AA17 AB8 AB9 AB13 AB17 E5 E7 E9 G5 J5 L5 H8 H9 J8 J9 J10 J13 K9 K11 K13 L10 N9 N10 N5 R5 U5 W5 P9 P10 R9 R10 T9 T10 T11 W10 Y11 Y13 Y15 Y17 J14 J15 K15 K10 K12 K14 M10 P11 +3V FOR AUX1.8 1 2 0.1U GND FOR AUX3.3 & PVDDM C558 1 C658 C653 1 1 2 1U 0603 C611 1 C612 1 GND C619 1 2 10U 2 1U 0603 2 0.1U 2 0.1U GND

2 0.1U

U4D VTT_0 VTT_1 VTT_2 VTT_3 VTT_4 VTT_5 VTT_6 VTT_7 VTT_8 VTT_9 VTT_10 VTT_11 VTT_12 VTT_13 VTT_14 VTT_15 VTT_16 VTT_17 VTT_18 VTT_19 VTT_20

IVDD_0 IVDD_1 IVDD_2 IVDD_3 IVDD_4 IVDD_5 IVDD_6 IVDD_7 IVDD_8 IVDD_9 IVDD_10 IVDD_11 IVDD_12 IVDD_13 IVDD_14 IVDD_15 IVDD_16

PVDDM_0 PVDDM_1 PVDDM_2 PVDDM_3 PVDDM_4

PVDDZ

OVDD_0 OVDD_1 OVDD_2 PVDD_0 PVDD_1 PVDD_2 PVDD_3

VTT_21 VTT_22 VTT_23 VTT_24 VTT_25 VTT_26 VTT_27 VTT_28 VTT_29 VTT_30 VTT_31 VTT_32 VTT_33 VTT_34 VTT_35 VTT_36 VTT_37 VTT_38 VTT_39 VTT_40 VTT_41 VTT_42 VTT_43 VTT_44 VTT_45 VTT_46 VTT_47 VTT_48 VTT_49

AUX1.8 AUX3.3 VSS_0 VSS_1 VSS_2 VSS_3 VSS_4 VSS_5 VSS_6 VSS_7 VSS_8 VSS_9 VSS_10 VSS_11 VSS_12 VSS_13 VSS_14 VSS_15 VSS_16 VSS_17 VSS_18 VSS_19 VSS_20 VSS_21 VSS_22 VSS_23 VSS_24 VSS_25 VSS_26 VSS_27 VSS_28 VSS_29 VSS_30 VSS_31 VSS_32 VSS_33 VSS_34 VSS_35 VSS_36 VSS_37 VSS_38 VSS_39 VSS_40 VSS_41 VSS_42 VSS_43 VSS_44 VSS_45 VSS_46 VSS_47 VSS_48 VSS_49 VSS_50 VSS_51 VSS_52 VSS_53 VSS_54 VSS_55 VSS_56 VSS_57 VSS_58 VSS_59 VSS_60 VSS_61 VSS_62 VSS_63 VSS_64 VSS_65 VSS_66 VSS_67 VSS_68 VSS_69 VSS_70 VSS_71 VSS_72 VSS_73 VSS_74 VSS_75 VSS_76 VSS_77 VSS_78 VSS_79 VSS_80 VSS_81 VSS_82 VSS_83 VSS_84

U10 U9 A20 A22 A24 A26 C19 C21 C23 C25 C27 E20 E22 E24 F25 H25 K25 M25 P25 T25 V25 Y25 AB25 AD25 E27 G27 J27 L27 N27 R27 U27 W27 AA27 AC27 AE27 D29 F29 H29 K29 M29 P29 T29 V29 Y29 AB29 AD29 AF29 AE24 AG25 B4 B6 C8 C10 D2 F2 H2 K2 P2 T2 V4 AD1 AF1 AC3 AE3 AG3 AG5 AG7 AG9 AG11 AG13 AG15 AG17 AG19 AG21 AG23 AJ4 AJ6 AJ8 AJ10 AJ12 AJ14 AJ16 AJ18 AJ20 AJ22 AJ24 AG27

FOR OVDD & PVDD

+VCC_CORE +1.8VS C565 1 C603 1 C665 1 C590 1 2 10U 2 10U 2 10U 2 10U C605 1 C633 1 C644 1 C616 1 2 1U 0603 2 1U 0603 2 1U 0603 2 1U 0603 C629 1 C585 1 C586 1 C596 1 2 0.1U 2 0.1U 2 0.1U 2 0.1U C608 1 C677 1 2 0.1U 2 0.1U C631 1 C647 1 C634 1 C617 1 2 10U 2 1U 0603 2 0.1U 2 0.1U
B

+2.5V_DDR

+3VS
C

VDDM_0 VDDM_1 VDDM_2 VDDM_3 VDDM_4 VDDM_5 VDDM_6 VDDM_7 VDDM_8 VDDM_9 VDDM_10 VDDM_11 VDDM_12 VDDM_13 VDDM_14 VDDM_15 VDDM_16 VDDM_17 VDDM_18 VDDM_19 VDDM_20 VDDM_21 VDDM_22 VDDM_23 VDDM_24 VDDM_25 VDDM_26 VDDM_27 VDDM_28 VDDM_29 VDDM_30 VDDM_31 VDDM_32 VDDQ_0 VDDQ_1 VDDQ_2 VDDQ_3 VDDQ_4 VDDQ_5 VDDQ_6 VDDQ_7 VDDQ_8 VDDQ_9 VDDQ_10 VDDQ_11 VDDQ_12 VDDQ_13 VDDQ_14 VDDQ_15 VDDQ_16 VDDQ_17 VDDZ_0 VDDZ_1 VDDZ_2 VDDZ_3 VDDZ_4 VDDZ_5 VDDZ_6 VDDZ_7 VDDZ_8 VDDZ_9 VDDZ_10

GND

GND FOR VTT

GND

GND

GND

+3VS

+2.5V_DDR

C620 1 C594 1 C587 1 C598 1

2 0.1U 2 0.1U 2 0.1U 2 0.1U

C609 1

2 0.1U 1 1 1 1 C680 10U 1206 10V C674 10U 1206 10V C666 10U 1206 10V C659 10U 1206 10V C673 1 C672 1 C671 1 GND C670 1 2 1U 0603 2 1U 0603 2 0.1U 2 0.1U C669 1 C668 1 C682 1 C681 1 2 1U 0603 2 1U 0603 2 0.1U 2 0.1U

GND 2

GND FOR VDDQ

FOR VDDM

GND

GND

+1.8VS +VCC_CORE C591 1 C604 1 C626 1 C655 1 2 0.1U 2 0.1U 2 0.1U 2 0.1U +1.8VS C645 1 C621 1 C622 1 C639 1 2 0.1U 2 0.1U 2 0.1U 2 0.1U GND FOR VTT GND GND FOR VDDM C618 1 C613 1 2 0.1U 2 0.1U +2.5V_DDR C685 1 C690 1 C686 1 2 0.1U 2 0.1U 2 0.1U +3VS C646 1 C636 1 2 0.1U 2 1U 0603

+3V C649 1 C657 1 2 0.1U 2 0.1U

+1.8VS

GND

GND

PVDDP_0 PVDDP_1 PVDDP_2 PVDDP_3 PVDDP_4 PVDDP_5 L17 L19 N19 R19 U19 W19

M12 VSS_85 M13 VSS_86 M14 VSS_87 M15 VSS_88 M16 VSS_89 M17 VSS_90 M18 VSS_91 N12 VSS_92 N13 VSS_93 N14 VSS_94 N15 VSS_95 N16 VSS_96 N17 VSS_97 N18 VSS_98 P12 VSS_99 P13 VSS_100 P14 VSS_101 P15 VSS_102 P16 VSS_103 P17 VSS_104 P18 VSS_105 R12 VSS_106 R13 VSS_107 R14 VSS_108 R15 VSS_109 R16 VSS_110 R17 VSS_111 R18 VSS_112 T12 VSS_113 T13 VSS_114 T14 VSS_115 T15 VSS_116 T16 VSS_117 T17 VSS_118 T18 VSS_119 U12 VSS_120 U13 VSS_121 U14 VSS_122 U15 VSS_123 U16 VSS_124 U17 VSS_125 U18 VSS_126 V12 VSS_127 V13 VSS_128 V14 VSS_129 V15 VSS_130 V16 VSS_131 V17 VSS_132 V18 VSS_133 B25 VSS_134 C28 VSS_135 C29 VSS_136 D27 VSS_137 D28 VSS_138 E28 VSS_139 E29 VSS_140 AF23 VSS_141 AF24 VSS_142 AF25 VSS_143 AG24VSS_144 AG26VSS_145 AH23VSS_146 AH24VSS_147

SIS650 BGA540_77_85

GND GND
D

+1.8VS
D

GND

Title Size C Date:


1 2 3 4 5 6 7

8575A SIS650 (3/3) Document Number Rev 01 of


8

BD 311671700001 & TU 411671700011 Sheet 8 30

Monday, June 17, 2002

CLOSE TO CH7017 11 14.318MHZ_TV +DVDD R133 1 10K/NA 2 0603 R54 R53 R78 1 10K/NA 2 0603 1 10K/NA 2 0603 1 10K/NA 2 0603 R124 1 357K/NA 2 0603 R48 R47 R77 1 357K/NA 2 0603 1 1 357K/NA 2 0603 1 357K/NA 2 0603 2 1 0/NA 0603 1 14.318MHZ C610 22P 0603 5% R565 2 X501 2 1 C651 22P 0603 5% MOD_XOUT

SiS301LV/CH7019
R831 1 0 U522 1 2 3 4 XIN XOUT FS0 VSS P2010/NA SO8 GND +DAC_VDD 2 0603 1 2 3 4 75*4/NA 1206 RP508 8 7 6 5 GND 2 VDD SR0 MODOUT SSON 8 7 6 5 2 0603 MOD_XOUT +DVDD 1

Spread Range Selection


FS0 SR0 Spreading Range 1 0 +/- 1.50% 1 1 +/- 2.50% 0 +/- 1.25% 0 0 1 +/- 2.00% Input Frequency
10 MHz to 20 MHz 10 MHz to 20 MHz 20 MHz to 35 MHz 20 MHz to 35 MHz

Modulation Rate
(Fin/10)*20.83 KHz (Fin/10)*20.83 KHz (Fin/10)*20.83 KHz (Fin/10)*20.83 KHz

R593 1 10K/NA 2 0603

R592 1 357K/NA 2 0603 AS GPIO2 GPIO3 GPIO4 GPIO5

R832 1M/NA 0603 1 1 2 0/NA 2 0 0603 R600 1 GND 2 0 0603 2

1 R833 1M/NA 0603

7,14,17,18,21,28,29 -PCIRST

-PCIRST

R55 R59 6 VBCLK

R510 1 0 1 R511 75/NA 0603 2

6 +3VS 1 L541

VBDE

VBDE

FS0 and SR0 HAVE INTERNAL PULL_UP 100K Ohm


SiS301LV 01 02
TV_LUMA 27

CLOSE TO CH7017 6 VBCTL1 R603 1 2 0 0603

CH7019 75 ohm 4.7K ohm 0 ohm NA 10K ohm 10K ohm NA NA NA 0 ohm NA 140 ohm 2.4K ohm 10K ohm 10K ohm NA NA 0 ohm NA NA NA 75 ohm NA 0.1u 0.1u NA NA NA 0 ohm NA 10K ohm
B C

2 120Z/100M 2012

+TVPLL_VCC L542 1 120Z/100M 2012 1 2 JL539 +VDDV 2 +TVPLL_VDD C727 10U 1206 25V C697 0.1U 0603 C615 10U 1206 25V C627 1U 0603

R40 R51 R55 R59 R60 R63 R76 R79 R248 R541 R542 R549 R550 R586 R588 R589 R597 R598 R600 R602 R603 R834 R835 C32 C72 C307 C887 C888 R604 R601 R111

NA NA NA 0 ohm 0 ohm NA 0 ohm 0 ohm 0 ohm NA 0 ohm 147 ohm 6.04K ohm 0 ohm NA 0 ohm 0 ohm NA 0 ohm 0 ohm 0 ohm NA 2K ohm NA NA 0.1u 0.1u 1u NA 0 ohm NA PAGE 06

03 04 05 06 07 08
C564

+3VS

C602 0.1U 0603 50V

C625 0.1U 0603 50V

TP518

TV_CRMA 27

TVPLL_GND 1 R834 75/NA 0603 MOD_XOUT 2 C887 0.1U 0603 50V +DAC_VDD 2 R543 75 0603 R540 1 0/NA 1 2 U503 0805 5 4 +3VS L512 +DAC_VDD 1 1 U504 CH7017 PQFP128A_0.5MM 1 140 CH7019 R549 1 2 147 R550 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1 2 6.04K 2.4K CH7019 R835 1 2K TXOUT0TXOUT0+ TXOUT1TXOUT1+ TXOUT2TXOUT2+ TXCLKTXCLK+ R542 1 TX2OUT0TX2OUT0+ TX2OUT1TX2OUT1+ TX2OUT2TX2OUT2+ 2 0603 1 1U C888 2 0603 2 C581 0.1U 0603 50V C572 1U 0603 C567 10U 1206 25V 1 120Z/100M 2012 JL533 1 2 JP_NET20 1 1 1 1 C573 0.1U 0603 50V C574 1U 0603 C568 10U 1206 25V L508 2 120Z/100M 2012 JL534 1 2 JP_NET20 +3VS 2 AME8800AEEV/NA SOT25 2 NC0 NC1 GND0 VIN VOUT 1 2 3 1 1 +5VS

L528 1 120Z/100M 2012 2 1

JP_NET20 1 C740 10U 1206 25V C738 0.1U 0603 50V

TVPLL_GND +VREF1 1 2 C739 0.1U/NA 0603 R518 0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 2 1 2

09 10 11 12 13 14 15 16 17 18 19 20 21 22 23

2.2U/NA 0805C

L540 1
C

R559 2 1 10K/NA 0603

DVDD1 DE1 FLD/STL1 VREF1 VDDV P-OUT RESET* GPIO[5] GPIO[4] TVPLL_VDD TVPLL_VCC XO XI / FIN TVPLL_GND BCO/VSYNC C/HSYNC DAC_GND0 DACA[3] DACB[3] DACA[2[ DACB[2] DACA[1] DACB[1] DACA[0] DACB[0] DAC_GND1

120Z/100M 2012 6 6 6 6 VBVSYNC VBHSYNC VBCTL0 FC_VBD[0..11]

0603 10K CH7019

DAC_GND

R604 1 R597 1 FC_VBD[0..11] 2 0 0603

2 0/NA 0603 FC_VBD0 FC_VBD1 FC_VBD2 FC_VBD3 FC_VBD4 FC_VBD5

+DVDD 6 6 VBGCLK# VBGCLK

R9

2 0 0603

+DVDD 1 1 1 C652 10U 1206 25V C39 0.1U 0603

R8 C40 0.1U 0603

2 0/NA 0603

FC_VBD6 FC_VBD7 FC_VBD8 FC_VBD9 FC_VBD10 FC_VBD11 FC_VAD0 FC_VAD1 FC_VAD2 FC_VAD3 FC_VAD4 FC_VAD5

CLOSE TO CH7017 DGND +DVDD 6 6


B

R40

2 0 0603

VAGCLK# VAGCLK

FC_VAD6 FC_VAD7 FC_VAD8 FC_VAD9 FC_VAD10 FC_VAD11 FC_VAD[0..11]

FC_VAD[0..11] 6 VAHSYNC 6 VAVSYNC +3VS L519 1

65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102

V1 H1 DGND3 D1[0] D1[1] D1[2] D1[3] D1[4] D1[5] XCLK1* DGND2 XCLK1 D1[6] D1[7] D1[8] D1[9] D1[10] D1[11] DVDD3 DVDD2 D2[0] D2[1] D2[2] D2[3] D2[4] D2[5] XCLK2* DGND1 XCLK2 D2[6] D2[7] D2[8] D2[9] D2[10] D2[11] DGND0 H2 V2

SiS301LV/ Chrontel CH7019

ISET DAC_VDD VSWING LGND5 LDC0* LDC0 LVDD5 LDC1* LDC1 LGND4 LDC2* LDC2 LVDD4 LL1C* LL1C LGND3 LDC3* LDC3 LVDD3 LVDD2 LDC4* LDC4 LGND2 LDC5* LDC5 LVDD1 LDC6* LDC6 LGND1 LDC7* LDC7 LVDD0 LL2C* LL2C LGND0 LPLL_GND LPLLCAP LPLL_VDD

TXOUT0- 10 TXOUT0+ 10 TXOUT1- 10 TXOUT1+ 10 TXOUT2- 10 TXOUT2+ 10 TXCLKTXCLK+ 2 0 0603 TX2OUT0- 10 TX2OUT0+ 10 10 10

+LVDD3 LGND

R541 1 +LPLL_VDD +LVDD2 1 1

2 0/NA 0603 1 1

+LVDD0/1 L509 2 120Z/100M 2012 JL540 1 2 JP_NET20 L510 1 2 120Z/100M 2012

+3VS

24 25 26 27 28
+3VS

TX2OUT1- 10 TX2OUT1+ 10 TX2OUT2- 10 TX2OUT2+ 10

C578 0.1U 0603 50V

C570 1U 0603

C569 10U 1206 25V

LGND1 +LVDD0/1 1 1 C575 0.1U 0603 50V C576 1U 0603 1 C566 10U 1206 25V

29 30 31

TX2CLKTX2CLK+

TX2CLKTX2CLK+

10 10

JL541 1 2 JP_NET20 L513 1 2 1 120Z/100M 2012 1 JL537 2 JP_NET20 C560 0.1U 0603 50V +5VS +3VS

LGND2 +LPLL_VDD 1 1 1 C579 100P 0603 10% 2 50V 0603 2 0 0603 100 R74 1 0603 2 ENABKL ENAVDD C582 1U 0603 C571 10U 1206 25V

32 33 34 35 36 37 38
1 R104 4.7K/NA 0603 2 2 1 R81 4.7K/NA 0603

R45 R23 R19 R22 R108 R110 R34

NA 22 ohm 0 ohm 0 ohm NA NA NA

22 ohm NA NA NA 0 ohm 0 ohm 22 ohm

+DVDD 2 1 1 1

DVDD0 DE2 FLD/STL2 AS SPD SPC HIN VIN VREF2 SDD SDC DD1 DC1 DD2 DC2 V5V HOUT VOUT HPD HPINT* GPIO[0] GPIO[1] GPIO[2] GPIO[3] ENAVDD ENABKL

103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128

GPIOA GPIOB GPIOC GPIOD DD2 DC2

120Z/100M 2012 JL538 2 JP_NET20

C664 10U 1206 25V

C42 0.1U 0603

C640 0.1U 0603

14x20 LQFP

C307 1 0.1U R79 1 1 TP521

LPLLGND PCI_INTA# 7,14,17

HPD

DGND VADE R594 1 AS 2 0 0603

VADE

GPIO3 GPIO2 R278 0/NA 2 1 0603 R76 1 1 C72 0.1U/NA 0603 50V 1 C32 0.1U/NA 0603 50V

ENABKL ENAVDD

22,27 10

+VREF2 +3VS +3VS 1 120Z/100M 2012 1 1


A

2 0 0603

-PCIRST

7,14,17,18,21,28,29

DD2

R105

1 0/NA

2 0603

R106

2 33/NA 0603

GPIOC

L25 2 1

R113 0 0603 2 2

R52 4.7K 0603 6 6 VBCAD VBHCLK VBCAD VBHCLK 2 2

R51 4.7K/NA 0603

R123 1 2 10K/NA 0603 C75 0.1U 50V 0603

+5VS 1 C614 0.1U 0603 50V 1 C73 10U 1206 25V

DC2

R82

1 0/NA

VGA GPIOA GPIOB 0 0

YUV TV 0 1

SCART 1 0

Normal TV 1 1

2 0603

R84

2 33/NA 0603

GPIOD

R586 1 0603 R588 1

2 0

C55 27P/NA 0603 5%

2 10K/NA 0603 2 0 0603

+3VS GPIOA R115 1 R122 1 GPIOB R111 1 R112 1 2 10K/NA 0603 2 4.7K/NA 0603 2 4.7K/NA 0603 2 4.7K/NA 0603

+3VS

C51 27P/NA 0603 5%

R589 1

GPIOC
+3VS

0 0 Normal PAL 525I

0 1 PAL-M 525P

1 0 PAL-N 750P

1 1 Normal NTSC 1080I


Title Size C Date: 8575A TV/LVDS ENCODER (SiS301LV) Document Number BD 311671700001 & TU 411671700011 Sheet
1

GPIOD Normal TV YUV TV

+3VS

Rev 01 of 30

Monday, June 17, 2002

LCD & CRT INTERFACE


LED INDICATOR

3
+3V

2
+3V

D16 CDROM

D15 HDD

D13 NUM

D14 CAP

D15

+3V

-BATT_LED

14

14

R723 1 1M/NA 0603 2 1

D
22 -SCROLL 22 -NUM 22 -CAP

C810 1U 0603

C808 1U 0603

C807 1U 0603

+5VS

2 74AHC14_V/NA TSSOP14

4 74AHC14_V/NA TSSOP14

6 74AHC14_V/NA TSSOP14

R1 1

Q526

15,24,27

PSON

R1 1

3 DTC144TKA/NA Q527 DTC144TKA/NA

U516A

U516B

14

SCROLL

(NA D10,D8,D9,D11,D15,R586 ,R211,R212,R213,R96, For LCD 15")

U516C

R201 470 0603 2 2 D22 D20 D21 K K K

R157 470 0603 2

R156 470 0603

GND

GND 2

C802 4.7U/NA 0805C_1206 16V

GND

BATT_POWER#

A PG1102W A PG1102W A PG1102W +3V 1

R740 2 220K/NA 0603 +5VS

+3V +5VA 1 -BATT_LED R199 10K 0603 2 3 -BATT_LED 27 1 2 R869 10K 0603 Q17 DTC144TKA 1 15,28 MPCI_PD MPCI_PD 2 D23 K A PG1102W 2 R1 1 3 Q21 DTC144TKA GND U517

1 R264 470 0603 2 R1

74VHC164

22 LED_DATA

LED_DATA

1 2

A B

22 LED_CLK 22 -H8_RESET

LED_CLK -H8_RESET

8 9 7

CLK CLR GND

QA QB QC QD QE QF QG QH VCC

3 4 5 6 10 11 12 13 14 1 C809 0.1U 0603 50V

-SCROLL -NUM -CAP -AC_POWER BATT_POWER# -BATT_R -BATT_G -AC_POWER 27 -BATT_R -BATT_G 27 27 15 ACPILED ACPILED

74VHC164 TSSOP14

BATT_POWER#

LCD CONNECTOR

C
9 9 9 9 9 9 9 9 7 7 7 LCD_ID0 LCD_ID1 LCD_ID2 4 3 2 1 TX2CLK+ TX2CLKTX2OUT0+ TX2OUT0TX2OUT2+ TX2OUT2TXOUT2+ TXOUT2LCD_ID0 LCD_ID1 LCD_ID2 TX2CLK+ TX2CLK-

LCD
LCDVCC TXCLK+ TXCLKTX2OUT1+ TX2OUT1TXOUT0+ TXOUT0TXOUT1+ TXOUT11 RP1 2 3 4 1K*4 1206 8 7 6 5 +3VS

14" 330mA,15"800mA
2 F503mircoSMDC110 1 3 2 1

Q503 NDS9410

SO8 8 7 6 5

+3VS

LCDVCC

J3 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 GND1 GND2 MA/20PX2/ST ACES 87216-4000 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40

120Z/100M 2012 L504 1 2

C
CLOSE TO NDS 9410
1 C506 0.1U 0603 50V 1 2 C508 10U_NA 1206 10V 2

TXCLK+ TXCLK-

9 9

TX2OUT0+ TX2OUT0TX2OUT2+ TX2OUT2TXOUT2+ TXOUT2-

TX2OUT1+ 9 TX2OUT1- 9 TXOUT0+ 9 TXOUT0- 9 TXOUT1+ 9 TXOUT1- 9

C2 1000P 0603

C3 0.1U 0603 50V

C509 1000P 0603

C510 10U 1206 10V

+12VS 1 2 R505 2 470K 0603

3 1

4 C507 0.1U 0603 50V Q2 R1 DTC144TKA ENAVDD 2

Close to LCD Connector

ENAVDD

RP40 10K*4 1206

5 6 7 8

Layout Note: DISPLAY UNIQAC HYUNDAI HANNSTAR CMO LCD_ID2 0 0 0 1 LCD_ID1 0 1 1 0 LCD_ID0 1 0 1 0
S/W/W/S=12/6/6/12 mils as short as possible

+5VS

U501

1 +5VS 2 3 F502 mircoSMDC110/NA 1 4

8 7 6 5

+5VS

+5VS 2 PACDN006/NA SSOP8 D2 3 16 1 9 2 10 3 11 4 12 5 13 6 14 7 15 8 +3VS JL1 1 5 6 7 8 5 6 7 8 2 SHORT-SMT3 JL501 2 SHORT-SMT3 GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15 GND_CRT15 1 C1 100P 0603 10% 2

R558 2.2K 0603 7 CRT_RED CRT_GREEN CRT_BLUE CRT_RED CRT_GREEN CRT_BLUE 2 2

R552 2.2K 0603

Close to VGA Connector


1 1 1 2 L503130Z/100M 2 L502130Z/100M 2 L501130Z/100M 1608 1608 1608

DDC2B 1Amp (40mil-60mil)

2 EC11FS2/NA D501 GND_CRT15 1 BAV99_NA

K DDC2B

W/S=16/12/12/12/16 mils

7 7

CRT_DDDA

CRT_DDDA Q502 D D S

Q505 D D S 2N7002

4 3 2 1

5 6 7 8 FA501 130OHM/100MHZ 4 3 2 1 4 3 2 1 1 CP501 22P*4 1206 CP502 22P*4 1206 C503 10U_NA 1206 10V

CRT_HSYNC

CRT_HSYNC Q501 D D S 2N7002 D 2N7002

5 6 7 8

Q506

CRT_VSYNC

CRT_VSYNC

CP1 22P*4/NA 1206

4 3 2 1

2N7002

4 3 2 1

Close to VGA Connector


RP502 75*4 1206

External VGA Connector


17

J2 VGA SUYIN 7535S-15G2T-05

CRT_DDCK

CRT_DDCK

S D S

R2 100K 0603 R1 1 1K 0603 2 CRT_IN# 15 GND_CRT15

5 6 7 8

Title GND_CRT15 Size Date:

8575A LCD/VGA INTERFACE Document Number BD 311671700001 & TU 411671700011 Rev 01 of 30

Monday, June 17, 2002

Sheet

10

+3VS L17 1 130Z/100M 1608 2 1 VDDREF C91 0.1U 0603 50V

CLOCK GEN/BUFFER
+3VS L23 1 2 1 VDDA48 U508 C113 0.1U 0603 50V VDDREF VDDZ VDDPCI R268 10K 0603 2 VDDA48 VDDAGP VDDCPU VDDSD A RLS4148/NA 1 11 13 19 28 29 42 48 12 45 5 8 18 24 25 32 41 46 VDDREF VDDZ VDDPCI0 VDDPCI1 VDDA48 VDDAGP VDDCPU VDDSD *PCI_STOP# CPU_STOP#* GNDREF GNDZ GNDPCI0 GNDPCI1 GND48 GNDAGP GNDCPU GNDSD
A

+3VS

GND 1

+3VS L19 1 130Z/100M 1608 2 1 VDDZ GND C96 0.1U 0603 50V 2

130Z/100M C114 1608 0.1U 0603 50V

CPUCLKT_0 CPUCLKC_0 CPUCLKT_1 CPUCLKC_1 SDRAM AGPCLK0 AGPCLK1 ZCLK0 ZCLK1 **FS3/PCICLK_F0 **FS4/PCICLK_F1 PCICLK0 PCICLK1 PCICLK2 PCICLK3 PCICLK4 PCICLK5

40 39 44 43 47 31 30 9 10 14 15 16 17 20 21 22 23 2 3 4 27 26 35 34

R644 R648 R635 R639 R632 R661 R641 R646 FS3 R668 FS4 R656 R660 R755 R756 FS0 FS1 FS2 R630 R633 R638 R625 R667 R670 R83 R658 R662

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 33 2 33 2 33 2 33 2 22 2 22 2 22 2 22 2 33 2 33 2 33 2 33 2 33 2 2 2 2 2 2 2 33 33 33 33 22 22 33

HCLK_CPU HCLK_CPU# HCLK_SIS650 HCLK_SIS650# SDRAMCLK AGP_CLK ZCLK0 ZCLK1 CLK_SBPCI CLK_LPC33 CLK_CARDPCI CLK_1394PCI CLK_MINIPCI REFCLK0 REFCLK1 14.318MHZ_AUDIO REFCLK3 USBCLK_SB CLK_SIO 14.318MHZ_TV SMBCLK SMBDATA

HCLK_CPU 4 HCLK_CPU# 4 HCLK_SIS650 6 HCLK_SIS650# 6 SDRAMCLK 7 AGP_CLK 6

CPU_STP# 15 CPU_STP# +3VS

K D520

CLOSE TO U525
R628 R629 1 1 2 33/NA 2 33/NA

R622 1

49.9/NA 1% 0603D 2

GND

R623 1

GND

49.9/NA 1% 0603D 2

+3VS L21 1 130Z/100M 1608 2 1 VDDAGP C107 0.1U 0603 50V 1 +3VS

+3VS 2

R875 10K 0603 GND

ZCLK0 ZCLK1

7 14

GND

CLK_SBPCI 14 CLK_LPC33 21 CLK_CARDPCI 18

USE WIRE JUMPING WHEN DEBUG PORT IS INSTALLED

1 R664 10K 0603 33 Q516 MMBT3904L GND +3VS GND 1 1 C715 120Z/100M 0.1U 2012 0603 50V L520 2 1 1 C719 0.1U 0603 50V C718 1000P 0603 36 VDDA E R85 1 2 475 1% 0603 38 2 PD#*/VTT_PWRGD IREF

CLK_1394PCI 29 CLK_MINIPCI 28

+VCC_CORE 1

R673 10K 0603 2

GND B 2
B

R678 10K 0603

**FS0/REF0 **FS1/REF1 **FS2/REF2

48MHZ 24_48MHZ/MULTISEL* SCLK SDATA

Q517 MMBT3904L E

REFCLK0 7 REFCLK1 15 14.318MHZ_AUDIO 20 REFCLK3 15 USBCLK_SB 16 CLK_SIO 21 14.318MHZ_TV 9 SMBCLK 12,15 SMBDATA 12,15

+3VS L16 1 130Z/100M 1608 2 1 VDDSD C90 0.1U 0603 50V

2 33 2 33

HCLK_CPU HCLK_CPU# HCLK_SIS650 HCLK_SIS650# SDRAMCLK

R645 R649 R636 R640

1 1 1 1

2 2 2 2

49.9 49.9 49.9 49.9

1% 1% 1% 1%

0603D 0603D 0603D 0603D

GND 2

C705 1 C711 1 C713 1 C724 1 C717 1 C721 1 C720 1 C703 1 C92 1

2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA

0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D

37

X1

X2

GNDA ICS952001 SSOP48

ZCLK0 ZCLK1 CLK_SBPCI CLK_LPC33 +3VS AGP_CLK CLK_CARDPCI SMBCLK SMBDATA 1 C702 10P 0603 5% R836 1 4.7K R837 1 4.7K 2 0603 2 0603 REFCLK3 14.318MHZ_AUDIO REFCLK0 REFCLK1 USBCLK_SB CLK_SIO GND

GND

GND 1 +3VS +3VS L20 1 1 1 130Z/100M 1608 2 1 1 C98 0.1U 0603 50V VDDPCI +3VS C108 0.1U 0603 50V 1 2 L18 1 130Z/100M 1608 2 1 VDDCPU C94 0.1U 0603 50V GND C85 22U 1210 10V C97 22U 1210 10V 1 C109 22U 1210 10V 2 1

X502 3 2 4 14.318MHZ C701 10P 0603 5%

C704 1 C706 1 C722 1 C725 1 C89 1

Layout note: Place crystal within 500 mils of CLK Gen.

14.318MHZ_TV CLK_1394PCI CLK_MINIPCI

C812 1 C813 1

GND
C

C95 0.1U 0603 50V

GND GND

U9 SMBCLK SMBDATA 7 22 20 8 3 12 23 10 6 11 15 28 R626 R624 R637 R669 R650 1 1 1 1 1 2 2 2 2 2 4.7K 4.7K 4.7K 4.7K 4.7K FS0 FS1 FS2 FS3 FS4 GND 21 18 9 SCLK SDATA FBINT CLK_INT VDD0 VDD1 VDD2 VDDA GND0 GND1 GND2 GND3 N/C0 N/C1 N/C2 ICS93722 SSOP28A FB_OUTT CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 19 2 1 4 5 13 14 17 16 24 25 26 27 R99 R90 R91 R89 R88 R94 R93 R98 R97 1 1 1 1 1 1 1 1 1 2 22 2 2 2 2 2 2 2 2 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 BF_OUT CLK_DDR0 CLK_DDR0# CLK_DDR1 CLK_DDR1# CLK_DDR2 CLK_DDR2# CLK_DDR3 CLK_DDR3# CLK_DDR4 CLK_DDR4# CLK_DDR5 CLK_DDR5# CLK_DDR0 12 CLK_DDR0# 12 CLK_DDR1 12 CLK_DDR1# 12 CLK_DDR2 12 CLK_DDR2# 12 CLK_DDR3 12 CLK_DDR3# 12 CLK_DDR4 12 CLK_DDR4# 12 CLK_DDR5 12 CLK_DDR5# 12 BF_OUT C196 1 2 10P 0603D

Bit 2 Bit 7 Bit 6 Bit 4 Bit 5

FS4 FS3 FS2 FS1 FS0


0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1

CPU (MHz)

SDRAM (MHz)

ZCLK (MHz)

AGP (MHz)

FWDSDCLKO

BF_OUT FWDSDCLKO CBVDD CBVDDA

CLK_DDR0 CLK_DDR0# CLK_DDR1 CLK_DDR1# CLK_DDR2 CLK_DDR2# CLK_DDR3 CLK_DDR3# CLK_DDR4 CLK_DDR4# CLK_DDR5

C104 1 C105 1 C103 1 C102 1 C135 1 C134 1 C195 1 C194 1 C197 1 C198 1 C199 1 C200 1

2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA 2 10P/NA

0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D 0603D
D

66.67 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 100.00 80.00 80.00 95.00 95.00 66.67

66.67 100.00 200.00 133.33 150.00 125.00 160.00 133.33 200.00 166.67 166.67 133.33 133.33 95.00 126.67 66.67

66.67 66.67 66.67 66.67 60.00 62.50 66.67 80.00 66.67 62.50 71.43 66.67 66.67 63.33 63.33 50.00

66.67 66.67 66.67 66.67 60.00 62.50 66.67 66.67 66.67 62.50 83.33 66.67 66.67 63.33 63.33 50.00
+2.5V_DDR L22 1 120Z/100M 2012 2 1 1 C111 0.1U 0603 50V GND +3VS

0 0 0 0 0 0 0 0

R100 1 R101 1 R102 1 R103 1

CLK_DDR5#

0 0 0 0 0

GND +2.5V_DDR CBVDDA 1 C101 1000P 0603 C99 10U 1206 10V 1 120Z/100M 2012 L24 2 1 1 C112 0.1U 0603 50V C150 0.1U 0603 50V 1 C110 0.1U 0603 50V CBVDD

Title Size C Date:

8575A MAIN CLOCK & CLOCK BUFFER Document Number Rev 01 of


8

GND
1 2 3 4

GND

BD 311671700001 & TU 411671700011 Sheet 11 30

Monday, June 17, 2002

7 7 7 7 7 7

DDR_WE# DDR_CAS# DDR_CS3# DDR_CS2# DDR_CS0# DDR_CS1#

DDR_WE# DDR_CAS# DDR_CS3# DDR_CS2# DDR_CS0# DDR_CS1#

RP13

1 2 3 4 5 6 7 8

0*8

16 15 14 13 12 11 10 9

RPX8

WE# CAS# CS3# CS2# CS0# CS1#

WE# CAS# CS3# CS2# CS0# CS1#

13 13 13 13 13 13

DDR SODIMM
+2.5V_DDR PLACE CLOSE TO J507 PLACE CLOSE TO J508 J505 MD0 MD1 DQS0 MD2 MD3 MD8 MD9 DQS1 7 7 7 7 CKE0 CKE1 CKE2 CKE3 CKE0 CKE1 CKE2 CKE3 MD10 MD11 CLK_DDR0 CLK_DDR0# 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 0.6MM/200P/H5.2 AMP1376408-1 R556 1K 0603 1% 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 MD4 MD5 DQM0 MD6 MD7 MD12 MD13 DQM1 MD14 MD15 +DDRVREF 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 0.6MM/200P/H5.2 AMP1376409-1 J506 MD0 MD1 DQS0 MD2 MD3 MD8 MD9 DQS1 MD10 MD11 CLK_DDR3 CLK_DDR3# 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200
4

+2.5V_DDR

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7

DDR_MA5 DDR_MA12 DDR_MA8 DDR_MA9 DDR_MA1 DDR_MA4 DDR_BA0 DDR_RAS# DDR_MA3 DDR_MA2 DDR_MA10 DDR_MA0 DDR_BA1 DDR_MA11 DDR_MA7 DDR_MA6

DDR_MA5 DDR_MA12 DDR_MA8 DDR_MA9 DDR_MA1 DDR_MA4 DDR_BA0 DDR_RAS# DDR_MA3 DDR_MA2 DDR_MA10 DDR_MA0 DDR_BA1 DDR_MA11 DDR_MA7 DDR_MA6

RP14

RP15

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

0*8

0*8

16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9

RPX8

RPX8

MA5 MA12 MA8 MA9 MA1 MA4 BA0 RAS# MA3 MA2 MA10 MA0 BA1 MA11 MA7 MA6

MA5 MA12 MA8 MA9 MA1 MA4 BA0 RAS# MA3 MA2 MA10 MA0 BA1 MA11 MA7 MA6

13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13

+DDRVREF

C106 0.1U 0603 50V

C130 1000P 0603

C148 0.1U 0603 50V

C588 1000P 0603

MD4 MD5 DQM0 MD6 MD7 MD12 MD13 DQM1 MD14 MD15

GND GND

GND

GND

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7

DDR_MD4 DDR_MD5 DDR_DQM0 DDR_MD0 DDR_MD1 DDR_DQS0 DDR_MD6 DDR_MD7 DDR_MD2 DDR_MD3 DDR_MD8 DDR_MD13 DDR_MD12 DDR_MD9 DDR_DQS1 DDR_DQM1 DDR_MD18 DDR_MD23 DDR_DQM2 DDR_MD22 DDR_MD21 DDR_MD19 DDR_MD24 DDR_MD29 DDR_MD30 DDR_MD27 DDR_MD28 DDR_MD25 DDR_DQS3 DDR_MD31 DDR_DQM3 DDR_MD26 DDR_MD39 DDR_MD38 DDR_MD45 DDR_MD44 DDR_MD40 DDR_DQM5 DDR_MD46 DDR_MD42 DDR_MD41 DDR_DQS5 DDR_MD43 DDR_MD47 DDR_MD49 DDR_MD55 DDR_MD48 DDR_MD54 DDR_MD52 DDR_DQM6 DDR_MD53 DDR_DQS6 DDR_MD50 DDR_MD51 DDR_MD57 DDR_MD61 DDR_MD62 DDR_MD60 DDR_DQM7 DDR_DQS7 DDR_MD63 DDR_MD59 DDR_MD56 DDR_MD58

DDR_MD4 DDR_MD5 DDR_DQM0 DDR_MD0 DDR_MD1 DDR_DQS0 DDR_MD6 DDR_MD7 DDR_MD2 DDR_MD3 DDR_MD8 DDR_MD13 DDR_MD12 DDR_MD9 DDR_DQS1 DDR_DQM1 DDR_MD18 DDR_MD23 DDR_DQM2 DDR_MD22 DDR_MD21 DDR_MD19 DDR_MD24 DDR_MD29 DDR_MD30 DDR_MD27 DDR_MD28 DDR_MD25 DDR_DQS3 DDR_MD31 DDR_DQM3 DDR_MD26 DDR_MD39 DDR_MD38 DDR_MD45 DDR_MD44 DDR_MD40 DDR_DQM5 DDR_MD46 DDR_MD42 DDR_MD41 DDR_DQS5 DDR_MD43 DDR_MD47 DDR_MD49 DDR_MD55 DDR_MD48 DDR_MD54 DDR_MD52 DDR_DQM6 DDR_MD53 DDR_DQS6 DDR_MD50 DDR_MD51 DDR_MD57 DDR_MD61 DDR_MD62 DDR_MD60 DDR_DQM7 DDR_DQS7 DDR_MD63 DDR_MD59 DDR_MD56 DDR_MD58

RP20

RP19

RP17

RP16

RP11

RP10

RP9

RP8

1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

10*8

10*8

10*8

10*8

10*8

10*8

10*8

10*8

16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9

RPX8

RPX8

RPX8

RPX8

RPX8

RPX8

RPX8

RPX8

MD4 MD5 DQM0 MD0 MD1 DQS0 MD6 MD7 MD2 MD3 MD8 MD13 MD12 MD9 DQS1 DQM1 MD18 MD23 DQM2 MD22 MD21 MD19 MD24 MD29 MD30 MD27 MD28 MD25 DQS3 MD31 DQM3 MD26 MD39 MD38 MD45 MD44 MD40 DQM5 MD46 MD42 MD41 DQS5 MD43 MD47 MD49 MD55 MD48 MD54 MD52 DQM6 MD53 DQS6 MD50 MD51 MD57 MD61 MD62 MD60 DQM7 DQS7 MD63 MD59 MD56 MD58

MD4 MD5 DQM0 MD0 MD1 DQS0 MD6 MD7 MD2 MD3 MD8 MD13 MD12 MD9 DQS1 DQM1 MD18 MD23 DQM2 MD22 MD21 MD19 MD24 MD29 MD30 MD27 MD28 MD25 DQS3 MD31 DQM3 MD26 MD39 MD38 MD45 MD44 MD40 DQM5 MD46 MD42 MD41 DQS5 MD43 MD47 MD49 MD55 MD48 MD54 MD52 DQM6 MD53 DQS6 MD50 MD51 MD57 MD61 MD62 MD60 DQM7 DQS7 MD63 MD59 MD56 MD58

7 7 7 7 7 7 7 7 7 7 7 7 7 7 7 7

13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13

11 11 11 11 11 11 11 11 11 11 11 11

CLK_DDR0 CLK_DDR0# CLK_DDR1 CLK_DDR1# CLK_DDR2 CLK_DDR2# CLK_DDR3 CLK_DDR3# CLK_DDR4 CLK_DDR4# CLK_DDR5 CLK_DDR5#

CLK_DDR0 CLK_DDR0# CLK_DDR1 CLK_DDR1# CLK_DDR2 CLK_DDR2# CLK_DDR3 CLK_DDR3# CLK_DDR4 CLK_DDR4# CLK_DDR5 CLK_DDR5#

MD16 MD17 DQS2 MD18 MD19 MD24 MD25 DQS3 MD26 MD27

MD20 MD21 DQM2 MD22 MD23 MD28 MD29 DQM3 MD30 MD31

MD16 MD17 DQS2 MD18 MD19 MD24 MD25 DQS3 MD26 MD27

MD20 MD21 DQM2 MD22 MD23 MD28 MD29 DQM3 MD30 MD31
3

CLK_DDR2 CLK_DDR2# CKE1 MA12 MA9 MA7 MA5 MA3 MA1 RP12 1 2 3 4 5 6 7 8 RP18 1 2 3 4 5 6 7 8 10*8 RPX8 16 15 14 13 12 11 10 9 RPX8 16 15 14 13 12 11 10 9 MA10 BA0 WE# CS0# MD32 MD33 DQS4 MD34 MD35 MD40 MD41 DQS5 MD42 MD43

CLK_DDR5 CLK_DDR5# CKE0 MA11 MA8 MA6 MA4 MA2 MA0 BA1 RAS# CAS# CS1# MD36 MD37 DQM4 MD38 MD39 MD44 MD45 DQM5 MD46 MD47 CLK_DDR1# CLK_DDR1 MD52 MD53 DQM6 MD54 MD55 MD60 MD61 DQM7 MD62 MD63 11,15 SMBDATA 11,15 SMBCLK MD48 MD49 DQS6 MD50 MD51 MD56 MD57 DQS7 MD58 MD59 SMBDATA SMBCLK CKE3 MA12 MA9 MA7 MA5 MA3 MA1 MA10 BA0 WE# CS2# MD32 MD33 DQS4 MD34 MD35 MD40 MD41 DQS5 MD42 MD43

CKE2 MA11 MA8 MA6 MA4 MA2 MA0 BA1 RAS# CAS# CS3# MD36 MD37 DQM4 MD38 MD39 MD44 MD45 DQM5 MD46 MD47 CLK_DDR4# CLK_DDR4 MD52 MD53 DQM6 MD54 MD55 MD60 MD61 DQM7 MD62 MD63

DDR_MD32 DDR_MD37 DDR_DQS4 DDR_DQM4 DDR_MD36 DDR_MD33 DDR_MD34 DDR_MD35 DDR_MD14 DDR_MD10 DDR_MD11 DDR_MD15 DDR_MD16 DDR_MD20 DDR_DQS2 DDR_MD17

DDR_MD32 DDR_MD37 DDR_DQS4 DDR_DQM4 DDR_MD36 DDR_MD33 DDR_MD34 DDR_MD35 DDR_MD14 DDR_MD10 DDR_MD11 DDR_MD15 DDR_MD16 DDR_MD20 DDR_DQS2 DDR_MD17

MD32 MD37 DQS4 DQM4 MD36 MD33 MD34 MD35 MD14 MD10 MD11 MD15 MD16 MD20 DQS2 MD17

MD32 MD37 DQS4 DQM4 MD36 MD33 MD34 MD35 MD14 MD10 MD11 MD15 MD16 MD20 DQS2 MD17

13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13

10*8

MD48 MD49 DQS6 MD50 MD51 MD56 MD57 DQS7 MD58 MD59 1 R95 1K 0603 1% 1 2 11,15 SMBDATA 11,15 SMBCLK SMBDATA SMBCLK

+2.5V_DDR

+DDRVREF

GND GND
1

+2.5V_DDR
1

GND +2.5V_DDR PLACE CLOSE TO J507 +2.5V_DDR PLACE CLOSE TO J508

C132 10U 1210 10V

C138 1U 0603D

C137 1U 0603D

C136 1U 2 0603D

C141 1U 0603D

C133 10U 1210 10V

C100 10U 1210 10V

C143 0.1U 0603D

C147 0.1U 0603D

C146 0.1U 0603D

C145 0.1U 0603D

C144 0.1U 0603D

C140 1U

1 2

C142 1U 0603D

C139 1U 0603D Title Size C Date:

0603D

8575A DDR SO-DIMMs Document Number Rev 01 of 30

GND
A B C

GND

BD 311671700001 & TU 411671700011 Sheet


E

Monday, June 17, 2002

12

+1.25V MD32 MD36 MD33 MD37 DQS4 DQM4 MD34 MD35 RP25 16 15 14 13 12 11 10 9 1 33*8 2 3 4 5 6 7 8 RPX8 1 C158 0.1U 0603 16V 1 C160 1000P 0603 1 1 1 1 1 C184 0.1U 0603 16V C175 0.1U 0603 16V C176 0.1U 0603 16V C156 0.1U 0603 16V C188 0.1U 0603 16V 1 2 C180 0.1U 0603 16V +1.25V

12 12 12 12 12 12 12 12

MD32 MD36 MD33 MD37 DQS4 DQM4 MD34 MD35

GND 2 1 12 12
D

WE# CAS# CS0# CS1# CS2# CS3# MA10 MA6 MA2 MA4 BA0 MA0 RAS# BA1

WE# CAS# CS0# CS1# CS2# CS3# MA10 MA6 MA2 MA4 BA0 MA0 RAS# BA1

RP26

12 12 12 12 12 12 12 12 12 12 12 12

RP27

16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9

1 33*8 2 3 4 5 6 7 8 1 33*8 2 3 4 5 6 7 8

RPX8

C162 0.1U 0603 16V

C163 1000P 0603 GND


D

+1.25V

RPX8 2

C167 0.1U 0603 16V

GND C164 1000P 0603 1 1 1 1 GND C165 0.1U 0603 16V C161 0.1U 0603 16V C168 0.1U 0603 16V C159 0.1U 0603 16V 1 2 C166 0.1U 0603 16V

C171 0.1U 0603 16V

12

MD[0..63]

MD[0..63] MD5 MD4 MD0 DQM0 DQS0 MD1 MD7 MD6 MD3 MD2 MD12 MD8 MD9 MD13 DQM1 DQS1 MD10 MD14 MD15 MD11 MD16 MD17 DQS2 MD20 MD25 MD29 DQS3 DQM3 MD31 MD30 MD26 MD27 MD39 MD38 MD45 MD44 MD40 DQM5 MD41 MD46 MD42 DQS5 MD47 MD43 MD49 MD48 MD53 MD52 MD54 DQM6 DQS6 MD55 MD51 MD50 MD56 MD60 MD57 MD61 DQM7 DQS7 MD63 MD62 MD59 MD58 MD18 MD21 MD22 DQM2 MD19 MD23 MD24 MD28 MA12 MA9 MA7 MA5 MA8 MA11 MA3 MA1 RP33 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8 33*8 RPX8 GND GND +1.25V +1.25V C178 1000P 0603 GND 2 GND 1 33*8 RPX8 2 C169 0.1U 0603 16V 1 C170 1000P 0603 GND 1 1 C173 1000P 0603 C190 1000P 0603 1 C187 1000P 0603

RP32

33*8

RPX8 2

C193 1000P 0603

C153 1000P 0603

C155 1000P 0603

1 2

C181 0.1U 0603 16V

C151 1000P 0603

RP31

GND 33*8 RPX8 +1.25V

RP29

1 33*8 RPX8 GND 1 C174 0.1U 0603 16V 1 C177 1000P 0603 33*8 RPX8 2 2

RP24

C152 0.015U 0603

RP23

+1.25V GND 1 1 C154 0.015U 0603 C192 0.015U 0603 1 2 C172 0.015U 0603

RP22

33*8

RPX8

C179 0.1U 0603 16V

2 C182 1000P 0603 GND

GND 33*8 RPX8 1 C183 0.1U 0603 16V 1 C186 1000P 0603

RP21

RP30

33*8

RPX8

GND

THESE DECOUPLING CAPACITOR SHOULD BE PLACE WITHIN 150 Mils OF +1.25V THERMINATION R-PACKs

12 12 12 12 12 12 12 12

MA12 MA9 MA7 MA5 MA8 MA11 MA3 MA1

RP28

33*8

RPX8

C189 0.1U 0603 16V

1 2

C191 1000P 0603

GND

C157 0.1U 0603 16V

1 2

C185 1000P 0603

12 DQM[0..7]
A

DQM[0..7]

12 DQS[0..7]

DQS[0..7]

DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DQS0 DQS1 DQS2 DQS3 DQS4 DQS5 DQS6 DQS7

GND
A

Title Size C Date:

8575A DDR TERMINATION Document Number BD 311671700001 & TU 411671700011 Sheet


1

Rev 01 of 30

Monday, June 17, 2002

13

SIS961(1/3)
18,28,29 PCI_AD[0..31]
D

L38 IDEAVDD 1 120Z/100M 2012 C266 0.1U 0603 50V JL514 1 2 JP_NET20 2

+1.8VS

PCI_AD[0..31] 2 IDEAVSS PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0

C265 0.01U 0603

1 2

C257 10U 1206 10V

GND

U14A 17 17 17,28 17,29 17,18 PCI_REQ4# PCI_REQ3# PCI_REQ2# PCI_REQ1# PCI_REQ0# PCI_REQ4# PCI_REQ3# PCI_REQ2# PCI_REQ1# PCI_REQ0# PCI_GNT4# PCI_GNT3# PCI_GNT2# PCI_GNT1# PCI_GNT0# PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#0 PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_SERR# PCI_PAR PCI_DEVSEL# PCI_LOCK# CLK_SBPCI -PCIRST F1 F2 E1 H5 F3 H3 G1 G2 G3 H4 K3 M4 P1 R4 E3 F4 E2 G4 M3 M1 M2 N4 M5 N3 N1 N2 Y2 C3 PREQ4# PREQ3# PREQ2# PREQ1# PREQ0# PGNT4# PGNT3# PGNT2# PGNT1# PGNT0# C/BE3# C/BE2# C/BE1# C/BE0# INTA# INTB# INTC# INTD# FRAME# IRDY# TRDY# STOP# SERR# PAR DEVSEL# PLOCK# PCICLK PCIRST#

J5 J4 H2 H1 J3 K4 J2 J1 K5 K2 L3 K1 L1 L4 L5 L2 N5 P2 P3 P4 R2 R3 R1 T1 P5 T2 U1 U2 T3 R5 U3 V1

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0

IDEAVDD IDEAVSS ICHRDYA IDREQA IIRQA CBLIDA IIORA# IIOWA# IDACKA# IDSAA2 IDSAA1 IDSAA0 IDECSA1# IDECSA0# ICHRDYB IDREQB IIRQB CBLIDB IIORB# IIOWB# IDACKB# IDSAB2 IDSAB1 IDSAB0 IDECSB1# IDECSB0# IDA0 IDA1 IDA2 IDA3 IDA4 IDA5 IDA6 IDA7 IDA8 IDA9 IDA10 IDA11 IDA12 IDA13 IDA14 IDA15 IDB0 IDB1 IDB2 IDB3 IDB4 IDB5 IDB6 IDB7 IDB8 IDB9 IDB10 IDB11 IDB12 IDB13 IDB14 IDB15 SIS961 BGA335_36

Y3 Y4 W10 V10 Y11 U12 V11 Y9 Y10 T11 U11 W11 T12 V12 W17 Y17 T16 U17 T14 W16 V16 Y18 T15 V17 U16 W18 U10 V9 W8 T9 Y7 V7 Y6 Y5 W6 U8 W7 V8 U9 Y8 T10 W9 Y16 V15 U14 W14 V13 T13 Y13 Y12 W12 W13 U13 Y14 V14 W15 Y15 U15

IDEAVDD IDEAVSS IDE_PIORDY IDE_PDDREQ IDE_IRQ14 1 IDE_PDIOR# IDE_PDIOW# IDE_PDDACK# IDE_PDA2 IDE_PDA1 IDE_PDA0 IDE_PDCS3# IDE_PDCS1# IDE_SIORDY IDE_SDDREQ IDE_IRQ15 1 IDE_SDIOR# IDE_SDIOW# IDE_SDDACK# IDE_SDA2 IDE_SDA1 IDE_SDCS3# IDE_SDCS1# IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 IDE_SDD0 IDE_SDD1 IDE_SDD2 IDE_SDD3 IDE_SDD4 IDE_SDD5 IDE_SDD6 IDE_SDD7 IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15 IDE_PDD[0..15] IDE_PDD[0..15] 17 IDE_PIORDY 17 IDE_PDDREQ 17 IDE_IRQ14 17 TP517 IDE_PDIOR# 17 IDE_PDIOW# 17 IDE_PDDACK# 17 IDE_PDA2 17 IDE_PDA1 17 IDE_PDA0 17 IDE_PDCS3# 17 IDE_PDCS1# 17 IDE_SIORDY 17 IDE_SDDREQ 17 IDE_IRQ15 17 TP516 IDE_SDIOR# 17 IDE_SDIOW# 17 IDE_SDDACK# 17 IDE_SDA2 17 IDE_SDA1 17 IDE_SDA0 17 IDE_SDCS3# 17 IDE_SDCS1# 17

17 PCI_GNT4# 17 PCI_GNT3# 17,28 PCI_GNT2# 17,29 PCI_GNT1# 17,18 PCI_GNT0# 18,28,29 PCI_C/BE#[0..3]

7,9,17 17,18 17,28,29 17,28

PCI_INTA# PCI_INTB# PCI_INTC# PCI_INTD#

17,18,28,29 PCI_FRAME# 17,18,28,29 PCI_IRDY# 17,18,28,29 PCI_TRDY# 17,18,28,29 PCI_STOP# 17,18,28,29 PCI_SERR# 17,18,28,29 PCI_PAR 17,18,28,29 PCI_DEVSEL# 17 PCI_LOCK# 11 CLK_SBPCI 7,9,17,18,21,28,29 -PCIRST

+1.8VS RP516 ZSTB0 ZSTB1 ZSTB0# ZSTB1# 1 2 3 4 4.7K*4/NA 1206 8 7 6 5 GND

11 7 7 7 7 7 7

ZCLK1 ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZUREQ ZDREQ

ZCLK1 ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZUREQ ZDREQ SVDDZCMP SZCMP_N SZCMP_P SVSSZCMP SZ1XAVDD SZ1XAVSS SZ4XAVDD SZ4XAVSS SZVREF SZVSSREF

V20 N19 N20 K20 K19 N16 N17 R19 N18 R18 P18 U20 U19 T20 T19 R20 P20

ZCLK ZSTB0 ZSTB0# ZSTB1 ZSTB1# ZUREQ ZDREQ VDDZCMP ZCMP_N ZCMP_P VSSZCMP Z1XAVDD Z1XAVSS Z4XAVDD Z4XAVSS ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15 ZVREF ZVSSREF

Place near to 961 chip

ZAD[0..15]

ZAD[0..15]

+1.8VS L524 SVDDZCMP 1 1 R109 150 0603D 2 C202 0.1U 0603D 50V SZVREF 1 SZCMP_N R605 1 SZCMP_P R676 1 SVSSZCMP 56 1% 56 1% 2 0603 2 0603 2 1 120Z/100M 2012 C642 0.1U 0603 50V 1 JL519 2 JP_NET20 C208 0.1U 0603D 50V SZVSSREF Title Size C Date:
5 4 3 2

+1.8VS 2 SZ4XAVDD 1

ZAD0 ZAD1 ZAD2 ZAD3 ZAD4 ZAD5 ZAD6 ZAD7 ZAD8 ZAD9 ZAD10 ZAD11 ZAD12 ZAD13 ZAD14 ZAD15

M18 M19 M17 M16 M20 L16 L20 L18 K18 J20 K17 K16 H20 J18 H19 H18

IDE_SDD[0..15]

IDE_SDD[0..15]

17

L26 2 120Z/100M 2012 C206 0.1U 0603 50V 1 JL520 2 JP_NET20

+3VS SZ1XAVDD 1

L517 2 120Z/100M 2012 C207 0.1U 0603 50V 1 JL521 2 JP_NET20

+3VS

C592 0.01U 0603

C312 10U 1206 10V SZ4XAVSS GND

C212 0.01U 0603

C213 0.01U 0603

1 2

C700 10U 1206 10V


A

SZ1XAVSS GND

R116 150 0603D 2

GND

1 GND

JL531 2 JP_NET20

8575A SIS961 (1/3) Document Number BD 311671700001 & TU 411671700011 Sheet


1

Rev 01 of 30

Monday, June 17, 2002

14

+3V D513 C291 1 2 1 1 10P 0603 C290 1


A

RTC_X1

A RLS4148

SIS961(2/3)
U14B 4 4 4 7 4 4 4 4 4 4 11 H_INIT# H_A20M# H_SMI# H_INTR H_NMI H_IGNNE# H_961_FERR# H_STPCLK# H_SLP# REFCLK3 GND GND GND 21 21 21 21 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 LPC_FRAME# LPC_DRQ# SERIRQ RTC_X1 RTC_X2 +3V BATOK 7 PWROK 1 PWROK C786 0.1U 0603 50V H_INIT# H_A20M# H_SMI# H_INTR H_NMI H_IGNNE# H_FERR# H_STPCLK# SLP# REFCLK3 T18 P16 R17 R16 Y20 U18 T17 W20 V19 Y19 V18 W19 V5 T7 U6 W5 W4 U7 V6 C2 D2 D3 D1 C1 E4 B2 A1 A2 D5 W2 T5 D6 Y1 W3 G5 V3 A14 B14 D14 A3 A15 2 0603 2 0603 B1 E5 INIT# A20M# SMI# INTR NMI IGNNE# FERR# STPCLK# CPUSLP# APICCK APICD0 APTCD1 LAD0 LAD1 LAD2 LAD3 LFRAME# LDRQ# SIRQ OSC32KHI OSC32KHO BATOK PWROK RTCVDD RTCVSS GPIO20 GPIO19 AC_SDIN0 AC_SDIN1 AC_SDOUT AC_SYNC AC_RESET# AC_BIT_CLK OSCI ENTEST SPK PWRBTN# PME# PSON# AUXOK ACPILED GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 SIS961 BGA335_36 MIIAVDD MIIAVSS MIICOL MIICRS MIIMDC MIIMDIO MIICLK25M MIITXCLK MIITXEN A8 A6 B6 OSC25MHI LAN_MTXC LAN_MTXE LAN_MTXC 19 LAN_MTXE 19 16 OSC25MHO AUXOK AUXOK 1 R706 100K 0603 2 1 C782 22U 1210 10V MIITXD0 MIITXD1 MIITXD2 MIITXD3 E8 D7 C6 B4 R166 1 33 R167 1 33 R172 1 33 R178 1 33 LAN_MRXC LAN_MRXDV LAN_MRXER LAN_MRXD0 LAN_MRXD1 LAN_MRXD2 LAN_MRXD3 2 0603 2 0603 2 0603 2 0603 LAN_MTXD0 LAN_MTXD1 LAN_MTXD2 LAN_MTXD3 LAN_MTXD0 19 LAN_MTXD1 19 LAN_MTXD2 19 2

Need very close to 961


OSC25MHI OSC25MHO 1 10M/NA 0603 X4 3 2 4 1 C305 0 0603 10% 1 R244 2

X5 32.768KHZ CM200 4 2

R189 10M 0603D RTC_X2

R705 1 1K 2 0603

2 0603

20P GND

1 GND +3V 2

25MHZ

LAN_MTXD3 19 2

C306 10P/NA 0603 10%

MIIRXCLK MIIRXDV MIIRXER MIIRXD0 MIIRXD1 MIIRXD2 MIIRXD3

A7 C7 C8 D8 A5 B5 A4

LAN_MRXC 19 LAN_MRXDV 19 LAN_MRXER 19 LAN_MRXD0 19 LAN_MRXD1 19 LAN_MRXD2 19 LAN_MRXD3 19 GND

+3VS -SB_THRM -EXTSMI R250 R251 1 10K 1 10K 2 0603 2 0603

21 LPC_FRAME# 21 LPC_DRQ# 18,21 SERIRQ

-WAKE_UP -SCI S3AUXSW# MPCIACT# VR_GATE VR_HI/LO# CPU_STP#

R851 R852 R853 R252 R265 R266 R850

1 1 1 1 1 1

10K 10K 10K/NA 10K 10K/NA 10K/NA

2 2 2 2 2 2

0603 0603 0603 0603 0603

+VCC_RTC GND

B7 E9 C5 E7 B9 B8

LAN_COL LAN_CRS R177 1 33 R171 1 33 MIIAVDD MIIAVSS 2 0603 2 0603

LAN_COL 19 LAN_CRS 19 LAN_DCLK LAN_DATAIO LAN_DCLK 19 LAN_DATAIO 19

Need very close to 961


R153 GPIO11 1 22/NA 0603D C240 47P/NA 0603 2 3 2 OSC1 OUT GND VDD E/D 4 1 1
B

GND 11,12 11,12 R181 2 100K R702 2 100K GND AC97_SDIN 1 0603D MDC_SDIN 1 0603D 20 19 SMBDATA SMBCLK AC97_SDIN MDC_SDIN SMBDATA SMBCLK AC97_SDIN MDC_SDIN AC97_SDOUT AC97_RST# AC97_BITCLK REFCLK1 ENTEST SB_SPKR SIS_PWRBTN# -PME PSON# AUXOK

1 10K/NA 2 0603

16,19,20 AC97_SDOUT 19,20 AC97_RST# 19,20 AC97_BITCLK 11 16,20 REFCLK1 SB_SPKR

25MHZ/NA OSC_TXC30CO

C234 0.01U/NA 0603D

19,20 AC97_SYNC

AC97_SYNC

R746 1 1 C811 10P/NA 0603 10%

2 22

0603

Need no close to 961 chip


R701 1 2 0 0603D

GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6

V2 T8 T4 T6 W1 U5 U4 C4 C14 E6 B3 F5 D4

R188 1 CD_RST

2 0/NA 0603 CD_RST

SPDIFOUT 20 17 +3VS

GND

GND

2 GND -SB_THRM 22 -EXTSMI LCD_ID3 MB_ID0 MB_ID1 R840 1 0 2 0603D_DFS -WAKE_UP 22 -SCI CRT_IN# GPIO11 CPU_STP# 11 1 C780 0.1U 0603 16V GND GND +3VS +3VS 1 +3VS 1 1 2 R282 10K 0603 2 R1 1 3 Q13 DTC114TKA CPU_DPSLP# 4
C

GND +3VA 5 1 1 C281 1U 0603D C288 4.7U/NA 0805 +80-20% 4

Close to 961 chip

GND

22 SIS_PWRBTN# -PME

22 R253 10K/NA 0603 LCD_ID3 2 1 R256 10K 0603 2 MIIAVSS 2 MIIAVDD 1

L32 2

+3V

U17 NC0 NC1 GND0 VIN VOUT 1 2 3

+5VA 1

AC97_BITCLK C119 10P/NA 0603

10 26 28

ACPILED DPRSLPVR MPCIACT# VR_HI/LO# R254 1 0 R255 1 0 R257 1 100K R258 1 0 R259 1 0 R279 1 0

C283 AME8800AEEV SOT25 2.2U 0805C 2

GPIO8 GPIO9 GPIO10 GPIO11 GPIO12

close to 961
4 G_LO/HI# VR_GATE MPCI_PD 26 10,28

2 0603 E13 2 0603 A16 2 0603 D13 2 0603 B15

22 10

JP_NET20 GND

GND GND

+3VA +VCC_RTC Q14 MMBT3906L E C K D16 B R184 51K 0603 2 RLS4148 R162 10K 0603 2 R175 A 1 10K 1 1 1 R180 0 0603 2 C279 1U 0603 C282 0.01U 0603 2 0603 1 C277 10U 1206 10V 1 1 C256 1U 0603 C255 22U 1210 10V BATOK 1 GND D17 K A RLS4148 1 2 3 4 4.7K*4 1206 R729 1 R715 1 GND GND GND 4.7K 2 4.7K 2 0603D LPC_AD1 0603D LPC_DRQ#

R685 10K/NA 0603 2 MB_ID0 1 R686 10K 0603 2 2 MB_ID1 1 2

R862 10K/NA 0603

Need no close to 961 chip


+3VS RP36 8 7 6 5 LPC_AD3 LPC_AD0 SERIRQ LPC_AD2

CPU_STP#

R863 10K 0603

+3V

+3V

+5V

GND

GND 2

R716 10K 0603

R707 10K 0603 2 32

R708 10K 0603 -SUSC -SUSC 22,24

R183 10K 0603 2

7,22

S3AUXSW#

S3AUXSW#

3 BAW56

R1 1

Q522 DTC144TKA

Q15 MMBT3904L

PSON#

D514 2

R551 1M/NA 0603 2

PLACE CLOSE TO 961


GND GND GND GND +5V +5V 1 29 1394_PME# 1 JL545 2 JP_NET10 R717 10K 0603 PSON 3 JL547 R1 1 2 PSON# 28 MPCI_PME# 1 2 JP_NET10 Q524 DTC144TKA 2 JL546 18 CARD_PME# 1 2 JP_NET10 10,24,27 PSON 2 1 +3V

GND

GND

J508
D

1 2 GND1 GND2

1 2 3 4

R693 1

2 1K

0603 2

R627 10K 0603 H8_SUSC 3 Q513 DTC144TKA 1 R1 2

R619 4.7K 0603D R620 2 0 0603D_DFS -PME

GPIO7

SPK_OFF 20

C232 0.01U 0603

130Z/100M 1608 C230 0.1U 0603 50V JL522 1 2

C754 10U 1206 10V

22 DF13-2P-1.25H GND

H8_SUSC

-SUSC

Title Size C Date:


1 2 3 4 5 6 7

8575A SIS961 (2/3) Document Number Rev 01 of


8

BD 311671700001 & TU 411671700011 Sheet 15 30

Monday, June 17, 2002

R147 27 USBP0+ 1 22 1 22 2 0603D 2

CLOSE TO 961
USBP0_P

R148 27 USBP0USBP0_N 1 C87 47P 0603 1 C86 47P 0603 11 USBCLK_SB USBCLK_SB USBP0_P USBP0_N USBP1_P USBP1_N USBP2_P USBP2_N USBP3_P USBP3_N USBP4_P USBP4_N USBP5_P USBP5_N 27 1 C84 47P 0603 1 C83 47P 0603 27 USB_OC0_1# USB_OC3_5# USB_OC0_1# USB_OC2# USB_OC3_5# USB_OC4# USB_OC5# USBVDD

SIS961(3/3)
U14C V4 B18 C18 E14 D15 E16 E15 D18 D19 E18 F18 G18 G19 G20 J16 H17 G17 H16 G16 D16 F17 B17 E19 H10 H11 H12 H13 H8 H9 J10 J11 J12 J8 J9 K10 K11 K8 K9 L10 L11 L8 L9 M10 M11 M8 M9 N10 N11 N12 N13 N8 N9 J13 J19 K12 K13 L12 L13 L19 M12 M13 P19 CTL1 D0 D1 D2 D5 D3 SCLK_1394 D4 D6 D7 C11 A12 B12 C12 A13 D12 E11 E12 B13 C13 USBCLK48M UV0+ UV0UV1+ UV1UV2+ UV2UV3+ UV3UV4+ UV4UV5+ UV5OC0# OC1# OC2# OC3# OC4# OC5# USBVDD0 USBVDD1 USBVSS0 USBVSS1 VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11 VSS12 VSS13 VSS14 VSS15 VSS16 VSS17 VSS18 VSS19 VSS20 VSS21 VSS22 VSS23 VSS24 VSS25 VSS26 VSS27 VSS28 VSSZ0 VSSZ1 VSSZ2 VSSZ3 VSSZ4 VSSZ5 VSSZ6 VSSZ7 VSSZ8 VSSZ9 NC0 NC1 NC2 NC3 NC4 NC5 NC6 NC7 NC8 NC9 SIS961 BGA335_36 IVDD0 IVDD1 IVDD2 IVDD3 IVDD4 IVDD5 IVDD6 IVDD_AUX0 IVDD_AUX1 OVDD0 OVDD1 OVDD2 OVDD3 OVDD4 OVDD5 OVDD6 OVDD7 OVDD_AUX0 OVDD_AUX1 OVDD_AUX2 OVDD_AUX3 OVDD_AUX4 PVDD0 PVDD1 PVDD2 PVDD3 PVDD_AUX0 PVDD_AUX1 PVDDZ VDDZ0 VDDZ1 VDDZ2 VDDZ3 VDDZ4 VDDZ5 VDDZ6 VTT0 VTT1 G6 H15 L6 M15 R10 R14 R6 F12 F9 H6 K6 M6 P6 R11 R13 R7 R9 F10 F11 F14 F15 F7 J6 N6 R12 R8 F13 F8 K15 G15 J15 J17 L15 L17 N15 P17 P15 R15 +1.8VS +1.8V +3VS

+3VS C766 1 C757 1 C767 1 C764 1 C760 1

1U 2 0603 2 0.1U 2 0.1U 2 0.1U 2 0.1U

+1.8VS C748 1 C749 C750 C751 1 1 1

1U 2 0603 2 0.1U 0603D 2 0.1U 0603D 2 0.1U 0603D


A

0603D

GND

GND

GND GND

R142 27 USBP3+ 1 22 1 22 2 0603D 2 0603D

CLOSE TO 961
USBP3_P

R143 27 USBP3USBP3_N

R269 1 R270 1

2 15K 2 15K

USBP5_P USBP5_N

+3V +3V C787 1 C779 1 1U 2 10U 2 0603 2 0.1U GND

R114 1 R107 1 +3V GND

2 15K 2 15K

USBP2_P USBP2_N

C753 1

USBVSS GND

+3VS USBVDD 1

L523 2 120Z/100M 2012 C745 1U 0603

+3V

R75 27 USBP1+ 1 22 1 22 2 0603D R158 27


B

CLOSE TO 961
USBP1_P

+3V +1.8VS +1.8VS USBVSS

C744 0.1U 0603 50V

1 2

C743 10U 1206 10V 1

R757 2 432/NA 0603 1% USBREF


B

USBP1-

2 1 1 0603D C121 47P 0603 C122 47P 0603

USBP1_N

USBVSS

SHOULD BE 433 1% +VCC_CORE OSC12MHI OSC12MHO R160 1 10M/NA 0603 X2 3 2 4 1 C123 20P/NA 0603 5% 1 2 C816 1 0.1U/NA C817 1 1U/NA 2 0603 50V 2 0603

GND

GND

R161 27 USBP5+ 1 22 1 22 2 0603D R163 27 USBP52

CLOSE TO 961
USBP4_P

USBP4_N 1 1 C125 47P 0603 C126 47P 0603

0603D

GND

GND

GND

GND D0 D1 D2 D3 RP521 1 2 3 4 5 4.7K*8/NA 1206 CTL0 CTL1 SCLK_1394 LINKON RP522 1 2 3 4 5 4.7K*8/NA 1206 10 9 LREQ 8 LPS 7 6 10 9 8 7 6 D4 D5 D6 D7 GND

NC10 NC11 NC12 NC13 NC14 NC15 NC16 NC17 NC18 NC19 NC20 NC21 NC22 NC23 NC24 NC25 NC26 NC27 NC28 NC29 NC30 NC31 NC32 NC33 NC34 NC35 NC36 NC37 NC38 NC39

A19 C16 E17 C19 D20 F20 A20 C17 D17 C20 E20 F19 F16 B16 C15 A18 A17 B20 B19 B11 D11 A11 E10 D9 B10 A10 A9 C9 C10 D10

LREQ IVDD_AUX USBVDD LINKON GPIO22_EEDI GPIO21_EESK LPS IVDD_AUX USBVDD GPIO24_EECS GPIO23_EEDO USBVSS USBREF OSC12MHI USBPVSS USBPVDD OSC12MHO USBREFAVDD USBVSS CTL0

12MHZ/NA

C124 20P/NA 0603 5% USBVSS

L538 1 0 0603 GND 2

GND

GND

OSC25MHO

OSC25MHO 15

PLACE UNDER 961 SOLDER SIDE


R164 USBREFAVDD 1 0/NA 0603 2 C763 1 C824 10U/NA 1206 10V C772 C775 C778 C752 GND 1 1 1 1 1 2 0.1U 0603D 2 0.1U 0603D 2 0.1U 0603D 2 0.1U 0603D 2 0.1U 0603D GND +1.8V C768 C758 1 1 2 0.1U 0603D 2 0.1U 0603D GND +3V +1.8VS

C127 0.01U/NA 0603 2

C128 0.1U/NA 0603 50V 1 JL542 2 JP_NET20

+3V C762 1 2 0.1U 0603D

+3V U512 1 2 3 VIN GND EN OUT BYP

+1.8V IVDD_AUX 5 4 2 R764 1 0/NA 0603 2

+1.8V USBPVDD 1

L539 2

+3V

C825 0.01U/NA 0603 2

AME8801MEEV SOT25 1 1 C769 1U 0603 10V C761 0.01U 0603 1 C756 4.7U 0805 +80-20%

C826 0.1U/NA 0603 50V 1 JL543 2 JP_NET20

C827 10U/NA 1206 10V USBPVSS

C829 0.01U/NA 0603 2

120Z/100M/NA 2012 C828 0.1U/NA 0603 50V JL544 1 2 JP_NET20

+3VS 1 C313 10U/NA 1206 10V C773 C774 C776 GND +3V 1 1 1 2 0.1U 0603D 2 0.1U 0603D 2 0.1U 0603D GND

+VCC_CORE C746 C747 1 1 2 0.1U 0603D 2 0.1U 0603D

GND

GND

GND

+3V R182 1 R179 1 R555 1 R608 1 2 10K/NA 2 10K/NA 2 10K/NA 2 10K/NA AC97_SDOUT SB_SPKR USB_OC2# USB_OC5# 1 2 3 4 10K*4 1 R169 4.7K/NA 0603 RP518 8 7 6 5 1206 USB_OC2# USB_OC5# U13 1 2 3 4 CS SK DI DO VCC NC1 NC0 GND 8 7 6 5 GPIO24_EECS GPIO21_EESK GPIO22_EEDI GPIO23_EEDO 2

0 SB_SPKR (LPC addr mapping) AC97_SDOUT (PCICLK PLL) USB_OC2# (SB debug mode) USB_OC5# (Trap mode) disable enable enable PCI AD

1 enable disable disable ROM

Default 0 0 1 1
GND

AC97_SDOUT 15,19,20 SB_SPKR 15,20 +3V

+3V

C129 1U/NA 0603

Title Size C
7

NM93C46/NA SO8 GND

8575A SIS961 (3/3) Document Number Rev 01 of


8

BD 311671700001 & TU 411671700011 Sheet 16 30

Date: Monday, June 17, 2002


1 2 3 4 5 6

MTG23 1

IDE INTERFACE
14 IDE_PDD[0..15]

terminating resistors should be place close to South Bridge


IDE_PDD[0..15] IDE_PDD0 IDE_PDD1 IDE_PDD2 IDE_PDD3 IDE_PDD4 IDE_PDD5 IDE_PDD6 IDE_PDD7 1 2 3 4 5 6 7 8 10*8 RPX8

14 IDE_SDD[0..15]

IDE_SDD[0..15] IDE_SDD0 IDE_SDD1 IDE_SDD2 IDE_SDD3 IDE_SDD4 IDE_SDD5 IDE_SDD6 IDE_SDD7 1 2 3 4 5 6 7 8

RP41 16 15 14 13 12 11 10 9 10*8 RPX8 SDD0 SDD1 SDD2 SDD3 SDD4 SDD5 SDD6 SDD7 1 14 IDE_SDDACK# 14 IDE_SDIOR# 14 IDE_SDIOW# IDE_SDDACK# R170 1 22 IDE_SDIOR# R176 1 10 IDE_SDIOW# R203 1 22 2 0603 2 0603 2 0603 SDDACK# SDIOR# SDIOW#

RP42 16 15 14 13 12 11 10 9 PDD0 PDD1 PDD2 PDD3 PDD4 PDD5 PDD6 PDD7 1 R209 10K 0603

14 14

IDE_PIORDY IDE_SIORDY

IDE_PIORDY IDE_SIORDY

R202 1 10 R204 1 10

2 2

0603 0603

PIORDY SIORDY 14 14 14 14 14

ID2.2/OD3.8

R206 14 IDE_PDDREQ 10K/NA 0603 14 IDE_SDDREQ 2

IDE_PDDREQ IDE_SDDREQ

R205 1 R207 1

82 82

2 2

PDDREQ SDDREQ

IDE_SDA0 IDE_SDA1 IDE_SDA2 IDE_SDCS3# IDE_SDCS1#

IDE_SDA0 IDE_SDA1 IDE_SDA2 IDE_SDCS3# IDE_SDCS1#

RP43 33*4 1 RPSOA_8C 8 2 7 3 6 4 5 R208 1 33 2 0603

SDA0 SDA1 SDA2 SDCS3# SDCS1#

RP44 IDE_SDD8 IDE_SDD9 IDE_SDD10 IDE_SDD11 IDE_SDD12 IDE_SDD13 IDE_SDD14 IDE_SDD15 1 2 3 4 5 6 7 8 10*8 RPX8 16 15 14 13 12 11 10 9 SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15

GND

14 14

IDE_IRQ14 IDE_IRQ15

IDE_IRQ14 IDE_IRQ15

R210 R777

1 1

82 82

2 2

IRQ14 IRQ15 IDE_PDDACK# R211 1 22 IDE_PDIOR# R212 1 10 IDE_PDIOW# R213 1 22 2 0603 2 0603 2 0603 PDDACK# PDIOR# PDIOW#

GND IDE_PDD8 IDE_PDD9 IDE_PDD10 IDE_PDD11 IDE_PDD12 IDE_PDD13 IDE_PDD14 IDE_PDD15 1 RP45 2 3 4 5 6 7 8 10*8 RPX8 16 15 14 13 12 11 10 9 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15

14 IDE_PDDACK# 14 IDE_PDIOR# 14 IDE_PDIOW#

14 14 14 14 14

IDE_PDA0 IDE_PDA1 IDE_PDA2 IDE_PDCS3# IDE_PDCS1#

IDE_PDA0 IDE_PDA1 IDE_PDA2 IDE_PDCS3# IDE_PDCS1#

RP528 33*4 1 RPSOA_8C 8 2 7 3 6 4 5 R781 1 33 2 0603

PDA0 PDA1 PDA2 PDCS3# PDCS1#

GND
2

+5VS
2

R151 10K 0603 2 2

1 R144 4.7K 0603 IDE_RST# PDD7 PDD6 PDD5 PDD4 PDD3 PDD2 PDD1 PDD0 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43

J19 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 PDD8 PDD9 PDD10 PDD11 PDD12 PDD13 PDD14 PDD15

+5VS

Primary EIDE Connector

PDDREQ PDIOW# PDIOR# PIORDY PDDACK# IRQ14 PDA1 PDA0

R137 1 470 0603 2 1 R711 100K/NA 0603 2 IDE_RST# 3 15 CD_RST +3VS 1 2 1 2 Q508 DTC144WK/NA R730 10K/NA 0603 +5VS GND R214 1 1 R215 10K 0603 10K 0603 3 2 3 R1 1 Q19 DTC144TKA 1 GND Q18 DTC144TKA 2 C273 4.7U 1206 16V C258 0.1U 0603 50V 7,9,14,18,21,28,29 -PCIRST 2 1 2 R1

PDA2 PDCS3# PDCS1#

+5VS

1 R131 5.6K 0603 R200 2

MA/22PX2/ST C16822-X44XX

PCI BUS
14,29 PCI_REQ1# 14 PCI_GNT4# 14,18,28,29 PCI_PAR PCI_REQ1# PCI_GNT4# PCI_PAR 14 PCI_LOCK# 14,18,28,29 PCI_DEVSEL# 14,18,28,29 PCI_STOP# 14,18,28,29 PCI_FRAME#

470 0603 +3VS +3VS A D19 PG1102W RP38 1 2 3 4 5 8.2K*8 RP39 1 2 3 4 5 8.2K*8 RP37 1 2 3 4 5 8.2K*8 1 8.2K 0603 1206 2 CLKRUN# 1206 10 9 8 7 6 2 PCI_REQ3# PCI_REQ4# PCI_INTD# PCI_REQ0# 1206 10 9 8 7 6 PCI_IRDY# PCI_SERR# PCI_PERR# PCI_TRDY# 1 PCI_IRDY# 14,18,28,29 PCI_SERR# 14,18,28,29 PCI_PERR# 18,28,29 PCI_TRDY# 14,18,28,29 10 9 8 7 6 PCI_GNT0# PCI_GNT1# PCI_GNT2# PCI_GNT3# PCI_GNT0# 14,18 PCI_GNT1# 14,29 PCI_GNT2# 14,28 PCI_GNT3# 14 K +5VS K D512 EC10QS04/NA 22 -HDDACTP -HDDACTP 1 JS4 SHORT-SMT3 2 JS5 2 SHORT-SMT3 A 1

+5VS_HDD 2

PCI_LOCK# PCI_DEVSEL# PCI_STOP# PCI_FRAME#

Close to IDE Connector


1 C261 0.1U 0603 50V 1 2

7,9,14 PCI_INTA# 14,28,29 PCI_INTC# 14,28 PCI_REQ2# 14,18 PCI_INTB#

PCI_INTA# PCI_INTC# PCI_REQ2# PCI_INTB#

PCI_REQ3# 14 PCI_REQ4# 14 PCI_INTD# 14,28 PCI_REQ0# 14,18

R190 CLKRUN# 18,21,28,29 +5VS GND

PLACE CLOSE TO CDROM CONNECTOR


0

W/S=16/12/12/16 mils
2 0603 CDROM_COMM CDROM_LEFT CDROM_RIGHT J12 CDROM_COMM 20 CDROM_LEFT 20 CDROM_RIGHT 20

R141 1

+3VS 21,22 SD[0..7] SD[0..7] SD4 SD5 SD6 SD7 SD0 SD1 SD2 SD3 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA12 SA13 SA14 SA15 SA8 SA9 SA10 SA11 SA16 SA17 SA18 SA19 RP530 1206 RP531 1206 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 RP514 1 2 3 4 5 4.7K*8 1206 RP519 1 2 3 4 5 4.7K*8 1206
A

8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 10 9 8 7 6

4.7K*4

ISA BUS
SDIOW# SIORDY IRQ15 SDA1 SDA0 SDCS1#

R73 4.7K 0603

R68 10K 0603 SDD7 SDD6 SDD5 SDD4 SDD3 SDD2 SDD1 SDD0

To Audio Codec
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50

GND IDE_RST#

4.7K*4

RP46 1206

4.7K*4

Secondary EIDE Connector

21 21 21,22 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21 21

SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA12 SA13 SA14 SA15 SA8 SA9 SA10 SA11 SA16 SA17 SA18 SA19

RP532 1206

4.7K*4

RP534 1206 RP47 1206

4.7K*4

470 0603

D18 PG1102W

CABLE_SEL 1

D13 R140 5.6K 0603 2

4.7K*4

+5VS

R743

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 GND1 GND2

1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49

SDD8 SDD9 SDD10 SDD11 SDD12 SDD13 SDD14 SDD15 SDDREQ SDIOR# SDDACK# SDA2

+5VS_CD +5VS_CD

Close to IDE Connector


C643 0.1U 0603 50V C74 0.1U 0603 50V C648 4.7U 1206 16V

EC10QS04/NA 2 A

R44 470/NA 0603 2

GND1 GND2

FM/25PX2-R/A C12441-X50XX

-P_INIT

-P_INIT

21,27

22 -CDACTP

-CDACTP

+5VS JS6 SHORT-SMT3 2 JS7 1 2 Title Size C Date:


B

SDCS3# 10 9 8 7 6 -MCCS -IOR -IOW -P_STB

21,22 21,22 21

IRQ1 IRQ12 -MEMR

IRQ1 IRQ12 -MEMR

-MCCS -IOR -IOW -P_STB

21,22 21,22 21,22 21,27

SHORT-SMT3

8575A IDE INTERFACE & PULL-UPs Document Number BD 311671700001 & TU 411671700011 Sheet 17 of 30 Rev 01

Monday, June 17, 2002

PCI1410
AD20 PCI_INTB#
D

PCMCIA CONTROLLER & CARDBUS SCOKET


+3V +3VS 1 R784 0/NA 0603 2 2 2 1 R785 0 0603 -VCCEN0 -VCCEN1 VPPEN0 VPPEN1

FOR TI 1410
7,9,14,17,21,28,29 -PCIRST R216 1 0 +3VS 0603 2

+3VS
D

REQ0#/GNT0#

C832 0.1U 0603 50V

C833 0.1U 0603 50V

C131 0.1U 0603 50V

C149 0.1U 0603 50V 1

SIGNAL CCD#1 CCD#2 CBLOCK# CSTOP# CDEVSEL# CTRDY# CVS1 CVS2 CRST# CSERR# CPERR# CINT# CIRDY# CREQ# CSTSCHG# CAUDIO

PC CARD PULL UP +3V +3V CARD_VCC CARD_VCC CARD_VCC CARD_VCC +3V +3V CARD_VCC CARD_VCC CARD_VCC CARD_VCC CARD_VCC CARD_VCC CARD_VCC CARD_VCC

VOLT

R217 1 0/NA 0603

VCCA 2

C836 0.1U 0603 50V

C837 0.1U 0603 50V

C838 0.1U 0603 50V

C839 0.1U 0603 50V

F3 M10 H11 D12 C8 B4

N13 M13 N12 M12

G1 K2 N4 L6

L9

U6 G13 A7 B2 C3 B3 A3 C4 A6 D7 C7 A8 D8 A9 C9 A10 B10 D10 E12 F10 E13 F13 F11 G10 G11 G12 H12 H10 J11 J12 K13 J10 K10 K12 L13 B12 B11 A12 A13 B13 C12 D13 C13 A5 B8 C11 D6 D11 D5 B9 A2 J13 E10 C6 D9 L12 A4 B5 C5 B7 A11 E11 H13 CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0

PCI_VCC0 PCI_VCC1 PCI_VCC2 PCI_VCC3

AUX_VCC

VCCD0#/VCC5#/SDAT VCCD1#/VCC3#/SCLK VPPD0/VPP_PGM/SLAT VPPD1/VPP_VCC

CORE_VCC0 CORE_VCC1 CORE_VCC2 CORE_VCC3 CORE_VCC4 CORE_VCC5

14,28,29 PCI_AD[0..31]

PCI_AD[0..31]

SKT_VCC0 SKT_VCC1 CAD31 CAD30 CAD29 CAD28 CAD27 CAD26 CAD25 CAD24 CAD23 CAD22 CAD21 CAD20 CAD19 CAD18 CAD17 CAD16 CAD15 CAD14 CAD13 CAD12 CAD11 CAD10 CAD9 CAD8 CAD7 CAD6 CAD5 CAD4 CAD3 CAD2 CAD1 CAD0 CCLK CFRAME# CIRDY# CTRDY# CDEVSEL# CSTOP# CPAR CPERR# CSERR# CREQ# CGNT# CINT# CBLOCK# CCLKRUN# CRST# R2_D2 R2_D14 R2_A18 CVS1 CVS2 CCD1# CCD2# CAUDIO CSTSCHG CC/BE3# CC/BE2# CC/BE1# CC/BE0#

C203 0.1U 0603 50V

GND

PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#0

GND

C2 C1 D4 D2 D1 E4 E3 E2 F2 F1 G2 G3 H3 H4 J1 J2 N2 M3 N3 K4 M4 K5 L5 M5 K6 M6 N6 M7 N7 L7 K7 N8 E1 J3 N1 N5 F4 H1 L1 J4 K1 K3 L2 M2 L3 M1 A1 B1 G4 L8 L11 M9 M11 N11 L10 N10 K9 N9 K8

AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 C/BE3# C/BE2# C/BE1# C/BE0# IDSEL PCI_CLK DEVSEL# FRAME# IRDY# TRDY# STOP# PAR PERR# SERR# REQ# GNT# RST#

PCI1410 HAVE INTEGRATED ALL PULL UP RES ABOVE

Card Bus Socket


VCCA
C

1 2

C650 0.1U 0603 50V J11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 GND1 GND2 0.635/H5/68P CL640 HIROSE 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 GND3 GND4 2 -CCD1 CAD2 CAD4 CAD6 R2_D14 CAD8 CAD10 CVS1 CAD13 CAD15 CAD16 R2_A18 -CBLOCK -CSTOP -CDEVSEL -CTRDY -CFRAME CAD17 CAD19 CVS2 -CRST -CSERR -CREQ -CCBE3 CAUDIO CSTSCHG CAD28 CAD30 CAD31 -CCD2 1 C81 270P 0603 10%

PCI_AD20

R789 1 100

0603 CLK_CARDPCI PCI_DEVSEL# PCI_FRAME# PCI_IRDY# PCI_TRDY# PCI_STOP# PCI_PAR PCI_PERR# PCI_SERR# PCI_REQ0# PCI_GNT0# -PCIRST CARD_PME# -CARDSPK CLKRUN# SERIRQ

CAD9 1

R219 C205 10P/NA 0603 10%

1 0 0603

2 CAD12 1 R220 1 0 2

+3VS R249 1 10K 2

11 CLK_CARDPCI 14,17,28,29 PCI_DEVSEL# 14,17,28,29 PCI_FRAME# 14,17,28,29 PCI_IRDY# 14,17,28,29 PCI_TRDY# 14,17,28,29 PCI_STOP# 14,17,28,29 PCI_PAR 17,28,29 PCI_PERR# 14,17,28,29 PCI_SERR# 14,17 PCI_REQ0# 14,17 PCI_GNT0# 7,9,14,17,21,28,29 -PCIRST 15 0603 20 CARD_PME# -CARDSPK

CAD11 CAD14 -CCBE1 CPAR -CPERR -CGNT -CINT CCLK -CIRDY -CCBE2 CAD18 CAD20 CAD21 CAD22 CAD23 CAD24 CAD25 CAD26 CAD27 CAD29 R2_D2

GND 2

0603 C211 10P/NA 0603 VPPA 10%

VPPA

RI_OUT#/PME# SUSPEND# SPKR_OUT# MF6 MF5 MF4 MF3 MF2 MF1 MF0

R221 10K 0603 2

VCCA

17,21,28,29 CLKRUN# 15,21 14,17 PCI_INTB# SERIRQ 2 +3VS

VCCA

C661 0.1U 0603 50V

C678 10P/NA 0603 10%

GND0 GND1 GND2 GND3 GND4 GND5 GND6 GND7

R793 1 0 0603

-CCBE3 -CCBE2 -CCBE1 -CCBE0

R134 47K 0603 2 -CCLKRUN 1 R222 C215 10P/NA 0603 10% 1 0 0603 2

14,28,29 14,28,29 14,28,29 14,28,29

PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#0

-CFRAME -CIRDY -CTRDY -CDEVSEL -CSTOP CPAR -CPERR -CSERR -CREQ -CGNT -CINT -CBLOCK -CCLKRUN -CRST R2_D2 R2_D14 R2_A18 CVS1 CVS2 -CCD1 -CCD2 CAUDIO CSTSCHG

1 0 R218

2 1

CCLK C204 10P/NA 0603 10%

CAD0 CAD1 CAD3 CAD5 CAD7 -CCBE0

C38 270P 0603 10%

D3 H2 L4 M8 K11 F12 C10 B6

PCI1410GGU BGA144_0.8MM 2

1 R223 10K 0603 C217 1 2 0.1U 50V 0603 1 Q20 DTC144WK 2

GND

22

-CARD_RI

U505 +3VS +5VS -VCCEN0 -VCCEN1 1 2 3 4 5 6 7 8 VCCD0 VCCD1 3.3VA 3.3VB 5VA 5VB GND OC TPS2211 SHDN VDDP0 VDDP1 AVCCA AVCCB AVCCC AVPP 12V SSOP16
A

Close to TPS2211
1 1 1 1 C696 0.1U 0603 50V C695 0.1U 0603 50V C687 0.1U 0603 50V C683 0.1U 0603 50V

16 15 14 13 12 11 10 9

VPPEN0 VPPEN1

+3VS

VCCA

VPPA +12VS

C675 0.1U 0603 50V

C676 0.1U 0603 50V

C662 0.1U 0603 50V

C679 4.7U/NA 1206 16V

C684 0.1U 0603 50V

1 2

C694 4.7U/NA 1206 16V

Close to TPS2211

Title 8575A PCI1410 & 1394 PHY Size Date:


5 4 3 2

Document Number

BD 311671700001 & TU 411671700011 Sheet


1

Rev 01 of 30

Monday, June 17, 2002

18

+3V_LAN +3V 1 120Z/100M 2012 L8 2 +3V_LAN +3V_LAN 1 R61 10K 0603D 2 A

LAN LED FOR DEBUG CONVENIENCE

D507 CL-190G/NA 2

1 R595 10K 0603D

C64 0.1U 0603D 50V

C59 0.1U 0603D 50V

C62 0.1U 0603D 50V

C48 0.1U 0603D 50V

C45 0.1U 0603D 50V

C44 0.1U 0603D 50V

R609 0 1 R66 1 0

0603D 2 0603D 2

PHY Address = 00001


LAN_GND
D

15 15 15 15 15 15 15

LAN_MRXD0 LAN_MRXD1 LAN_MRXD2 LAN_MRXD3 LAN_MRXDV LAN_MRXER LAN_MRXC

+3V_LAN

LAN_GND 15 15 15 15 LAN_MTXD0 LAN_MTXD1 LAN_MTXD2 LAN_MTXD3

1 2 3 4 RP6 1 2 3 4 R70 1

8 7 6 5 22*4 1206 8 7 6 5 2 1K 0603D

VDD0 VDD1 VDD2 VDD3 VDD4 VDD5 VDD6 VDD_IO0 VDD_IO1

35 34 33 32 36 39 38 41 45 46 47 48

7 8 15 16 25 54 63 37 51

RP5

22*4

1206 RXD0 RXD1 RXD2 RXD3 RXDV RXER RXCLK RXTRI TXD0 TXD1 TXD2 TXD3 TXEN TXER TXCLK MDC MDIO COL CRS RESETN REF_OUT REF_IN

284501893001 ISC1893Y-10 PQFP64_0.5MM U5 55 60 59 62 64 21 2 14 13 6 5 3 23 10 9 1 27 26 24 20 19 2 RXINRXIN+

P0AC P2LI P1CL P3TD P4RD LSTA 10/100SEL TP_RXN TP_RXP TP_TXN TP_TXP TP_CT HW/SW 100TCSR 10TCSR NOD/REP LOCK ANSEL DPXSEL NC MII/SI

8 7 6 5 RP4 10K*4 RPSOA_8C

1 2 3 4

LAN_GND

+3V

15 15 15 15

LAN_DCLK LAN_DATAIO LAN_COL LAN_CRS

R69 R67

1 1

2 22 2 22

0603D 0603D

31 30 49 50 18 52 53

+3V_LAN

R49 1 22K 2 0603 1 C57 1U 0603

2 R65 1M/NA 0603D

C47 0.1U/NA 0603D 50V 2

R577 2K 0603D

C46 0.1U/NA 0603D 50V 2

1 R579 1.5K 1% 0603D 1

R64 15 LAN_MTXE 1.5K 0603D LAN_GND 15 LAN_MTXC

R71 R72

1 1

2 1K 0603D 2 22 0603D

44 42 43

TXDTXD+ LAN_CT

R58 1K 0603D

1 R578 12.1k 1% 0603D

1.51K

VSS0 VSS1 VSS2 VSS3 VSS4 VSS5 VSS6 VSS7 VSS8 VSS9 VSS10 VSS11

X1 LAN_GND 3 2 4 1 C68 27P 0603D 5% 1

4 11 12 17 22 28 29 40 56 57 58 61

R56 1K 0603D 2 2 1 C65 27P 0603D 5%

R841 1K 0603D 2

LAN_GND R43 1K 0603D

LAN_GND

LAN_GND LAN_GND

25MHZ TXC7X5 274012500401

R260 1 0 0603 GND R261 1 0 0603 GND R262 1 0 0603 GND LAN_GND 2 PJ4 3 4 6 5 PJRXPJRX+ PJ7 PJRXPJ4 PJRX+ PJTXPJTX+ LAN_GND 2 PJTXPJTX+ 1 2 U20 PJ7 LAN_GND +3V_LAN 2 GND GND LAN_GND

LAN_GND LAN_GND

LAN_GND

8 7

RJ45
J9 1 2 3 4 5 6 7 8 1 2 3 4 5 6 7 8

R263
B

1 0 0603 GND

2 CLOSE TO ICS1839

GND_45

PACDN006/NA

SSOP8

GND1 GND2 GND3 GND4

GND1 GND2 GND3 GND4 20 MONO_OUT MONO_OUT 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29

J18 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30

+3V

+5V R121 0603 0_NA 2 1 1 C210 1U 0603


B

JO1 C54 0.1U 0603 50V LAN_GND

JO2

JO3

JO4

JO5

JO6

Modem Dougther Board

LAN_GND

8PX1/1.016MM CONN_PJS-AST_8

MODEM_SPK

MODEM_SPK 20

+3V

GND_45

R120 4.7K 1 2 0603

CLOSE TO MDC
R119 1 R118 1 R117 1 22 22 22 2 0603 2 0603 2 0603

Layout Note:
, EX: GND SHIELDING
S/W/W/S=12/6/6/12 mils as short as possible

SHOULD BE 4.7PF C41 10P 0603 10%

CHOKE_PLP3216S_1 PLP3216S L6 3 4

15,16,20 AC97_SDOUT 15,20 AC97_RST#

AC97_SDOUT AC97_RST#

AC97_SYNC MDC_SDIN AC97_BITCLK

AC97_SYNC 15,20 MDC_SDIN 15 AC97_BITCLK 15,20

CLOSE TO MDC
1 C730 1U 0603

R46 56 0603 1% 2 2

1 R41 56 0603 1% R38 R39

FM/0.8MM/H2.4 AMP C-179373

U3 1 0/NA 1 0/NA 2 2 2 2 0603 0603 7 6 8 1 3 2 4 5 TD+ TDC TDRD+ RDC RDNC0 NC1 LF-H80P SOX16 TX+ TXC TXRX+ RXC RXNC2 NC3 10 11 9 16 14 15 12 13 PJRX+ PJRX2

C209 10P/NA 0603

RXIN+ RXIN-

MDC SCREW HOLE


1 MDC_GND1 JO508 1 2 SHORT-SMT3 JO509 1 2 SHORT-SMT3

TXD+ TXD1 1 R30 61.9 0603 1% 2 2 L5 1 130Z/100M 1608 2 1 C311 0.1U 0603 50V LAN_GND R27 61.9 0603 1%

R28 R26

1 0/NA 1 0/NA

0603 0603

PJTX+ PJTX-

MDC HARDWARE STRAP

HIGH

LOW
AUDIO CODEC ON DAUGHTER BOARD

MTG24 ID2.8/OD5.0 1 MTG25 ID2.8/OD5.0

MDC_GND2

C37 100P 0603 10%

PJ4 PJ7

PIN 16

AUDIO CODEC ON MOTHER BD

1 L4 3 4 2

C310 0.1U 0603 50V

CHOKE_PLP3216S_1 PLP3216S

LAN_GND 2

R35 75 0603 2

R31 75 0603 2

R537 R538 75 75 0603 0603 2

R3 1 0/NA

JO55 0805 C501 1000P 1808B 3KV 10%

JO56

GND_HOLE

LAN_GND LAN_CT R32 1 2 0 0603 1

JS502 2 SHORT-SMT4

C577 1000P 1808 3KV 10%

J5 1 2

L1 50UH 3 2 2 CHOKE_WLT04020201

S501 Protector/NA 1808A

RJ11
J1 1 2 GND1 GND2 1 2 GND1 GND2 1.016MM/H8.6 OCTEKCONN PJS-OXSXT

GND_45 GND_45

ST/MA-2 HIROSE DF13-2P-1.25V

R4 1 0/NA

F501 2 0805 1 2 MINISMDC110

C502 1000P 1808B 3KV 10%

Title 8575A LAN PHY (ICS1893) & MDC Size


Custom

GND_HOLE

Document Number

BD 311671700001 & TU 411671700011 Monday, June 17, 2002


1

Rev 01 of 30

Date:
5 4 3 2

Sheet

19

5
AUDIO CODE & AMPLIFIER

3
JS505 SHORT-SMT4 +3VS 1 2

+5VS

1 L554 120Z/100M 2012

C796 1 2 U514 1 2 3 4 OUT0 OUT1 NR GND IN0 IN1 ERR SD 8 7 6 5 1 JP501 2 JP

L553 130Z/100M 1608

+12VS

R173 0 0603 2 2

1 R165 0 0603

AVDDAD

AC97_BITCLK 1 C765 10P/NA 0603

0.01U/NA 0603

Close to Codec
1 1 1 1 C759 10U_NA 1206 10V C88 0.1U 0603 50V C116 0.1U 0603 50V

Close to Codec
1 1 C120 0.1U 0603 50V C117 0.1U 0603 50V C784 10U 1206 10V

Close to ADP3301
1 C797 1U/NA 0603

D
AGND

ADP3301AR-5/NA SO8 R738 1 330K/NA 2 0603

R704 15,19 AC97_RST# 15,16,19 AC97_SDOUT 15 AC97_SDIN AC97_RST# 25 38 1 9 AC97_SDOUT AC97_SDIN AC97_SYNC AC97_BITCLK 22 1 R699 2 0603 22 1 R154 2 0603 11 5 8 10 6 2 3 12 RESET# SDATA/OUT SDATA/IN SYNC BIT/CLK XTL/IN XTL/OUT PC_BEEP

AGND

AGND
U15

AGND
1 R709 1K 0603 MIC 2 1

1 C790 0.1U_NA 0603 50V

MODEM_SPK

MODEM_SPK 19

10K/NA 0603

DVDD1 DVDD2

AVDD1 AVDD2

LINE/IN/L LINE/IN/R MIC1 MIC2 CD/R CD/L CD/GND VIDEO/L VIDEO/R

23 24 21 22 20 18 19 16 17 14 15 35 36 13 37 39 41 29 30 27 28 1 MIC1 MIC2

C274 1 C260 1 C272 1 C264 1 C271 1 C269 1 C270 1 C267 1 C268 1 C263 1 C278 1

2 0.1U 2 0.1U 2

50V 50V

0603 0603 0603 0603 0603 0603 0603 1 1 50V 50V 50V 50V 0603 0603 0603 0603 AOUT_L AOUT_R 2 R187 1 R185 1 R186 1 1 2 6.8K 2 6.8K 2 6.8K 5% 5% 5%

1U 10V 50V

15,19 AC97_SYNC 15,19 AC97_BITCLK R139 11 14.318MHZ_AUDIO 1 0 0603 2 1 R150 0603 X3 1 C227 10P/NA 0603 1 2 24.576MHZ/NA 1 C246 10P/NA 0603 2 1M/NA

2 0.1U 2 2 2

AGND
CDROM_RIGHT CDROM_LEFT CDROM_COMM CDROM_RIGHT 17 CDROM_LEFT 17 CDROM_COMM 17

1U 10V 1U 10V 1U 10V

CLOSE TO CODEC

2 0.1U/NA 2 0.1U/NA 2 0.1U/NA 2 0.1U/NA

AUX/L 0603 0603 0603 10V 1U 10V 1U 10V 1U 1 1 1 1 2 C242 2 C243 2 C238 2 C236 31 32 33 34 40 43 44 45 46 47 48 BPCFG FLT3D FLTI FLTO NC1 NC2 NC3 ID0# ID1# EAPD S/PDIF_OUT AUX/R LINE/OUT/L LINE/OUT/R PHONE MONO_OUT ALT_LINE_OUT_L ALT_LINE_OUT_R AFLT1 AFLT2 DVSS1 DVSS2 AVSS1 AVSS2 R136 0 0603 2 REFFLT VREFOUT

R193 100K 0603 2

R191 100K 0603 2

R192 100K 0603

AGND AGND

AGND

AGND

AVDDAD

15,16

SB_SPKR

SB_SPKR AVDDAD R703 1 10K 2 0603 U513 4 AHCT1G86DBV SOT25 0.1U 50V 0603 1 R697 2 5 1 C771 2

C225 1 C224 1 C219 1 C250 1 C251 1

1U 10V 50V 50V

0603 0603 0603 0603 0603

MONO_OUT

MONO_OUT 19

0603 50V 1000P_NA

C262 1

1U 10V

0603 D25 BAV99/NA 3

C
INTERNAL MICROPHONE
J21 HIROSE ST/MA-2 DF13-2P-1.25V

C237

AGND

1 0.1U_NA 1 0.1U_NA

2 50V C244 2 50V

0603 1

2 0.1U 2 0.1U

AGND

18

-CARDSPK

-CARDSPK

2 3

1 1

2 2 0.1U 0603 50V

33K 0603

20mil
1

AGND

C777

2 1000P 50V

0603

R271 0 0603

2 1000P 50V

C118 47P 0603

JO57 SPARKGAP_6

R698 10K 0603 2

Very Close to Codec


1 C249 0.1U 0603 50V C254 0.1U 0603 50V 1 C253 10U 1206 10V

CHIP

ALC200

CS4299 X 0.01U X 1000P

R700 10K 0603 2

Cap pin32: 0.1U Cap pin33: Cap p33/34 1U X

SPDIFOUT 15

Cap pin31: 0.1U

SPDIFOUT

ALC201 PQFP48_0.5MM

C220 1000P/NA 0603

AGND

26 42

4 7

AGND

AGND

AGND
R155 1 0/NA

AGND

AGND AGND

AGND

2 0603

MIC_VREF 5V_AMP 1 +3VS_SPD +3VS 1 1 R745 10K/NA 0603 Q529 DTA144WK 3 1 1 2 1 D522 BAV99/NA 3 3 L532 600Z/100M 1608 0603D AVDDAD 2 R728 R1 1 2 -DECT_HP/OPT 1 2.7K 0603 1 C801 1U 0603 C788 2.2U 0805 +80-20% 1 1 R739 2.7K 0603 2 R727 2 MIC_VREF 1 2.2K 0603 2 MIC_3 MIC_2 1 L531 2 600Z/100M 1608 0603D 5 4 3 2 1 2 D521 BAV99/NA 2 AVDDAD

L545 1 36Z/100M 2012 2 1

L34 2 36Z/100M 2012 2 36Z/100M 2012 2

R96 4.7K 0603

MIC

1 2

AGND
1

L546

AGND
1

L40 2 36Z/100M 2012

AMP_MUTE

AGND

L547 1 36Z/100M 2012

AGND

L35 1 36Z/100M 2012 2

AGND
15 SPK_OFF

DTC144TKA

Q528 DTC144TKA

AGND

AGND

+5V JS3 1 2 SHORT-SMT4

5V_AMP

-DEVICE_DECT

AVDDAD 1 C289 100U 6.3V EW6.3 1 2 + 1

C803 1 2 1

R731 2 1

C798 220P 0603 10% L535 1 600Z/100M 1608 2

External Micro Phone Jack

RA/D3.6/5P HCH IDJ-B27-F6T

R719 20K 2 0603

AOUT_R/L Cap x2 - SIZE0805


VR1_5 VR1 10K 7 6 3 2

2.2U 0805 10K +80-20% 0603

C792 1 2 10% 470P/NA 0603 21 20 1 R720 2 10K 0603 4 5 6 19 1 1 C248 1U 0603 C285 1U 0603 14 16 11 9 8 30 31 32 33 34 U16

L27 120Z/100M 2012

R713 10K 0603 0603 2 0603 2 AVDDAD -DEVICE_DECT

AGND

Amplifier
R OUT+ R OUTL OUT+ L OUTRVDD LVDD GND0 GND1 GND2 GND3 NC0 NC1 NC2 G1 G2 G3 G4 G5 22 15 3 10 18 7 1 12 13 24 2 17 23 25 26 27 28 29

RLINE IN RHP IN LLINE IN LHP IN L BYPASS R BYPASS SE/BTL# HP/LINE# MUTE IN MUTE OUT SHUTDOWN G6 G7 G8 G9 G10 TPA0202_GND

SPKROUT+ SPKROUTSPKLOUT+ SPKLOUT-

0805 4.7U +80-20% AOUT_R 2 1 C286 AOUT_L 2 1 C287 0805 4.7U +80-20% 1 1

4 1

C804 1 2 1

R732 2

C793 1 2 10% 470P/NA 0603

1608 1 600Z/100M 1608 1 600Z/100M 1608 1 600Z/100M 1608 1 600Z/100M

2 L39 2 L43 2 L44 2 L45

1 2 1 2

R L

2.2U 0805 10K +80-20% 0603

Very Close to TPA0202 Pin 18/7


1 1 1 C247 0.1U 0603 50V C284 0.1U 0603 50V

C280 100U 6.3V 1 2 +

J25 R710 22 LINE_OUT_5 HIROSE 1 ST/MA-2 R714 22 DF13-2P-1.25V LINE_OUT_2 J23 1 HIROSE R194 R174 ST/MA-2 DF13-2P-1.25V C791 100P 1K 1K C789 100P EW6.3 0603 0603 0603 0603 1 1 2 2 2 2 L536 2 600Z/100M 1608 1

Internal Speaker Connector

Line Out Phone Jack


J24 1 600Z/100M 2 L537 5 4 2 3 1 7 8 9 Drive IC LED 6 11

AGND

CAGND

AGND

1608

1 600Z/100M

2 1608 L534

-DECT_HP/OPT 1 4.7K 2 R726 0603 SPDIFOUT 1 2 1608 600Z/100M L28 L533 1 1608 2 600Z/100M/NA L525 1 1608 2 600Z/100M/NA

+3VS_SPD

JO33 JO32 C805 R733 2 1 R721 20K 2 0603 1 2 2 2 1 2.2U 0805 10K +80-20% 0603 VR1_2

AGND

470P/NA

0603 AMP_MUTE

AGND

TSSOP24_TPA0102

R159 47K 0603

L526 1 1 2 600Z/100M/NA 1608

AGND

AGND
1

R168 2 100K 0603

L527 1 1608 2 600Z/100M/NA

C806 1 2 1

R734 2

1 R722 2 10K 0603 C795 1 2 10% 470P/NA 0603

2.2U 0805 10K +80-20% 0603

C201 0.1U 0603 50V

SPK_OFF AGND

Shut Down

Normal

Signal

HI

LOW

Q523 R1

2 -DEVICE_DECT

L552 130Z/100M 1608 Title 8575A AUDIO CODEC & AUDIO AMP BD 311671700001 & TU 411671700011 Rev 01 of 30

0 Ohms?

DTC144TKA

AGND

AGND

AGND

5V_AMP CHOKE_PLP3216S_1 PLP3216S 3 4 1 CHOKE_PLP3216S_1 PLP3216S

CAGND

L530

AGND

AGND

C245 + 100U 16V EW6.3

2F1138-TJ1 FOXCONN

AGND

L529

C794 1 2 10%

Size Document Custom Number

Date:

Monday, June 17, 2002

Sheet

20

R.CH

Q10 R1

2 3

J28

L.CH

TOUCH_PAD
F1 +5V 1 1.1A L29 22 22 T_DATA T_CLK T_DATA L31 1 T_CLK L33 1 2 130Z/100M 2 130Z/100M 1608 1608 1 130Z/100M 1608 2 1 2 3 4 5 6 7 8 J20 HIROSE MA/8P/ST DF13B-8P-1.25V J501 GND2 GND1 8 7 6 5 4 3 2 1 ACES HDR/MA-8/NA 88206-0800 TP_GND 1 2 5 TP_GND RIGHT LEFT SCRL_UP SCRL_DOWN SW3 1 2 5 3 4 12V/50MA/NA STS-042-A SW2 3 4 12V/50MA/NA STS-042-A SW1 1 2 5 SA[0..17] 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 30 22 24 31 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 -MEMR -MEMW TP_GND TP_GND -MEMR SA[0..17] 17,22 3 4 12V/50MA/NA STS-042-A MTG1 ID2.2/OD5.5 MTG2 ID2.2/OD5.5 SW4 1 2 5 3 4 12V/50MA/NA STS-042-A TP_GND TP_GND MTG19 ID2.2/OD5.5 -ROMCS 17 MTG18 ID2.2/OD5.5 3 BAV99/NA
2

J502 2 TP_VCC DATA CLK 1 2 3 4 HIROSE ST/MA-4/NA DF13-4P-1.25V

D3 3 BAV99/NA 2 1

C222 47P 0603

C228 C221 47P 0.1U 0603 0603 50V

RIGHT

KO0 KO1 KI0 KI5

22 22 22 22

D4 2 3 BAV99/NA 1

LEFT

D1 2 1

17,22 SD[0..7]

SD[0..7] SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 13 14 15 17 18 19 20 21 1 +5VS 1 C218 0.1U 0603 50V

Flash ROM
U10 O0 O1 O2 O3 O4 O5 O6 O7 VPP A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 CE# OE#

SCRL UP

D6 2 3 BAV99/NA 1

R132 +5VS SA18 0 1 R128 0/NA 1 2 0603 2 0603

SCRL DOWN

TP_GND

Close to EEPROM
1 C216 0.1U 0603 50V

32

VCC

Flash ROM

TP_GND

-ROMCS

22

16

VSS

WE#

28F020-PLCC

8575 T/P BRD

STRAP OPTION XCNF2 X X 0 1 0 1 XCNF1 0 0 1 1 1 1 XCNF0 0 1 0 0 1 1 FUNCTIONALITY NO BIOS NORMAL MODE , XRDY DISABLE LATCH MODE ,XA12-19, XRDY ENABLE LATCH MODE , GPIO 10-17 , XRDY ENABLE LATCH MODE , XA12-19, XRDY DISABLE
1 1 1 1 2 +3VS

LATCH MODE , GPIO 10-17 ,XRDY DISABLE

C735 0.1U

C726 0.1U

C729 0.1U

C741 0.1U 50V 0603DA

BASE ADDRESS SELECT R303 MOUNTED OPEN DATA REGISTER INDEX REGISTER
15 LPC_AD[0..3] VDD0 VDD1 VDD2 VDD3 U511 LPC_AD0 LPC_AD1 LPC_AD2 LPC_AD3 11 CLK_LPC33 7,9,14,17,18,28,29 -PCIRST 15 LPC_FRAME# 15 LPC_DRQ# 17,18,28,29 CLKRUN# 15,18 SERIRQ 1 R737 100K 0603 SW503 4 3 1 2 HDS402 SW_HDS402 GND 2 11 CLK_SIO CLK_LPC33 -PCIRST LPC_FRAME# LPC_DRQ# -LPCPD CLKRUN# SERIRQ KBD_US/JP# CLK_SIO 14 39 63 88

50V 0603DA

50V 0603DA

50V 0603DA

4EH 2EH

4FH 2FH

LPC_AD[0..3] 15 16 17 18 8 9 12 11 7 6 10 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 SA0 SA1 SA2 SA3 -XSTB XCNF2 IRQ1 IRQ12 -IOR -IOW SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 95 94 93 92 91 90 87 86 85 84 83 82 81 80 79 78 77 76 75 74

P_LPD[0..7] PD0/INDEX# PD1/TRK0# PD2/WP# PD3/RDATA# PD4/DSKCHG# PD5/MSEN0 PD6/DRATE0 PD7/MSEN1 PNF/XRDY SLCT/WGATE# PE/WDATA# BUSY_WAIT#/MTR1# ACK#/DR1# SLIN#_ASTRB#/STEP# INIT#/DIR# ERR#/HDSEL# AFD#_DSTRB#/DENSEL STB#_WRITE# DCD1# DSR1# SIN1 RTS1#/TEST SOUT1/XCNF0 CTS1# DTR1#_BOUT1/BADDR RI1# IRTX IRRX1 IRRX2_IRSL0 IRSL1 IRSL3/PWUREQ# XD0/GPIO00/JOYABTN1 XD1/GPIO01/JOYBBTN1 XD2/GPIO02/JOYAY XD3/GPIO03/JOYBY XD4/GPIO04/JOYBX XD5/GPIO05/JOYAX XD6/GPIO06/JOYBBTN0 XD7/GPIO07/JOYABTN0 XWR#/XCNF1 XRD#/GPIO34/WDO# XIOWR#/XCS1#/MTR1#/DRATE0 XIORD#/GPIO37/IRSL2/DR1# XCS0#/DR1#/XDRY/GPIO25 52 50 48 46 45 44 43 42 35 36 37 40 41 47 49 51 53 54 55 56 57 58 59 60 61 62 70 69 68 67 66 3 2 1 100 99 98 97 96 4 5 73 71 72 P_LPD0 P_LPD1 P_LPD2 P_LPD3 P_LPD4 P_LPD5 P_LPD6 P_LPD7 PIO/-PNF P_SLCT P_PE P_BUSY -P_ACK -P_SLIN -P_INIT -P_ERR -P_AFD -P_STB -COM1DCD -COM1DSR COM1RXD -COM1RTS COM1TXD -COM1CTS -COM1DTR -COM1RI IRTX IRRX FIRSEL +3VS 1

P_LPD[0..7] 27

+3VS 1

LAD0 LAD1 LAD2 LAD3 LCLK LRESET# LFRAME# LDRQ# LPCPD# CLKRUN#/GPIO36 SERIRQ SMI#/GPIO35 CLKIN DSKCHG# HDSEL# RDATA# WP# TRK0# WGATE# WDATA# SETP# DIR# DR0# MTR0# INDEX# DENSEL DRATE0/IRSL2

R675 10K 0603 2

R681 10K 0603 2 P_SLCT P_PE P_BUSY -P_ACK -P_SLIN -P_INIT -P_ERR -P_AFD -P_STB 27 27 27 27 27 17,27 27 27 17,27

+3VS

+3VS 1

+3VS 1

+3VS 1

R149 10K 0603 COM1TXD XCNF0 2 2

R152 10K/NA 0603 2

R677 10K 0603

R744 10K 0603 2

J507 -MEMW IRTX IRRX FIRSEL SD0[0..7] 27 27 27 SD[0..7] 17,22 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 -XSTB 3 4 7 8 13 14 17 18 1 11 XCNF1 -COM1DCD -COM1DSR COM1RXD -COM1RTS COM1TXD -COM1CTS -COM1DTR -COM1RI Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 VCC GND 2 5 6 9 12 15 16 19 20 10 1 C115 0.1U 50V 0603DA SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 +3VS SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 +3VS 17 17 17 17 17 17 17 17 1 2 3 4 5 6 7 8 9 10 11 12 1 2 3 4 5 6 7 8 9 10 11 12

GND

17 17 17,22 17 17,22 17,22

SA0 SA1 SA2 SA3 TP515 IRQ1 IRQ12 1

VSS0 VSS1 VSS2 VSS3

282574373004

284587393002 PQFP100_0.5MM Title Size Date:


A B

13 38 64 89

PC87393

R245 1 4.7K 0603

+3VS

22 FAN_SPD0/1# 17,22 -IOR 17,22 -IOW 17 SA12 17 SA13 17 SA14 17 SA15 17 SA16 17 SA17 17 SA18 17 SA19

XA0/GPIO20 XA1/GPIO21 XA2/GPIO22 XA3/GPIO23 XA4/GPIO24/XSTB0# XA5/XSTB1#/XCNF2 XA6/GPIO26/PRIQA/XSTB2# XA7/GPIO27/PIRQB XA8/GPIO30/PIRQC XA9/GPIO31/MTR1#/PIRQD XA10/GPIO32/XIORD#/MDRX XA11/GPIO33/XIOWR#/MDTX XA12/GPIO10/JOYABTN1/RI2# XA13/GPIO11/JOYBBTN1/DTR2#_BOUT2 XA14/GPIO12/JOYAY/CTS2# XA15/GPIO13/JOYBY/SOUT2 XA16/GPIO14/JOYBX/RTS2# XA17/GPIO15/JOYAX/SIN2 XA18/GPIO16/JOYBBTN0/DSR2# XA19/DCD2#/JOYABTN0/GPIO17

SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 -MEMW -MEMR -MCCS -ROMCS

U8 D0 D1 D2 D3 D4 D5 D6 D7 OC G

FPC/FFC-12P/1MM/NA

-MEMR -MCCS -ROMCS

17 17,22 22

74AHC373_V 1 R92 10K 0603 TSSOP20

8575A SUPER I/O, T/P & BUTTON Document Number BD 311671700001 & TU 411671700011 Monday, June 17, 2002 Sheet 21 of 30 Rev 01

MICROCONTROLLER (H8)
+5VA BAV99/NA +5VA BAV99/NA 2 1 3 D503 BAV99/NA 2 1 3 D504 BAV99/NA 2 1 3 D505 +5VS 3 D7 BAV99/NA 2 3 D8 BAV99/NA 1 2 1 1 C522 1U_NA 0603

H8 Mode Select Table MD0 MD1 MODE 0 1 1 1 0 1 MODE1 MODE2 MODE3 Description Expended mode with On-Chip ROM disable Expended mode with On-Chip ROM enable Single-Chip mode
KO1 KI3 KI2 KI1 KI4

DEFAULT SHORT
RP510 1 2 3 4 0*4 1206 8 7 6 5 2 0603 -HDDACTP_KO1 -CAP_KI3 -NUM_KI2 -SCROLL_KI1 -CDACTP_KI4

R611 1 0

+5VA

H8_AVREF1 L521 1 2 120Z/100M/NA 1608

+5VA +3V 3 D511 +2.5V_DDR +VCC_CORE 1 2 BAV70LT1

Close to H8-3437F
1 1 1 C709 0.1U 0603 50V C708 0.1U 0603 50V C731 0.1U 0603 50V

Close to H8-3437F
1 C728 0.1U 0603 50V

10 10 10 17 17

-SCROLL -NUM -CAP -HDDACTP -CDACTP

-SCROLL -NUM -CAP -HDDACTP -CDACTP

RP509 1 2 3 4

0*4/NA

1206 8 7 6 5 2 0603

R610 1 0/NA

EASY START BTN


-HDDACTP_KO1 KO0 -PWRSW 1 3 5 7 9

3 J6 2 -SCROLL_KI1 4 -NUM_KI2 6 -CAP_KI3 8 -CDACTP_KI4 10 D9 BAV99/NA

2 1

2 3 D502 1 L522 1 2 JP_BEAD_DFS 0603B_DFS 9 59 37 4 70 71 92 15 46 36

Quick Switch Button: Stuff RP589, R1359 LED: Stuff RP590, R1360

GND_H8
4 3 2 1 1 1

BAT_VOLT BAT_TEMP RP512 22*4 1206 C736 0.1U 0603 50V C737 0.1U 0603 50V

R672 R671

1 2.2K 1 22

2 0603 2 0603

BAT_V BAT_T

Come From Battery


BAT_V BAT_T 23 23

SPEED S100-0000-101 HDR/SHR/MA/5PX2

GND_H8
J13
2

U509

Signal GND_H8
2.2K 1 R674 2 0603 I_LIMIT 27 5 6 7 8

HI Normal

LOW Suspend

+5VA

VSS1 VSS2 VSS3 VSS4 AVSS AVREF

VCC1 VCC2 AVCC VCCB

KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7

2 2 2 2 2 2 2 2 2 2 2 2

1 JO30 1 JO28 1 JO26 1 JO24 1 JO22 1 JO20 1 JO18 1 JO16 1 JO14 1 JO12 1 JO10 1 JO8 2 2 2 2 2 2 2 2 2 2 2 2

1 JO29 1 JO27 1 JO25 1 JO23 1 JO21 1 JO19 1 JO17 1 JO15 1 JO13 1 JO11 1 JO9 1 JO7

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 17,21 SD[0..7] SD[0..7]

Internal Keyboard Connector

KO0 KO1 KO2 KO3 KO4 KO5 KO6 KO7 KO8 KO9 KO10 KO11 KO12 KO13 KO14 KO15 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 H8_PWRON -H8_THRM SCI#/FAN_SWITCH SCI#/FAN_SPD IRQ1 IRQ12 -FAN0 -FAN1 LED_DATA -H8_SMI LED_CLK KI0 KI1 KI2 KI3 KI4 KI5 KI6 KI7

FPC/FFC/1MM/24P 85203-24-02 ACES

17,21 IRQ1 17,21 IRQ12 10 10 LED_DATA LED_CLK

KI5 KI0 KO1 KO0

KI5 KI0 KO1 KO0

21 21 21 21

CPU Fan Control


+5VS R682 H8_PWRON 1 1 R679 20K 0603 R684 2 33 0603 -FAN1 GND GND -EXTSMI -ROMCS -SB_THRM -MCCS 1 R146 1 R690 R691 1 R135 1 R127 27 -SW_+5VA 1 0 0603 2 1 R126 0/NA 0603 2 2 0 2 0 0603 0603 2 0 2 0 2 1 1K 0603 2 1 PWR_ON

79 78 77 76 75 74 73 72 67 66 65 64 63 62 61 60 82 83 84 85 86 87 88 89 49 50 51 52 53 54 55 56 14 13 12 26 27 28 29 32 33 34 35

-H8_RESET 10 2

P10/A0 P11/A1 P12/A2 P13/A3 P14/A4 P15/A5 P16/A6 P17/A7 P20/A8 P21/A9 P22/A10 P23/A11 P24/A12 P25/A13 P26/A14 P27/A15 P30/HDB0/D0 P31/HDB1/D1 P32/HDB2/D2 P33/HDB3/D3 P34/HDB4/D4 P35/HDB5/D5 P36/HDB6/D6 P37/HDB7/D7 P40/TMCI0 P41/TMO0 P42/TMRI0 P43/TMCI1/HIRQ1 P44/TMO1/HIRQ1 P45/TMRI1/HIRQ1 P46/PW0 P47/PW1 P50/TXD0 P51/RXD0 P52/SCK0 P60/KEYIN0/FTCI P61/KEYIN1/FTOA P62/KEYIN2/FTIA P63/KEYIN3/FTIB P64/KEYIN4/FTIC P65/KEYIN5/FTID P66/KEYIN6/IRQ6 P67/KEYIN7/IRQ7

Micro Controller

Close to NDS352P
1 C733 0.1U 0603 50V S R683 470K 0603 1 2

PWR_ON 24,27 H8/F3437

P70/AN0 P71/AN1 P72/AN2 P73/AN3 P74/AN4 P75/AN5 P76/AN6/DA0 P77/AN7/DA1 P80/HA0 P81/GA20 P82/CS1 P83/IOR P84/IRQ2/TXD1/I P85/IRQ4/RXD1/C P86/IRQ5/SCK1/S P90/IRQ2/ESC2 P91/IRQ1/EIOW P92/IRQ0 P93/RD P94/WR P95/AS P96/0 P97/WAIT/SDA MD0 MD1 PB0/XDB0 PB1/XDB1 PB2/XDB2 PB3/XDB3 PB4/XDB4 PB5/XDB5 PB6/XDB6 PB7/XDB7 PA0/KEYIN8 PA1/KEYIN9 PA2/KEYIN10 PA3/KEYIN11 PA4/KEYIN12 PA5/KEYIN13 PA6/KEYIN14 PA7/KEYIN15 /STBY/FVPP /NMI /RES XTAL EXTAL /RESO PQFP100_0.5MM

38 39 40 41 42 43 44 CHARGE_I_CTR BLADJ 45 SA2 93 94 -H8_KBCS 95 -IOR 96 -IOW_H8 97 -H8_MCCS_H8 98 BAT_CLK 99 PORT90 25 PORT91 24 T_CLK_H8 23 22 19 T_DATA 18 H8_ENABKL 17 BAT_DATA 16 H8_MODE0 6 H8_MODE1 5 SIS_PWRBTN 91 -H8_WAKE_UP 90 LEARNING 81 CHARGING_RP 80 SW_+5VA 69 H8_PWROK 68 D/VADJ_1_RP 58 D/VADJ_2_RP 57 -LID 48 -ADEN 47 31 -BATT_DEAD 30 H8_SUSC 21 -SUSC 20 BAT_CLK 11 H8_SUSB 10 -H8_STBY 8 -POWERBTN 7 -H8_RESET 1 2 3 100 R655 1 1M 1 2 0603 X503 2

-LID
+5VS 1

1 CHARGE_I_CTR 25 BLADJ 27 SA2 17,21 -IOR 17,21 9,27 ENABKL ENABKL 2 R647 10K/NA 0603 D12 1 3 BAT54/NA D509 1 BAT54 3 2 1 U507 RESET GND IMP811/NA SOT143 27 -LID -LID H8_ENABKL 1 0 0603 MN VCC 3 2 4 C714 2.2U 16V 1206 R663 2 2 R642 10K 0603

NA WHILE ASSEMBLY
R659 1 1K/NA 0603 2 1 2 SW5 3 4 MPU-101-80/NA

Cover Switch AGND

T_DATA

21

RP515 1 2 3 4 0*4 1206 C723 1 0 0603 +5VA Q520 R1 1 3 2 BATT_DEAD 8 7 6 5 CHARGING D/VADJ1 D/VADJ2 CHARGING D/VADJ1 D/VADJ2 25 25 25 -POWERBTN C712 0.1U 50V 0603 1 1 2 R643 1K 0603

SECOND POWER SWITCH


-PWRSW SW501 1 2 3 4 MPU-101-80/NA

LEARNING 27 SW_+5VA 27 H8_PWROK 7

NA WHILE ASSEMBLY

-ADEN

23,27

-CARD_RI 18

H8_SUSC 15 -SUSC 15,24

H8_MODE0 -H8_RESET -IOW_D PORT91

J26 1 3 5 7 9 2 4 6 8 10

H8_MODE1 -H8_MCCS_D PORT90 T_CLK_D +5VA

R654 10K 0603

BATT_DEAD 25

DTC144TKA

MA/.1/GOLD/NA -IOW_H8 -H8_MCCS_H8 T_CLK_H8 RP48 1 0*4 2 3 4 1206 8 7 6 5 -IOW -H8_MCCS T_CLK -IOW_D -H8_MCCS_D T_CLK_D

+3V C716 0.1U 0603 50V 1

+3V 2

-IOW T_CLK

17,21 21

C732 10P 0603 5% 2

+5VA 1

+5VA 1

+VCC_CORE

D10 J8 RLZ5.6B MLL34B 1 2 3

Q6 NDS352P G

R1

R747 10K 0603 15 -WAKE_UP -WAKE_UP 3 Q11 +3V 2

RP49

17,21 R15 +5VS 1 10K 0603 2 1 33 0603D R16 2 1 FAN1_SPD C25 1000P 0603D 4 4

-MCCS SCL_THRM SDA_THRM

Level Shift

14 17 18 21 22 1 13

2A1 2A2 2A3 2A4 2A5 1OE# 2OE#

2B1 2B2 2B3 2B4 2B5

15 16 19 20 23 24 12

-H8_MCCS BAT_CLK BAT_DATA R129 R130 JS2 1 2 SHORT-SMT3 1 JO31 2 OPEN-SMT3 1 2 5 1 1 2 22 2 22 +5VS BAT_C BAT_D +5VA 23 23 4 4 -THRMTRIP -THERM_ERR

Q504 DTC144TKA -THRMTRIP E -THERM_ERR 1 Q533 DTC144TKA

HIROSE ST/MA-3 DF13-3P-1.25V

FAN

Signal -FAN

HI FAN Off

LOW FAN On

U11 3 4 7 8 11 1A1 1A2 1A3 1A4 1A5 1B1 1B2 1B3 1B4 1B5 2 5 6 9 10

R138 10K 0603 -H8_SMI -H8_KBCS -H8_THRM

R125 10K 0603

15 21 15

-EXTSMI -ROMCS -SB_THRM

16MHZ C707 TXC8X4.5 68P 0603 5%

C710 68P 0603 5%

R519 0 0603

-H8_WAKE_UP

1 0*4/NA 1206 8 2 7 3 6 4 5

DTC144TKA

External Pull Up/Down


+5VA RP517 R665 10K 0603 -ADEN H8_MODE0 H8_MODE1 1 2 3 4 5 47K*8 1206 RP513 1 2 3 4 5 47K*8 BAT_CLK R666 1 R653 1 1206 2 10K 0603 2 10K 0603
1

+5VA 10 9 8 7 6

C 3 +5VA 15 SIS_PWRBTN# 1 SIS_PWRBTN# 3 Q515 DTC144TKA 1 2 R1

-BATT_DEAD -POWERBTN

VCC GND

SN74CBTD3384 QSOP24A

Close to 74CBTD3384DBQ
1 C214 0.1U 0603 50V

Small Fan Control


+5VS

GND

Reset Switch
SW502 3 4 K 12V/50MA TC010-PSs11CET-B(T) SW_STS-042A A

+3VS R718 1 1K 0603 D515 ESD0805A/NA 2 1 2

R725 10K 0603 U515 3 4 C799 0.01U 0603 MN VCC IMP811 SOT143 RESET GND 2 1 1

R1

SIS_PWRBTN

KI0 KI1 KI2 KI3

10 9 8 7 6

KI4 KI5 KI6 KI7

-H8_RESET

Close to NDS352P
1 1
1

C4 0.1U 0603 50V S

D5 J503 1 2 3 RLZ5.6B MLL34B 1 2 3

Q1 NDS352P G

R7 470K 0603 1 2

GND R5 2 33 0603 -FAN0 +5VS 3 BAT54 R17 100K 0603 2 D510 1 -SCI 15

GND 2

R724 100K 0603

BAT_DATA

+5V RP511 GND T_CLK T_DATA 1 2 3 4 4.7K*4 1206 HYST GND VTEMP 1 2 3 8 7 6 5

FAN

Signal -DC/DC_FAN

HI FAN Off

LOW FAN On

GND

+5V 1 -H8_RESET R680 10K 0603 Q518 R1 DTC144TKA SCI#/FAN_SWITCH 3 2 2 SCI#/FAN_SPD 2 +5VAS 1 5 4

U510 OS V+

DF13-3P-1.25H R6 +5VS 1 10K 0603 2 1 33 0603D R502 2 1 FAN0_SPD C505 1000P 0603D 21 FAN_SPD0/1# 2

Q5 DTC144WK

+5V GND +3V 2 1 R634 10K 0603 Q514 -SUSB 2 R1 1 3 Q512 DTC144TKA -SUSB Title Size Date: 8575A MICROCONTROLLER (H8) Document Number Rev 01 of 30 2 +5V

LM26/NA C734 1U/NA SOT25 0603

1 R652 10K 0603 2 H8_SUSB 3 DTC144TKA

GND

GND R1 G G Q519 R1 DTC144TKA 3 S3AUXSW# 1

FAN1_SPD

S D S

D Q4 2N7002

D D S

S Q3 2N7002

FAN0_SPD

7,15

S3AUXSW#

FAN_SPD

BD 311671700001 & TU 411671700011 Sheet 22

Monday, June 17, 2002

1.25V CM8500 CONNECTOR


4

& BATTERY

PL8 +1.25V 1 PC20 + 220U 7243 4V DDR_IN PR18 200K 0603 1 1% 1 PR19 1K 0603 1% 2 1 GND 2 2 1 2 PC28 1000P 0603 10% 1 PC29 1000P 0603 10% GND
3

1 3.3UH

2 1

PR17 5.1 0603 2

DDR_IN

PL506 1 120Z/100M 2012 2 +3VS

PC24 10U 1206 10V

PC25 0.1U 0805 25V +80-20% 1 2

1 2 3 4 5 6 7 8

VCC1 PVDD1 VL1 PGND1 AGND1 SD VIN/2 AGND2 CM8500 TSSOP16_GND

VCC2 PVDD2 VL2 PGND2 AGND4 VFB VCCQ AGND3 GND

16 15 14 13 12 11 10 9 17

PU10

PC26 0.1U 0805 25V +80-20% 1 1 2

1 PD9 RLZ3.6B/NA MLL34B GND 2

PC21 0.1U 0603 50V

GND +2.5V_DDR PC30 0.01U 50V 10% 0603D

R539 1K 0603 2

GND
3

GND

PC22 0.1U 0805 25V +80-20% 1 2

PC23 0.1U 0805 25V +80-20% 2

PC590 1000P 0603 10%

PC27 10U 1206 10V

+5VA 2 PR553 100K 0603 PR548 100K/NA 0603 2 1

VMAIN

4 1 -ADEN 22,27 PR552 33K 0603 2 G

4 G

5 6 7 8

PQ509 25,27 ADINP 1 PR551 226K 0603B 1% 1 2 2 S DTC144WK SOT23AN_1 G

D S

PQ508 2N7002 SOT23_FET GND

5 6 7 8

GND

25

BATT

BATT1

Battary connector
PL505 BEAD_120Z/100M_6A 0805D 25 BATT 1 1 2 PL504 BEAD_120Z/100M_6A PR564 301K 0603D 1% 2 0805D 1 2 1 PC588 0.01U/NA 50V 10% 0603D 22 PC582 0.1U 0603D BAT_T 1 PC19 0.1U 0603D 1 PR12 22 20K 0603D 1% 2 BAT_C 3 1 PR11 4.99K 0603D 1% GND 1 2 PD5 2 1 2 BAV99 PD8 GND 22 BAT_D 2 3 1 BAV99 GND GND +5VA BATTGND +5VAS 1 PF502 TR/SFT-10A FUSE_2917 2 J14 1 2 3 4 5 6 7 R/A-7P/2.5MM SUYIN 250005MR07G100ZU

PC579 1000P 0603

PC578 0.01U 50V 10% 0603D

GND

22

BAT_V 1

PR563 100K 0603D 1% 2

PC584 1000P 0603

PC583 0.01U 0805

GND

PU512 SI4835DY SO8

PU513 SI4835DY SO8

PC585 1000P 0603 10%

PC36 1000P 0603 10%

1 2

PC587 1000P 0603 10%

1 2 3

1 2 3

GND

Title Size C Date:

8575A Bat con, DDR 1.25V Document Number BD 311671700001 & TU 411671700011 Sheet
A

Rev 01 of 30

Monday, June 17, 2002

23

+1.8V_P 1

JO45 2 SHORT-SMT4 JO46

+1.8VS

SHORT-SMT4

PL7 VMAIN 1 1 120Z/100M 2012 2

D/VMAIN_P1 1 1 +2.5V_P 1 1 + PC11 10U 25V 2 PC10 0.1U 0603 50V 5 6 7 8 PU507 SI4416DY SO8 PC528 1000P 0603 25V 10% 1 PC546 10U 1210 25V 20% JO504 1 2 SHORT-SMT4 JO503 1 GND 2 SHORT-SMT4 +2.5V_DDR

PC37 1000P 0603 25V 10%

+ PC12 10U 25V 2

+5VA 1

GND PR538 100K 0603

GND TG1.8 4

D G

PR537 1 1K 0603 D PQ504 S 2N7002 SOT23_FET S 3 2 +5V 2 1 R877 10K 2 0603 R1 R878 1 5 6 7 8 1 1 0/NA 0603 2 +5V 1 PC553 0.1U 0603 50V PR570 0/NA 0603 GND 28 1 27 26 25 24 23 22 21 20 19 18 17 16 15 2 2 PSON 10,15,27 PC545 0.1U 0603 50V BG1.8 K 4 S PD506 BAS32L 2 BST1.8 1 GND A A 1 2 3 PD1 EC10QS04/NA D G PU7 SI4810DY SO8 +3VS SW1.8 S 1 2 3 PL3 1 10UH D124C 2 1.8V_2 1 PR515 0.015 2512 1% 1 1 1 2 1 +1.8V_P

G D D S S 2 GND PQ505 2N7002 SOT23_FET

22,27

PWR_ON

G 1 PR539

INTVCC1

1M PR530 0603 11K 0603 1% 1 2

PC548 0.022U 25V 0603 10% 1 2

Q538 DTC144TKA

PR508 12.7K 0603 1% 2 PC35 0.1U 0603 50V FB1.8V

1 2

PC521 1000P 0603

PR531 1 2.7K 1 2 2 2 PC563 2 1 2 2 0603

PC544 1000P 25V 0603 10% SENSE3+ SENSE3FB1.8V 1 2 3 4 5 6 7 8 9 10 11 12 13 14

SENSE3+ SENSE3-

PC524 + 150U 7343 6.3V

PC531 + 150U 7343 6.3V

1 PR507 10K 0603 1% 2

PU510 RUN/SS1 SENSE1+ SENSE1VOSENSE1 FREQSET STBYMD FCB ITH1 SGND 3.3VOUT ITH2 VOSENSE2 SENSE2SENSE2+ LTC3707 QSOP28 PGOOD TG1 SW1 BOOST1 VIN BG1 EXTVCC INTVCC PGND BG2 BOOST2 SW2 TG2 RUN/SS2

PC522 1000P/NA 0603

PC551 0.01U 0603 PC565 33P_NA 50V 0603 PR532 15K 0603 1% PR528 15K 0603 PC559 33P_NA 0603 1% 50V

1 1 1

FCB 1 470P 50V 1 2 0603 2

INTVCC1 PC554 10U 1206 16V A 1 2

PC550 0.1U 0603 50V

PC556 470P 50V 0603 1 2 PC561 1000P 25V 0603 10%

PD507 GND BAS32L 5 6 7 8 D G TG2.5 4 S PU509 SI4416DY SO8

GND

PC549 1000P 0603 25V 10%

PD510 K -SUSC 15,22 BAS32L A 1

PR529 2 0 0603 PC562 0.022U 0603 25V 10% 1 1 PC557 0.1U 0603 50V SW2.5 2

GND

FCB 1

PR523 1 0/NA 0603 2

1 2 3

PR524 0 0603 2 INTVCC1

PL4 1 10UH 2 2.5V_2 1

PR525 2 .01 2512 1% +2.5V_P

D G BG2.5 4 S 1 2 3

PU8 SI4810DY SO8 K 1 1 1 PD2 EC10QS04 2 A PC560 + 150U 7343 6.3V PC552 + 150U 7343 6.3V PC547 + 150U 7343 6.3V 1 PC564 0.1U 0603 50V

PR526 21.5K 0603 1% 2

PC558 470P/NA 50V 0603

5 6 7 8

1 2

PC543 10U 1206 16V

SENSE4+ SENSE4JS503 1 SHORT-SMT1 GND FB2.5V 2 2

PR527 10K 0603 1%

1 2

PC555 1000P/NA 0603

Title Size C Date:


E D C B

8575A +1.8V,+2.5V_DDR Document Number BD 311671700001 & TU 411671700011 Sheet


A

Rev 01 of 30

Monday, June 17, 2002

24

PQ1 PD3 L1
D

SO8 SI4835DY 8 7 6 5 PL6 L4 1 33UH IND_CDR127_1 PD4 EC31QS04 DC2010 A 2 1 1 L5 5 6

PL5 K L2 1 2 1 1 L3

3,27

ADINP

3 2 1 S G

PU9B SI4925DY SO8 3 L6 1

PU9A SI4925DY SO8 8 7 BATT K 23


D

PC38 1000P 0603 10%

PC39 1000P 0603 10%

PR4 4.7K 0603 2 2

PR14 4.7K 0603

EC31QS04 DC2010

BEAD_120Z/100M 0805D PC13 0.01U 10% 50V 0603

+ PC14 10U 25V

PC567 0.01U 0603 50V 10%

PC15 100U 25V

PC577PC17 10U 100U 1210 25V 25V

+ 2

+ PC18 100U 25V

PC576 0.1U 0603 50V

PR15 PR7 20K 0603 0.1% 100K 0603B A GND PR16 33K 0603 G LI_OVP GND D/VADJ1 22 D/VADJ2 22 1

PD511 RLZ20C MLL34B

B 2 PQ3 MMBT2222A E

PR3 100K 0603D

PR560 130K 0603 .1% 2

PC16 0.1U_NA 0603 50V 2IN+ 2

+5VAS 1 8

GND

GND

GND 1

PF501 2 K 1A-1206 FUSE_1206

1.25V

PD7 A BAS32L MLL34B PC581 0.1U 0603 50V 1 1

3 2

+ -

100K 0603 1 PU514A LMV393M SSOP8 GND

LI_OVP 1 1 1 PR10 13.7K 0603 0.1% 2 2 PR8 976K 0603 1% 1 PR9 487K 0603 1% 2 PQ4 D 2N7002 S SOT23_FET S D/VADJ_1 1 D/VADJ_2 PQ2A NDC7002N 3 2 4 6 D

PQ506 DTA144WK SOT23AN_1 22 CHARGING 1 PR544 47K 0603 G S PR545 1M 0603 2 2 2 PQ507 2N7002 SOT23_FET D S 1

PR558 13.7K 0603 0.1% 2

PC573 150P 0603

PU511 PC569 0.1U 0603B 50V 9 10 11 12 13 14 15 16 E1 C1 E2 GND C2 RT VCC CT OUTPUTCTRL DTC REF FEEDBACK 2IN1IN2IN+ 1IN+ TL594C SO16 1 PC575 0.01U 50V 10% 1 2 0603 8 7 6 5 4 3 2 1

PC571 0.01U_NA 0603 50V 10% 1 2

GND

GND

PR562 2

GND

2IN+ 1

PQ2B NDC7002N 1 1 PC568 1000P 0603B 10%,X7R

PC566 1U 0805 16V 2

PR541 100K 0603B

GND 2

PR550 1M 0603 1% 2 2

PC574 0.1U_NA 0603B 50V

1 PR540 10K 0603B 1% PR6 1M 0603 PR549 8.66K 0603 1% 2

1 PR5 1M 0603 2

PR542 10K 0603B 1% REF PC570 1 2 0.1U 50V 0603B 2

1 1 2 PC572 0.1U 25V 0603 20% 1 PR543 6.19K 0603 1% 2 1 1 PR547 249K 0603 1% 2 2.49K 0603 1% PR546 JO506 1 OPEN-SMT2 2 2 GND JO507 OPEN-SMT2 PR13 0.02 2512 1%

BATTGND

JS1 2 1 1 SHORT-SMT3 VMAIN


B

CHARGE_I_CTR 22
B

+5VAS

1 PR561 4.7K 0603 2

PC580 1U 0805 25V

PR556 576K 0603 2 8

1 PR559 100K 0603

VADJ_2_P 12.30V
BATT_DEAD 22

VADJ_1_P 0 1 0 1

BAT_TYPE 0 0 0 0

NIMH_CELL 0 0 0 0

PQ510 SOT23N SCK431LCSK-.5 2

GND 1.25V

5 6

+ 4

0 0 1 1

7 PU514B LMV393M SSOP8

12.40V 12.50V 12.60V

1 3

1 C898 0.1U 0603 50V 2 PR557 100K 0603 1%

GND

LI

9.68V

GND

Title Size C Date:


5 4 3 2

8575A Charger Document Number Rev 01 of 30

BD 311671700001 & TU 411671700011 Sheet


1

Monday, June 17, 2002

25

PL502 120Z/100M 2012 1 1 PC507 1000P 0603 PL501 120Z/100M 2012 1 2 2 1 1 1 1 PC505 0.1U 0603 50V PC530 0.1U 0603 50V PC513 0.1U 0603 50V PC512 0.1U 0603 50V core_in

CPU CORE
1 1 1 1 1 1 + PC31 47U 25V 2 2 + PC32 47U 25V 2 + PC33 47U 25V 2 + PC34 10U/NA 25V 1 PC516 0.1U 0603 + PC7 820U 4V 2 2 2 2 2 2 GND GND 1 PR519 18.2K 0603 1% 1 PC534 1 2 2 1000P 0603 10% 2 RUN/SS 2 22K 0603 VID0_P VID1 VID2 VID3 VID4 PC541 PD517 BAS32L MLL34B 1 A PR576 0 0603 1 2 1 INTVCC_3 2 PR511 1 2.2K 0603 2 1% PR513 1 0603 10K 2 INTVCC_3 1% 1 470P 0603 10% 1 8 36 4 4 4 4 4 VID0_P VID1 VID2 VID3 VID4 17 18 19 20 21 4 15 16 10 5 6 22 23 7 PR518 43.2K 0603 1% +5V 1 PR571 2 1 0 0603 PC532 1U 0805 10V 1 INTVCC_3 A PR514 1 2 5.1 0603 PC526 0.1U 0603 50V PU508 TG1 BOOST1 SW1 BG1 35 33 34 31 PU501 FDD6676 SOT252B_FET D D 2

+VCC_CORE

VMAIN

+ PC9 820U 4V 2

PC6 + 220U 7343 2.5V

PC8 + 220U 7343 2.5V

PC591 + 220U 7343 2.5V

1 2

PC592 + 220U 7343 2.5V

GND
D

GND
D

GND

H_PWRGD

PD504 EC10QS04 K G

G DH1_CORE_2 S S

PU515 FDD6676 SOT252B_FET

CORE_PG

PR572 2 0 0603

PGOOD K K VID0 VID1 VID2 VID3 VID4 EAIN ATTENOUT ATTENIN VDIFFIUT PLLFLTR PLLIN VBIAS SGND PGND AMPMD FCB SENSE1+ SENSE12 3 1 24 26 25 27 DH2_CORE_1 G PC527 2 1000P 25V 0603 10% S PU1 FDD6676 SOT252B_FET G S PU2 FDD6676 SOT252B_FET G S PU3 FDD6672A SOT252B_FET

PC525 1 2 0.022U 0603 25V 10% PC536 PR522 1 2 1000P 10% 1 0603 25V

30 29 32

GND

GND DH1_CORE_1

RUN/SS ITH

EXTVCC INTVCC VIN

PC529 0.1U 0603 50V

CORE_1

PL1 1 1.25UH 0.8X3 30% PD501 EC31QS04-TE12L A A 2 1

PR502 2 .005 1% 2512 1 2 1 PR501 0.003 2512 1% PC503 10U 1206 10V 1 PC504 10U 1206 10V 1 1

+VCC_CORE

DL1_CORE

+3V

RUN/SS

+ PC3 820U 4V 2 2

+ PC5 820U 4V

1 2

PC506 0.1U 0603 50V

INTVCC_3 1 1

PR573 2K 0603 PR575 130K 0603 1% 2

TG2 BOOST2 SW2 BG2

PD515 EC31QS04-TE12L

S1+ S1GND

PR574 10K 0603 2 2

PC595 2 0.01U 0603 2 PR577 0_NA 0603

+3V

PR521 2 10 0603 MOBO/DT# 2 PC542 0.1U 0603 1

SENSE2+ SENSE2VOS+ VOS-

14 13 12 11 FB+

GND

S2+ S2GND
C

B D PQ512 2N7002 G E

PQ511 MMBT3904L 1

2 PR580 0_NA 0603 2

PR579 0_NA 0603

LTC3716 SSOP36A 2 1 JO511 SHORT-SMT2 PC533 PD505 10U 1206 EC10QS04 10V PU502 FDD6672A SOT252B_FET D PU516 FDD6672A SOT252B_FET D

D S S

PC596 680P 0603 10%

GND

PR581 2 20K 1% 0603

PC517 0.1U 0603 50V

PC537 1 2 1000P 25V 0603 10% 2

1 PR1 10 0603 GND GND 2 K G S G S PR503 0.003 2512 1% 2 1.25UH 0.8X3 30% K K PD502 EC31QS04-TE12L S A A 1 PR504 1 .005 2512 1% 2 2 2 GND 1 PR2 10 0603 4 VCC_SENSE DT/MOBO# 2 PC538 0.1U 0603 50V 1 DH2_CORE_2 CORE_2 PU4 FDD6672A SOT252B_FET D D D PU5 FDD6672A SOT252B_FET PL2 1 2 PU6 FDD6672A SOT252B_FET PQ9 2N7002 DL2_CORE PR20 187K 0603 1% 2 G S D 1 G S G G S D S PD516 EC31QS04-TE12L 2

PR582 2 1 0/NA 0603 JS501 SGND1 1 SHORT-SMT1 PQ513 2N7002 D JO34 2 PQ514 2N7002 G 1 SHORT-SMT2 D S S DT/MOBO# D GND D PQ515 S 2N7002 SOT23_FET S 2

GND

15

VR_GATE

+5VA RUN/SS 1 PR585 100K 0603 2

G
B

5 CPU_CORE_EN

G S

D S

PQ516 2N7002 SOT23_FET

JO35 SHORT-SMT2 1

For Mobile

28

D S

GND FBPQ10 2N7002 D D S

VSS_SENSE 4 JO36 2 1 SHORT-SMT2 D PQ7 2N7002 MOBO/DT# G S 1 1

S PR21

GND

+5VA

R909 0_NA 0603 1 2

PR22 412K 0603 1% 2

2 20K 1% 0603

VID0 1 PR23 750K 0603 1% 2 0_NA 0603 PR29 26.7K 0603 1% 2 PQ519 D 2N7002 S PQ520 2N7002 G 1 PR601 1M 0603 2 DT/MOBO# D D 2 PR25 PR27 PR30 PR31 PR33 1 1 1 1 1 2 0603 2 0603 2 0603 2 0603 2 0603 VID2 VID3 VID4 PQ8 2N7002 DT/MOBO#G S VID0

D S

+5VA

PR24 D PQ518 S 2N7002 1

+5VS

PR590 2 1 0 0603 PR593 10K/NA 0603

G S

VID0_P VID1 1 PR28 100K 0603 SW6 DT/MOBO# W/N# PQ6 2N7002 D S W/N# G S PQ5 2N7002/NA D S G S 1 2 3 4 FHDS-04 PR34 2M 0603 2 8 7 6 5 2

0_NA 100K 0_NA 0_NA 0_NA

FB-

MOBO/DT# Mobile Northwood Willamette ON OFF OFF

DT/MOBO# OFF ON ON

W/N# OFF OFF ON


A

GND PR32 15 DPRSLPVR 1 0 0603 K A


A

MOBO/DT#

2 1

G S PR602 1M 0603 PD10 BAS32L/NA MLL34B A K 2

D S S

FB-

PD6 BAS32L MLL34B

D S 2

PR35 2M 0603 2

PR26 2M 0603

GND

GND GND GND GND Title Size C Date: 8575A CPU CORE Document Number Rev 01 of 30

BD 311671700001 & TU 411671700011 Sheet


1

Monday, June 17, 2002

26

+5VA
ALWAYS F504 1 3216FF-1 1 2 8 2 7 3 R618 10K 0603 2 U506 IN SENSE F/B SHUTDN LP2951-02BM SO8 5VTAP OUT ERRGND 6 1 5 4 H8_AVREF1 D K K Q509 +5VA S 1 C699 4.7U 1206 16V 1 S Q511 +5VA D D S D S +5V

+5VAS
Q8 +5VAS S 1 R80 100K 0603 2 D D S G

D508 GND A RLZ5.6B MLL34B A

D516 UDZ5.6B SOD323

C698 10U 1206 16V

SI2301DSG 2 GND

R621 100K 0603 2

SI2301DS

SI2301DS D11 A RLS4148 K -ADEN 22,23


1

-SW_+5VA 22 3

GND GND

GND

GND 22 SW_+5VA 2

Q510 DTC144WK

Q9 DTC144WK 2

+3V

GND 1 GND 4 5 6 7 8 9 3 2 1 12 11 10

MTG26 ID2.8/OD7.6

J7 P_LPD0 P_LPD1 P_LPD2 P_LPD3 P_LPD4 P_LPD5 P_LPD6 P_LPD7 P_SLCT -P_STB -P_AFD -P_ERR -P_INIT -P_SLIN -P_ACK P_BUSY P_PE 0603 16 16 21 21 21 USB_OC0_1# USB_OC3_5# FIRSEL IRRX IRTX 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 50 48 46 44 42 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 49 47 45 43 41 39 37 35 33 31 29 27 25 23 21 19 17 15 13 11 9 7 5 3 1 LEARNING DP_LPD0 DP_LPD1 DP_LPD2 DP_LPD3 DP_LPD4 DP_LPD5 DP_LPD6 DP_LPD7 DP_SLCT -DP_STB -DP_AFD -DP_ERR -DP_INIT -DP_SLIN -AC_POWER -BATT_LED -BATT_G -BATT_R ENPBLT PWR_ON USBP_5USBP_5+ -LID 22 I_LIMIT 22 LEARNING 22

GND MTG27 ID2.8/OD7.6 12 11 10 7 8 9

21 21 21 21 21 21 21 21 21 17,21 21 21 17,21 21 21 21 21

P_LPD0 P_LPD1 P_LPD2 P_LPD3 P_LPD4 P_LPD5 P_LPD6 P_LPD7 P_SLCT -P_STB -P_AFD -P_ERR -P_INIT -P_SLIN -P_ACK P_BUSY P_PE

8 7 6 5 8 7 6 5 8 7 6 5 8 7 6 5 R501 1

1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 2

DP_LPD0 DP_LPD1 DP_LPD2 DP_LPD3 DP_LPD4 DP_LPD5 DP_LPD6 DP_LPD7 DP_SLCT -DP_STB -DP_AFD -DP_ERR -DP_INIT -DP_SLIN -DP_ACK DP_BUSY DP_PE

RP501 0*4 1206 RP503 0*4 1206 RP504 0*4 1206 RP505 0*4 1206

DP_BUSY FIRSEL DP_PE IRRX IRTX -DP_ACK USBP_0USBP_0+ USBP_1USBP_1+

4 5 6

3 2 1

9 9

TV_CRMA TV_LUMA USBP_3USBP_3+ +5VA +5VAS BLADJ +12VS PSON BLADJ PSON

GND -AC_POWER 10 -BATT_LED 10 -BATT_G 10 -BATT_R 10 ENABKL 9,22 PWR_ON 22,24

22 4 3 2 1 4 3 2 1 4 3 2 1 4 3 2 1 10,15,24 1 C504 22P 0603 5%

FM/22PX2/1.27 B06P-0110-441 SPEED GND

5 6 7 8

5 6 7 8

5 6 7 8

CP503 22P*4 1206

CP504 22P*4 1206

CP505 22P*4 1206

J4
3

+5V +3VS +3V 23,25 ADINP

1 3 5 7 9 11 13 15 17 19 1 1 1 PC1 10U 1210 16V PC2 10U 1210 16V PC4 0.1U 0603

5 6 7 8 CP506 22P*4 1206 2 4 6 8 10 12 14 16 18 20

+5VS

ALWAYS DVMAIN1 VMAIN

USBP_02 1

USBP0- 1616

USBP12 1

USBP_1-

HDR/10PX2/H8.4 PH/PS-D-RA-44-X-X CEN

PC502 0.1U 0603

CHOKE_PLP3216S_1 PLP3216S/NA 1 PC501 0.01U 0805 USBP_0+ L555 USBP0+ 1616 0603 USBP1+ 3 4 3 4

CHOKE_PLP3216S_1 PLP3216S/NA L556 USBP_1+

GND

GND

GND

GND

GND

GND

R886 0 2 R888 2

R887 2 0 1 0603 0 1 R889 2 0 1

1 0603 0603

USBP_52 1

USBP5-

16

USBP_32 1

USBP3-

16

CHOKE_PLP3216S_1 PLP3216S/NA
4

CHOKE_PLP3216S_1 PLP3216S/NA L558 USBP3+ 16


4

L557 USBP5+ 16 USBP_3+

USBP_5+

R890 2 0 R892 0 2

1 0603 0603

R891 R893

2 2

0 0

1 0603 1 0603

Title Size C Date:


A B C D

8575A TO D/D Connector & H8 power Document Number BD 311671700001 & TU 411671700011 Sheet
E

Rev 01 of 30

Monday, June 17, 2002

27

MINI-PCI
D

MINI-PCI
D

AD21 PCI_INTD# REQ2#/GNT2#

+3VS

14,18,29 PCI_AD[0..31] +3VS 2

AD[0..31] J509 R873 10K/NA 0603 3 2 0603 MPCI_PD1 2 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 GND1 GND2 TIP RX+ RXPJ7 PJ8 LED1_GRNP LED1_GRNN CHSGND INTB# 3.3V[0] RESERVED0 GROUND0 CLK GROUND1 REQ# 3.3V[1] AD[31] AD[29] GROUND2 AD[27] AD[25] RESERVED1 C/BE[3]# AD[23] GROUND3 AD[21] AD[19] GROUND4 AD[17] C/BE[2]# IRDY# 3.3V[2] CLKRUN# SERR# GROUND5 PERR# C/BE[1]# AD[14] GROUND6 AD[12] AD[10] GROUND7 AD[8] AD[7] 3.3V[3] AD[5] RESERVED2 AD[3] 5V[0] AD[1] GROUND8 AC_SYNC AC_SDATA_IN AC_BIT_CLK AC_CODEC_ID1# MOD_AUDIO_MON AUDIO_GND0 SYS_AUDIO_OUT SYS_AUDIO_OUT_GND AUDIO_GND1 RESERVED3 VCC5VA GND1 GND2 124P/0.8MM/H6 SPEED B27-101-0038 1 RING TX+ TXPJ4 PJ5 LED2_YELP LED2_YELN RESERVED4 5V[1] INTA# RESERVED5 3.3VAUX[0] RST# 3.3V[4] GNT# GROUND9 PME# RESERVED6 AD[30] 3.3V[5] AD[28] AD[26] AD[24] IDSEL GROUND10 AD[22] AD[20] PAR AD[18] AD[16] GROUND11 FRAME# TRDY# STOP# 3.3V[6] DEVSEL# GROUND12 AD[15] AD[13] AD[11] GROUND13 AD[9] C/BE[0]# 3.3V[7] AD[6] AD[4] AD[2] AD[0] RESERVED_WIP4[0] RESERVED_WIP4[1] GROUND14 M66EN AC_SDATA_OUT AC_CODEC_ID0# AC_RESET# RESERVED7 GROUND15 SYS_AUDIO_IN SYS_AUDIO_IN_GND AUDIO_GND2 MPCIACT# 3.3VAUX[1] 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 1

10,15

MPCI_PD

DTC144TKA/NA Q536 1 R874 1 0 R801 1 0/NA

14,17,29 PCI_INTC# 11 CLK_MINIPCI


C

2 0603

R1

MINIPCI_INTC#

+5VS MINIPCI_INTD# R800 1 0 2 0603 PCI_INTD# 14,17 7,9,14,17,18,21,29


C

-PCIRST

14,17 PCI_REQ2# AD31 AD29 AD27 AD25 14,18,29 PCI_C/BE#3 PCI_C/BE#3 AD23 AD21 AD19 AD17 PCI_C/BE#2 PCI_IRDY# CLKRUN# PCI_SERR# PCI_PERR# PCI_C/BE#1 AD14 AD12 AD10 AD8 AD7 AD5 AD3 +3VS AD1+5VS 1 C851 0.1U 0603 50V C852 0.1U 0603 50V

PCI_GNT2# 14,17 MPCI_PME# AD30 AD28 AD26 AD24 1 AD22 AD20 PCI_PAR AD18 AD16 PCI_FRAME# PCI_TRDY# PCI_STOP# PCI_DEVSEL# AD15 AD13 AD11 AD9 PCI_C/BE#0 AD6 AD4 AD2 AD0 1 +3VS 1 +3VS R803 10K 0603 2 0 0603 100 0603 PCI_PAR 14,17,18,29 MPCI_PME# 15

R802 2 PCI_AD21

14,18,29 PCI_C/BE#2 14,17,18,29 PCI_IRDY# 17,18,21,29 CLKRUN# 14,17,18,29 PCI_SERR# 17,18,29 PCI_PERR# 14,18,29 PCI_C/BE#1

PCI_FRAME# 14,17,18,29 PCI_TRDY# 14,17,18,29 PCI_STOP# 14,17,18,29 PCI_DEVSEL# 14,17,18,29

PCI_C/BE#0 14,18,29

R885 2 MPCI_PD1

GND +3VS

C849 10U 1206 10V

C850 0.1U 0603 50V

Q534 D MPCIACT# MPCIACT# 15

S D S

SI2302DS JS511 1 2 SHORT-SMT4 C846 0.1U 0603 50V

C853 0.1U 0603 50V

C854 0.1U 0603 50V

C855 0.1U 0603 50V

+3V

C856 0.1U 0603 50V

GND

PIN24, 124 ARE AUX_POWER

GND

GND

GND

Title Size C Date:


5 4 3 2

8575A Mini PCI Rev 01 of 30

Document Number

BD 311671700001 & TU 411671700011 Sheet


1

Monday, June 17, 2002

28

NEC UPD72872
D

AD22 INTC# REQ1#/GNT1#

IEEE1394-uPD72872
14,18,28 PCI_AD[0..31] PCI_AD[0..31] PCI_AD31 PCI_AD30 PCI_AD29 PCI_AD28 PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23 PCI_AD22 PCI_AD21 PCI_AD20 PCI_AD19 PCI_AD18 PCI_AD17 PCI_AD16 PCI_AD15 PCI_AD14 PCI_AD13 PCI_AD12 PCI_AD11 PCI_AD10 PCI_AD9 PCI_AD8 PCI_AD7 PCI_AD6 PCI_AD5 PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 PCI_AD0 CLKRUN# 1394_PME# 9 10 12 13 15 16 17 18 23 24 26 27 28 29 32 33 47 48 49 50 52 53 55 56 58 59 62 63 65 66 67 68 2 3 4 8 35 36 37 39 40 41 42 44 87 U18 AD31 AD30 AD29 AD28 AD27 AD26 AD25 AD24 AD23 AD22 AD21 AD20 AD19 AD18 AD17 AD16 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 CLKRUN PME INTA REQ FRAME IRDY TRDY DEVSEL STOP PERR SERR PAR XI PC2 PC1 PC0 72 71 70 PC2 PC1 PC0 +3VS

+PHYVDD +3V L543 1 2 130Z/100M 0603D +3V L544 1 2 130Z/100M 0603D C233 0.1U 50V 0603D

+PHYAVDD

C857 4.7U 0805 +80-20%

C231 0.1U 50V 0603D

C859 0.1U 50V 0603D

C861 4.7U 0805 +80-20%

C235 0.1U 50V 0603D

C863 0.1U 50V 0603D

C239 0.1U 50V 0603D

C241 0.1U 50V 0603D

1 2

C252 0.1U 50V 0603D


D

GND

GND

C259 0.1U 50V 0603D

C275 0.1U 50V 0603D

C276 0.1U 50V 0603D

C292 0.1U 50V 0603D

C293 0.1U 50V 0603D

C294 0.1U 50V 0603D

C295 0.1U 50V 0603D

C296 0.1U 50V 0603D

GND

TPB1N TPB1P TPA1N TPA1P

98 99 100 101

TPBTPB+ TPATPA+ TPBIAS1 C875 1 C876 1 C297 1 C298 1 2 1U/NA 0603 2 1U/NA 0603 2 1U/NA 0603 2 1U/NA 0603

TPBIAS1 TPBIAS0 TPB0N TPB0P TPA0N TPA0P GROM_SDA GROM_SCL LVDD0 LVDD1 LVDD2 LVDD3 LVDD4 LVDD5 LVDD6 PCI_VDD0 PCI_VDD1 P_DVDD2 P_DVDD3 P_DVDD4 P_AVDD5 P_AVDD6 P_AVDD7 P_AVDD8 P_AVDD9 P_AVDD10 DGND0 DGND1 DGND2 DGND3 DGND4 DGND5 DGND6 DGND7 DGND8 DGND9 DGND10 AGND0 AGND1 AGND2 AGND3 AGND4 AGND5 AGND6 AGND7

96 97 102 103 104 105 116 117 1 14 25 31 43 51 64 19 60 73 79 112 82 86 90 95 110 111 11 20 30 38 46 54 61 69 80 113 120 83 84 89 94 106 107 108 109 0 GND SDATA SCLK 2

14,17,28 PCI_INTC#

R224 1 0 0603

17,18,21,28 CLKRUN# 15 1394_PME#

R804 0 0603

GND
C

XI XO R225 1 1M X6 C299 22P 0603D 3 2 4 24.576MHZ NOTE P/N:274012457405 1 2 0603D 1 1 C300 22P 0603D

14,17 PCI_REQ1# 14,17,18,28 PCI_FRAME# 14,17,18,28 PCI_IRDY# 14,17,18,28 PCI_TRDY# 14,17,18,28 PCI_DEVSEL# 14,17,18,28 PCI_STOP# 17,18,28 PCI_PERR# 14,17,18,28 PCI_SERR# 14,17,18,28 PCI_PAR XI

uPD72872
GND +3VS

uPD72873/74
NA 0 R811 NA

R227 R229 R811 R813

0 NA NA 0

R230
+PHYVDD R227 R229 R811 R813 0603 1 R272 0603 1 R273 2 0 2 0 1 1 1 1 0 0/NA 0/NA 0 2 2 2 2 0603 0603 0603 0603 +PHYVDD +PHYAVDD

NA 0 0 0

0 NA NA NA

RI0 & RI1 connect an external resistor of 9.1K 0.5% to limit the LSI's current.
7,9,14,17,18,21,28 -PCIRST 11 CLK_1394PCI 14,17 PCI_GNT1# R231 1 100 2 0603 1 C301 0.1U 0603 50V

XO R228 9.09K 1% 1 2 0603

88 91 92 5 6 7 22 78 81 93 85 115 114 77 76

R882 R883 R884

XO RI0 RI1 PRST PCLK GNT IDSEL PORTDIS P_RESETB CPS ICN ICL4 ICL3 ICL2 ICL1 CARD_ON GROM_EN ICH2 ICH1 CBE3 CBE2 CBE1 CBE0 UPD72872 PQFP120_0.4MM

GND

GND 14,18,28 PCI_AD22

PORTDIS CPS

TP519 1

+PHYAVDD

ALWAYS 1

PC2
B

R232 1 10K 1 RP529 2 3 4

2 0603D +3VS 8 7 6 5

GND R233 1 10K 0603 R234 1 10K 0603 2 2

CARDON

119 118 75 74

R230 1 GND 100K 0603 2 2

R226 390K/NA 0603 CPS

PORTDIS PC1 PC0 CARDON

+PHYVDD

10K*4 RPSOA_8C GND

PCI_C/BE#3 PCI_C/BE#2 PCI_C/BE#1 PCI_C/BE#0 14,18,28 PCI_C/BE#[0..3]

21 34 45 57

1 R274

2 0603

GND

TPB+ +5VS +3VS +3VS TPB1 1 1 1 1 TPBTPB+ TPATPA+

R195 1 2 0 0603 CHOKE_PLP3216S_1 PLP3216S/NA 1 2 J27 1 2 3 4 JO505 JO501 JO502 JO510 2 4 6 8 1 1 1 R196 1 0 1 2 2 0603 1 GND1 GND2 1 2 3 4 GND1 GND2 IEEE1394/4P LINKTEK AVR20-4XXX0X 1 3 5 7
A

R235 0/NA 0603 2 2 U7 1 2


A

R236 0 0603 2

R237 2.7K/NA 0603 2

R86 2.7K 0603 2

R87 2.7K 0603 R239 1

C302 2 5.1K

56 270P 10% 0603 R238 1 56 1 2 2 0603D

A0 A1 A2 GND NM24C02N SO8

SDA SCLK WCVCC

5 6 7

SDATA SCLK C303 1

2 1%

0603D

R240

0603D

0.01U 2 1U

0603D

R241

56 56

0603D 4

3 4

L42 3 PLP3216S/NA CHOKE_PLP3216S_1 R197 1 2 0 0603 R198 1 0 2 D24 ESD41A/NA RPSOA_8_1

TPBTPB+ TPATPA+

L41

JS506 1 2 SHORT-SMT4 1394_GND

8 1 C93 0.1U 0603 50V

R242 0 0603 2

C304

0603D

R243

0603D

TPA+ GND TPBIAS1 TPA-

0603 Title Size C Date: 8575A IEEE 1394 Rev 01 of 30

Document Number

BD 311671700001 & TU 411671700011 Sheet


1

Monday, June 17, 2002

29

8575 A MB R01
D D

R00 R0A PVT R01 MP

First Generation
Page-15 R280,R281,D26 --->DEL Page-15 R257 (VR HI/LO#)/100K--->Pull-down Page-22 R909 to +5VA/NA Reserve for Pull-up

Title Size C Date:


5 4 3 2

8575A M/B Revision Document Number BD 311671700001 & TU 411671700011 Sheet


1

Rev 01 of 30

Monday, June 17, 2002

30





  
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Reference Material

Intel Pentium 4 Processor mPGA478 Socket SiS650 IGUI Host / Memory Controller SiS691 MuTIOL Media I/O Controller SiS301LV / Chrontel CH7019 TV/LVDS Encoder PCI1410GGU PCMCIA Controller uPD72872 IEEE1394 Controller 8575A Hardware Engineering Specification

Intel, INC SiS, INC SiS, INC SiS, INC TI, INC NEC, INC Technology Corp./MiTAC

SERVICE SERVICE MANUAL MANUAL FOR FOR 8575A 8575A


Sponsoring Editor : Jesse Jan Author : Sissel Diao Assistant Editor : Janne Liu Publisher : MiTAC International Corp. Address : 1, R&D Road 2, Hsinchu Science-Based Industrial, Hsinchu, Taiwan, R.O.C. Tel : 886-3-5779250 First Edition : Aug. 2002 E-mail : Willy.Chen @ mic.com.tw Web : http: //www.mitac.com http: //www.mitacservice.com Fax : 886-3-5781245

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