Verilogesoterica PDF

Implementation of Digital Systems
Robert J. Jump and Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University
Synthesizable Verilog
Last class
Behavioral models for combinational logic Dont cares and combinational logic synthesis Describing sequential machines Different types of sequential machines And their synthesis
Today

ELEC 327 Implementation of Digital Systems
Case statement simplification

module fred ( f, a, b, c ); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3b000: f = 1b0; 3b001: f = 1b1; 3b010: f = 1b1; 3b011: f = 1b1; 3b100: f = 1b1; 3b101: f = 1b0; 3b110: f = 1b0; 3b111: f = 1b1; endcase endmodule
module fred ( f, a, b, c ); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3b000: f = 1b0; 3b101: f = 1b0; 3b110: f = 1b0; default: f = 1b1; endcase endmodule
Dont cares in synthesis

An unknown x on the right-hand side will be interpreted as a dont care a b
module caseExample ( f, a, b, c ); output f; input a, b, c; reg f; always @ (a or b or c) case ({a, b, c}) 3b001: f = 1b1; 3b010: f = 1b1; 3b011: f = 1b1; 3b100: f = 1b1; 3b111: f = 1b1; 3b110: f = 1b0; default: f = 1bx; endcase endmodule
ab
0 1
00 01
11
10
x 1
1 1
0 1
1 x
The inverse function was implemented; xs taken as ones

ELEC 327 Implementation of Digital Systems 4
Dont cares in synthesis

full_case attribute Tells synthesis tool that case is full though not all case items are specified Unspecified cases are taken to be dont cares
module fullCaseExample ( f, a, b, c ); output reg f; input a, b, c; always @ (a or b or c) // synthesis full_case case ( {a, b, c} ) 3b001: f = 1b1; 3b010: f = 1b1; 3b011: f = 1b1; 3b100: f = 1b1; 3b111: f = 1b1; 3b110: f = 1b0; endcase endmodule
Example from previous slide shown here full_case can always be replaced by default: f = 1bx;
One-hot encoding (with casex)

parallel_case attribute
Can you remove the full_case attribute and replace it by a default case?
Case statements can have overlapping case items Statements executed in the order specified, with complex priority logic parallel_case tells synthesis tool that there is no overlap i.e., only one case item can be true at any time parallel, full cases can be realized as sum-of-products with very simple decoding logic
module oneHot ( oneHot, a, b, c ); output [2:0] oneHot; input a, b, c; reg [2:0] oneHot; always @ (a or b or c) //synthesis full_case, parallel_case casex ({a, b, c}) 3b1xx : oneHot = 3b010; 3bx1x : oneHot = 3b001; 3bxx1 : oneHot = 3b100; endcase endmodule
One-hot encoding (with casex)

Semantics of casex without parallel_case

if ( a == 1 ) oneHot = 3b010; else if ( b == 1 ) oneHot = 3b001; else if ( c == 1 ) oneHot = 3b100; else oneHot == 3bxxx;
Semantics of casex with parallel_case directive to synthesis

if ( a == 1 ) oneHot = 3b010; if ( b == 1 ) oneHot = 3b001; if ( c == 1 ) oneHot = 3b100;
Priority decoding implicit when case and casex are used
Synthesis assumes one and only one of {a, b, c} will be true at any time Synthesis ignores xs
Casex after synthesis

latch
oneHot[2]
c b a
oneHot[0] oneHot[1]
c a
oneHot[1] oneHot[2]
latch latch
oneHot[0]
latch
oneHot[1] oneHot[0] oneHot[2]
b a c
latch latch
c a b
oneHot[2] oneHot[1] oneHot[0]
What does synthesis do here?

Draw the Karnaugh map

module question ( dataOut, a, b ); output dataOut; input a, b; reg dataOut; always @ (a or b) casex ({a, b}) 2b1x : dataOut = 1b1; 2bx1 : dataOut = 1b0; default : dataOut = bx; endcase endmodule
Sequential Machines (Finite State Machines)

All machines that we will design in this class are synchronous

i.e., all activity is synchronized to clock edges Positive or negative edge of a single system clock
Single-phase clocking

What are description styles that Verilog supports? How do you specify and synthesize equivalent machines?
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A first example
4-bit shift register

Single port dataIn Right shift each cycle
module shiftReg ( A, B, C, D, dataIn, clock ); output A, B, C, D; input dataIn, clock; reg A, B, C, D; always @ (posedge clock) begin A = B; B = C; clock DFF DFF C = D; dataIn D = dataIn; end endmodule
B
DFF DFF
A C D
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First, flip-flop (FF) inference

If a variable is assigned a value under the control of a clock edge, a FF is inferred

Exception is when a variable is assigned and used locally within the always block as an intermediate variable always@(posedge clock) means that a positive-edge triggered FF is inferred always@(negedge clock) for a negative-edge triggered FF Order of statements can also cause problems
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What about this?

module shiftReg ( A, B, C, D, dataIn, clock ); output A, B, C, D; input dataIn, clock; reg A, B, C, D; always @ (posedge clock) begin D = dataIn; C = D; B = C; A = B; clock end endmodule DFF DFF
A B C D
clock dataIn
DFF DFF
OR ...
B
DFF DFF DFF DFF
dataIn
A C D
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Non-blocking assignment
Used blocking assignment (=) so far

Alternative is the non-blocking assignment (<=)

Think of it as an immediate assignment Its result can be immediately consumed Statements following a blocking assignment are blocked from execution until the statement with the blocking procedural assignment completes Think of it as a delayed, concurrent assignment Order of listing implies no precedence
Rule of thumb
Edge-sensitive (i.e., synchronous) operations described with non-blocking assignments (in a separate always block) Combinational logic with blocking assignments (in a separate always block)
What about this?

module shiftReg ( A, B, C, D, dataIn, clock ); output A, B, C, D; input dataIn, clock; reg A, B, C, D; always @ (posedge clock) begin D <= dataIn; C <= D; B <= C; A <= B; end endmodule
Synthesis ALWAYS produces
B
DFF DFF DFF DFF
clock dataIn
A C D
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Moore Sequential Machine

Output dependent only on the state of the machine

Not on the primary inputs Use an always block State transitions and output logic described with case statements
Verilog description

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Moore Sequential Machine

clock DFF DFF module mooreFSM (A, clock, Z); parameter S0 = 0, S1 = 1, S2 = 2, S3 = 3; input A, clock; A output reg Z; reg [0:1] mooreState; always@(posedge clock) case (mooreState) S0: begin Z <= 1; mooreState <= (!A) ? S0 : S2; end S1: begin Z <= 0; mooreState <= (!A) ? S0 : S2; end S2: begin Z <= 0; mooreState <= (!A) ? S2 : S3; end S3: begin Z <= 1; mooreState <= (!A) ? S1 : S2; end endcase endmodule
DFF
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Moore machine with non-registered outputs

Previous style of description produces registered outputs

i.e., an extra DFF is inferred for each primary output Thus, changes in the primary output are synchronized to the system clock Possible to move output to a combinational block Primary outputs no longer registered
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Moore machine with non-registered outputs

module mooreFSM (A, clock, Z); input A, clock; output Z; clock reg Z; DFF reg [0:1] mooreState; parameter S0 = 0, S1 = 1, A S2 = 2, S3 = 3; always@(posedge clock) case (mooreState) S0: begin mooreState <= (!A) ? S0 : S2; end S1: begin mooreState <= (!A) ? S0 : S2; end S2: begin mooreState <= (!A) ? S2 : S3; end S3: begin mooreState <= (!A) ? S1 : S2; end endcase always@(mooreState) case (mooreState) S0: Z = 1; S1: Z = 0; S2: Z = 0; S3: Z = 1; endcase endmodule
DFF
Mealy Sequential Machine

Primary outputs dependent on

State of the machine as well as Primary inputs Can thus change asynchronously with respect to system clock Use two always blocks State transitions and output logic described with case statements (combinational logic block) Sequential logic block Example on next slide uses asynchronous reset
Verilog description

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Mealy FSM
module mealyFSM (A, clock, reset, Z); input A, clock, reset; output Z; reg Z; reg [0:1] mealyState, nextState; parameter ST0 = 0, ST1 = 1, ST2 = 2; always@(posedge reset or posedge clock) if (reset) mealyState <= ST0; else Note the use of the dummy mealyState <= nextState; nextState register
Yet, only 2 DFFs are synthesized always@(mealyState or A) case(mealyState) ST0 : begin Z = A ? 1 : 0; nextState = A ? ST2 : ST0; end ST1 : begin Z = A ? 1 : 0; nextState = A ? ST0 : ST1; end ST2 : begin Z = 0; nextState = A ? ST1 : ST2; end default : begin Z = 0; nextState = ST0; end endcase
endmodule
Synthesized Mealy FSM

A
reset clock
RDFF RDFF
Note: RDFF is a DFF with asynchronous reset
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Mealy FSM with registered output

module mealyFSM (A, clock, reset, Z); input A, clock, reset; output Z; reg Z, nextZ; reg [0:1] mealyState, nextState; parameter ST0 = 0, ST1 = 1, ST2 = 2; always@(posedge reset or posedge clock) if (reset) begin mealyState <= ST0; Z <= 0; end else begin mealyState <= nextState; Z <= nextZ; end always@(mealyState or A) case(mealyState) ST0 : begin nextZ = A ? 1 : 0; nextState = A ? ST2 : ST0; end ST1 : begin nextZ = A ? 1 : 0; nextState = A ? ST0 : ST1; end ST2 : begin nextZ = 0; nextState = A ? ST1 : ST2; end default : begin nextZ = 0; nextState = ST0; end endcase endmodule
Mealy FSM with registered output

clock
reset
RDFF
RDFF RDFF
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J. Robert Jump and Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University
Mixing things up
module flagBits ( clock, A, B, C, X, Y, Z ); input clock, A, B, C; output X, Y, Z; reg X, Y, Z; always@(negedge clock) begin X = X & A; Y <= X | B; Z <= Y ^ C; end endmodule
?
DFF DFF
?
clock DFF
? ?
?
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Implicit FSM
module implicitFSM ( dataIn, c1, c2, clock, dataOut ); input dataIn, c1, c2; input clock; output dataOut; reg dataOut, temp; always begin @(posedge clock) temp = dataIn | c1 | c2; @(posedge clock) dataOut = temp; end endmodule dataIn, c1, c2 clock DFF
0 1
0 1
DFF
DFF
How many states are there in the FSM? Is an output produced on every cycle? Are the inputs sampled every cycle?
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Three stage pipeline

module threeStagePipe(dataIn, c1, c2, clock, dataOut); input dataIn, c1, c2; input clock; output dataOut; reg dataOut, stageOne, stageTwo; always@(posedge clock) stageOne <= dataIn + c1; always@(posedge clock) stageTwo <= stageOne & c2; always@(posedge clock) dataOut <= stageTwo + stageOne; endmodule
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Three stage pipeline

clock dataIn c1 c2 DFF DFF DFF
dataOut

Is an output produced on every cycle? Are the inputs sampled every cycle?
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Four-valued logic
Verilog Logic Values

What basis do these have in reality?

The underlying data representation allows for any bit to have one of four values 1, 0, x (unknown), z (high impedance) x one of: 1, 0, z, or in the state of change z the high impedance output of a tri-state gate 0, 1 logic levels z A tri-state gate drives either a zero or one on its output If its not doing that, its output is high impedance Tri-state gates are real devices z is a real electrical affect x is not a real value but a debugging aid There is no real gate that drives an x on to a wire x means the simulator cant determine the answer and so maybe you should worry. All values in simulation start as x.

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Four-valued logic
Logic with multi-level logic values

Nand anything with a 0, and you get a 1. This includes having an x or z on the other input. Thats the nature of the nand gate Nand two xs and you get an x Note that z is treated as an x on an input Rows and columns are the same A dangling input will be seen as a z
Input B nand 0 1 x z 0 1 1 1 1 1 1 0 x x x 1 x x x z 1 x x x Input A A 4-valued truth table for a nand gate with two inputs
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Tri-state logic synthesis

When is tri-state logic used?
module triState(ready, d1, d2, select); input ready, d1, d2; output select; reg select; ready always@(ready or d1 or d2) if(ready) select = 1'bz; else select = d1 & d2; endmodule
select
d1 d2
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Tri-state logic synthesis

module triState(ready, d1, d2, select); input ready, d1, d2; output select; reg select; always@(posedge clock) if(ready) select <= 1'bz; else select <= d1 & d2; ready endmodule clock
Assignment to z under clock edge results in extra FF to hold tri-state enable How is this fixed?
Disadvantages
D Q select
clk
d1 d2
D Q clk
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Use before assignment

Use before assign produces inferred flip-flops in some cases

module useBeforeAssign(clock, PS, NS); input clock, PS; output NS; reg NS, temp; always@(posedge clock) begin NS <= temp; temp = PS; end endmodule temp D Q L Q D Q L Q
PS clock
NS
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Multi-phase clocks
Restriction is that a variable cannot be assigned under 2 different clock conditions

What about asynchronous preset, etc.
module multiPhaseClk(clk, A, B, C, Out); input clk, A, B, C; output Out; C reg Out, D; always@(posedge clk) Out <= D | C; always@(negedge clk) D <= A & B; endmodule
clk A B
DFF
DFF
Out
Asynchronous preset and clear

Synthesis template
module asyncCtr(clock, preset, clear, presetData, data); input clock, preset, clear, presetData; output data; reg data; always@(posedge preset or posedge clear or posedge clock) if(preset) data <= presetData; else if(clear) data <= 0; else data <= data + 1; endmodule
always@(posedge clock or negedge A or negedge B or ... ) if(A) // negedge A <statement> // asynchronous logic else if (!B) // negedge B <statement> // asynchronous logic else if(!C) // negedge C <statement> // asynchronous logic ... else // posedge clock implied <statement> // synchronous logic
clock clear presetData preset
data
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J. Robert Jump and Kartik Mohanram Dept. of Electrical and Computer Engineering Rice University
Simulation techniques
Digital simulation

Compiled code Event driven simulation (discrete event simulation) How the simulator is built Trade-offs Examples Timing and delay
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Levels of simulation
SPICE

Switch and transistor levels Elaborate process libraries required Precise, but takes forever Based on numerical analysis techniques Higher level of abstraction Faster
Digital logic simulation

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Simulation of HDLs
Programming languages (say, C)

Sequential Statements executed in order of appearance Parallel (concurrent) instances Algorithmic approaches to logic simulation
Digital circuits

Levelized compiled code Discrete time simulation Event driven simulation

Execution modeled in terms of events Simulation with inertial and transport delays
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Levelized (compiled code) simulation

Levelize the circuit

Sort gates in topological order

Generate code (say, C) for each gate Add I/O routines Add control loop Compile Run
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Levelization
Topological sort

Level equals 0 for all the inputs Level (gate) = max { Levels of fanin } + 1
a b
L=1 L=2 L=2 L=3
L=4
L=5
c d L=1 L=4
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Code generation
Circuit { x1 = ~a; x2 = ~d; How is levelization done in practice? x3 = x1 & b; x4 = x1 & d; x1 a x5 = x3 + x4 + c; x6 = ~x5; x7 = x5 & x2; b x3 Out = x6 & x7; x6 }
0 delay simulation (why?)

Cycle accurate
c d
x4
x5
x2
Out x7
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Kinds of delays
Transport delay
Input to output delay (sometimes propagation)
a b
Zero delay models (all transport delays = 0)

Functional testing Theres no delay, not cool for circuits with feedback
transport delay nand #(3, 4, 5) (c, a, b);
Unit delay models (all transport delays = 1)

All gates have delay 1. OK for feedback
rising delay
delay to z
falling delay
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Delay
Transport delay input to output delay

nand #35 (f1, a, b, c);
#35 is the transport delay
What if the input changes during that time?

How wide must an input spike be to affect the output? Think of the gate as having inertia the input change must be present long enough to get the output to change. (That long enough time is called inertial delay) In Verilog, this time is equal to the transport delay
a b c pulse too small, no output change c
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a b
transport delay
a b
Discrete time simulation

Try to address loss in timing information

Noise, performance, power, etc. all require embedded timing information
General approach divide time into small increments and simulate all element outputs for each increment of time
Problem computationally very intensive and slow
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Discrete time simulation

Models evaluated and state updated only at time intervals (n)

Even if there is no change on an input Even if there is no state to be changed Need to execute at finest time granularity Might think of this as cycle accurate things only happen @(posedge clock) You could do logic circuits this way, but either: Lots of gate detail lost as with cycle accurate levelized simulation (no gates!) Lots of simulation where nothing happens every gate is executed whether an input changes or not
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Exercise
Assume all signals are x to begin with

Simulate (a,b,c,d,e,f) switching to (1,1,0,0,1,0) Then, simulate (a,b,c,d,e,f) switching to (0,0,0,0,1,1)
a b c d e f
g,#2 h,#4
j,#2
L,#1
i,#3
k,#2
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Discrete event simulation

Also called event driven simulation

Picks up simulation efficiency due to its selective evaluation Event driven approach simulate an element only when its inputs have changed Why is this effective? For any time increment, very few signals change (< 10% in large circuits), so activity limited
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Event driven simulation

Events changes in state at discrete times

Quick example

These cause other events to occur. Execute something (?!) when an event occurs at its input Events are maintained in time order Time advances in discrete steps when all events for a given time have been processed B Gate A changes its output Only then will B and C execute A C
Observations

The elements in the diagram dont need to be logic gates This works because there is a sparseness to gate execution Maybe only 10-15% of gates change at any one time The overhead of the event list pays off then
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Formally, an event occurs when a signal changes in value Simulation is event driven if new values are computed:
only for signals affected by events that have already occurred, and only at those times when changes can occur
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Event driven simulation without delay

A B C D
0
A=x B=x C=x D=x
x x x x
10
A=1 B=0 C=0 D=0 D=1 D=1
A B
20
B=1
30
A=0
40
B=0
50
tsim
C=1
C=0
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Even driven simulation with delay

A B C D
0
x x x
13
A x B
15 20
10
30
40
50 tsim
A=x B=x C=x D=x
A=1 B=0
B=1
A=0
B=0
C=1 C=0 D=0 D=1
C=0
D=1
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Inside the simulator

A time-ordered list of events is maintained

All events for a given time are kept together Propagates values, executes gate models, creates new events
time-ordered event list tn t3 t2 t1 schedules new events Scheduler executes Gate Models
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The scheduler removes events for a given time and

remove current events updates
looks at
all the events for time ti
Gate outputs
Network connections (fanouts)
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Event list Delays are g1 = #2, g2 = #3, and g3 = #5 initial A=1 at values as 25 shown Eval g1 B=0 at 27 initial A=1 at values as 25 shown 1 A=1 1 1 A=0 g1 0 1 g1 0 1 initial C=1 at B=0 at A=1 at values as 27 25 30 shown
g2 B=1 g3 g2 B=0 g3
C=0 D=1
C=0 D=1
Eval g2, g3 g2 B=0 0 g3

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C=1 D=1
1 A=1
g1
How does it keep track of time?

Events are stored in an event list 2-dimensional list ordered by time Events execute at a time and possibly schedule their output to change at a later time (a new event) When no more events for the current time, move to the next Events within a time are executed in arbitrary order
Lets say A changes to 0 here. B and C have delay 2. time a time a + 2 time a+75 event event event event event Events to update B and C are added. event
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event
1 A 1
time a+792
event
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Two types of events

Update events
Action: update state and propagate new values along a fanout Possibly produces new events Action: evaluate or execute a model Possibly produces new events
Evaluation events

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Event-Driven Simulation
1
#2
B=0
while something in time-ordered event list { 0 A= 1 C=0 advance simulation time to top events time update #2 retrieve all events for this time 1 For each event in arbitrary order { If its an update event { 1 B= 0 1 Update the value specified #2 Follow fanout, evaluate gates there A= 0 1 If an output changes C= 0 schedule update event for it #2 1 } else { // its an evaluation event update evaluate the model } } }
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What about zero delay events?

Update events on gates/models with 0 delay are scheduled for the current time
But are not retrieved and executed until the next simulation cycle The simulator can spend several iterations (even loop forever) at the same simulation time
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Exercise
Assume all signals are x to begin with

Simulate (a,b,c,d,e,f) switching to (1,1,0,0,1,0) Then, simulate (a,b,c,d,e,f) switching to (0,0,0,0,1,1)
a b c d e f
g,#2 h,#4
j,#2
L,#1
i,#3
k,#2
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30
De-scheduling of events
A B C D
0 10 20 30 40 50 time
A B
A=x B=x C=x D=x
A=1 B=0
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B=1 C=1 D=0
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C=1 A=0
35
D=0 C=0
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Sensitivity lists
In the gate level timing model

Model execution was sensitive to any change on any of the inputs at any time. Sensitivity list Lists dont change in the gate level timing model
However, in procedural models, the sensitivity list changes as a function of time and execution
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Procedural Timing Model

What is the behavioral model sensitive to?

Behavioral statements execute in sequence So, a behavioral model is sensitive to its context i.e., it is only sensitive to what it is currently waiting for time, edge, level (#, @, wait) The following model is not sensitive to a change on y or w.
always begin @ (negedge clock1) Here, it is only sensitive to clock1 q = y; Here, it is only sensitive to @ (negedge clock2) clock2. Any activity on q = w; clock1 will have no effect @ (posedge clock1) when waiting here. /*nothing*/ ; end
Fanout Lists
Outputs of things are connected to inputs of other things

The simulator maintains a fanout list of inputs driven by each output When the output changes, its easy to figure out what other models need (to be) evaluated Because of procedural models sensitivity lists change fanout lists change sensitivity lists fanout lists
Why maintain a fanout list?

Whats an output in a behavioral model?
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Scheduling #, @, and wait

How are #, @, and wait tied into the event list?

# delay schedule the resumption of the process i.e., put it in the event queue delay units into the future. Essentially an evaluation event scheduled in the future @ change when suspended for an @v, the behavioral model is put on the fanout list of the variable v. i.e., the behavioral model is now sensitive to v. When an update event for v occurs, (e.g. posedge), then the behavioral model resumes at the current time. Wait (exp) If exp is TRUE, dont stop; if exp is FALSE, then the behavioral model is put on the fanout list(s) of the variable(s) in exp. (its now sensitive to the variable(s)) When there is an update event for any of the variables in exp , exp is evaluated. If exp is TRUE, resume executing in the current time , else go back to sleep
Procedural model sensitivity

Quick example

Gate A changes its output What models get executed?

B A C
Yes
In what order do these models execute? Arbitrary! The simulator will try to make them look like they all occur at the same time
always @(A) begin R = ~A; end always @(posedge clock) Q <= A;
Maybe
always begin @(A) R = ~A; @(D) R = ~B; end
No
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Formal Verification
Design correctness
FV can be used to verify a design against a reference design as it progresses through the different levels of abstraction
Testbenches and simulation that we have adopted in this class
Three main categories:

Verifies functionality without test vectors
Model Checking: compare a design to an existing set of logical properties (that are a direct representation of the specifications of the design). Properties have to be specified by the user (far from a push-button methodology) Theorem Proving: requires that the design is represented using a formal specification language. Present-day HDLs are not suitable for this purpose. Equivalence Checking: it is the most widely used. It performs an exhaustive check on the two designs to ensure they behave identically under all possible conditions. Blows up very, very fast
Procedural timing model

How does the procedural model advance time? always begin # delaying a specific amount of time #5 q = w; @ delaying until an event occurs @ (negedge v) posedge, negedge, or any change q = y; edge-sensitive and level-sensitive behavior wait (c == 0) When the statement is encountered, q = 3; the value v is sampled. When v changes end in the specified way, execution continues. wait possibly delaying until an event occurs Everything executes in level sensitive behavior zero time time While one model is waiting for one of the advances when youre above reasons, other models execute not executing!` Values change, and time marches on
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An example of wait
Semantics
wait (expression) statement; wait (a == 35) q = q + 4; if the expression is FALSE, the process is stopped when a becomes 35, it resumes with q = q + 4 if the expression is TRUE, the process is not stopped it continues executing
module handshake (ready, dataOut, ); input ready; output reg [7:0] dataOut; reg [7:0] valueWeCalculated; always begin wait (ready); dataOut = valueWeCalculated; wait (~ready) end ready
No. Not if ready is already true when the first wait is executed. Youre not guaranteed to get the value at the edge
Do you always get the value at the edge when ready goes from 0 to 1? Isnt this edge behavior?
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Wait vs. while

Wait is used to wait for an expression to become TRUE

The expression eventually becomes TRUE because a variable in the expression is changed by another process For the case below, if the expression is TRUE, the simulator will continuously execute the loop. Another process will never have the chance to change in. Infinite loop.
module no (input in); while (in != 1); endmodule while cant be used to wait for a change on an input to the process. Need other variable in loop, or # or @ in loop.
While is used in the normal programming sense

module yes (input in); ... wait (in == 1); endmodule
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Blocking assignments and #

Weve seen #delay

Delay for specified time Options for specifying delay #10 a = b + c; Wait #10, then do the statement a = #10 b + c; Calculate b+c, wait 10, then do assignment Note the action of the second one: Termed an intra-assignment time delay The event list is used for temporary storage! The differences: #10 a = b + c; Values b and c are from time (now + 10) a = #10 b + c; Values b and c are from time (now)
And blocking assignments they use =

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Intra-assignment delay
Allows for delay to occur within the assignment

Between when the RHS is evaluated and when the LHS is assigned Inputs sampled, a delay occurs, outputs are then assigned Which is correct for a D flip-flops specification @posedge clock q = #10 d; q = @(posedge clock) d;
OR
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What does blocking really mean?

Blocking the always or initial block stops (blocks) for some reason
#, @, wait(FALSE)
always begin
q = blahblah; It blocks (stops) here, other things (always, gates, assigns) execute. Finally at t+10, this continues executing
r = q - someInput;
a = #10 q + r;
t = a - someOtherInput; end
Event-Driven Simulation
while (something in time-ordered event list) { Advance simulation time to immediate events time Retrieve all events E for this time E For each event E in arbitrary order { Update the value specified Follow fanout Evaluate the model(s) Schedule resulting events } Evaluate these } One traversal of the while loop is a simulation cycle. In 1 cycle, we remove all events for a time & execute them. New events may be scheduled for the current time they are put in the event list and retrieved in the next simulation cycle.
New event
74
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Implementation of Digital Systems

ELEC 327 Implementation of Digital Systems

Case statement simplification

ELEC 327 Implementation of Digital Systems

Dont cares in synthesis

An unknown x on the right-hand side will be interpreted as a dont care a b

The inverse function was implemented; xs taken as ones

Dont cares in synthesis

ELEC 327 Implementation of Digital Systems

One-hot encoding (with casex)

ELEC 327 Implementation of Digital Systems

One-hot encoding (with casex)

Semantics of casex without parallel_case

Semantics of casex with parallel_case directive to synthesis

Priority decoding implicit when case and casex are used

ELEC 327 Implementation of Digital Systems

Casex after synthesis

oneHot[1] oneHot[0] oneHot[2]

oneHot[2] oneHot[1] oneHot[0]

ELEC 327 Implementation of Digital Systems

What does synthesis do here?

Draw the Karnaugh map

ELEC 327 Implementation of Digital Systems

Sequential Machines (Finite State Machines)

All machines that we will design in this class are synchronous

ELEC 327 Implementation of Digital Systems

4-bit shift register

Single port dataIn Right shift each cycle

First, flip-flop (FF) inference

If a variable is assigned a value under the control of a clock edge, a FF is inferred

ELEC 327 Implementation of Digital Systems

What about this?

ELEC 327 Implementation of Digital Systems

Used blocking assignment (=) so far

Alternative is the non-blocking assignment (<=)

What about this?

Synthesis ALWAYS produces

ELEC 327 Implementation of Digital Systems

Moore Sequential Machine

Output dependent only on the state of the machine

ELEC 327 Implementation of Digital Systems

Moore Sequential Machine

Moore machine with non-registered outputs

Previous style of description produces registered outputs

ELEC 327 Implementation of Digital Systems

Moore machine with non-registered outputs

Mealy Sequential Machine

Primary outputs dependent on

ELEC 327 Implementation of Digital Systems

Synthesized Mealy FSM

Note: RDFF is a DFF with asynchronous reset

ELEC 327 Implementation of Digital Systems

Mealy FSM with registered output

Mealy FSM with registered output

ELEC 327 Implementation of Digital Systems

Implementation of Digital Systems

ELEC 327 Implementation of Digital Systems

Three stage pipeline

ELEC 327 Implementation of Digital Systems

Three stage pipeline

ELEC 327 Implementation of Digital Systems

Verilog Logic Values

What basis do these have in reality?