European Journal of Scientific Research ISSN 1450-216X Vol.74 No.1 (2012), pp. 96-105 EuroJournals Publishing, Inc.

. 2012 http://www.europeanjournalofscientificresearch.com

A Novel Leakage Power Reduction Technique for CMOS VLSI Circuits

M. Geetha Priya Assistant Professor Amrita Vishwa Vidyapeetham, Coimbatore, India E-mail: geetha.sri82@gmail.com K. Baskaran Associate Professor Government College of Technology, Coimbatore, India E-mail: baski_101@gmail.com D. Krishnaveni Assistant Professor APS College of Engineering, Bangalore, India E-mail: mailkveni@gmail.com

Abstract In recent years, with shrinking of device technologies, leakage power (static power) dissipation has become an inevitable proportion of the total power dissipation in an integrated circuit. The leakage power dissipation is projected to grow exponentially during the next decade according to the International Technology Roadmap for Semiconductors (ITRS). This directly affects portable battery operated devices. In this paper a robust method which is equally effectual for static power control for CMOS VLSI circuits in deep submicron technologies has been proposed. It is also referred to as sleepy pass gate uses two complementary sleep transistors connected in parallel forming a pass gate structure. In our leakage reduction technique, the exact output logic state is preserved in both active and standby mode of operation. Thus, experiments conducted with a range of process technologies on combinational logic gates and MCNC91 benchmark circuits show that the proposed method gives significant savings in leakage power upto 2 orders of magnitude, with lesser area and delay penalty.

Keywords: CMOS, leakage power, static power, sleep transistor, threshold voltage, stacking.

1. Introduction
Power dissipation of VLSI chips is traditionally a neglected subject. In the past, device-density and operating frequency were low enough, also that it was not a constraining factor in the chips. As the scale of integration improves, more transistors, faster and smaller than their predecessors, are being

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packed into a chip. This leads to the steady growth of the operating frequency and processing capacity per chip, resulting in increased power dissipation [2, 7]. There are three sources of power dissipation in a digital CMOS circuit. The first source is the logic transitions. In this source, nodes in a digital CMOS circuit transition back and forth between the two logic levels, the parasitic capacitances are charged and discharged [10]. Current flows through the channel resistance of transistors, and electrical energy is converted into heat and dissipated away. This component of power dissipation is proportional to the supply voltage, node voltage swing, and average switched capacitance per cycle. The voltage swing in most cases is simply equal to supply voltage, the dissipation due to transitions varies overall as the square of supply voltage [10]. Short-circuit currents that flow directly from supply to ground when the Pull-Up Network (PUN) and the Pull-Down Network (PDN) of a CMOS gate both conduct simultaneously are the second source of power dissipation. With input(s) to gate stability at their logic levels, only one of the two networks conduct and no short-circuit current flow. But when the output of a gate is changing in response to change in input(s), both PUD and PDN conduct simultaneously for a brief interval. The last source of dissipation is leakage current that flows when input(s) to, and therefore outputs of, a gate are not changing. This is termed as static power dissipation. In past days technology the magnitude of leakage current was low and usually neglected. In current trends, the supply voltage is being scaled down to reduce dynamic power and MOS field-effect transistors (MOSFETs) with low threshold voltages (Vth) have to be used. This could be inferred as lower the threshold voltage, lower the degree to which MOSFETs in logic gates are turned off and higher is the standby leakage current [10]. Scaling down of Vth, leads to an exponential increase in subthreshold leakage current. Subthreshold leakage current is the drain-to-source leakage current when the transistor is OFF. This happens when the applied gate to source voltage Vgs is less than threshold voltage Vth of transistor (weak inversion mode). The Sub-threshold current flows due to diffusion current of minority carriers in the channel of MOSFET. The following equation-1 relates subthreshold current ISUB with other device parameters [14].
Vgs Vth yVds Vsb

I SUB = I o e I 0 = Cox (

nV

(1 - e

Vds V

(1)

W ). V2 e1.8 (2) L where, Cox is the gate oxide capacitance per unit area, denotes carrier mobility, W and L denote the width and length of the transistor, V=kT/q is the thermal voltage, is body effect coefficient, denotes the drain-induced barrier lowering coefficient, n is the slope shape factor sub-threshold swing coefficient. Figure-1 shows the subthreshold leakage trends with deep-submicron technologies [5].
Figure 1: Subthreshold leakage power trends

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In this work, we present a circuit level design technique that reduces the overall leakage power in conventional CMOS cells. The focus of this paper is on static power dissipation in standby mode of operation using sleep transistors in pass gate structure. The rest of the paper is organized as follows, in Section 2, a review of the related work is presented. In Section 3, the proposed work on a leakage reduction for combinational CMOS logic gates is presented, which is followed by the simulation results and conclusions in Sections 4 and 5, respectively.

2. Existing Methods for Leakage Power Reduction

Numerous methods for leakage power control have been reported in literature. All these techniques and algorithms are effective in reducing leakage power and ultimately all come down to a fundamental set of concepts: dissipation is reduced by lowering supply voltage, voltage swing, physical capacitance, switching activity or by introduction of a high resistance path between VDD and ground. The input vector method by Abdollahi et.al. makes use of dependence of leakage current on the input vector to gate [1]. Additional control logic is used to put the circuit in a low-leakage standby state when it is idle and restored to its original state when reactivated. Upon reactivation, the circuit no longer retains the original state information before going into low-leakage standby state. Thus, to retain original state information, it requires special latches thereby increasing the area of circuit by about five times in worst cases. Another technique for leakage power control is power-gating approach [9] proposed by Agarwal et.al., which turns off the devices by cutting of their supply voltages. Moreover, bulky PMOS and/or NMOS devices (sleep transistors) are introduced in between either supply or ground and circuit. Introduction of sleep transistors creates virtual power and ground rails in the circuit. The sleep transistor is turned on while circuit is in active state and turned off when circuit is in idle mode. This is done with the help of sleep signals. As leakage power varies exponentially with the threshold voltage, it is necessary for sleep transistors to have a high threshold voltage. This leads to use of multiple threshold voltage CMOS (MTCMOS) [6] technology. Douseki et.al. [16] introduced the concept of Multi-Threshold CMOS (MTCMOS) which has emerged as a very popular technique for standby mode leakage power reduction. The transistors of logic gates are low threshold devices and ground is connected to gate through a high threshold voltage NMOS gating transistor. The logical functioning of a gating transistor is similar to that of a sleep transistor. The use of this technique gives rise to existence of reverse conduction paths that reduce noise margin or as a worst case scenario results in complete failure of gates. A variation of MTCMOS technique is the Dual Vth technique (DTMOS) [13,15], which uses transistors with two different threshold voltages. Low threshold transistors are used for gates in the critical paths and high threshold transistors are used for those not on critical path. Stacking of transistors [11] is another method for leakage power reduction. The forced stacking involves introducing an additional transistor for every input of gate in both PUN and PDN. This ensures that two transistors are off instead of one based on input of the gate. Hence, makes a significant savings on the leakage current. Also, forced stacking creates loading requirements for each input and this reduces the drive current of gate significantly. This results in detrimental impact on the speed of circuit. The LECTOR work [12] is an adaptation of the technique of effective stacking of transistors in order to reduce leakage power. Experimental results obtained using proposed technique described later in this paper is compared with the LECTOR results. Hence, a brief description of working of LECTOR technique is given in results section.

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3. Proposed Method
3.1. Preliminaries

The basic idea behind this approach is to reduce leakage power by introducing a high resistance in the path from supply to ground by means of a CMOS analog switch. This analog solid-state switch will block or pass a signal level selectively from input to the output. This switch is comprised of a PMOS transistor and NMOS transistor. The control gates are biased in a complementary manner so that both transistors are either on or off. The switches can be implemented either by a single NMOS transistor or PMOS transistor in sleep transistor or pass transistor logic as shown in figure-2. The NMOS transistors pass a strong 0 but a weak 1(threshold voltage drop. High =VDD -Vthn) and PMOS transistors pass a strong 1 but a weak 0(threshold voltage drop. Low = Vthp). Thus, NMOS switches are best for pulldown network and the PMOS switches are best for pull-up network [3].
Figure 2: Pass transistor logic

g s

g=0 d g=1 d g=0 s g=1 d s d d

Input g = 1 Output 0 strong 0 g=1 1 Input 0 1 g=0 g=0 degraded 1 Output degraded 0 strong 1

Figure 3: Sleepy-Pass gate logic

G G = 1, G= 0 OUT IN OUT

IN

G = 0, G = 1 IN OUT Strong 1/0

The figure-3 represents a pair of complementary MOS transistors connected in parallel known as the CMOS pass gate configuration, which pass both 0 and 1 well. When the voltage on node G is a Logic 1, the complementary Logic 0 is applied to node active-low G, allowing both transistors to conduct and pass the signal at IN to OUT. When the voltage on node active-low G is Logic 0, complementary Logic 1 is applied to node G, turning both transistors off and forcing a high-impedance condition on both IN and OUT nodes. This high-impedance condition represents third "state" (high, low, or high-Z). Thus, pass gate acts as an open circuit offering high resistance. This design acts as a voltage controlled resistor connecting input and output providing true bidirectional connectivity without degradation of the input signal.

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Figure 4: ON resistance of Pass gate

The figure-4 plots ON resistance of pass gate as input voltage is swept from GND to VDD, assuming the output voltage closely follows. The effective ON resistance is a parallel combination of two resistances and is relatively constant across full range of input voltages. However the OFF resistance is very high and it is in the range of several mega ohms.
3.2. Sleepy-Pass Gate Technique

In this section, we describe our new leakage reduction technique, which is termed as Sleepy-Pass gate approach. This section explains the structure of proposed approach as well as, how it operates. In comparison with single sleep transistor (PMOS or NMOS) connected between PUN (Pull up network) and PDN (Pull down network), which pass degraded output. Also, the pass gate is capable of passing logic 1 and 0 well. In addition to that, output logic state is not lost when the circuit enters from active mode to sleep mode and vice-versa. This seems attractive in comparison with some of the existing ways to use far lower VDD values and additional transistors to maintain logic state. For example, Martin et.al. propose that some reduced VDD values sufficient to maintain the logic state [8]. The sleep circuit consists of two complementary MOS transistors S1 (PMOS) and S2 (NMOS). The sleep transistors S1 and S2 are connected in parallel to form pass gate configuration between PUN and PDN as shown in figure-5.
Figure 5: Block diagram of proposed method

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The two control signals sleep and its complement sleep_bar feed the gates of S1 and S2 respectively. The sleep transistors S1 and S2 are high threshold voltage devices and the logic gate transistors are standard threshold voltage devices. This is to provide a well balanced trade-off between high speed and leakage loss. The CMOS circuit output can be drawn either between PUN and sleep circuit or between sleep circuit and PDN. The working of the Sleepy-Pass gate approach is now explained. During the normal (active) mode of operation, sleep=0 and sleep_bar=1. This makes the transistors S1 and S2 to turn ON and acts as a pass gate. The circuit behaves as a normal CMOS circuit without any hindrance from the sleep circuit. This can be seen from the DC characteristics obtained from HSPICE simulations. The figure-6 shows the DC characteristics of the NAND gate with the proposed method (the input A is fixed at 1 V and B is varied from 0 to 1 V).
Figure 6: DC characteristic of a 2-input NAND with proposed method

Figure 7: Input output waveforms of a 2-input NAND with proposed method

The ON resistance of the pass gate will be constant and lesser than its OFF resistance, allowing conduction between PUN and PDN. Even though the ON resistance of pass gate is not as high as its OFF state resistance, it increases the resistance of VDD to ground path, controlling the flow of leakage currents, resulting in leakage power reduction in active mode. In standby mode of operation, sleep=1 and sleep_bar=0 makes the transistors S1 and S2 to turn OFF forcing a high-impedance condition between PUN and PDN nodes. Thus, the introduction of sleepy- pass gate increases the resistance of the path from VDD to ground during standby mode of operation resulting in reduction of leakage

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current. Figure-7 shows the input-output curves of the NAND gate with proposed method simulated for 100-nm technology at 1-V supply voltage. It can be observed from the curves that the proposed NAND gate produces exact output logic levels.

4. Results & Discussion

In order to compare the results of the Sleepy-Pass gate method with the base case, an experiment was carried out with a set of combinational logic gates. The schematics are designed for all the mentioned techniques using Custom Designer in Synopsys for TSMC 0.18m technology. Netlists extracted from the schematics are modified with respect to the Berkeley Predictive Technology Models (BPTM) [4]. The modified netlists are simulated using Synopsys HSPICE for power and delay measurements. All circuits were simulated at a temperature of 25C. The Berkeley Predictive Technology Models (BPTM) contained process parameters and values for both standard threshold voltage and high threshold voltage devices. The worst case leakage power measurements are made for some of the CMOS combinational logic cells and tabulated in table I. The Column 3 of table-I shows proposed method has two orders of magnitude of leakage savings in comparison with the base case. Moreover, Figure 8 shows the delay measurements for the CMOS cells.
Table I: Experimental results for Combinational logic gates
Leakage power for 100nm Process Technology with VDD = 1 Volt Base case Proposed method 5.1700 E-08 2.8710E-10 5.4830 E-08 3.1959E-10 12.3677E-08 8.2780E-10 6.3950E-08 4.8477E-10 6.9464E-08 5.2567E-10 6.3748E-07 7.3758E-09 8.9000 E-07 3.5600 E-09

CMOS Gate 2 input NAND 2 input NOR 2 input XOR 2 input AND 2 input OR 2 input MUX 1-bit Full Adder

Figure 8: Propagation delay(s) results

The sleepy- pass gate technique was implemented and tested on MCNC91 benchmark circuits. They were sized appropriately to fit in to 180-nm, 130-nm, 100-nm and 70-nm BPTM models. Simulations were carried out using HSPICE in the standby mode of operation and their leakage power was measured. The proposed method provides exact logic levels and higher leakage savings as the process technology shrinks. Columns 1 of table-III lists MCNC91 benchmark names. Columns 2 to 5 of Table III give the leakage power values of the various benchmark circuits implemented for BPTM

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models. Table-II lists the supply and standard threshold voltage values of PMOS and NMOS devices used for various BPTM models.
Table II: Threshold voltages of MOS models used
NMOS Threshold Voltage(Vtn) 0.2 V 0.26 V 0.33 V 0.4 V PMOS Threshold Voltage(Vtp) -0.22 V -0.3 V -0.35 V -0.42 V VDD 0.85 V 1V 1.3 V 1.8 V

Process Tech. 70-nm 100-nm 130-nm 180-nm

Table III: Experimental results for MCNC 91 benchmark circuits with proposed method
MCNC91 Circuits I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 C432 C499 C880 C1355 C1908 C2670 C3540 C5315 C6288 C7552 Leakage power ( nW) 130-nm 100-nm 1.132 0.213 2.674 0.672 2.143 0.569 3.122 0.745 7.348 1.934 8.947 2.148 11.392 3.198 47.518 12.347 12.573 2.186 67.927 30.616 3.816 1.034 4.230 1.322 8.503 1.673 13.214 3.428 19.409 5.160 28.016 5.916 38.285 10.271 56.291 13.157 60.172 14.049 78.642 21.580

180-nm 2.892 6.186 5.943 7.989 18.623 21.927 30.957 122.294 33.183 149.846 8.385 11.285 22.127 35.634 52.460 73.519 102.835 147.277 157.268 213.497

70-nm 0.124 0.372 0.312 0.401 0.968 1.013 1.104 6.506 1.478 16.268 0.374 0.578 1.376 1.245 2.736 3.178 4.119 7.432 7.163 11.039

4.1. Comparison with LECTOR

To evaluate the proposed sleepy- pass gate technique in terms of leakage savings and delay, we compare with the existing LECTOR technique. A two-input NAND gate implemented using the BPTM 100 nm process technology with a supply voltage of 1 volt was used for the evaluation. Figure 9 shows the topology of a generic LECTOR CMOS circuit. Two Leakage Control Transistors (LTs), LT1 and LT2, are introduced between PUN and PDN. These LTs act as self-controlled stacked transistors. This wiring configuration ensures that one of the LTs is always near its cut-off region, irrespective of the input vector applied to the CMOS circuit. The introduction of LTs increases the resistance of the path from VDD to ground, thereby reducing the leakage. Table IV shows the delay and leakage power comparison for the LECTOR and proposed technique. All the transistors were appropriately sized. Analysis of table-IV shows that the proposed technique has the least leakage power dissipation. Column 7 of table-IV gives the delay penalty. The proposed technique gives less delay as shown in figure 10 when compared with the LECTOR and achieves 180X leakage reduction over the base case. The VLSI chip designers could add the sleepy pass gate cells in non-critical paths thereby not affecting the overall circuit delay, while significantly saving on leakage power loss.

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Figure 9: Generic LECTOR CMOS circuit

M. Geetha Priya, K. Baskaran and D. Krishnaveni

Figure 10: Propagation delay for 2-input NAND gate

Table IV: Leakage power and delay comparison for 2-input NAND gate
100nm Process Technology with VDD = 1 Volt Leakage power for input vectors Avg. leakage in W 01 10 11 4.1158E-08 4.6137E-09 3.7341E-10 4.2515E-08 4.1881E-09 3.5013E-09 1.1841E-07 3.3269E-09 3.8653E-10 5.170E-08 4.7065E-09 2.8710E-10

Method Base CMOS Lector Sleepy pass gate

00

Delay (s) 1.3E-10 1.8E-10 1.5E-10

Delay Penalty % 38.46 15.38

Avg. Leakage savings 10.98X 180X

4.7335E-09 6.6976E-09 3.8344E-10

5. Conclusion
Scaling down of the CMOS technology feature size and threshold voltage for achieving high performance has resulted in increase of leakage power dissipation. We have presented an efficient methodology for reducing leakage power in VLSI design. Throughout logic design, the proposed method could be used to reduce the static power of CMOS circuits. Minimal additional circuitry is used to modify the original logic design to force the combinational logic into a low-leakage state during both active and idle mode of operations. The drawback of the proposed technique is that it requires a controller to automatically generate sleep signals to put the circuit in standby mode and also to activate it when necessary.

References
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