DPDK Packet Processing Ia Overview Presentation

TRANSFORMING COMMUNICATIONS
COMMUNICATIONS INFRASTRUCTURE DIVISION
Intel Data Plane Development Kit (Intel DPDK) Overview Packet Processing on Intel Architecture
December 2012
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Intel Restricted Secret
TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS
Agenda 1. Intels Packet Processing Motivation and Value Proposition 2. Overview of Intel DPDK
3. Intel DPDK Performance Benchmarks 4. Lead Ecosystem Offerings

5. Intel DPDK Website and Collateral 6. Summary
CID Mission TRANSFORMING COMMUNICATIONS

ACCESS NETWORKS EDGE/CORE NETWORKS ENTERPRISE NETWORKS
+
Intel Architecture Ecosystem + Standards
WIRELESS BASE STATION WIRELESS INFRASTRUCTURE INTELLIGENT EDGE ROUTERS AND SWITCHES
MEDIA PROCESSING
NETWORK APPLIANCES
NETWORK SECURITY
>10 Years Serving Communications and Networking Segments

4
4:1 Workload Consolidation Assets

Unleashed by Multi-Core IA and Software
2011 Application Processing Control Processing 2012 2013
Intel Xeon Processor C3500/C5500

Intel QuickAssist Software Library
Intel Communications Chipset Series 89xx for Cryptography, Compression
Next Generation
Packet Processing
Signal Processing
NPU/ASIC
Intel Data Plane Development Kit
DSP
DSP
Intel Signal Processing Development Kit
One Instruction Set Architecture
One Tool Suite
Multiple Opportunities
TRANSFORMING COMMUNICATIONS
Intels Data Plane Value Proposition

Datacom/Telecom convergence increasing Data Plane processing requirements exponentially TCO concerns leading customers to seek single architecture design topto-bottom
Intel addresses TCO and TTM concerns with single architecture, multiworkload IA capability, allied to an industry-leading beat-rate of process and uArchitectural advancements (Tick-Tock Model)
Optimized Data Plane Software solutions will help unleash IA platform potential
The Engineering Problem Statement

10Gbps Line Rate
16,000,000 14,000,000
From a CPU perspective:

A Last-level-cache (L3) hit on Intel Xeon processor 5500 is ~40 cycles L3 miss, memory read is ~70ns (201 cycles at 3 GHz) This problem gets much worse at 40 Gb and 100 Gb rates
Packets per second
12,000,000 10,000,000 8,000,000 6,000,000 4,000,000 2,000,000
Intel Silicon and Software advances are proactively addressing this problem statement, making high performance Packet Processing on IA a reality!
PPS
0 136 640
100 172 208 244 280 316 352 388 424 460 496 532 568 604 676 712 748 784 820 856 892 928 964
1252
1000
1036
1072
1108
1144
1180
1216
1288
1324
1360
1396
1432
1468
Packet Size
Network Infrastructure Packet Sizes

Packet Size 10G Packets/second Packet arrival rate 64 bytes 14.88 Million each way 67.2 ns
Typical Server Packet Sizes

Packet Size 10G Packets/second 1024 bytes 1.2 Million each way
Packet arrival rate

2 GHz Clock cycles 3 Ghz Clock cycles
835 ns
1670 cycles 2505 cycles
2 GHz Clock cycles

3 Ghz Clock cycles
135 cycles
201 cycles
1504
64
Ongoing Silicon Architectural Enhancements

Packet Processing Enhancements: Pipeline Depth Direct Cache Access Integration of Memory Controller Integration of High Bandwidth PCIe Gen3 New AVX Extensions Intel Virtualization Technology (Intel VT) Intel Data Direct I/O Technology (Intel DDIO)
Intel Core 2 Microarchitecture
Hyper-Threading, Smart Cache, QuickPath, Integrated Memory Controller, SSE2/SSE3/SSE4 Instructions
Multi-Core Introduction Advanced Smart Cache Wide Dynamic Execution SSE2/SSE3, Power Management
Intel Xeon processor E52600 Microarchitecture
Intel Core i5 / i7 Microarchitecture

Enhanced Intel Core Microarchitecture 8C, 6C, 4C, 2C Product Choices 1S, 2S, 4S Configurations Intel Hyper-Threading Technology Integrated Memory Controller(s) Integrated High BW PCIe gen3 2 QPI Links for 2S Configurations Up to 20MB of L3 Cache
Intel Pentium 4 Processor Extreme Edition
Supporting Hyper-Threading Technology
Netburst microarchitecture Intel Extended Memory 64 Technology, Hyperthreading
Improved Packet Processing Capability
IA Performance over the Years

IPv4 Layer 3 Forwarding on an IA Platform
90
Introduction of Integrated PCIe* Controller
80
70
Introduction of Integrated Memory Controller + Intel DPDK
80 Mpps DPDK R1.1
60
50
40
30
20
10
Mpps
2006 2007 2008 DP Intel Xeon DP Intel Xeon DP Intel Xeon Processor LV Processor E5345 Processor E5410 2 x 2 Core 2 x 4 Core 2 x 4 Core 2.0 GHz, 667 MHz FSB 2.33 GHz, 1333 MHz FSB 2.33 GHz, 1333 MHz FSB
2009 2S Intel Xeon processor E5540 2 x 4 Core 2.53 GHz
2011 1S Intel Xeon Processor E5-2600 (B0 stepping) 1 x 8 Core 2.0 GHz PCIe* Gen2 Performance
Standard off-the-shelf IA platform can deliver huge performance. Performance jump can be attributed to Core, Memory architecture (iMC) + Intel DPDK
9
Evolution of Data Plane Support

Integrated Memory Controller SSE 4.2 128-bit SSE CRC32 Faster Cache Data Direct IO 1 GB pages Faster AES instructions
Software & Hardware performance enhancements over the next 2-3 years
Core
Increasing Cache Sizes Increasing Core Count
PCIe* Gen 2
Integrated PCI-E (Latency) PCIe* Gen 3
40G Networking silicon (Intel)
Platform
Increasing I/O bandwidth

Increasing memory bandwidth
Acceleration
AES-NI instruction
Intel Communications Chipset Series 89xx for Cryptography, Compression
Next Gen Chipset for Cryptography, Compression
2010/2011 Intel Xeon processors E5540/E5640
2012/2013 Intel Xeon processor E5-2600
2013/14 Next Tick/Tock Processors
1010
Management, Control & Data Plane Environments

Typically more Data Plane elements than Management/Control Plane
Ecosystem or Data Proprietary Plane
Packet Processing Packet Processing Processor Switch Switch Processor Packet Processing Packet Processing
Intel Provided
Intel DPDK
Control Plane Data Plane
Processor Blade Control Plane
Packet Processing Blade Data Plane
Rack Mount Server, Enterprise Servers

Typically have Control and Data Plane on same board
AdvancedTCA*
Typically Control and Data Plane on different boards
Value Proposition is Consolidation of DP + CP

Customers have come up with solutions to add additional 3rd party boards for Data Plane IA can fill both roles
Value Proposition single blade for multiple purposes

Normally many more Packet Processing Blades IA allows a single Blade Architecture for both now
Value proposition of Intel DPDK is workload consolidation: Provides framework and performance for NPU workloads on IA cores
1111

1212
Goals of this Overview Section

Look into the Intel DPDK architecture and see how its designed to squeeze the best packet processing performance out of an IA-based platform Be able to articulate the most common performance bottlenecks for packet processing software on IA Understand the optimization tricks to remove them
1313
The Intel DPDK Philosophy

Intel DPDK Fundamentals
Implements a run to completion model or pipeline model No scheduler - all devices accessed by polling Supports 32-bit and 64-bit with/without NUMA Scales from Intel Atom to Intel Xeon processors Number of Cores and Processors not limited Optimal packet allocation across DRAM channels
Control Plane
Data Plane
Must run on any IA CPU

From Intel Atom processor to the latest Intel Xeon processor family Essential to the IA value proposition
Provide software examples that address common network performance deficits

Best practices for software architecture Tips for data structure design and storage Help the compiler generate optimum code Address the challenges of achieving 80 Mpps per CPU Socket
Focus on the fast-path

Sending large number of packets to the Linux Kernel /GPOS will bog the system down
1414
Intel Data Plane Development Kit (Intel DPDK)

Intel DPDK embeds optimizations for the IA platform: - Data Plane Libraries and Optimized NIC Drivers in Linux
User Space
Queue & Buffer Management, Packet Flow Classification, Poll-Mode NIC Drivers (1/10GbE), and more! Simple API Interface, Uses standard tool chain (gcc/icc, gdb, profiling tools)
Intel DPDK Libraries

Buffer Management Queue/Ring Functions
Customer Application
Packet Flow Classification

NIC Poll Mode Library
- Run-time Environment
Low overhead, run-to-completion model optimized for fastest possible data plane performance
Environment Abstraction Layer
- Environment Abstraction Layer and Boot Code

Primarily platform-specific boot guidelines and initialization code, eases application porting effort
User Space Kernel Space

Environment Abstraction Layer
- BSD-licensed & source downloadable from Intel and leading ecopartners

Provided under a very flexible BSD licensing model
Offered as a free, unsupported standalone solution by Intel or as part of commercial solutions and offerings from leading ecopartners
Linux Kernel
Platform Hardware
The Intel DPDK is a great starting point for customers and the industry in general delivering breakthrough packet processing performance.
1515
Intel DPDK Libraries and Drivers

Memory Manager: Responsible for allocating pools of objects in memory. A pool is created in huge page memory space and uses a ring to store free objects. It also provides an alignment helper to ensure that objects are padded to spread them equally on all DRAM channels. Buffer Manager: Reduces by a significant amount the time the operating system spends allocating and de-allocating buffers. The Intel DPDK pre-allocates fixed size buffers which are stored in memory pools. Queue Manager:: Implements safe lockless queues, instead of using spinlocks, that allow different software components to process packets, while avoiding unnecessary wait times. Flow Classification: Provides an efficient mechanism which incorporates Intel Streaming SIMD Extensions (Intel SSE) to produce a hash based on tuple information so that packets may be placed into flows quickly for processing, thus greatly improving throughput. Poll Mode Drivers: The Intel DPDK includes Poll Mode Drivers for 1 GbE and 10 GbE Ethernet* controllers which are designed to work without asynchronous, interrupt-based signaling mechanisms, which greatly speeds up the packet pipeline.
1616
Component Overviews
EAL Memory Management Overview Queue/Ring Overview Buffer Management Overview Flow Classification Overview
1717
Memory Usage
Basic unit for runtime object allocation is the memory zone Zones contain rings, pools, LPM routing tables, or any other performance-critical structures Always backed by Huge Page (2 MB/1 GB page) memory
Ring:
Ring:
Memory Pool: mbuf_pool Memory Zone: MP_mbuf_pool
RX_RING_0
TX_RING_0
Memory Zone:
RG_RX_RING_0
Memory Zone:
RG_TX_RING_0
Memory Segment 0
Memory Segment 1
Memory Segment N
2MB page
2MB page
2MB page
2MB 2MB page page
2MB 2MB page page
2MB 2MB page page
2MB 2MB page page
2MB 2MB page page
Physically contiguous memory

1818
Physically contiguous memory
Queue/Ring Management API

Effectively a FIFO implementation in software
Lockless implementations for single or multi-producer, single or multi- consumer enqueue/dequeue Supports bulk enqueue/dequeue to support packet-bunching Implements high & low watermark thresholds for back-pressure/flow control
Essential to optimizing throughput

Used to decouple stages of a pipeline
1919
The Buffer Management API (mempool)

The Buffer Manager allocates memory from the EAL and creates pools with fixed element sizes.
Typical usage is packet buffers, descriptor ring buffers, etc. Intent is to speed up runtime allocation/deallocation Does not support runtime resizing of pools
Memory Pool
Pkt Buffers (60K 2K buffers) Events (2K 100B buffers) Events (2K 100B buffers)
Multi-producer/multi-consumer safe
Pools are based on Intel DPDK rings so are multiproducer and multi-consumer safe No locking; use CAS instructions Pools can also be used in multi-process environments
Rings for Cached buffers

Data Plane
Processor 0
Optimized for performance

Cache alignment Per core buffer caches for each buffer pool so that allocation/freeing can be done without using shared variables Bulk allocation/freeing support
Data Plane
Data Plane
Data Plane
Intel DPDK C1
Intel DPDK C2
Intel DPDK C3
Intel DPDK C4
10G
10G
2020
Flow Classification API
The Intel DPDK provides a Flow Classification API
Not expecting every customer to use it more of a showcase to demonstrate how to do optimization for IA Classification is something that is very customer-specific Each customer/segment has different needs
Router implementations typically use longest-prefix-match Security implementations need to identify individual flows and can use flow classification
The Flow classification API is designed to take advantage of current and future hardware-based flow classification capabilities
Intel 82599 10GbE Ethernet Controller implements flow classification (limited in number of flows) Future Chipsets are expected to implement an extensive classifier
2121
30,000 ft Overview of Packet Flow

1. Initialization
Initialization
Initialize memory zones and pools Initialize devices and device queues Start the packet forwarding application
Poll devices RX queues and receive packets in bursts Allocate new RX buffers from per queue memory pools to stuff into descriptors Transmit the received packets from RX Free the buffers used to store the packets
Polling
2. Packet Reception (RX)

RX
Packets to send
3. Packet Transmission (TX)

TX
2222
Overcoming The Challenge of Achieving 80 Mpps (and More) Per CPU Socket
Memory and PCIe* access is really, really slow compared to CPU operation
Process a bunch of packets (e.g. 4 packets at a time) to minimize external memory and PCIe bandwidth. Avoid read-modify-write transactions in favour of single write, and multiple reads in favour of single read.
Data doesnt seem to be near the CPU when it needs it (and so it waits)
For memory access, use HW or SW controlled prefetching and align data structures to cache line size (64 Byte) to minimize external memory and PCIe* bandwidth, as all external memory accesses are in cache line increments; for PCIe access, use Direct Data IO (available on Intel Xeon processor E5 Product Family) to read data directly into cache.
The system cant keep up with the amount of interrupts for packet Rx
Switch from an interrupt-driven network device driver to a polled-mode driver.
Access to shared data structures is a bottleneck in the application

Figure out clever access schemes that reduce the amount of sharing (e.g. use lockless queues for message passing as semaphores/spinlocks are costly).
The out-of-the-box Linux* Scheduler causes too much overhead to task switch
Bind a single software thread to a logical core. Use CPU core isolation and thread affinities for 1:1 mapping of SW threads to HW threads.
Intel PTU Tool indicates that page tables are constantly evicted (D-TLB Thrashing)
Use 2MB or 1G Huge Pages in Linux* to reduce TLB misses.
The Challenge can be Overcome with Smart Programming and Hardware assists!!
2323
PCIe* connectivity and core usage

Using run-to-completion or pipeline software models NUMA
Physical Core 0 Linux* Control Plane
Pkt Pkt
Pool Caches Queue/Rings Buffers
NUMA
Processor 0
QPI
PCIe
Pkt Pkt
Pool Caches Queue/Rings Buffers
Processor 1
10 GbE Physical Rx Core 0 Tx Intel DPDK Physical Core 1 Intel DPDK
PMD Packet I/O Flow Classification
10 GbE
PCIe
Physical Core 1 Intel DPDK
PMD Packet I/O Packet work
Rx Tx
PCIe
10 GbE
Pkt
App A
App B
App C
Pkt
Physical PMD Packet I/O Core 2 Flow work Intel DPDK

Physical PMD Packet I/O Core 3 Flow Classification Intel DPDK App A, B, C Physical PMD Packet I/O Core 4 Flow Classification Intel DPDK App A, B, C Physical PMD Packet I/O Core 5 Flow Classification Intel DPDK App A, B, C
Rx Tx
10 GbE
Physical Core 2 Intel DPDK Physical Core 3 Intel DPDK
PCIe PCIe
App A
App B
App C
Rx Tx
Pkt Pkt
Rx Tx
10 GbE
RSS Mode

Rx Tx
Run to Completion model I/O and Application workload can be handled on a single core I/O can be scaled over multiple cores
Pipeline model I/O application disperses packets to other cores Application work performed on other cores
2424
Tools for Optimizing Intel DPDK
Intel VTune Amplifier XE profiles performance
Intel Performance Tuning Utility (Intel PTU) offers specific tuning advice
Download both tools at whatif.intel.com

2525

2626
Performance Going Forward

IPv4 Layer 3 Forwarding on an IA Platform
250
200
150
Introduction of Integrated Memory Controller + Intel DPDK
Introduction of Integrated PCIe* Controller
Testing with PCIe* Gen3 expected to be higher
164.9 Mpps DPDK R1.2
100
50
93 Mpps DPDK R1.2
Mpps
2011 1S Intel Xeon E5-2658 processors C1 Stepping 1 x 8 Core 2.1 GHz PCIe Gen2 Performance
2012 2S Intel Xeon E5-2658 processors C1 Stepping 2 x 8 Core 2.1 GHz PCIe Gen2 Performance
2012 2S Intel Xeon E5-2658 processors C1 Stepping 2 x 8 Core 2.1 GHz PCIe Gen3 Performance (Estimate ONLY)
Software and workloads used in performance tests may have been optimized for performance only on Intel microprocessors. Performance tests, such as SYSmark and MobileMark, are measured using specific computer systems, components, software, operations and functions. Any change to any of those factors may cause the results to vary. You should consult other information and performance tests to assist you in fully evaluating your contemplated purchases, including the performance of that product when combined with other products.
PCIe* Gen 3 will offer better performance and more options

In the case of IPv4 Layer 3 forwarding, we are still I/O limited i.e. cores capability is not maxed out!!
2727
Intel DPDK Native and Virtualized Forwarding Performance
2828

2929
Intel DPDK Go To Market Options

Intel DPDK free, unsupported standalone package for integration with proprietary customer stacks
Data Plane Applications
Dispatch Loop Services Memory & Buffer API PMD
Intel DPDK
Core 1 - n
Ecosystem Provided: Intel DPDK Integrated into Commercial Solutions and Intel DPDK services offerings For more information about ecosystem solutions, visit www.intel.com/go/dpdk
Intel Provided: Intel DPDK Free, Unsupported Package
3030

3131
Intel DPDK
www.intel.com/go/dpdk
Your One-Stop-Shop for: Documentation and articles, white papers, pod casts Ecosystem information and articles
Examples
See the Video: Intel Data Plane Development Kit (Intel DPDK). Found on EDC site at www.intel.com/go/dpdk under Video: Intel Data Plane Development Kit (Intel DPDK)
3232

3333
Summary
Intel DPDK enables multi-workload/single architecture potential by making IA extremely competitive for packet processing workloads
Distribution of enabling software under flexible and cost-free licensing model enabling maximum customer usability
Fully featured and supported IA Data Plane software solutions via Intels lead Ecosystem partners
3434
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TRANSFORMING COMMUNICATIONS

COMMUNICATIONS INFRASTRUCTURE DIVISION

Intel Restricted Secret

TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS

3. Intel DPDK Performance Benchmarks 4. Lead Ecosystem Offerings

Intel Restricted Secret

TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS

CID Mission TRANSFORMING COMMUNICATIONS

>10 Years Serving Communications and Networking Segments

Intel Restricted Secret

TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS

4:1 Workload Consolidation Assets

Intel Xeon Processor C3500/C5500

Intel Communications Chipset Series 89xx for Cryptography, Compression

Intel Data Plane Development Kit

Intel Signal Processing Development Kit

One Instruction Set Architecture

One Tool Suite

Intels Data Plane Value Proposition

Intel Restricted Secret

TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS

The Engineering Problem Statement

From a CPU perspective:

Packets per second

12,000,000 10,000,000 8,000,000 6,000,000 4,000,000 2,000,000

Network Infrastructure Packet Sizes

Typical Server Packet Sizes

Packet arrival rate

2 GHz Clock cycles

Intel Restricted Secret

TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS

Ongoing Silicon Architectural Enhancements

Intel Xeon processor E52600 Microarchitecture

Intel Core i5 / i7 Microarchitecture

Intel Pentium 4 Processor Extreme Edition

Supporting Hyper-Threading Technology

Netburst microarchitecture Intel Extended Memory 64 Technology, Hyperthreading

Improved Packet Processing Capability

Intel Restricted Secret

TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS

IA Performance over the Years

Introduction of Integrated PCIe* Controller

Introduction of Integrated Memory Controller + Intel DPDK

80 Mpps DPDK R1.1

2009 2S Intel Xeon processor E5540 2 x 4 Core 2.53 GHz

2010 2S Intel Xeon processor E5645 2 x 6 Core 2.40 GHz

Intel Restricted Secret

TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS

Evolution of Data Plane Support

Increasing Cache Sizes Increasing Core Count

Integrated PCI-E (Latency) PCIe* Gen 3

40G Networking silicon (Intel)

Increasing I/O bandwidth

Intel Communications Chipset Series 89xx for Cryptography, Compression

Next Gen Chipset for Cryptography, Compression

2010/2011 Intel Xeon processors E5540/E5640

2012/2013 Intel Xeon processor E5-2600

2013/14 Next Tick/Tock Processors

Intel Restricted Secret

TRANSFORMING COMMUNICATIONS TRANSFORMING COMMUNICATIONS

Management, Control & Data Plane Environments

Control Plane Data Plane