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Digital System Design Lab

Last date for submission of hard copy of Lab Report : 05/NOV/13


Module I. Design the following in Structural model 1) Half Adder, Half Subtractor 2) Full Adder, Full Subtractor 3) 4 Bit Binary Adder 4) Synchronous Counter (Up, Down, UpDown ) Module II. Design the following in data flow model 1) Half adder 2) Full Adder 3) Comparator (4 bit) 4) Shift register 16 bit and 64 bit 5) Multiplexer with tristating 6) Decoder with tristating Module III. Design the following in behavioral model (process model) 1) 4 bit binary counter 2) Up/down decade counter 3) BCD Subtractor and adder 4) D Flip Flop 5) T Flip Flop 6) JK Flip Flop Module IV. Design the following in behavioral model (process model) 1) Memory -16 bit 2) LIFO Stack 3) FIFO stack

Module V. Design the following using Structural model 1) 2) 3) 4) 3- bit Counter (using generate statement) 4- bit Shift register Ring counter Johnson counter

Module VI. 1) Write a VHDL code for Read, Write Operations of RAM ( 4 bit Data) 2) Build a 64 x 8 byte Memory (structural mode with generate statements) using a 16 x 4 memory chip (in the behavioral mode, which has signals as write, read, and chip enable) as the structural component. Write the behavioral code in another library and bind it using a configuration. Module VII. 1. Design a 16 bit counter using a FF as a component, the design of which is placed in another library. Bind it using a configuration. 2.Write a number of functions and store in a package .Use these functions from a different design library (find applications to use the functions) The functions are a) Conversion from bit vector to integer and vice versa.

b) Counting the number of zeros (and number of ones) in a 16 bit word. c) Store a 64 bit number in hexadecimal format as a string in a variable. Read the variable and convert it to base-256. 3. Design the following as state machines a) b) c) Up/down counter counting from 0 to 5. A clock serial adder for four bits A sequence detector to detect the sequence 0101.

d) A sequence detector to detect the sequence 0101 or 0110 the output should be two consecutive ones.The first of these 1s should occur coincident with the last input of 0101 or 0110.

Input sequence: 1000101001011011001010 Output : 0000001100011110110011 e) e) 8 x8 shift and add multiplier Barrel shifter

Module VIII.

Hardware Implementation

(Use FPGA Spartan kit and show the result on the hardware.) Implement the questions below 1) Module VII-3.a 2) 2-bit x 2-bit multiplier. (Use switches for input and LEDs for output). Instructions: -> You can form batches(2 per batch). -> Report format: Aim, Theory of Operation, VHDL Code (Courier new font), Simulation Results, Schematic Diagram. -> Prepare report on your own words. -> Use Time and Resources wisely. -> Copying of reports will be penalised

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