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Logic Family Logic Families Significance and Types

There are a variety of circuit configurations or more appropriately various approaches used to produce different types of digital integrated circuit. Each such fundamental approach is called a logic family. Significance: A digital system in general comprises digital ICs performing different logic functions, and choosing these ICs from the same logic family guarantees that different ICs are compatible with respect to each other and that the system as a whole performs the intended logic function. In the case where the output of an IC belonging to a certain family feeds the inputs of another IC belonging to a different family. Types of Logic Family: The entire range of digital ICs is fabricated using either bipolar devices or MO devices or a combination of the two. Bipolar families include diode logic !"#$, resistor transistor logic !%T#$, diode transistor logic !"T#$, transistor transistor logic !TT#$, emitter coupled logic !EC#$ also &nown as current mode logic !CM#$, and integrated in'ection logic !I (#$. "iode logic !"#$, resistor transistor logic !%T#$ and diode transistor logic !"T#$ are of historical importance only. MOS families are the )MO family !using )*channel MO +ETs$, the ,MO family !using ,*channel MO +ETs$ and the CMO family !using both ,* and )*channel devices$.

Note: The -i*MO logic family uses both bipolar and MO devices. Note: "iode logic used diodes and resistors and in fact was never implemented in integrated circuits. The %T# family used resistors and bipolar transistors, while the "T# family used resistors, diodes and bipolar transistors. -oth %T# and "T# suffered from large propagation delay owing to the need for the transistor base charge to lea& out if the transistor were to switch from conducting to nonconducting state. #ogic families that are still in widespread use include TT#, CMO , EC#, ,MO and -i* CMO . The )MO and I(# logic families, which were mainly intended for use in custom large*scale integrated !# I$ circuit devices, have also been rendered more or less obsolete, with the ,MO logic family replacing them for # I and .# I applications.

Fig1 !a$ "iode logic !b$ resistor transistor logic and !c$ diode transistor logic. Note: The /0*series devices are MI#*1ualified !operational temperature range2 3// 4C to 56(/ 4C$ versions of the corresponding 70*series ICs !operational temperature range2 8 4C to 78 4C$. +or e9ample, 7088 and /088 are both 1uad two*input ,A," gates. Characteristic Parameters : !" #le$el inp%t c%rrent& !! . This is the current flowing into !ta&en as positive$ or out of !ta&en as negative$ an input when a ;I<;*level input voltage e1ual to the minimum ;I<;*level output voltage specified for the family is applied. In the case of bipolar logic families such as TT#, the circuit design is such that this current flows into the input pin and is therefore specified as positive. In the case of CMO logic families, it could be either positive or negative, and only an absolute value is specified in this case. : LO'#le$el inp%t c%rrent& !!L. The #O=*level input current is the ma9imum current flowing into !ta&en as positive$ or out of !ta&en as negative$ the input of a logic function when the voltage applied at the input e1uals the ma9imum #O=*level output voltage specified for the family. In the case of bipolar logic families such as TT#, the circuit design is such that this current flows out of the input pin and is therefore specified as negative. In the case of CMO logic families, it could be either positive or negative. In this case, only an absolute value is specified. Note: ;I<;*level and #O=*level input current or loading is also sometimes defined in terms of unit load !>#$. +or devices of the TT# family, 6 ># !;I<;$ ? 08A and 6 ># !#O=$ ?6.@ mA. : !" #le$el o%tp%t c%rrent& !O 2 This is the ma9imum current flowing out of an output when the input conditions are such that the output is in the logic ;I<; state. It is normally shown as a negative number. It tells about the c%rrent so%rcing capa(ility of the output. The magnitude of IO; determines the number of inputs the logic function can drive when its output is in the logic ;I<; state. +or e9ample, for the standard TT# family, the minimum guaranteed IO; is 3088A, which can drive 68 standard TT# inputs with each re1uiring 08A in the ;I<; state, as shown in +ig. /.(!a$. : LO'#le$el o%tp%t c%rrent& !OL. This is the ma9imum current flowing into the output pin of a logic function when the input conditions are such that the output is in the logic #O= state. It tells about the c%rrent sin)ing capa(ility of the output. The magnitude of I O# determines the number of inputs the logic function can drive when its output is in the logic #O= state. +or e9ample, for the standard TT# family, the minimum guaranteed IO# is 6@ mA, which can drive 68 standard TT# inputs with each re1uiring 6.@mA in the #O= state, as shown in +ig. /.(!b$.

: !" #le$el off#state *high#impedance state+ o%tp%t c%rrent& !O, . This is the current flowing into an output of a tristate logic function with the E,A-#E input chosen so as to establish a high*impedance state and a logic ;I<; voltage level applied at the output. The input conditions are chosen so as to produce logic #O= if the device is enabled.

: LO'#le$el off#state *high#impedance state+ o%tp%t c%rrent& !O,L. This is the current flowing into an output of a tristate logic function with the E,A-#E input chosen so as to establish a high*impedance state and a logic #O= voltage level applied at the output. The input conditions are chosen so as to produce logic ;I<; if the device is enabled. : !" #le$el inp%t $oltage& -! . This is the minimum voltage level that needs to be applied at the input to be recogniAed as a legal ;I<; level for the specified family. +or the standard TT# family, a ( . input voltage is a legal ;I<; logic state. : LO'#le$el inp%t $oltage& -!L. This is the ma9imum voltage level applied at the input that is recogniAed as a legal #O= level for the specified family. +or the standard TT# family, an input voltage of 8.B . is a legal #O= logic state. : !" #le$el o%tp%t $oltage& -O . This is the minimum voltage on the output pin of a logic function when the input conditions establish logic ;I<; at the output for the specified family. In the case of the standard TT# family of devices, the ;I<; level output voltage can be as low as (.0. and still be treated as a legal ;I<; logic state. It may be mentioned here that, for a given logic family, the . O; specification is always greater than the .I; specification to ensure output*to*input compatibility when the output of one device feeds the input of another. : LO'#le$el o%tp%t $oltage& -OL. This is the ma9imum voltage on the output pin of a logic function when the input conditions establish logic #O= at the output for the specified family. In the case of the standard TT# family of devices, the #O=*level output voltage can be as high as 8.0. and still be treated as a legal #O= logic state. It may be mentioned here that, for a given logic family, the . O# specification is always smaller than the .I# specification to ensure output*to*input compatibility when the output of one device feeds the input of another. The different inputCoutput current and voltage parameters are shown in +ig. /.D, with ;I<;*level current and voltage parameters in +ig. /.D!a$ and #O=*level current and voltage parameters in +ig. /.D!b$. It may be mentioned here that the direction of the #O=*level input and output currents shown in +ig. /.D!b$ is applicable to logic families with current*sin&ing action such as TT#.

: .ise time& tr/ This is the time that elapses between 68 and E8 F of the final signal level when the signal is ma&ing a transition from logic #O= to logic ;I<;. : Fall time& tf/ This is the time that elapses between E8 and 68 F of the signal level when it is ma&ing ;I<; to #O= transition. : Propagation delay tp/ The propagation delay is the time delay between the occurrence of change in the logical level at the input and before it is reflected at the output. It is the time delay between the specified voltage points on the input and output waveforms. )ropagation delays are separately defined for #O=*to* ;I<; and ;I<;*to*#O= transitions at the output. In addition, we also define enable and disable time delays that occur during transition between the high*impedance state and defined logic #O= or ;I<; states.

: Propagation delay t pL / This is the time delay between specified voltage points on the input and output waveforms with the output changing from #O= to ;I<;. : Propagation delay t p L/ This is the time delay between specified voltage points on the input and output waveforms with the output changing from ;I<; to #O=. : Noise margin/ This is a 1uantitative measure of noise immunity offered by the logic family. =hen the output of a logic device feeds the input of another device of the same family, a legal ;I<; logic state at the output of the feeding device should be treated as a legal ;I<; logic state by the input of the device being fed. imilarly, a legal #O= logic state of the feeding device should be treated as a legal #O= logic state by the device being fed. =e have seen in earlier paragraphs while defining important characteristic parameters that legal ;I<; and #O= voltage levels for a given logic family are different for outputs and inputs. +igure /./ shows the generaliAed case of legal ;I<; and #O= voltage levels for output G+ig. /./!a$H and input G+ig. /./!b$H. As we can see from the two diagrams, there is a disallowed range of output voltage levels from .O# !ma9.$ to .O; !min.$ and an indeterminate range of input voltage levels from .I# !ma9.$ to .I; !min.$. ince .I# !ma9.$ is greater than .O# !ma9.$, the #O= output state can therefore tolerate a positive voltage spi&e e1ual to .I# !ma9.$ 3 .O# !ma9.$ and still be a legal #O= input. imilarly, .O; !min.$ is greater than .I; !min.$, and the ;I<; output state can tolerate a negative voltage spi&e e1ual to .O; !min.$ 3 .I; !min.$ and still be a legal ;I<; input. ;ere, . I# !ma9.$ 3 .O# !ma9.$ and .O; !min.$ 3 .I; !min.$ are respectively &nown as the #O=*level and ;I<;*level noise margin. #et us illustrate it further with the help of data for the standard TT# family. The minimum legal ;I<; output voltage level in the case of the standard TT# is (.0 .. Also, the minimum legal ;I<; input voltage level for this family is ( .. This implies that, when the output of one device feeds the input of another, there is an available margin of 8.0 .. That is, any negative voltage spi&es of amplitude less than or e1ual to 8.0. on the signal line do not cause any spurious transitions. imilarly, when the output is in the logic #O= state, the ma9imum legal #O= output voltage level in the case of the standard TT# is 8.0 .. Also, the ma9imum legal #O= input voltage level for this family is 8.B .. This implies that, when the output of one device feeds the input of another, there is again an available margin of 8.0 .. That is, any positive voltage spi&es of amplitude less than or e1ual to 8.0. on the signal line do not cause any spurious transitions. This leads to the standard TT# family offering a noise margin of 8.0 .. To generaliAe, the noise margin offered by a logic family, as outlined earlier, can be computed from the ;I<;*state noise margin, .,; ? .O; !min.$ 3 .I; !min.$, and the #O=*state noise margin, .,# ? .I# !ma9.$ 3 .O# !ma9.$. If the two values are different, the noise margin is ta&en as the lower of the two.

Pro(lems 6. The data sheet of a 1uad two*input ,A," gate specifies the following parameters2 I O; !ma9.$?8.0 mA, .O; !min.$ ? (.7 ., .I; !min.$ ? (., .I# !ma9.$?8.B ., .O# !ma9.$?8.0 ., IO# !ma9.$?B mA, II# !ma9.$?8.0 mA, II; !ma9.$?(8A, ICC; !ma9.$?6.@ mA, ICC# !ma9.$?0.0 mA, tp#; ? tp;# ?6/ ns and a supply voltage range of / .. "etermine !a$ the average power dissipation of a single ,A," gate, !b$ the ma9imum average propagation delay of a single gate, !c$ the ;I<;*state noise margin and !d$ the #O=*state noise margin Sol%tion !a$ The average supply current ? !ICC; 5ICC#$C( ? !6.@ 5 0.0$C(?D mA. The supply voltage .CC ?/.. Therefore, the power dissipation for all four gates in the IC?/ I D?6/ m=. The average power dissipation per gate?6/C0?D.7/ m=. !b$ The propagation delay?6/ ns. !c$ The ;I<;*state noise margin?.O; !min.$ 3 .I; !min.$ ? (.7 3 (?8.7 .. !d$ The #O=*state noise margin?.I# !ma9.$ 3 .O# !ma9.$?8.B 3 8.0?8.0 .. (. %efer to e9ample /.6. ;ow many ,A," gate inputs can be driven from the output of a ,A," gate of this typeJ Sol%tion : This figure is given by the worst*case fan*out specification of the device. : ,ow, the ;I<;*state fan*out?IO;CII; ?088C(8 ? (8. : The #O=*state fan*out?IO#CII# ?BC8.0?(8. : Therefore, the number of inputs that can be driven from a single output?(8. D. "etermine the fan*out of IC 70# 80, given the following data2 input loading factor !;I<; state$ ?8./ >#, input loading factor !#O= state$ ? 8.(/ >#, output loading factor !;I<; state$ ?68 >#, output loading factor !#O= state$ ? / >#, where ># is the unit load. Sol%tion : The ;I<;*state fan*out can be computed from2 fan*out?output loading factor !;I<;$Cinput loading factor !;I<;$ ? 68 >#C8./ >#?(8. : The #O=*state fan*out can be computed from2 fan*out ? output loading factor !#O=$Cinput loading factor !#O=$ ? / >#C8.(/ >#?(8. : ince the fan*out in the two cases turns out to be the same, it follows that the fan*out?(8. 0/ A certain TT# gate has II; ?(8A, II# ?8.6 mA, IO; ?8.0 mA and IO# ?0 mA. "etermine the input and output loading in the ;I<; and #O= states in terms of >#. Sol%tion Note: 6 ># !#O= state$ ? 6.@ mA and 6 ># !;I<; state$ ? 08A. : The input loading factor !;I<; state$ ? (8 A ? (8C08?8./ >#. : The input loading factor !#O= state$ ? 8.6mA?8.6C6.@ ?6C6@ ># : The output loading factor !;I<; state$ ? 8.0mA ? 8.0C8.80?68 >#. : The output loading factor !#O= state$ ? 0mA?0C6.@ ? (./ >#.

Transistor Transistor Logic *TTL+: It is a logic family implemented with bipolar process technology that combines or integrates ,), transistors, ), 'unction diodes and diffused resistors in a single monolithic structure to get the desired logic function. The ,A," gate is the basic building bloc& of this logic family.

Standard TTL +igure /.@ shows the internal schematic of a standard TT# ,A," gate. It is one of the four circuits of /088C7088, which is a 1uad two*input ,A," gate. The circuit operates as follows. Transistor K 6 is a two* emitter ,), transistor, which is e1uivalent to two ,), transistors with their base and emitter terminals tied together. The two emitters are the two inputs of the ,A," gate. "iodes " ( and "D are used to limit negative input voltages. =e will now e9amine the behavior of the circuit for various possible logic states at the two inputs. Circ%it Operation =hen both the inputs are in the logic ;I<; state as specified by the TT# family !. I; ?( . minimum$, the current flows through the base*collector ), 'unction diode of transistor K 6 into the base of transistor K(. Transistor K( is turned O, to saturation, with the result that transistor K D is switched O++ and transistor K0 is switched O,. This produces a logic #O= at the output, with . O# being 8.0 . ma9imum when it is sin&ing a current of 6@ mA from e9ternal loads represented by inputs of logic functions being driven by the output. The current*sin&ing action is shown in +ig. /.7!a$. Transistor 10 is also referred to as the c%rrent#sin)ing or p%ll#do2n transistor, for obvious reasons. "iode "6 is used to prevent transistor KD from conducting even a small amount of current when the output is #O=. =hen the output is #O=, K 0 is in saturation and KD will conduct slightly in the absence of " 6. Also, the input current II; in the ;I<; state is nothing but the reverse*biased 'unction diode lea&age current and is typically 08 LA. =hen either of the two inputs or both inputs are in the logic #O= state, the base*emitter region of K 6 conducts current, driving K( to cut*off in the process. =hen K ( is in the cut*off state, KD is driven to conduction and K0 to cut*off. This produces a logic ;I<; output with . O; !min.$ ? (.0 . guaranteed for minimum supply voltage .CC and a source current of 088 A. The current*sourcing action is shown in

+ig. /.7!b$. Transistor 13 is also referred to as the c%rrent#so%rcing or p%ll#%p transistor . Also, the #O=*level input current II#, given by !.CC3.-E6$C %6 is 6.@ mA !ma9.$ for ma9imum .CC.

Totem#Pole O%tp%t Stage Transistors KD and K0 constitute what is &nown as a totem*pole output arrangement. In such an arrangement, either KD or K0 conducts at a time depending upon the logic status of the inputs. The totem* pole arrangement at the output has certain distinct advantages. The ma'or ad$antage of %sing a totem# pole connection is that it offers lo2#o%tp%t impedance in (oth the !" and LO' o%tp%t states . In the ;I<; state, KD acts as an emitter follower and has an output impedance of about 78 . In the #O= state, K0 is saturated and the output impedance is appro9imately 68 . -ecause of the low output impedance, any stray capacitance at the output can be charged or discharged very rapidly through this low impedance, thus allowing 1uic& transitions at the output from one state to the other. Another advantage is that, when the output is in the logic #O= state, transistor K 0 would need to conduct a fairly large current if its collector were tied to .CC through % D only. A nonconducting KD overcomes this problem. A disadvantage of the totem*pole output configuration results from the switch*off action of K 0 being slower than the switch*on action of KD. On account of this, there will be a small fraction of time, of the order of a few nanoseconds, when both the transistors are conducting, thus drawing heavy current from the supply. Characteristic Feat%res The characteristic parameters and features of the standard TT# family of devices include the following2 .I# ?8.B .M .I; ?(.M II; ?08 LAM II# ?6.@ mAM .O; ?(.0 .M .O# ?8.0 .M IO; ?088 LAM IO# ?6@ mAM .CC ?0.7/N/.(/. !70*series$ and 0./N/./. !/0*series$M propagation delay !for a load resistance of 088O, a

load capacitance of 6/ p+ and an ambient temperature of (/ 4C$?(( ns !ma9.$ for #O=*to*;I<; transition at the output and 6/ ns !ma9.$ for ;I<;*to*#O= output transitionM worst*case noise margin?8.0 .M fan*out?68M ICC; !for all four gates$?B mAM ICC# !for all four gates$?(( mAM operating temperature range?8N78 4C !70* series$ and 3// to 56(/ 4C !/0*series$M speedNpower product?688 pPM ma9imum flip*flop toggle fre1uency?D/ M;A. Open Collector "ate An open collector gate in TT# is one that is without a totem*pole output stage. The output stage in this case does not have the active pull*up transistor. An e9ternal pull*up resistor needs to be connected from the open collector terminal of the pull*down transistor to the .CC terminal. The pull*up resistor is typically 68 &. +igure /.60 shows the internal schematic of a ,A," gate with an open collector output. The schematic shown is that of one of the four gates of a 1uad two*input ,A," !type 70C/086$. The advantage of open collector outputs is that the outputs of different gates can be wired together, resulting in A,"ing of their outputs !similar to =I%E A," operation$. It may be mentioned here that the outputs of totem*pole TT# devices cannot be tied together. Although a common tied output may end up producing an A,"ing of individual outputs, such a connection is impractical. This is illustrated in +ig. /.6/, where outputs of two totem*poles output TT# gates have been tied together. #et us assume that the output of one of the gates, say gate*(, is #O=, and the output of the other is ;I<;. The result is that a relatively heavier current flows through KD6 and K0(. This current, which is of the order of /8N@8 mA, e9ceeds the IO# !ma9.$ rating of K0(. This may eventually lead to both transistors getting damaged. Even if they survive, .O# !ma9.$ of K0( is no longer guaranteed. In view of this, although totem*pole output TT# gates are not tied together, an accidental shorting of outputs is not ruled out. In such a case, both devices are li&ely to get damaged. In the case of open collector devices, deliberate or nondeliberate, shorting of outputs produces A,"ing of outputs with no ris& of either damage or compromised performance specifications.

3/ Tristate "ate A tristate gate has three output states, namely the logic #O= state, the logic ;I<; state and the high* impedance state. An e9ternal enable input decides whether the logic gate wor&s according to its truth table or is in the high*impedance state. +igure /.6@ shows the typical internal schematic of a tristate inverter with an active ;I<; enable input. The circuit functions as follows. =hen the enable input is ;I<;, it reverse*biases diode "6 and also applies a logic ;I<; on one of the emitters of the input transistor K 6. The circuit behaves li&e an inverter. =hen the enable input is #O=, diode " 6 becomes forward biased. A #O= enable input forces K ( and K0 to cut*off. Also, a forward*biased "6 forces KD to cut*off. =ith both output transistors in cut*off, the output essentially is an open circuit and thus presents high output impedance.

0/ Schott)y TTL *40S560S+


The chott&y TT# offers a speed that is about twice that offered by the high*power TT# for the same power consumption. +igure /.6E shows the internal schematic of a chott&y TT# ,A," gate. The circuit shown is that of one of the four gates inside a 1uad two*input ,A," !type 70 88 or /0 88$. The circuit, as we can see, is nearly the same as that of the high*power TT# ,A," gate. The transistors used in the circuit are all chott&y transistors with the e9ception of K /. A chott&y K/ would serve no purpose, with K0 being a chott&y transistor. A chott&y transistor is nothing but a conventional bipolar transistor with a chott&y diode connected between its base and collector terminals. The chott&y diode with its metalNsemiconductor 'unction not only is faster but also offers a lower forward voltage drop of 8.0. as against 8.7. for a )N, 'unction diode for the same value of forward current. The presence of a chott&y diode does not allow the transistor to go to deep saturation. The

moment the collector voltage of the transistor tends to go below about 8.D ., the chott&y diode becomes forward biased and bypasses part of the base current through it. The collector voltage is thus not allowed to go to the saturation value of 8.6. and gets clamped around 8.D .. =hile the power consumption of a chott&y TT# gate is almost the same as that of a high*power TT# gate owing to nearly the same values of the resistors used in the circuit, the chott&y TT# offers a higher speed on account of the use of chott&y transistors.

Salient feat%res of 7LS#TTL and 7S#TTL incl%de the follo2ing: A# *TT#QAdvanced #ow power chott&y TT# A *TT#QAdvanced chott&y TT# 6. All saturating transistors are clamped by using chott&y diodes. This virtually eliminates the storage of e9cessive base charge, thus significantly reducing the turn*off time of the transistors. Elimination of transistor storage time also provides stable switching times over the entire operational temperature range. (. Inputs and outputs are clamped by chott&y diodes to limit the negative*going e9cursions. D. -oth A# *TT# and A *TT# use ion implantation rather than a diffusion process, which allows the use of small geometries leading to smaller parasitic capacitances and hence reduced switching times. 0. -oth A# *TT# and A *TT# use o9ide isolation rather than 'unction isolation between transistors. This leads to reduced epita9ial layerNsubstrate capacitance, which further reduces the switching times. /. -oth A# *TT# and A *TT# offer improved input threshold voltage and reduced low*level input current. @. -oth A# *TT# and A *TT# feature active turn*off of the #O=*level output transistor, producing a better ;I<;*level output voltage and thus higher ;I<;*level noise immunity.

Floating and 8n%sed !np%ts The floating input of TT# family devices behaves as if logic ;I<; has been applied to the input. uch behavior is e9plained from the input circuit of a TT# device. =hen the input is ;I<;, the input emitter* base 'unction is reverse biased and the current that flows into the input is the reverse*biased diode lea&age current. The input diode will be reverse biased even when the input terminal is left unconnected or floating, which implies that a floating input behaves as if there were logic ;I<; applied to it. As an initial thought, we may tend to believe that it should not ma&e any difference if we leave the unused inputs of ,A," and A," gates as floating, as logic ;I<; li&e behavior of the floating input ma&es no difference to the logical behavior of the gate, as shown in +igs /.(0!a$ and !b$. In spite of this, it is strongly recommended that the unused inputs of A," and ,A," gates be connected to a logic ;I<; input G+ig. /.(0!c$H because floating input behaves as an antenna and may pic& up stray noise and interference signals, thus causing the gate to function improperly. 6 & resistance is connected to protect the input from any current spi&es caused by any spi&es on the power supply line. More than one unused input !up to /8$ can share the same 6 & resistance, if needed. In the case of O% and ,O% gates, unused inputs are connected to ground !logic #O=$, as shown in +ig. /.(/!c$, for obvious reasons. A floating input or an input tied to logic ;I<; in this case produces a permanent logic ;I<; !for an O% gate$ and #O= !for a ,O% gate$ at the output as shown in +igs /.(/!a$ and !b$ respectively. An alternative solution is shown in +ig. /.(/!d$, where the unused input has been tied to one of the used inputs. This solution wor&s well for all gates, but one has to be conscious of the fact that the fan*out capability of the output driving the tied inputs is not e9ceeded. If we recall the internal circuit schematics of A," and ,A," gates, we will appreciate that, when more than one input is tied together, the input loading, that is, the current drawn by the tied inputs from the driving gate output, in the ;I<; state is n times the loading of one input !+ig. /.(@$M n is the number of inputs tied together. =hen the output is #O=, the input loading is the same as that of a single input. The reason for this is that, in the #O= input state, the current flowing out of the gate is determined by the resistance %6, as shown in +ig. /.(7. ;owever, the same is not true in the case of O% and ,O% gates, which do not use a multi*emitter input transistor and use separate input transistors instead, as shown in +ig. /.(B. In this case, the input loading is n times the loading of a single input for both ;I<; and #O= states.

Pro(lems
6. %efer to +ig. /.D8. "etermine the current being sourced by gate 6 when its output is ;I<; and sun& by it when its output is #O=. All gates are from the standard TT# family, given that I I; ? 08 A and II# ? 6.@ mA.

Solution : =hen the output is ;I<;, the inputs of all gates draw current individually. : Therefore, the input loading factor?e1uivalent of seven gate inputs?7 I 08 A?(B8 A. : The current being sourced by the gate 6 output?(B8 A. : =hen the output is #O=, shorted inputs of A," and ,A," gates offer a load e1ual to that of a single input owing to a multi*emitter transistor at the input of the gate. The inputs of O% and ,O% gates draw current individually on account of the use of separate transistors at the input of the gate. : Therefore, the input loading factor?e1uivalent of five gate inputs?/ I 6.@?B mA. : The current being sun& by the gate 6 output?B mA. (. %efer to the logic diagram of +ig. /.D6. <ate 6 and gate 0 belong to the standard TT# family, while gate ( and gate D belong to the chott&y TT# family and the low*power chott&y TT# family respectively. "etermine whether the fan*out capability of gate 6 is being e9ceeded. %elevant data for the three logic families are given in Table /.6.

Solution : In the ;I<;*state2 N The gate 6 output sourcing capability?088 AM N The gate ( input re1uirement?/8 I 0?(88 AM N The gate D input re1uirement?(8 I (?08 AM N The gate 0 input re1uirement?08 I 0?6@8 AM N The total input current re1uirement?088 AM N Therefore, the fan*out is not e9ceeded in the ;I<; state.

: In the #O=*state, N The gate 6 output sin&ing capability?6@ mAM N The gate ( input sin&ing re1uirement?( mAM N The gate D input sin&ing re1uirement?8.0 I (?8.B mAM N The gate 0 input sin&ing re1uirement?6.@ mAM N The total input current re1uirement?0.0 mAM ince the output of gate 6 has a current sin&ing capability of 6@ mA, the fan*out capability is not e9ceeded in the #O= state either. 9mitter Co%pled Logic *9CL+ or C%rrent Mode Logic*CML+: The EC# family is the fastest logic family in the group of bipolar logic families. The characteristic features that give this logic family its high speed or short propagation delay are outlined as follows2 6. It is a nonsaturating logic. That is, the transistors in this logic are always operated in the active region of their output characteristics. They are never driven to either cut*off or saturation, which means that logic #O= and ;I<; states correspond to different states of conduction of various bipolar transistors. (. The logic swing, that is, the difference in the voltage levels corresponding to logic #O= and ;I<; states, is &ept small !typically 8.B/ .$, with the result that the output capacitance needs to be charged and discharged by a relatively much smaller voltage differential. D. The circuit currents are relatively high and the output impedance is low, with the result that the output capacitance can be charged and discharged 1uic&ly. ,ote2 O%C,O% is the fundamental logic gate of the EC# family.

Salient Feat%res of 9CL There are many features possessed by MEC# family devices other than their high speed characteristics that ma&e them attractive for many high*performance applications. The ma'or ones are as follows2 6. EC# family devices produce the true and complementary output of the intended function simultaneously at the outputs without the use of any e9ternal inverters. This in turn reduces pac&age count, reduces power re1uirements and also minimiAes problems arising out of time delays that would be caused by e9ternal inverters. (. The EC# gate structure inherently has high input impedance and low output impedance, which is very conducive to achieving large fan*out and drive capability. D. EC# devices with open emitter outputs allow them to have transmission line drive capability. The outputs match any line impedance. Also, the absence of any pull*down resistors saves power. 0. EC# devices produce a near*constant current drain on the power supply, which simplifies power supply design. /. On account of the differential amplifier design, EC# devices offer a wide performance fle9ibility, which allows EC# circuits to be used both as linear and as digital circuits. @. Termination of unused inputs is easy. %esistors of appro9imately /8 & allow unused inputs to remain unconnected.

CMOS Logic Family The CMO !Complementary Metal O9ide emiconductor$ logic family uses both ,*type and )*type MO +ETs !enhancement MO +ETs, to be more precise$ to realiAe different logic functions. The two types of MO +ET are designed to have matching characteristics. That is, they e9hibit identical characteristics in switch*O++ and switch*O, conditions. The main advantage of the CMO logic family over bipolar logic families discussed so far lies in its e9tremely low power dissipation, which is near*Aero in static conditions. In fact, CMO devices draw power only when they are switching. This allows integration of a much larger number of CMO gates on a chip than would have been possible with bipolar or ,MO !to be discussed later$ technology. CMO technology today is the dominant semiconductor technology used for ma&ing microprocessors, memory devices and application*specific integrated circuits !A ICs$. Circ%it !mplementation of Logic F%nctions In the following paragraphs, we will briefly describe the internal schematics of basic logic functions when implemented in CMO logic. These include inverter, ,A,", ,O%, A,", O%, ER*O%, ER*,O% and A,"*O%*I,.E%T functions. 1/ CMOS !n$erter The inverter is the most fundamental building bloc& of CMO logic. It consists of a pair of ,*channel and )*channel MO +ETs connected in cascade configuration as shown in +ig. /.D0. The circuit functions as follows. =hen the input is in the ;I<; state !logic S6T$, )*channel MO +ET K 6 is in the cut*off state while the ,*channel MO +ET K( is conducting. The conducting MO +ET provides a path from ground to output and the output is #O= !logic S8T$. =hen the input is in the #O= state !logic S8T$, K 6 is in conduction while K( is in cut*off. The conducting )*channel device provides a path for ."" to appear at the output, so that the output is in ;I<; or logic S6T state. A floating input could lead to conduction of both MO +ETs and a short*circuit condition. It should therefore be avoided. It is also evident from +ig. /.D0 that there is no conduction path between ."" and ground in either of the input conditions, that is, when input is in logic S6T and S8T states. That is why there is practically Aero power dissipation in static conditions. There is only dynamic power dissipation, which occurs during switching operations as the MO +ET gate capacitance is charged and discharged. The power dissipated is directly proportional to the switching fre1uency.

:/ N7N; "ate +igure /.D/ shows the basic circuit implementation of a two*input ,A,". As shown in the figure, two )* channel MO +ETs !K6 and K($ are connected in parallel between ."" and the output terminal, and two ,*channel MO +ETs !KD and K0$ are connected in series between ground and output terminal. The circuit operates as follows. +or the output to be in a logic S8T state, it is essential that both the series*connected ,* channel devices conduct and both the parallel*connected )*channel devices remain in the cut*off state. This is possible only when both the inputs are in a logic S6T state. This verifies one of the entries of the ,A," gate truth table. =hen both the inputs are in a logic S8T state, both the ,*channel devices are nonconducting and both the )*channel devices are conducting, which produces logic S6T at the output. This verifies another entry of the ,A," truth table. +or the remaining two input combinations, either of the two ,*channel devices will be nonconducting and either of the two parallel*connected )*channel devices will be conducting. =e have either KD O++ and K( O, or K0 O++ and K6 O,. The output in both cases is a logic S6T, which verifies the remaining entries of the truth table. +rom the circuit schematic of +ig. /.D/ we can visualiAe that under no possible input combination of logic states is there a direct conduction path between . "" and ground. This further confirms that there is near* Aero power dissipation in CMO gates under static conditions.

3/ NO. "ate

0. A," gate2

/. O% gate

@. EXCLUSIVE-NOR Gate
An EXCLUSIVE-NOR gate is implemented using the logic diagram o !ig. ".#$%a&. As is e'ident rom the igure( the output o this logic arrangement can )e e*pressed )+

7. ER*O% gate
An EXCLUSIVE-OR gate is implemented using the logic diagram o !ig. ".#,%a&. As is e'ident rom the igure( the output o this logic arrangement can )e e*pressed )+

B. Two wide two input A,"*O%*I,.E%T gate

+igure /.0D shows the internal schematic of a typical two*wide, two*input A,"*O%*I,.E%T gate. The output of this gate can be logically e9pressed by the -oolean e1uation

+rom the above e9pression, we can say that the output should be in a logic S8T state for the following input conditions2 6. =hen either A.-?logic S6T or C."?logic S6T (. when both A.- and C." e1ual logic S6T. +or both these conditions there is a conduction path available from ground to output, which verifies that the circuit satisfies the logic e9pression. Also, according to the logic e9pression for the A,"*O%I,.E%T gate, the output should be in a logic S6T state when both A.- and C." e1ual logic S8T. This implies that2 6. Either A or - or both are in a logic S8T state. (. Either C or " or both are in a logic S8T state. If these conditions are applied to the circuit of +ig. /.0D, we find that the ground will remain disconnected from the output and also that there is always a path from ."" to output. This leads to logic S6T at the output. Thus, we have proved that the given circuit implements the intended logic e9pression for the A,"*O%*I,.E%T gate. </ O.#7N;#!N-9.T gate: The O%*A,"*I,.E%T gate can also be implemented in the same way. +igure /.00 shows a typical internal schematic of a two*wide, two*input O%*A,"*I,.E%T gate. The output of this gate can be e9pressed by the -oolean e1uation

Note: The transmission gate is also &nown as bilateral switch and essentially is a ingle )ole ingle Throw ! ) T$ witch. CMOS 2ith Open ;rain O%tp%ts The outputs of conventional CMO gates should never be shorted together, as illustrated by the case of two inverters shorted at the output terminals !+ig. /.0@$. If the input conditions are such that the output of one inverter is ;I<; and that of the other is #O=, the output circuit is then li&e a voltage divider networ& with two identical resistors e1ual to the O,*resistance of a conducting MO +ET. The output is then appro9imately e1ual to .""C(, which lies in the indeterminate range and is therefore unacceptable. Also, an arrangement li&e this draws e9cessive current and could lead to device damage. This problem does not e9ist in CMO gates with open drain outputs. uch a device is the counterpart to gates with open collector outputs in the TT# family. The output stage of a CMO gate with an open drain output is a single ,* channel MO +ET with an open drain terminal, and there is no )*channel MO +ET. The open drain terminal needs to be connected to ."" through an e9ternal pull*up resistor. +igure /.07 shows the internal schematic of a CMO inverter with an open drain output. The pull*up resistor shown in the circuit is e9ternal to the device.

CMOS 2ith Tristate O%tp%ts #i&e tristate TT#, CMO devices are also available with tristate outputs. The operation of tristate CMO devices is similar to that of tristate TT#. That is, when the device is enabled it performs its intended logic function, and when it is disabled its output goes to a high*impedance state. In the high impedance state, both ,*channel and )*channel MO +ETs are driven to an O++*state. +igure /.0B shows the internal schematic of a tristate buffer with active #O= E,A-#E input. The circuit shown is that of one of the buffers in CMO he9 buffer type C"0/8D-. The outputs of tristate CMO devices can be connected together in a bus arrangement, li&e tristate TT# devices with the same condition that only one device is enabled at a time.

Floating or 8n%sed !np%ts >nused inputs of CMO devices should never be left floating or unconnected. A floating input is highly susceptible to pic&ing up noise and accumulating static charge. This can often lead to simultaneous conduction of )*channel and ,*channel devices on the chip, which causes increased power dissipation and overheating. >nused inputs of CMO gates should either be connected to ground or ."" or shorted to another input. The same is applicable to the inputs of all those gates that are not in use. +or e9ample, we may be using only two of the four gates available on an IC having four gates. The inputs of the remaining two gates should be tied to either ground or ."". Latch#%p Condition This is an undesired condition that can occur in CMO devices owing to the e9istence of parasitic bipolar transistors !,), and ),)$ embedded in the substrate. =hile ,*channel MO +ETs lead to the presence of ,), transistors, )*channel MO +ETs are responsible for the e9istence of ),) transistors. If we loo& into the arrangement of different semiconductor regions in the most basic CMO building bloc&, that is, the inverter, we will find that these parasitic ,), and ),) transistors find themselves interconnected in a bac&*to*bac& arrangement, with the collector of one transistor connected to the base of the other, and vice versa. Two such pairs of transistors connected in series e9ist between ."" and ground in the case of an inverter, as shown in +ig. /./8. If for some reason these parasitic elements are triggered into conduction, on account of inherent positive feedbac& they get into a latch*up condition and remain in conduction permanently. This can lead to the flow of large current and subse1uently to destruction of the device. A latch*up condition can be triggered by high voltage spi&es and ringing present at the device inputs and outputs. The device can also be prone to latch*up if its ma9imum ratings are e9ceeded. Modern CMO devices use improved fabrication techni1ues so as to minimiAe factors that can cause this undesired effect. The use of e9ternal clamping diodes at inputs and outputs, proper termination of unused inputs and regulated power supply with a current*limiting feature also helps in minimiAing the chances of occurrence of the latch*up condition and in minimiAing its effects if it occurs.

E9amples
6. "raw the internal schematic of2 !a$ a two*wide, four*input A,"*O%*I,.E%T logic function in CMO and !b$ a two*wide, four*input O%*A,"*I,.E%T logic function in CMO . Sol%tion !a$ #et us assume that A, -, C, ", E, +, < and ; are the logic variables. The output U of this logic function can then be e9pressed by the e1uation +ollowing the principles e9plained earlier in the te9t, the internal schematic is shown in +ig. /./D!a$. eries connection of ,*channel MO +ETs on the left simulates A,"ing of A, -, C and ", whereas series connection of ,*channel MO +ETs on the right simulates A,"ing of E, +, < and ;. )arallel connection of two branches produces O%ing of the A,"ed outputs. ince the )*channel MO +ET arrangement is the complement of the ,*channel MO +ET arrangement, the final output is what is given by E1uation !/./$. !b$ The output U of this logic function can be e9pressed by the e1uation

(. "etermine the logic function performed by the CMO digital circuit of +ig. /./0. Sol%tion The given circuit can be divided into two stages. The first stage comprises two inverters that produce and . The second stage is a two*wide, two*input A,"*O%*I,.E%T circuit. Inputs to the first A," are and -, and inputs to the second A," are A and . The final output is therefore given by U ? which is an ER*,O% function.

BiCMOS Logic The -iCMO logic family integrates bipolar and CMO devices on a single chip with the ob'ective of deriving the advantages individually present in bipolar and CMO logic families. =hile bipolar logic families such as TT# and EC# have the advantages of faster switching speed and larger output drive current capability, CMO logic scores over bipolar counterparts when it comes to lower power dissipation, higher noise margin and larger pac&ing density. -iCMO logic attempts to get the best of both worlds. Two ma'or categories of -iCMO logic devices have emerged over the years since its introduction in 6EB/. In one type of device, moderate*speed bipolar circuits are combined with high* performance CMO circuits. ;ere, CMO circuitry continues to provide low power dissipation and larger pac&ing density. elective use of bipolar circuits gives improved performance. In the other category, the bipolar component is optimiAed to produce high*performance circuitry.

PMOS Logic The )MO logic family uses )*channel MO +ET . +igure /./7!a$ shows an inverter circuit using )MO logic. MO +ET K6 acts as an active load for the MO +ET switch K (. +or the circuit shown, <," and 3."" respectively represent logic S6T and logic S8T for a positive logic system. =hen the input is grounded !i.e. logic S6T$, K( remains in cut*off and 3."" appears at the output through the conducting K 6. =hen the input is at 3."" or near 3."", K( conducts and the output goes to near*Aero potential !i.e. logic S6T$. In the logic arrangement of +ig. /./7!b$, the output goes to logic S6T state !i.e. ground potential$ only when both K6 and K( are conducting. This is possible only when both the inputs are in logic S8T state. +or all other possible input combinations, the output is in logic S8T state, because, with either K 6 or K( nonconducting, the output is nearly 3."" through the conducting KD. The circuit of +ig. /./7!b$ thus behaves li&e a two*input ,O% gate in positive logic. It may be mentioned here that the MO +ET being used as load GK6 in +ig. /./7!a$ and KD in +ig. /./7!b$H is designed so as to have an O,*resistance that is much greater than the total O,*resistance of the MO +ETs being used as switches GK ( in +ig. /./7!a$ and K6 and K( in +ig. /./7!b$H.

NMOS Logic The ,MO logic family uses ,*channel MO +ET . ,*channel MO devices re1uire a smaller chip area per transistor compared with )*channel devices, with the result that ,MO logic offers a higher density. Also, owing to the greater mobility of the charge carriers in ,*channel devices, the ,MO logic family offers higher speed too. It is for this reason that most of the MO memory devices and microprocessors employ ,MO logic or some variation of it such as .MO , "MO and ;MO . .MO , "MO and ;MO are only structural variations of ,MO , aimed at further reducing the propagation delay. +igures /./B!a$, !b$ and !c$ respectively show an inverter, a two*input ,O% and a two*input ,A," using ,MO logic. The logic circuits are self*e9planatory.

Fig%re 6/6= !a$ ,MO logic circuit inverter, !b$ ,MO logic two*input ,O% and !c$ ,MO logic two* input ,A,". !ntegrated !n>ection Logic *!:L+ Family Integrated in'ection logic !I(#$, also &nown as current in'ection logic, is well suited to implementing # I and .# I digital functions and is a close competitor to the ,MO logic family. +igure /./E shows the basic I(# family building bloc&, which is a multi*collector bipolar transistor with a current source driving its base. Transistors KD and K0 constitute current sources. The magnitude of current depends upon e9ternally connected % and applied 5.. This current is also &nown as the in'ection current, which gives it its name of in'ection logic. If input A is ;I<;, the in'ection current through K D flows through the base* emitter 'unction of K6. Transistor K6 saturates and its collector drops to a low voltage, typically /8N688 m.. =hen A is #O=, the in'ection current is swept away from the base*emitter 'unction of K 6. Transistor K6 becomes open and the in'ection current through K0 saturates K(, with the result that the K6 collector potential e1uals the base*emitter saturation voltage of K(, typically 8.7 .. The speed of I(# family devices is a function of the in'ection current I and improves with increase in current, as a higher current allows a faster charging of capacitive loads present at bases of transistors. The programmable in'ection current feature is made use of in the I(# family of digital ICs to choose the desired speed depending upon intended application. The logic S8T level is . CE !sat.$ of the driving transistor !K 6 in the present case$, and the logic S6T level is .-E !sat.$ of the driven transistor !K( in the present case$. Typically, the logic S8T and logic S6T levels are 8.6 and 8.7. respectively. The speedNpower product of the I(# family is typically under 6 pP. Multiple collectors of different transistors can be connected together to form wired logic. +igure /.@8 shows one such arrangement, depicting the generation of O% and ,O% outputs of two logic variables A and -.

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