CHAPTER 2.

8085 MICROPROCESSOR

2.1 8085 MPU ARCHITECTURE

data bits are 8-bit( 8bit data bus) capable of addressing 64k of memory(16 bit address bus). 8085 can operate with 3MHz clock semi-CISC(74 instructions) 8085 chip has 40 pins requires +5v power supply

8085 Architecture

2.1 8085 MPU ARCHITECTURE

2 1 1 HOW INSTRUCTION EXECUTED 2.1.1

y memory memory CPU I/O / p port

Program Counter (PC)

16-bit special Register

Instruction Register (IR)

8-bit special Register g

IR decoder/ M-code M code encoder

2 1 2 ALU 2.1.2
ALU

logical

OR, XOR,AND,NOT

computational

ADD, SUB,MUL,DIV Greater/less than, equal to, positive/negative

Decision-making

Accumulator 8-bit register

Store result of operation Store the data during I/O Transfer

Flag register(status)

Sets the status of the result of operation p

8085 recognize the PSW(Program Status Word) in instruction set

2 1 3 GENERAL REGISTERS 2.1.3

B,

C, D, E, H and L registers are 8 bit registers. 6 Registers can be used as 16 bit register pairs, pairs BC, BC DE, DE HL. HL
Point into the area of memory Save data of another Register Execution of subroutine

These

Stack pointer Register (SP) 16-bit special register

Interrupt is serviced

LIFO(Last In First Out) Always decremented/incremented by 2

2 1 4 TIMING AND CONTROL UNIT 2.1.4

Timing control unit

The clock is a circuit that outputs a series of repetitive pulses occurrring at a set frequency

2 1 4 TIMING AND CONTROL UNIT 2.1.4

RESET OUT signal Pin3 carries the RESET OUT signal. signal When high high, it indicates that the 8085 is being reset; that is, the PC, IR and so on are being reset to zero. The RESET OUT signal goes to peripheral chips. Wh you first When fi t power up th the whole h l system t including i l di g the th 8085 and peripheral chips is reset or initialized. After the RESET OUT goes low, the processing begins. RESET IN signal Pin36 is an input carrying the RESET IN signal. When it is low the 8085 will reset the PC, IR and other circuits and also sends a high signal to Pin3 RESET OUT. The CPU remains in reset until the RESET IN signal goes high. high Then the data processing begins.

2 1 4 TIMING AND CONTROL UNIT 2.1.4

ALE signal Pin30 carries the ALE signal. signal Pins12 to 19 carry the lower 8 address bits or the 8 data bits High order bits of the address (A15-A8) remain on the bus (pin28-pin21)

2 1 4 TIMING AND CONTROL UNIT 2.1.4

Status signals (S0 and S1) Pins29 and pin33 carry output signals

Memory and I/O chips control signals. Signal (pin31), signal (pin32) and signal (pin34) function together. They are connected to memory and I/O chips. and are never both active at the same time. time

2 1 4 TIMING AND CONTROL UNIT 2.1.4

READY signal Pi 35 carries Pin35 i the h READY signal i l into i 8085. 8085 S Some peripheral devices are slow; they are unable to run at the same speed p at the 8085. One way y to slow down the 8085 is with the READY signal. The 8085 address a peripheral device. If the device is not ready it will return a low READY bit to the 8085. 8085 Then the 8085 generates a number of T states called WAIT states. When the peripheral device is ready it will send a high READY signal i l to t th the 8085. 8085

2 1 4 TIMING AND CONTROL UNIT 2.1.4

DMA control signals Direct Memory Access (DMA) is a process where data is transferred between two peripherals directly without the involvement of the microprocessor. U Usually ll one of f the th peripherals i h l is i memory d device. i This process employs the HOLD, pin38 on 8085 microprocessor. The external DMA controller sends a signal on the HOLD pin to the microprocessor. The microprocessor completes the current operation and sends a signal on HLDA, pin39 and stops using the buses. buses Once the DMA controller is done, it turns off the HOLD signal and the microprocessor takes back control of the buses.

2 1 4 TIMING AND CONTROL UNIT 2.1.4

Power supply signal Pin20 (Vss) is the 8085 chip ground. ground Pin40 (Vcc) connects to a source of +5v. the tolerance on the supply voltage is percent. Th power di The dissipation i ti is i less l than th 1.5W. 1 5W

1 5 INTERRUPT CONTROL UNIT 1.5

gnal that controls a processor at unexpected a random times alled an interrupt. p

sually occurs at random times depending on the need to ut down the processor. p maybe the processor is following a program.

er the data is inputted/outputted according to the errupt subroutine, the processor continues from the place as interrupted. The CPU keeps track of where the cessor is when the interrupt occurred

s 6 to 10 are input p p pins for interrupt p signals. g 11 is an output with a signal called the interrupt acknowledge

1 6 SERIAL I/O PORT 1.6

O ports provide an interface between the microprocessor nd peripheral I/O devices.

ns 4 and 5 are SOD and SID. OD stands for serial out data. D stands for serial in data.

sing the SOD and the SID pins, the user would not need to ports other with setting up input and output ports.