Digital Electronics Lab Master Manual1

SRINIVASAN ENGINEERING COLLEGE
PERAMBALUR 621 212

ELECTRONICS AND COMMUNICATION ENGINEERING ANNA UNIVERSITY - CHENNAI REGULATION 2008 II YEAR / III SEMESTER
EC 2207 DIGITAL ELECTRONICS LABORATORY

ISSUE: 01 REVISION: 00
APPROVED BY
Prof.B. Revathi HOD/ECE
PREPARED BY
P.P.Selvakumar, Assistant Professor A.Balasubramaniyan, Assistant Professor
DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR
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Preface
This laboratory manual is prepared by the Department of Electronics and Communication Engineering for D igital Electronics (EC 2207). This lab manual can be used as instructional book for students, staff and instructors to assist in performing and understanding the experiments. This manual will be available in electronic form from Colleges official website for the betterment of students.
Acknowledgement
We would like to express our profound gratitude and deep regards to the support offered by the Chairman Shri. A.Srinivasan. We also takes this opportunity to express a deep sense of gratitude to our Principal Dr.B.Karthikeyan, M.E, Ph.D for his valuable information and guidance, which helped us in completing this task through various stages. We extend our hearty thanks to our head of the department Prof.B.Revathi, M.E, (Ph.D) for her constant encouragement and constructive comments. Finally the valuable comments from fellow faculty and assistance provided by the department are highly acknowledged.
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INDEX S.NO 1 Syllabus 2 3 Lab Course Handout Experime nts 1. Study of logic gates. 2. Design and implementation of adders and subtractors using logic gates. 3. Design and implementation of code converters using logic gates. 4. Design and implementation of 4-bit binary adder/subtractor and BCD adder using IC 7483. 5. Design and implementation of 2-bit magnitude comparator using logic gates, 8-bit magnitude comparator using IC 7485. 6. Design and implementation of 16-bit odd/even parity checker / generator using IC 74180. 7. Design and implementation of multiplexer and demultiplexer using logic gates and study of IC 74150 and IC 74154. 8. Design and implementation of encoder and decoder using logic gates and study of IC 7445 and IC 74147. 61 53 49 42 35 21 13 7 TOPIC PAGE NO 4 5
9. Construction and verification of 4-bit ripple counter and Mod10/Mod-12 ripple counter. 67
10. Design and implementation of 3-bit synchronous up/down

counter. 73
11. Implementation of SISO, SIPO, PISO and PIPO shift

registers using flip- flops. 78 83
12. Design of expts 2,7,9,11 using Verilog HHDL.
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SYLLABUS 1. 2. Design and implementation of Adders and Subtractors using logic gates. Design and implementation of code converters using logic gates (i) BCD to excess-3 code and vice versa (ii) Binary to gray and vice-versa 3. Design and implementation of 4 bit binary Adder / Subtractor and BCD adder using IC 7483 4. Design and implementation of 2 Bit Magnitude Comparator using logic gates 8 Bit Magnitude Comparator using IC 7485 5. Design and implementation of 16 bit odd/even parity checker / generator using IC74180. 6. Design and implementation of Multiplexer and De-multiplexer using logic gates and study of IC74150 and IC 74154 7. Design and implementation of encoder and decoder using logic gates and study of IC7445 and IC74147 8. Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters 9. Design and implementation of 3-bit synchronous up/down counter
10. Implementation of SISO, SIPO, PISO and PIPO shift registers using Flip- Flops 11. Design of experiments 1,6,8,10 using Verilog Hardware Description Language
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LAB COURSE HANDOUT
Subject code Subject Title Staff name
: EC 2207 : Digital Electronics Lab : P.P.Selvakumar, A.Balasubramaniyan
Scope and Objective of the Subject: To learn the basic methods for the design of digital circuits and provide the fundamental concepts used in the design of digital systems. To outline the formal procedures for the analysis and design of combinational circuits and sequential circuits To study simulation of various digital combinational circuits using FPGA on Xilinx simulator.
Course Plan / Schedule: S.No 1 Topics to be covered Learning objectives Page No 13 No. of lectures 3 hrs
Design and implementation of Adders and Students will be able to learn the Subtractors using logic gates. logic gates and design of simple circuits. Design and implementation of code In this experiment students will converters using logic gates learn how to convert one form of (i) BCD to excess-3 code and vice versa code into another form. (ii) Binary to gray and vice-versa Design and implementation of 4 bit binary Students will learn how to Adder / subtractor and BCD adder using add/sub 4 bit binary numbers. IC 7483 Design and implementation of 2Bit Students will learn how to Magnitude Comparator using logic gates design a magnitude comparator. 8 Bit Magnitude Comparator using IC 7485 Design and implementation of 16 bit In this experiment students will odd/even parity checker /generator using know how to design a parity IC74180 checker. Design and implementation of In this experiment students learn Multiplexer and De- multiplexer using how to design and implement logic gates and study of IC74150 and IC multiplexer and demultiplexer. 74154 Design and implementation of encoder Students will learn how to and decoder using logic gates and study of implement encoder and decoder. IC7445 and IC74147
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3 hrs
35
3 hrs
42
3 hrs
49
3 hrs
53
3 hrs
61
3 hrs
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Construction and verification of 4 bit ripple counter and Mod-10 / Mod-12 Ripple counters Design and implementation of 3-bit synchronous up/down counter
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11
In this experiment students will learn how to construct different types of ripple counter. In this experiment students will learn how to design and implement synchronous up/down counter. Implementation of SISO, SIPO, PISO and Students will learn how to PIPO shift registers using Flip- Flops implement various types of shift registers. Design of experiments 1,6,8,10 using Students will learn how to Verilog Hardware Description Language design a digital circuit using Verilog HDL. Evaluation scheme Internal Assessment EC No. 1 2 3 4 Evaluation Components Observation Record Attendance Model lab Percentage of marks allotted 20 30 30 20
67
3 hrs
73
3 hrs
78
3 hrs
83
3 hrs
Percentage of marks obtained
Timings for chamber consultation : Students should contact the Course Instructor in her/his chamber during lunch break. STUDENTS GUIDELINES: There are 3 hours allocated to a laboratory session in DIGITAL ELECTRONICS LAB. It is a necessary part of the course at which attendance is compulsory. Here are some guidelines to help you perform the experiments and to submit the reports: 1. Read all instructions carefully and proceed according to that. 2. Ask the faculty if you are unsure of anything experiment or any concept. 3. Give the connection as per the diagrams. 4. Write up full and suitable conclusions for each experiment. 5. After completing the experiment complete the observation and get signature from the staff. 6. Before coming to next lab make sure that you complete the record and get sign from the faculty.
STAFF SIGNATURE ISSUE: 01 REVISION: 00
HOD 6
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EXPT NO. : DATE : AIM:
STUDY OF LOGIC GATES
To study about logic gates and verify their truth tables. APPARATUS REQUIRED: SL No. 1. 2. 3. 4. 5. 6. 8. 9. COMPONENT AND GATE OR GATE NOT GATE NAND GATE 2 I/P NOR GATE X-OR GATE IC TRAINER KIT WIRES SPECIFICATION IC 7408 IC 7432 IC 7404 IC 7400 IC 7402 IC 7486 QTY 1 1 1 1 1 1 1 AS REQUIRED
THEORY: Circuit that takes the logical decision and the process are called logic gates. Each gate has one or more input and only one output. OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as universal gates. Basic gates form these gates. AND GATE: The AND gate performs a logical multiplication commonly known as AND function. The output is high when both the inputs are high. The output is low level when any one of the inputs is low. OR GATE: The OR gate performs a logical addition commonly known as OR function. The output is high when any one of the inputs is high. The output is low level when both the inputs are low. NOT GATE: The NOT gate is called an inverter. The output is high when the input is low. The output is low when the input is high. ISSUE: 01 REVISION: 00 7
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NAND GATE: The NAND gate is a contraction of AND-NOT. The output is high when both inputs are low and any one of the input is low .The output is low level when both inputs are high. NOR GATE: The NOR gate is a contraction of OR-NOT. The output is high when both inputs are low. The output is low when one or both inputs are high. X-OR GATE: The output is high when any one of the inputs is high. The output is low when both the inputs are low and both the inputs are high.
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AND GATE: SYMBOL: PIN DIAGRAM:
OR GATE:
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NOT GATE: SYMBOL: PIN DIAGRAM:
X-OR GATE : SYMBOL : PIN DIAGRAM :
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2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM:
NOR GATE:
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PROCEDURE: (i) (ii) (iii) Connections are given as per circuit diagram. Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
RESULT: Thus the logic gates are studied and their truth tables were verified.
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EXPT NO. DATE AIM:
: :
DESIGN OF ADDER AND SUBTRACTOR
To design and construct half adder, full adder, half subtractor and full subtractor circuits and verify the truth table using logic gates. APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 5. 6. COMPONENT AND GATE X-OR GATE NOT GATE OR GATE IC TRAINER KIT WIRES SPECIFICATION IC 7408 IC 7486 IC 7404 IC 7432 QTY. 1 1 1 1 1 AS REQUIRED
THEORY: HALF ADDER: A half adder has two inputs for the two bits to be added and two outputs one from the sum S and other from the carry c into the higher adder position. Above circuit is called as a carry signal from the addition of the less significant bits sum from the X-OR Gate the carry out from the AND gate. FULL ADDER: A full adder is a combinational circuit that forms the arithmetic sum of input; it consists of three inputs and two outputs. A full adder is useful to add three bits at a time but a half adder cannot do so. In full adder sum output will be taken from X-OR Gate, carry output will be taken from OR Gate. HALF SUBTRACTOR: The half subtractor is constructed using X-OR and AND Gate. The half subtractor has two input and two outputs. The outputs are difference and borrow. The difference can be applied using X-OR Gate, borrow output can be implemented using an AND Gate and an inverter.
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FULL SUBTRACTOR: The full subtractor is a combination of X-OR, AND, OR, NOT Gates. In a full subtractor the logic circuit should have three inputs and two outputs. The two half subtractor put together gives a full subtractor .The first half subtractor will be C and A B. The output will be difference output of full subtractor. The expression AB assembles the borrow output of the half subtractor and the second term is the inverted difference output of first X-OR.
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HALF ADDER TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 CARRY 0 0 0 1 SUM 0 1 1 0
K-Map for SUM:
K-Map for CARRY:
SUM = AB + AB
CARRY = AB
LOGIC DIAGRAM:
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FULL ADDER TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 CARRY 0 0 0 1 0 1 1 1 SUM 0 1 1 0 1 0 0 1
K-Map for SUM:
SUM = ABC + ABC + ABC + ABC K-Map for CARRY:
CARRY = AB + BC + AC
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LOGIC DIAGRAM: FULL ADDER USING TWO HALF ADDER
HALF SUBTRACTOR TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 BORROW 0 1 0 0 DIFFERENCE 0 1 1 0
K-Map for DIFFERENCE:
DIFFERENCE = AB + AB K-Map for BORROW:
BORROW = AB
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LOGIC DIAGRAM:
FULL SUBTRACTOR TRUTH TABLE: A 0 0 0 0 1 1 1 1 K-Map for Difference:
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0 1 0 1
BORROW 0 1 1 1 0 0 0 1
DIFFERENCE 0 1 1 0 1 0 0 1
Difference = ABC + ABC + ABC + ABC K-Map for Borrow:
Borrow = AB + BC + AC ISSUE: 01 REVISION: 00 18
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LOGIC DIAGRAM:
FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:
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PROCEDURE: (i) Connections are given as per circuit diagram. (ii) (iii) Logical inputs are given as per circuit diagram. Observe the output and verify the truth table.
RESULT: Thus the half adder, full adder, half subtractor and full subtractor was designed and their truth table is verified.
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EXPT NO. DATE
: :
DESIGN AND IMPLEMENTATION OF CODE CONVERTER
AIM: To design and implement 4-bit (i) Binary to gray code converter (ii) Gray to binary code converter (iii) BCD to excess-3 code converter (iv) Excess-3 to BCD code converter APPARATUS REQUIRED: Sl.No. COMPONENT 1. X-OR GATE 2. AND GATE 3. OR GATE 4. NOT GATE 5. IC TRAINER KIT 6. WIRES
SPECIFICATION IC 7486 IC 7408 IC 7432 IC 7404 -
QTY. 1 1 1 1 1 AS REQUIRED
THEORY: The availability of large variety of codes for the same discrete elements of information results in the use of different codes by different systems. A conversion circuit must be inserted between the two systems if each uses different codes for same information. Thus, code converter is a circuit that makes the two systems compatible even though each uses different binary code. The bit combination assigned to binary code to gray code. Since each code uses four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a non-weighted code. The input variable are designated as B3, B2, B1, B0 and the output variables are designated as C3, C2, C1, Co. from the truth table, co mbinational circuit is designed. The Boolean functions are obtained from K-Map for each output variable. A code converter is a circuit that makes the two systems compatible even though each uses a different binary code. To convert from binary code to Excess-3 code, the input lines must supply the bit combination of elements as specified by code and the ISSUE: 01 REVISION: 00 21
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output lines generate the corresponding bit combination of code. Each one of the four maps represents one of the four outputs of the circuit as a function o f the four input variables. A two- level logic diagram may be obtained directly from the Boolean expressions derived by the maps. These are various other possibilities for a logic diagram that implements this circuit. Now the OR gate whose output is C+D has been used to implement partially each of three outputs.
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BINARY TO GRAY CODE CONVERTOR TRUTH TABLE: | Binary input | B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Gray code output G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0
K-Map for G3 :
G3 = B3 K-Map for G2 :
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K-Map for G1 :
K-Map for G0 :
LOGIC DIAGRAM:
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GRAY CODE TO BINARY CONVERTER TRUTH TABLE: | Gray Code G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 | B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Binary Code B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 |
K-Map for B3 :
B3 = G3 ISSUE: 01 REVISION: 00 25
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K-Map for B2 :
K-Map for B1 :
K-Map for B0 :
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LOGIC DIAGRAM:
BCD TO EXCESS-3 CONVERTOR TRUTH TABLE: | BCD input B3 B2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 | B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 1 1 1 1 1 x x x x x x Excess 3 output G2 G1 0 1 1 1 1 0 0 0 0 1 x x x x x x 1 0 0 1 1 0 0 1 1 0 x x x x x x | G0 1 0 1 0 1 0 1 0 1 0 x x x x x x
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K-Map for E3 :
E3 = B3 + B2 (B0 + B1)
K-Map for E2 :
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K-Map for E1 :
K-Map for E0 :
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LOGIC DIAGRAM:
EXCESS-3 TO BCD CONVERTOR TRUTH TABLE: | Excess 3 Input B3 0 0 0 0 0 1 1 1 1 1 B2 0 1 1 1 1 0 0 0 0 1 B1 1 0 0 1 1 0 0 1 1 0 B0 1 0 1 0 1 0 1 0 1 0 | G3 0 0 0 0 0 0 0 0 1 1 BCD Output G2 0 0 0 0 1 1 1 1 0 0 G1 0 0 1 1 0 0 1 1 0 0 G0 0 1 0 1 0 1 0 1 0 1 |
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K-Map for A:
A = X1 X2 + X3 X4 X1 K-Map for B:
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K-Map for C:
K-Map for D:
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LOGIC DIAGRAM:
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PROCEDURE: (i) (ii) (iii) Connections were given as per circuit diagram. Logical inputs were given as per truth table Observe the logical output and verify with the truth tables.
RESULT: Thus the Binary to gray code converter,Gray to binary code converter,BCD to excess-3 code converter and Excess-3 to BCD code converter was designed and implemented. ISSUE: 01 REVISION: 00 34
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EXPT NO. DATE : AIM:
DESIGN OF 4-BIT ADDER AND SUBTRACTOR
To design and implement 4-bit adder, subtractor and BCD adder using IC 7483. APPARATUS REQUIRED: Sl.No. COMPONENT 1. IC 2. EX-OR GATE 3. NOT GATE 3. IC TRAINER KIT 4. WIRES
SPECIFICATION IC 7483 IC 7486 IC 7404 -
QTY. 1 1 1 1 AS REQUIRED
THEORY: 4 BIT BINARY ADDER: A binary adder is a digital circuit that produces the arithmetic sum of two binary numbers. It can be constructed with full adders connected in cascade, with the output carry from each full adder connected to the input carry of next full adder in chain. The augends bits of A and the addend bits of B are designated by subscript numbers from right to left, with subscript 0 denoting the least significant bits. The carries are connected in chain through the full adder. The input carry to the adder is C 0 and it ripples through the full adder to the output carry C 4 . 4 BIT BINARY SUBTRACTOR: The circuit for subtracting A-B consists of an adder with inverters, placed between each data input B and the corresponding input of full adder. The input carry C 0 must be equal to 1 when performing subtraction.
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4 BIT BINARY ADDER/SUBTRACTOR: The addition and subtraction operation can be combined into one circuit with one common binary adder. The mode input M controls the operation. When M=0, the circuit is adder circuit. When M=1, it becomes subtractor.
4 BIT BCD ADDER: Consider the arithmetic addition of two decimal digits in BCD, together with an input carry from a previous stage. Since each input digit does not exceed 9, the output sum cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal digits must be represented in BCD and should appear in the form listed in the columns. ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2 decimal digits, together with the input carry, are first added in the top 4 bit adder to produce the binary sum.
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PIN DIAGRAM FOR IC 7483:
LOGIC DIAGRAM: 4-BIT BINARY ADDER
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LOGIC DIAGRAM: 4-BIT BINARY SUBTRACTOR
LOGIC DIAGRAM: 4-BIT BINARY ADDER/SUBTRACTOR
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TRUTH TABLE: Input Data A Input Data B C 0 1 0 0 1 1 Addition S4 S3 S2 S1 1 0 1 1 0 1 0 0 0 0 0 0 1 0 1 0 1 1 0 0 0 0 0 0 B 1 1 0 0 0 0 Subtraction D4 D3 D2 D1 0 0 1 1 1 1 1 0 0 0 1 1 1 0 1 1 1 1 0 0 0 0 1 1
A4 A3 A2 A1 B4 B3 B2 B1 1 1 0 0 1 1 0 0 0 0 0 1 0 0 1 0 1 1 0 0 0 1 0 0 0 1 1 0 1 1 0 0 0 1 0 1 1 0 0 1 1 1 0 0 0 1 1 1
LOGIC DIAGRAM: BCD ADDER
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K MAP
Y = S4 (S3 + S2) TRUTH TABLE: BCD SUM S3 S2 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 CARRY C 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1
S4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
S1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
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PROCEDURE: (i) (ii) (iii) Connections were given as per circuit diagram. Logical inputs were given as per truth table Observe the logical output and verify with the truth tables.
RESULT: Thus the 4-bit adder, subtractor and BCD adder using IC 7483 was designed and implemented.
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EXPT NO. DATE :
DESIGN AND IMPLEMENTATION OF MAGNITUDE COMPARATOR AIM: To design and implement (i) (ii) 2 bit magnitude comparator using basic gates. 8 bit magnitude comparator using IC 7485.
APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 5. 6. 7. COMPONENT AND GATE X-OR GATE OR GATE NOT GATE 4-BIT MAGNITUDE COMPARATOR IC TRAINER KIT WIRES SPECIFICATION IC 7408 IC 7486 IC 7432 IC 7404 IC 7485 QTY. 2 1 1 1 2 1 AS REQUIRED
THEORY: The comparison of two numbers is an operator greater than, less than (or) equal to the other number. combinational circuit that compares two numbers A and magnitude. The outcome of the comparator is specified indicate whether A>B, A=B (or) A<B. A = A3 A2 A1 A0 B = B3 B2 B1 B0 The equality of the two numbers and B is displayed in a combinational circuit designated by the symbol (A=B). ISSUE: 01 REVISION: 00 42 that determine one number is A magnitude comparator is a B and determine their relative by three binary variables that
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This indicates A greater than B, then inspect the relative magnitude of pairs of significant digits starting from most significant position. A is 0 and that of B is 0. We have A<B, the sequential comparison can be expanded as A>B = A3B3 1 + X3 A2 B21 + X3 X2 A1 B11 + X3 X2 X1 A0 B01 A<B = A3 1 B3 + X3 A2 1 B2 + X3 X2A11 B1 + X3 X2 X1 A01 B0 The same circuit can be used to compare the relative magnitude of two BCD digits. Where, A = B is expanded as, A = B = (A3 + B3 ) (A2 + B2 ) (A1 + B1 ) (A0 + B0 ) x3 x2 x1 x0
2 BIT MAGNITUDE COMPARATOR TRUTH TABLE A1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 A>B 0 0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 A=B 1 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 A<B 0 1 1 1 0 0 1 1 0 0 0 1 0 0 0 0
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K MAP
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LOGIC DIAGRAM:
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LOGIC DIAGRAM: 8 BIT MAGNITUDE COMPARATOR
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TRUTH TABLE:
A 0000 0001 0000 0000 0001 0000 0000 0000 0001
B 0000 0000 0001
A>B 0 1 0
A=B 1 0 0
A<B 0 0 1
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RESULT: Thus the 2 bit magnitude comparator using basic gates and 8 bit magnitude comparator using IC 7485 was designed and implemented.
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EXPT NO. DATE :
16 BIT ODD/EVEN PARITY CHECKER /GENERATOR AIM: To design and implement 16 bit odd/even parity checker generator using IC 74180. APPARATUS REQUIRED: Sl.No. 1. 2 3. 4. COMPONENT NOT GATE IC TRAINER KIT WIRES SPECIFICATION IC 7404 IC 74180 QTY. 1 2 1 AS REQUIRED
THEORY: A parity bit is used for detecting errors during transmission of binary information. A parity bit is an extra bit included with a binary message to make the number is either even or odd. The message including the parity bit is transmitted and then checked at the receiver ends for errors. An error is detected if the checked parity bit doesnt correspond to the one transmitted. The circuit that generates the parity bit in the transmitter is called a parity generator and the circuit that checks the parity in the receiver is called a parity checker. In even parity, the added parity bit will make the total number is even amount. In odd parity, the added parity bit will make the total number is odd amount. The parity checker circuit checks for possible errors in the transmission. If the information is passed in even parity, then the bits required must have an even number of 1s. An error occur during transmission, if the received bits have an odd number of 1s indicating that one bit has changed in value during transmission.
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FUNCTION TABLE: INPUTS Number of High Data Inputs (I0 I7) EVEN ODD EVEN ODD X X
PE 1 1 0 0 1 0
PO 0 0 1 1 1 0
OUTPUTS E O 1 0 0 1 0 1 0 1 1 0 0 1
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LOGIC DIAGRAM: 16 BIT ODD/EVEN PARITY CHECKER
TRUTH TABLE: I7 I6 I5 I4 I3 I2 I1 I0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 LOGIC DIAGRAM: 16 BIT ODD/EVEN PARITY GENERATOR I7I6I5 I4I3 I211 I0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 Active 1 0 1 E 1 1 0 O 0 0 1
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TRUTH TABLE: E 1 0 1 O 0 1 0
I7 I6 I5 I4 I3 I2 I1 I0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0
I7 I6 I5 I4 I3 I2 I1 I0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0
Active 1 0 0
RESULT: Thus the 16 bit odd/even parity checker generator using IC 74180 was designed and implemented. ISSUE: 01 REVISION: 00 52
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EXPT NO. DATE :
DESIGN AND IMPLEMENTATION OF MULTIPLEXER AND DEMULTIPLEXER AIM: To design and implement multiplexer and demultiplexer using logic gates and study of IC 74150 and IC 74154.
APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 5. COMPONENT 3 I/P AND GATE OR GATE NOT GATE IC TRAINER KIT WIRES SPECIFICATION IC 7411 IC 7432 IC 7404 QTY. 2 1 1 1 AS REQUIRED
THEORY: MULTIPLEXER: Multiplexer means transmitting a large number of information units over a smaller number of channels or lines. A digital multiplexer is a combinational circuit that selects binary information from one of many input lines and directs it to a single output line. The selection of a particular input line is controlled by a set of selection lines. Normally there are 2n input line and n selection lines whose bit combination determine which input is selected. DEMULTIPLEXER: The function of Demultiplexer is in contrast to multiplexer function. It takes information from one line and distributes it to a given number of output lines. For this reason, the demultiplexer is also known as a data distributor. Decoder can also be used as demultiplexer. In the 1: 4 demultiplexer circuit, the data input line goes to all of the AND gates. The data select lines enable only one gate at a time and the data on the data input line will pass through the selected gate to the associated data output line.
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BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:
FUNCTION TABLE:
S1 0 0 1 1
S0 0 1 0 1
INPUTS Y D0 D0 S1 S0 D1 D1 S1 S0 D2 D2 S1 S0 D3 D3 S1 S0
Y = D0 S1 S0 + D1 S1 S0 + D2 S1 S0 + D3 S1 S0
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CIRCUIT DIAGRAM FOR MULTIPLEXER:
TRUTH TABLE:
S1 0 0 1 1
S0 0 1 0 1
Y = OUTPUT D0 D1 D2 D3
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BLOCK DIAGRAM FOR 1:4 DEMULTIPLEXER:
FUNCTION TABLE:
S1 0 0 1 1
S0 0 1 0 1
INPUT X D0 = X S1 S0 X D1 = X S1 S0 X D2 = X S1 S0 X D3 = X S1 S0
Y = X S1 S0 + X S1 S0 + X S1 S0 + X S1 S0
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LOGIC DIAGRAM FOR DEMULTIPLEXER:
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TRUTH TABLE: INPUT S1 0 0 0 0 1 1 1 1 S0 0 0 1 1 0 0 1 1 I/P 0 1 0 1 0 1 0 1 D0 0 1 0 0 0 0 0 0 D1 0 0 0 1 0 0 0 0 OUTPUT D2 0 0 0 0 0 1 0 0 D3 0 0 0 0 0 0 0 1
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RESULT: Thus the multiplexer and demultiplexer using logic gates was designed IC 74150 and IC 74154 also studied. ISSUE: 01 REVISION: 00 60
II YEAR
EXPT NO. DATE :
DESIGN AND IMPLEMENTATION OF ENCODER AND DECODER
AIM: To design and implement encoder and decoder using logic gates and study of IC 7445 and IC 74147.
APPARATUS REQUIRED: Sl.No. 1. 2. 3. 2. 3. COMPONENT 3 I/P NAND GATE OR GATE NOT GATE IC TRAINER KIT PATCH CORDS SPECIFICATION IC 7410 IC 7432 IC 7404 QTY. 2 3 1 1 27
THEORY: ENCODER: An encoder is a digital circuit that perform inverse operation of a decoder. An encoder has 2n input lines and n output lines. In encoder the output lines generates the binary code corresponding to the input value. In octal to binary encoder it has eight inputs, one for each octal digit and three output that generate the corresponding binary code. In encoder it is assumed that only one input has a value of one at any given time otherwise the circuit is meaningless. It has an ambiguila that when all inputs are zero the outputs are zero. The zero outputs can also be generated when D0 = 1.
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II YEAR
DECODER: A decoder is a multiple input multiple output logic circuit which converts coded input into coded output where input and output codes are different. The input code generally has fewer bits than the output code. Each input code word produces a different output code word i.e there is one to one mapping can be expressed in truth table. In the block diagram of decoder circuit the encoded information is present as n input producing 2n possible outputs. 2n output values are from 0 through out 2n 1.
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II YEAR
PIN DIAGRAM FOR IC 7445: BCD TO DECIMAL DECODER:
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II YEAR
TRUTH TABLE FOR ENCODER: INPUT Y1 1 0 0 0 0 0 0 Y2 0 1 0 0 0 0 0 Y3 0 0 1 0 0 0 0 Y4 0 0 0 1 0 0 0 Y5 0 0 0 0 1 0 0 Y6 0 0 0 0 0 1 0 Y7 0 0 0 0 0 0 1 A 0 0 0 1 1 1 1 OUTPUT B 0 1 1 0 0 1 1 C 1 0 1 0 1 0 1
LOGIC DIAGRAM FOR ENCODER:
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II YEAR
TRUTH TABLE FOR DECODER:
INPUT E 1 0 0 0 0 A 0 0 0 1 1 B 0 0 1 0 1 D0 1 0 1 1 1
OUTPUT D1 1 1 0 1 1 D2 1 1 1 0 1 D3 1 1 1 1 0
LOGIC DIAGRAM FOR DECODER:
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II YEAR
RESULT: Thus the encoder and decoder using logic gates were designed and IC 7445, IC 74147 was studied. ISSUE: 01 REVISION: 00 66
II YEAR
EXPT NO.
DATE : CONSTRUCTION AND VERIFICATION OF 4 BIT RIPPLE COUNTER AND MOD 10/MOD 12 RIPPLE COUNTER AIM: To design and verify 4 bit ripple counter mod 10/ mod 12 ripple counter.
APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. COMPONENT JK FLIP FLOP NAND GATE IC TRAINER KIT WIRES SPECIFICATION IC 7476 IC 7400 QTY. 2 1 1 AS REQUIRED
THEORY: A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. A specified sequence of states appears as counter output. This is the main difference between a register and a counter. There are two types of counter, synchronous and asynchronous. In synchronous common clock is given to all flip flop and in asynchronous first flip flop is clocked by external pulse and then each successive flip flop is clocked by Q or Q output of previous stage. A soon the clock of second stage is triggered by output of first stage. Because of inherent propagation delay time all flip flops are not activated at same time which results in asynchronous operation.
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II YEAR
LOGIC DIAGRAM FOR 4 BIT RIPPLE COUNTER:
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TRUTH TABLE:
CLK 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
QA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
QB 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
QC 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
QD 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
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II YEAR
LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:
TRUTH TABLE:
CLK 0 1 2 3 4 5 6 7 8 9 10
QA 0 1 0 1 0 1 0 1 0 1 0
QB 0 0 1 1 0 0 1 1 0 0 0
QC 0 0 0 0 1 1 1 1 0 0 0
QD 0 0 0 0 0 0 0 0 1 1 0 70
II YEAR
LOGIC DIAGRAM FOR MOD - 12 RIPPLE COUNTER:
TRUTH TABLE:
CLK 0 1 2 3 4 5 6 7 8 9 10 11 12
QA 0 1 0 1 0 1 0 1 0 1 0 1 0
QB 0 0 1 1 0 0 1 1 0 0 1 1 0
QC 0 0 0 0 1 1 1 1 0 0 0 0 0
QD 0 0 0 0 0 0 0 0 1 1 1 1 0
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II YEAR
RESULT: Thus the 4 bit ripple counter mod 10/ mod 12 ripple counters was implemented and the truth table was verified.
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II YEAR
EXPT NO.
DATE : DESIGN AND IMPLEMENTATION OF 3 BIT SYNCHRONOUS UP/DOWN COUNTER AIM: To design and implement 3 bit synchronous up/down counter.
APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. 5. 6. 7. COMPONENT JK FLIP FLOP 3 I/P AND GATE OR GATE XOR GATE NOT GATE IC TRAINER KIT WIRES SPECIFICATION IC 7476 IC 7411 IC 7432 IC 7486 IC 7404 QTY. 2 1 1 1 1 1 AS REQUIRED
THEORY: A counter is a register capable of counting number of clock pulse arriving at its clock input. Counter represents the number of clock pulses arrived. An up/down counter is one that is capable of progressing in increasing order or decreasing order through a certain sequence. An up/down counter is also called bidirectional counter. Usually up/down operation of the counter is controlled by up/down signal. When this signal is high counter goes through up sequence and when up/down signal is low counter follows reverse sequence.
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K MAP
STATE DIAGRAM:
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II YEAR
CHARACTERISTICS TABLE: Q 0 0 1 1 Qt+1 0 1 0 1 J 0 1 X X K X X 1 0
LOGIC DIAGRAM:
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II YEAR
TRUTH TABLE: Input Up/Down 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Present State QA QB QC 0 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Next State QA+1 Q B+1 QC+1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 1 1 0 0 1 1 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A JA 1 X X X X 0 0 0 0 0 0 1 X X X X KA X 0 0 0 1 X X X X X X X 0 0 0 1 JB 1 X X 0 1 X X 0 0 1 X X 0 1 X X B KB X 0 1 X X 0 1 X X X 0 1 X X 0 1 JC 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1 X C KC X 1 X 1 X 1 X 1 X 1 X 1 X 1 X 1
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II YEAR
RESULT: Thus the 3 bit synchronous up/down counter was designed implemented.
77
II YEAR
EXPT NO. DATE :
: DESIGN AND IMPLEMENTATION OF SHIFT REGISTER
AIM: To design and implement (i) Serial in serial out shift register (ii) Serial in parallel out shift register (iii) Parallel in serial out shift register (iv) Parallel in parallel out shift register APPARATUS REQUIRED: Sl.No. 1. 2. 3. 4. COMPONENT D FLIP FLOP OR GATE IC TRAINER KIT WIRES SPECIFICATION IC 7474 IC 7432 QTY. 2 1 1 AS REQUIRED
THEORY: A register is capable of shifting its binary information in one or both directions is known as shift register. The logical configuration of shift register consist of a D-Flip flop cascaded with output of one flip flop connected to input of next flip flop. All flip flops receive common clock pulses which causes the shift in the output of the flip flop. The simplest possible shift register is one that uses only flip flop. The output of a given flip flop is connected to the input of next flip flop of the register. Each clock pulse shifts the content of register one bit position to right.
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II YEAR
PIN DIAGRAM:
LOGIC DIAGRAM:
SERIAL IN SERIAL OUT:
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II YEAR
TRUTH TABLE: Serial in CLK 1 2 3 4 5 6 7 1 0 0 1 X X X 0 0 0 1 0 0 1 Serial out
LOGIC DIAGRAM: SERIAL IN PARALLEL OUT:
TRUTH TABLE: OUTPUT CLK 1 2 3 4 DATA 1 0 0 1 QA 1 0 0 1 QB 0 1 0 0 QC 0 0 1 0 QD 0 0 1 1
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II YEAR
LOGIC DIAGRAM: PARALLEL IN SERIAL OUT:
TRUTH TABLE: CLK 0 1 2 3 Q3 1 0 0 0 Q2 0 0 0 0 Q1 0 0 0 0 Q0 1 0 0 0 O/P 1 0 0 1
LOGIC DIAGRAM: PARALLEL IN PARALLEL OUT:
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II YEAR
TRUTH TABLE: DATA INPUT CLK 1 2 DA 1 1 DB 0 0 DC 0 1 DD 1 0 QA 1 1 OUTPUT QB 0 0 QC 0 1 QD 1 0
RESULT: Thus the Serial in serial out, Serial in parallel out, Parallel in serial out and Parallel in parallel out shift registers were implemented using IC 7474.
82

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SRINIVASAN ENGINEERING COLLEGE

PERAMBALUR 621 212

EC 2207 DIGITAL ELECTRONICS LABORATORY

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

10. Design and implementation of 3-bit synchronous up/down

11. Implementation of SISO, SIPO, PISO and PIPO shift

12. Design of expts 2,7,9,11 using Verilog HHDL.

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

LAB COURSE HANDOUT

Subject code Subject Title Staff name

: EC 2207 : Digital Electronics Lab : P.P.Selvakumar, A.Balasubramaniyan

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

Percentage of marks obtained

STAFF SIGNATURE ISSUE: 01 REVISION: 00

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

EXPT NO. : DATE : AIM:

STUDY OF LOGIC GATES

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

AND GATE: SYMBOL: PIN DIAGRAM:

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

NOT GATE: SYMBOL: PIN DIAGRAM:

X-OR GATE : SYMBOL : PIN DIAGRAM :

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

2-INPUT NAND GATE: SYMBOL: PIN DIAGRAM:

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

EXPT NO. DATE AIM:

DESIGN OF ADDER AND SUBTRACTOR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

HALF ADDER TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 CARRY 0 0 0 1 SUM 0 1 1 0

K-Map for SUM:

K-Map for CARRY:

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

FULL ADDER TRUTH TABLE: A 0 0 0 0 1 1 1 1 B 0 0 1 1 0 0 1 1 C 0 1 0 1 0 1 0 1 CARRY 0 0 0 1 0 1 1 1 SUM 0 1 1 0 1 0 0 1

K-Map for SUM:

SUM = ABC + ABC + ABC + ABC K-Map for CARRY:

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

LOGIC DIAGRAM: FULL ADDER USING TWO HALF ADDER

HALF SUBTRACTOR TRUTH TABLE: A 0 0 1 1 B 0 1 0 1 BORROW 0 1 0 0 DIFFERENCE 0 1 1 0

K-Map for DIFFERENCE:

DIFFERENCE = AB + AB K-Map for BORROW:

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

FULL SUBTRACTOR TRUTH TABLE: A 0 0 0 0 1 1 1 1 K-Map for Difference:

Difference = ABC + ABC + ABC + ABC K-Map for Borrow:

Borrow = AB + BC + AC ISSUE: 01 REVISION: 00 18

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

FULL SUBTRACTOR USING TWO HALF SUBTRACTOR:

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

EXPT NO. DATE

DESIGN AND IMPLEMENTATION OF CODE CONVERTER

SPECIFICATION IC 7486 IC 7408 IC 7432 IC 7404 -

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

BINARY TO GRAY CODE CONVERTOR TRUTH TABLE: | Binary input | B3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 B2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 B1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 B0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 G3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1

Gray code output G2 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 G1 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 G0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR

DIGITAL ELECTRONICS LAB MANUAL SRINIVASAN ENGINEERING COLLEGE, PERAMBALUR