EMI Driven by PI

EMI Driven by PI
2008 Ansoft, LLC All rights reserved.
Ansoft, LLC Proprietary
Outline
SI + PI = EMI
These disciplines are no longer independent of each other
Fundamentals of EMI
Where does it come from and how is it minimized Five Step EMC Design Flow
Power Integrity design methodology to reduce EMI

Fundamentals of Power Integrity Design Process to meet design specs in the Time and Frequency domain
2nd Presentation on EMI Driven by SI

Fundamentals of Signal Integrity
Crosstalk is the main contributor to EMI
Case studies that show perils of crosstalk in real world designs
SI/PI/EMI Design Overview

Frequency Domain Time Domain
Display Panel
EMI/EMC Signal Integrity

Common mode radiation - Differential mode radiation
-
Pwr Noise Signal
Control IC
Memory
Driver IC
Power Integrity
Electromagnetic Interference
PCB
Signal Integrity Power Integrity

Switching Noise - Impedance Profile - Power/Gnd Plane Resonance - Decoupling Capacitors
Power Supplies
Impedance - Crosstalk - Reflection - Termination - Dielectric Losses

-
Three Basic Elements of EMC

Emission EMI EMIsource source
Coupling process
Conduction EMI EMIFilters Filters Capacitive Shields Shields Inductive Space & Field
Conductive
Radiative
Low, Middle & High Frequency

EMI EMIFilters Filters
Low & Middle Frequency LC Resonance

Shields Shields Shields Shields Immunity EMS EMS
High Frequency
Shields Shields
Loop Mode & Common Mode Noise

A PC Board & Cables
Loop mode current
A victim device
A Driver & Receiver
by AC Analysis of Q3D Extractor
Differential mode current flows --- Loop Common mode current flows --- Open We can see Common mode current is more serious than Normal mode.
Common mode current

2008 Ansoft, LLC All rights reserved. Ansoft, LLC Proprietary
Antenna theory
-A Differential mode current flow -A Common mode current flow Loop antenna theory Dipole antenna theory
131.6 10 -16 (f 2 AI) sin E= r
r : distance A : area of the loop
4 10 7 ( f Il ) sin E= r
r Length :l
I Illustration of a loop antenna
I Illustration of a dipole antenna
FCC B level Mag. E limit :40dBuV/m @ 3m Mag. E( Loop antenna) : 20mA Mag. E( Dipole antenna) : 8uA
EMC Design Flow
Impedance Analysis Planes deliver power to ICs and return path for signal Ensure that Plane impedance is smooth and low over broad frequency range
Resonance Analysis
Signal Extraction
Emissions Analysis
Enclosure Simulation
EMC Design Flow

Resonances indicate areas of high impedance and EMI potential Ensure power planes do not resonant in critical locations
Impedance Analysis
Resonance Analysis
Signal Extraction
Emissions Analysis
EMC Design Flow
Impedance Analysis
Resonance Analysis
Signal Extraction If signal is not at the receiver, it went somewhere else Ensure clean signal transmission and good return path for critical nets Enclosure Simulation
Emissions Analysis
EMC Design Flow
Impedance Analysis
Resonance Analysis
Signal Extraction
Emissions Analysis
Non-ideal planes and tight routing can lead to unintentional signals Ensure there are no unintentional radiators
EMC Design Flow
Impedance Analysis
Resonance Analysis
Signal Extraction
Emissions Analysis Real enclosures are non-ideal and can pass radiation Ensure minimal radiation from PCB escapes the chassis holes
PI Methodology
Signal Integrity
Power Integrity
Power Integrity A Case Study Active devices require clean power to operate correctly Power distribution system (PDS) design engineers must ensure that all parts receive voltage between certain limits and that noise is kept sufficiently low Todays designs with many separate power domains of high current and low voltage devices complicate power integrity analysis
Board Imported from Layout

VRM
Measuring impedance at the six VCC pins on U41
PDS Design Flow
Start
Finish Yes
EM extraction of impedance for critical devices
Determine frequencies of specification violations
Simulate in time domain to check for compliance
No
Choose capacitor or geometric change to address violations
Alter design according to findings
Frequency Domain PDS Targets

(Power _ Supply _ Voltage) (Allowed _ Ripple )
Current
target
Mag. of Z
ZTarget =
|Z|
f
1 GHz
1KHz 1MHz 100MHz
High Frequency Ceramic Capacitors Power/Ground Planes Buried Capacitance
Switching Power Supply
Electrolytic Bulk Capacitors
Defining the Target Impedance To define the target impedance we need to consider two factors:
VRM
VRM
Peak current
Determines maximum impedance
Package Model
C58 Cpkg L59 Lpkg R60 0 Rpkg 0 V35
logic_in enable pullup
Name=vrm
Spectral power
Determines cutoff frequency
Driver
R5
pulldown
50
VRM
VRM
io out_of_in
V33
DC=VCC 0
Peak Current Peak driver current 37.87 mA Example:

Six drivers and 0.18 V maximum voltage swing:
Ansoft Corporation
40.00
Driver Current
Curve Info mag(Ipositive(vrm)) Transient
Driver
max 37.8706
35.00
30.00
mag(Ipositive(vrm)) [mA]
25.00
20.00
15.00
0.18 V = 800 m 6(37.87 mA )
10.00
5.00
0.00 0.00 5.00 10.00 15.00 20.00 25.00 Time [ns] 30.00 35.00 40.00 45.00 50.00
Driver Spectrum
Ansoft Corporation
1.00E-003
XY Plot 4
Driver
1.00E-004
667 MHz
1.00E-005
Choose a frequency below which most of the signal energy lies
Curve Inf o
mag(vrm_pow er) Transient
1.00E-006
m ag(vrm _pow er)
1.00E-007
1.00E-008
667 MHz = 97% of Spectrum
1.00E-009
1.00E-010
1.00E-011
1.00E-012 0.00 0.20 0.40 0.60 0.80 1.00 Spectrum [GHz] 1.20 1.40 1.60 1.80 2.00
1 0.9 0.8
CDF
C D F
0.7 0.6 0.5 0.4
0.2
0.4
0.6
0.8
1 Frequency [GHz]
1.2
1.4
1.6
1.8
Power Integrity Investigation

Added two bulk 47 uF capacitors as specified by VRM manufacturer
Bare Board vs. Bulk Capacitors
Resonance @ 50 MHz Target impedance 800 mOhm to 667 MHz
Bare Board Board w/ Bulk Caps
Time Domain Schematic
J5_VCC
VCC_U41-2
VCC_U41-2
Driver
C58 Cpkg L59 Lpkg R60 0 Rpkg
pullup
Board
VCC_U41-44 VCC_U41-63 VCC_U41-84 VCC_U41-44 VCC_U41-63 VCC_U41-84
J5_VCC
logic_in enable
io
50
V35
out_of_in
R5
pulldown
VCC_U41-2 VCC_U41-21 VCC_U41-42
VCC_U41-2 VCC_U41-21 VCC_U41-42
x6
J5_VCC
800 Mbps data rate DDR2 IBIS driver into ideal termination used as load for PDS Package decoupling modeled using a capacitor w/ ESR, ESL
VRM
V33
DC=VCC 0
Switching Power Noise

Ansoft Corporation
2.40
Curve Info pk2pk
U41 Power
Bulk
Bulk Only
~11-12 ns period
2.20
V(VCC_U41-2) Transient V(VCC_U41-21) Transient V(VCC_U41-42) Transient V(VCC_U41-44) Transient V(VCC_U41-63) Transient
0.6787
0.6995
0.8191
2.00
0.7597
0.7882
Y 1 [V ]
1.80
V(VCC_U41-84) Transient
0.6858
1.60
1.40
Shaded area represents time domain violation of 1.8 V 10%

1.20 0.00 10.00 20.00 30.00 40.00 50.00 Time [ns] 60.00 70.00 80.00 90.00 100.00
3Meter FF
Choosing a Decoupling Capacitor To reduce the effect of a resonance, choose a capacitor with a low impedance at the resonant frequency
22 nF Capacitor
Board w/ Bulk Caps
Bulk vs. HF Capacitors 1
Target impedance 800 mOhm to 667 MHz
Board w/ Bulk Caps Board w/ HF Caps 1
No Resonance @ 50 MHz

Ansoft Corporation 2.40
Curve Info pk2pk
U41 Power
HF1
Bulk Only
V(VCC_U41-2) 0.6481 Transient V(VCC_U41-21) 0.6979 Transient V(VCC_U41-42) 0.8802 Transient V(VCC_U41-44) 0.9182 Transient V(VCC_U41-63) 0.6925 Transient
2.20
2.00
Y1 [V]
1.80
V(VCC_U41-84) 0.7319 Transient
1.60
1.40
1.20 0.00
Shaded area represents time domain violation of 1.8 V 10%

10.00 20.00 30.00 40.00 50.00 60.00 Time [ns] 70.00 80.00 90.00 100.00
3Meter FF
Extending Low Impedance 10 1.2 nF capacitors were added across the board to extend minimum high-frequency impedance 1.2 nF capacitor was chosen due to low impedance at 200 MHz 4 of these were located near U41
HF 1 vs. HF 2
New resonance @ 80 MHz
Board w/ HF Caps 1 Board w/ HF Caps 2
Impedance exceeds 800 mOhm @ 350 MHz
Ansoft Corporation
2.40
U41 Power
Curve Info V(VCC_U41-2) Transient pk2pk
HF2
0.2552
2.20
V(VCC_U41-21) Transient V(VCC_U41-42) Transient V(VCC_U41-44) Transient V(VCC_U41-63) Transient
0.2857
0.2930
2.00
0.4047
0.3083
Y1 [V]
1.80
0.3359
1.60
1.40
Shaded area represents time domain specification 1.8 V 10%

1.20 0.00 10.00 20.00 30.00 40.00 50.00 Time [ns] 60.00 70.00 80.00 90.00 100.00
Removing a Resonance Six 8 nF capacitors were added near U41 to cancel resonance at 80 MHz
Added capacitors
U41
HF 2 vs. HF 3
Board w/ HF Caps 2 Board w/ HF Caps 3
Impedance crosses 800 mOhm @ 500 No resonance @ 80 MHz MHz
Ansoft Corporation
2.40
U41 Power
Curve Info V(VCC_U41-2) Transient
Final
pk2pk
0.2416
2.20
Maximum peak to peak noise of 371 mV

2.00
0.2685
0.2660
0.3264
0.3709
Y1 [V]
1.80
0.3142
1.60
1.40

1.20 0.00 10.00 20.00 30.00 40.00 50.00 Time [ns] 60.00 70.00 80.00 90.00 100.00
Buried Capacitance
Due to parasitic inductance it is impossible to decouple the board with capacitors at frequencies greater than a few hundred MHz Using a thinner dielectric layer between power and ground planes introduces additional capacitance and reduces high frequency impedance
Capacitance of parallel plates:
A C = d
HF 3 vs. Buried Capacitance
Board w/ HF Caps 3 Target impedance specification met

Board w/ Buried Capacitance
Impedance crosses 800 mOhm @ >667 MHz
Specification Met!
Ansoft Corporation
2.40
U41 Power
Curve Info V(VCC_U41-2) Transient
Buried
pk2pk
2.20
Maximum peak to peak noise 273 mV 24% smaller than limit

0.2177
0.2295
0.2418
2.00
0.2549
0.2729
Y 1 [V ]
1.80
0.2169
1.60
Time-domain noise specification met

1.40

1.20 0.00 10.00 20.00 30.00 40.00 50.00 Time [ns] 60.00 70.00 80.00 90.00 100.00
3Meter FF
Conclusions SI / PI / EMI are all based on the same electromagnetic fundamentals and cannot be separated Impedance and resonant mode simulations connect the frequency domain to the spatial domain and allow selection of capacitor value and placement Frequency domain extractions are useful for quickly optimizing PDS designs, but time domain simulations are necessary to ensure compliance with device specs Using a single design environment can help reuse the same models for SI/PI/EMI simulations
Questions
Any Questions?
EMI Driven by Signal Integrity

Fundamentals of Coupled SI/PI/EMI Part 2 Aaron Edwards
SI + PI = EMI
SIGNAL INTEGRITY
Trend: Cost / Performance targets drive the integration of ICs, SoCs, and SiPs onto low cost printed circuit boards. Chip/Package/Board Co-design is required
EMC/EMI
Far Field - CPM2 - 1.27v Baseline
60.00 50.00 40.00 30.00 20.00 10.00 0.00 -10.00 -20.00 0.00
dBuV/m_
0.50
1.00
GHz
1.50
2.00
POWER INTEGRITY
Where is the problem? Intentional Signals

Focus on Clock and High Speed Signals
Stripline not necessarily better than Microstrip Examine Clock Harmonics filter if necessary
Differential signaling is a standard to improve signal-tonoise ratios, however, its use always leads to Common mode noise
Common Mode Conversion
SCD11=0.5*(S(1,1)-S(1,3)+S(3,1)-S(3,3)) SCD21=0.5*(S(2,1)-S(2,3)+S(4,1)-S(4,3))
Where is the problem? Unintentional Signaling Common mode will always exist
Common Mode noise is the main contributor to EMI
How? Through Crosstalk

Beware the low speed nets; use post-layout analysis to scan for unintended coupling Coupling may be direct, through intermediate metal or even from plane cavities
This presentation focuses on crosstalk, the primary SI contributor to EMI radiation
Crosstalk Definition and Sources Signal integrity examines the quality of transmitted waveforms through a physical interconnect; Traces, connectors, vias, etc Crosstalk is the coupling of energy from one current carrying conductor to another. It occurs when the electromagnetic fields from one conductor interferes with another conductor, thus changing its desired characteristics There are 2 main components to Crosstalk:
Mutual Inductance and Mutual Capacitance
How to calculate crosstalk Mutual Inductance

Mutual Inductance induces current from an aggressor line onto a victim line by the magnetic field.
The noise voltage that is injected onto the victim line can be calculated by 2 methods Method #1 Analytical Calculation Vnoise,Lm = Lm di/dt Method #2 Field Solution
How to calculate crosstalk Mutual Capacitance

Mutual Capacitance is the coupling between 2 conductors via the electric field.
The induced noise that shows up on the victim net can be calculated by 2 methods Method #1 Analytical Calculation Inoise,Cm = Cm dv/dt Method #2 Field Solution
Coupling Dictates Crosstalk Strength

Near and Far End Crosstalk
The magnitude of the Mutual Capacitive and Inductive Coupling will determine the amount of current induced on the victim net. The summation of these currents determine near and far end crosstalk
ICM ICM ILM
Inear = ICM + ILM Ifar = ICM - ILM

Analytical Crosstalk Calculations

Back of the envelope calculations can be used as a quick check:
Zo
Terminated Victim
Driven Line
Zo
Far End
Vinput LM CM A= + L C 4
TD
TD = X LC
B= Vinput X LC LM C M L C 2Tr
A B
Un-driven Line victim Zs

Driver
Near End
Zo
ZO =
L C
Tr
~Tr
Tr
Near - End Crosstalk [NEXT] = Vb Va Crosstalk Coefficient [kb] = Vb Va

Source signal Far End of Source Signal Near-end X-talk Far-end X-talk
Analytical Crosstalk Calculation Example

Vsource Vinput 1V 500mV 1in 50ohms 61.5ohm s 100ps 200ps
L /inch=
Trace Width Height Trace Separation Thickness Dk 13mil 10mil 7mil 2mil 3.55
8.55nH 2.39nH 2.26pF 0.389pF
2.39nH 8.55nH 0.389pF 2.26pF

TD
Trace Length Source Impedance Termination Impedance Risetime Delay Time
C/inch=
ZO =
L 8.55nH = = 61.5ohm C 2.26 pF

A B
Vinput LM C M 500mv 2.39nH 0.389 pF + = + A= = 56mV 4 4 8 . 55 nH 2 . 26 pF L C
TD = X LC = 1in 8.55nH * 2.26 pF = 0.139ns

B= Vinput X LC LM CM 500mV *1in 8.55nH * 2.26 pF = 2Tr C 2 *100 ps L
Tr ~Tr
Tr
2.39nH 0.389 pF 8.55nH 2.26 pF = 37 mV

Field Solution Crosstalk Example

Same example using Method #2 Field solutions
HFSS 2D Extractor SIwave
m2(A) = 57.4mV m1 (B) = -37.2mV m4-m3 (TD) = 0.1359ns
Parameterization Captures Trends Impact of Length and Spacing

Trace Length = 1,2,3,10in
Trace Spacing= 7, 12, 17, 22, 27mil As Length increases, Ifar accumulates As Trace Spacing increases, Inear decreases
As Trace Spacing increases, Ifar decreases

Parameterization Captures Trends
Crosstalk Cm Lm Trace Spacing

GND Plane Distance
Increase
Decrease
NE
FE
NE
FE
Dk Trace Width Under-etching
Good Coupling, when Xtalk is desired Differential Signaling
Why Differential Signaling?

When lines are tightly coupled, noise affects both lines. Thus at the receiver, the difference between the two lines remains constant Stray transient noise on the two conductors will selfcancel, which leads to a reduction of noise from the power supply Because differential signaling creates a known return path, signal quality will significantly improve in the presence of non-ideal ground return paths, or other discontinuities such as connectors, wirebonds, vias, etc..
Good Coupling Differential Signaling

Back of the envelope calculations of Differential and Common Mode Impedance can be used as a quick check Leven = L11 + L12 Lodd = L11 L12 Codd = C11 + C12 Ceven = C11 - C12 Lodd L11 L12 Leven L11 + L12 Z odd = = Z even = = Codd C11 +C12 Ceven C11 C12 Zdifferential = 2*Zodd Zcommon = ()*Zeven
Magnetic Field Magnetic Field
Electric Field
Electric Field
3D Crosstalk Needs Field Solution
2.2 inch total length of trace. 88 mil via transition
Peak Near-End Crosstalk: 25mV Peak Far-End Crosstalk: -21.8mV

Far-End Probe
Near-End Probe
Bad Coupling Via Transition
Peak Near-End Crosstalk: 13.1mV Peak Far-End Crosstalk: -14mV
2.2 inch total length of trace 88 mil via transition

Total length of parallel via routing is 4% of the total length. Yet the Near-End Crosstalk only reduces by 48%. The Far-End Crosstalk only reduces by 36%
Near-End Probe
Far-End Probe
Bad Coupling Via Transition

Added Ground Vias
Peak Near-End Crosstalk: 19mV 10.3mV Peak Far-End Crosstalk: -20mV -10.9mV
Total length of parallel via routing is 4% of the total length. Yet the Near-End Crosstalk only reduces by 24%. The Far-End Crosstalk only reduces by 8%
Near-End Probe
Far-End Probe
Chip/Package/Board Co-Design Case #1
Signal Integrity
Power Integrity
Capturing the Complete System Ansoft EMI Design Flow
S.O.C. Database
CPM
Package Database
PCB Database
S-Parameters SIwave
Nexxim Designer
FrequencyDomain Voltages
Resonance Analysis Impedance Analysis Near field plots Far field plots
Package and Board Models Case #1
Package has been merged onto board Coupling between the bondwires, leadframe, and board are simulated
Apaches Chip Power Model

SIwave Full-Wave Package/PCB Model
CPM
VDD
I/O Interface
VDDQ
Chip Power Model
Package PCB
Input Level Buffer Buffer Shifter
SIG
VSS
Designer & Nexxim
Terminations
SIwave Model CPM Model
Drive VDDs with CPM Capture coupled highfrequency noise Run Near/Far-Field Simulations using transient results
Time and Frequency Domain Results
Transient Power Noise

60.00 50.00 40.00 30.00 20.00 10.00 0.00 -10.00 -20.00 0
Far Field3m - 1.27VFar - No Decaps - Baseline Fields
dBuV/m__
0.5
1
G H z
1.5
Near Fields at 1GHz
Baseline
1.27 V w/ Decap
1.1 V
Chip/Package/Board Co-Design Case #2
Signal Integrity
Power Integrity
Ansoft Virtual Chamber
Driver settings
27
Solving the Field Solution Using Time Domain Information

FFT of Transient Data Near/Far Fields Computed in SIwave and HFSS
Time
28
Frequency
Radiation
Agreement captured in simulation

10 M Measurement
ONLY PCB Spectrum
SIwave
Excessive Common Mode coming from Driver

Transient Waveform
Glitch seen in falling waveform; this will create Common Mode Noise
Original Driver
Ideal Driver
Common Mode Spectrum

Intentional Signaling contributing to EMI

Original Driver Ideal Driver Even Harmonics are now absent but EMI is still high Problem is not just common mode
Adding a filter to reduce problematic higher harmonics
Pi Filter added to driver output to squelch higher harmonics of 13.56 MHz clock
Component values optimized in Designer

Reduced Common Mode after filtering

Transient Waveform
Ideal Driver
Filtered Driver Signal integrity still OK but high frequency spectrum is reduced
Common Mode Spectrum

EMI from Intentional and Unintentional Signaling suppressed

Original Driver Filtered Driver EMI is now sufficiently suppressed
Conclusions Crosstalk is major concern for SI

Need to examine all relevant coupling: vias, traces, etc. Simulation can help determine acceptable levels of coupling
Target impedance helps ensure good PI

Target impedance is defined in Frequency domain Need to verify ripple in time domain
EMC is comprised of good PI and SI

Poor plane design can spread common mode noise Unintentional coupling is a big source of radiated emissions

EMI Driven by PI

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EMI Driven by PI

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EMI Driven by PI

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

Power Integrity design methodology to reduce EMI

2nd Presentation on EMI Driven by SI

Case studies that show perils of crosstalk in real world designs

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

SI/PI/EMI Design Overview

EMI/EMC Signal Integrity

Pwr Noise Signal

Signal Integrity Power Integrity

Impedance - Crosstalk - Reflection - Termination - Dielectric Losses

Ansoft, LLC Proprietary

Three Basic Elements of EMC

Low, Middle & High Frequency

Low & Middle Frequency LC Resonance

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

Loop Mode & Common Mode Noise

A Driver & Receiver

by AC Analysis of Q3D Extractor

Common mode current

131.6 10 -16 (f 2 AI) sin E= r

r : distance A : area of the loop

I Illustration of a loop antenna

I Illustration of a dipole antenna

EMC Design Flow

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

EMC Design Flow

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

EMC Design Flow

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

EMC Design Flow

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

EMC Design Flow

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

Board Imported from Layout

Measuring impedance at the six VCC pins on U41

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

PDS Design Flow

EM extraction of impedance for critical devices

Determine frequencies of specification violations

Simulate in time domain to check for compliance

Choose capacitor or geometric change to address violations

Alter design according to findings

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

Frequency Domain PDS Targets

Switching Power Supply

Electrolytic Bulk Capacitors

2008 Ansoft, LLC All rights reserved.

Ansoft, LLC Proprietary

2008 Ansoft, LLC All rights reserved.