Over-Voltage Problems of Diode-Clamped Converters During Switchings

Over-voltage problems of diode-clamped converters during switchings
BARTHOLOMEUS Patrick

P. Bartholomes, P. Le Moigne, J.B. Akoe Mba Laboratoire dElectrotechnique et dElectronique de Puissance (L2EP) Ecole Centrale de Lille, B.P. 48, Cit Scientifique 59651 VILLENEUVE DASCQ Cedex FRANCE. Tel : +33 320 33 53 88, Fax : +33 320 33 54 54. e-mail : patrick.bartholomeus@ec-lille.fr
Keywords Multilevel converters, Abstract -
Semiconductor devices, Converter control
This paper presents a switching cell for high voltage applications based on a generalized diode-clamped converter. The concept and the working principle are presented. Thanks to the association of a low power diode network and a particular switching sequence, it allows for a dynamic equalization of the transistor voltages. A prototype (1000V/20A) has been developed in order to study the dynamic behaviour during the transistor switching. Experimental results highlight several over-voltage problems during the ON-Switching of the transistors. These problems have been analyzed. Simulations and experimentations have allowed us to determine the origin of these overvoltages.
1. Introduction
The development of more and more powerful converters implies an increase of the current and the voltage of the power electronic switches. But there are technological limitations: the 6500V IGBT, which had been announced for 2000 has been available on the market with two years of delay because of some problems of reliability. Furthermore the future electrical networks (decentralized generation, deregulation of the electricity sector, etc.) will need more and more devices like High Voltage DC line transmission (HVDC), Static VAR Compensators (SVC), Flexible AC Transmission Systems (FACTS) and other new systems [1]. Some solutions based on voltage source converters are already developed [2-3]. In the future, these new devices (small-to-medium power range) will certainly take the place of the old devices based on thyristors because of their best dynamic response, harmonics quality and their smaller size. Nowadays 100MVA products, which can be connected to a 10kV electrical network, are available [4]. For the direct connection of a 100MVA Voltage source inverter to a 10kV electrical network, a 20kV DC link voltage is necessary. To obtain these characteristics, transistors have to be connected in series. For this, two main solutions may be used : multilevel converters converters with direct series connection of transistors The first solution allows for the limitation of the transistor voltage and can produce a high quality voltage waveform with high frequency harmonics. But the control principle is more complex and often leads to more expensive solutions with more sensors and more power components. The second solution based on direct series connections of switches produces a high quality voltage waveform but leads to simpler and so more economic solutions, well adapted for industrial and economic constraints. Today, solutions using simple series connections of transistors are developed for high voltage applications. The only exception concerns the Neutral Point Clamped converter which benefits of the advantages of both solutions : it requires only a few power diodes to share the voltages between transistors and works in multilevel mode.
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In fact, the simple series connection of transistors is not sufficient according to the scattering of component characteristics. This imperfection involves imbalance between transistor voltages. Two main methods may be applied to solve this problem: the active control of the switching by the driver circuit [5-6]. the use of snubbers [7], of clamping circuit [8-9] or both [10],
The active gate control during commutations seems interesting but involves an increase of losses and a more complex gate driver circuit. The use of clamping circuits may be a good solution if it leads to a simple circuit which does not slow down too much the commutations and does not reduce the efficiency of the converter. This article presents a solution somewhere in between multilevel converters and direct series connections : a generalized diode-clamped cell using its diode network as a clamping circuit.
2. The generalized diode-clamped cell

The diode-clamped cell (also named Multi Point Clamped Converter, or MPC) is a multilevel cell, generalization to more than 3 levels of the Neutral Point Clamped converter (figure 1.a). In order to limit the voltages of the different clamping diodes, the diodes can also be replaced by a diode network (figure 1.b). In this case, a generalized diode-clamped cell is obtained with the same function as the previous one [11-12].
Figure 1: five-level version of the diode-clamped cell
These cells, used in converters, have a well-known drawback when working in multi-level mode : imbalance between DC link capacitors appears naturally when the converter transits active power [13]. A few solutions have been found, but are very complex to develop and are not industrially suitable nowadays [14-15]. But if this cell is not used in a multilevel mode, this drawback disappears. In the present paper, a simple control solution is proposed. It is based on a compromise : if this kind of converter can not be used in order to generate a high number of voltage levels, a reduction of this number to 3 (as NPC leg) or 2 (as classical leg) allows to obtain an equivalent conventional Source Voltage Cell or NPC Cell for high voltage applications. The harmonic performances are reduced but the control is simplified. In this case, the diodes are not used to clamp the output voltage to intermediate values of the voltage source (except the neutral point in the case of NPC converter working) but to limit the voltage stress of each component during switchings. This solution also allows for a reduction of the number of power semi-conductors. Indeed, high power diodes are not necessary and all of them can be replaced by low power clamping diodes for the two-level operation. In the case of a three-level
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mode, diodes connected to the middle point of the DC bus voltage have to be sized according to the rated current. The study is limited in the article to the two-level operation in the case of 8 transistors in series. It is representative of the more interesting solutions using 4.N transistors, which might well work in a 2 or a 3-level mode.
2.1 Assets of the proposed solution

Before describing in detail the specific operation of this cell, it is important to precise its assets apart from the fact that it has no limitation in voltage increase. Working in a two-level mode (or in a three-level mode), this cell uses the same process and the control circuits developed for classical inverter legs (or N.P.C. legs). An interface circuit only has to be developed and slotted between the PWM signal output and the transistor drivers. It may be integrated very easily on the PWM modulator if this one is implemented on an ASIC or a Programmable logic Device as a FPGA. Diodes of the clamping network and transistors have the same voltage characteristics but not the same current ones, as diodes conduct during switching periods only. Thus this network becomes very cheap and compact. Also the length of the switch net which is mainly linked to the size of capacitors as in a classical leg (length transistorcapacitor-transistor) will not introduce larger over-voltages. This problem will naturally increase with N, which modifies the whole length of the transistor modules. Finally, this solution is not sensitive to the component scattering.
2.2 Switching control sequence

A particular switching sequence must be applied in order to ensure a correct clamping of the transistor voltages in a safe way for each commutation. Figure 2 presents this sequence which is based on a shift of the transistor control signals similar to the NPC cell control [16-17]. The rule of the interface card slotted between the PWM signal and drivers is to introduce: a dead time TA between Tk and Tk+4 to avoid short-circuits as in classical legs a delay time TB to cadence the switching process between transistor pairs Tk/Tk+4 and Tk+1/Tk+5
ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF ON OFF
T5 T1 T6 T2 T7 T3 T8 T4
TA TA TA TB TA TB TB TA
TA
TB
TB
TA
TB
TA
Figure 2: switching sequence of the transistors
The only constraint is the necessity to have a PWM signal larger than the switching sequence Tmin= 4.(TA+TB). Acting in this way assures a theoretical voltage sharing between transistors.
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2.3 Influence of the switching sequence on the output voltage signal

The introduction of the delays TA and TB in the switching process may penalize this system, compared with a classical device with direct series connections and simultaneous control of the transistors. The figure 3 illustrates the comparison of these two solutions. For the classical one, the output voltage depends on the current polarity during the dead-times, so an error appears, error which may introduce a non-linearity which may disturb the converter control. For the proposed solution, dead times are introduced between the switchings of each complementary switch, so this process is longer and introduce an averaged delay (Td = 2.TA+ 3/2.TB) between the initial control signal and the output voltage. This problem involves a limitation of the minimum and maximum value of the duty cycle which can be applied :
1 Tmin > > Tmin T T

where Tmin = 4.(Ta+Tb) and T is the period of the PWM signal.
(1)
In regard to the error introduced by the dead times, the dashed zones on figure 3 represent the zones of loss of control involved by the dead time effect and the uncertainty of the current polarity. The surface of these zones are equivalent in both cases. So the global voltage error seems to be the same for the two solutions. In fact we think, on this point of view, that the proposed solution is the better one. Indeed, in the case of direct series connections, this process has to be slowed down in order to limit the over-voltages during the switchings. This leads to longer dead times and so more numerous errors. For the diode clamped converter, the transistors switch without any constraint and so the dead times are minimized.
control signal
t
output voltage
zone of loss of control involved by the deadtime effect
(a) synchronous control

control sign al
averaged delay output v oltage

zone of loss of control involved by the deadtime effect
averaged delay
(b) sequenced control
Figure 3: effect of TA and TB on the output voltage signal
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We also think that the proposed solution have advantages for the generation of highfrequency switchings on one hand, and the limitation of voltage stresses in the windings of the electrical machines and transformers [18] on the other hand. A more detailed study with experimental results should be engaged in order to synthesize the advantages and drawbacks of each kind of solutions.
3. Switching characteristics
The switching behaviour of the transistors has been studied, simulated and experimented in order to verify the capability of such a cell.
3.1. Simplified model

By considering the components (transistors and diodes) as perfect and identical, transistor voltage variations may be represented during the switching sequence. The figure n4 represents these voltages for a positive output current. This simplified model allows us to predict the presence of intermediate voltage steps during the switching, linked to the equal repartition of the partial input voltage k.V/4 applied on k or (k+1) transistors. This approach confirms the theoretical limitation of V/4 supposed on each transistor during each commutation.
V 4
VT1
V 4 3V 16 2V 12 V 8
VT5
VT5
0 V 4
VT1
t
0 V 4 3V 16 2V 12 V 8
VT2
VT6
VT6
0 V 4
VT2
t
0 V 4 3V 16 2V 12 V 8
VT3
VT 7
VT 7
0 V 4
VT3
t
0 V 4 3V 16 2V 12 V 8
VT4
VT8
VT8
0
VT4
t
0
Figure 4 : simulations with the simplified model 3.2. Experimental results In order to study the switching behavior and to check the control principle of this kind of cell, a reduced scale prototype (1000V/20A) has been developed (figure n 5 ). It is composed of 8 series connected IGBT (600V/50A) and of a clamping diode network (600V/4A). The DC bus is supplied via transformers and diode rectifiers. This solution assures the voltage balancing of each part of the DC bus for the tests. This supply must be simplified for industrial applications where small dissipative resistances must be sufficient for this balancing function. In order to develop a polyvalent prototype, the control sequence has been implemented in a Complex Programmable Logic Device (CPLD). It allows for the control of the duty cycle, the switching sequences of the transistor (TA ,TB), and the transistor protection. Furthermore, it is possible to choose the 3 or the 2-level operation. The load parameters are : L = 40mH, R= 8.
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The DC bus is constituted of electrochemical capacitors (2200F/350V) and polypropylene capacitors (220nF). The switching frequency is equal to 10 KHz.
T8 T7 T6
N
T5 i
T4 T3 T2 T1
Figure 5 : Experimental configuration The durations TA and TB have been chosen equal to 500ns and 1s respectively, the DC bus voltage is equal to 1000V and the load current I is positive and equal to 20A.
Figure 6.a: VT1, VT2, VT3 and VT4 during the switching-OFF
Figure 6.c: VT1, VT2, VT3 and VT4 during the switching-ON
Figure 6.b: VT5, VT6, VT7 and VT8 during the switching-OFF
Figure 6.d: VT5, VT6, VT7 and VT8 during the switching-ON
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The figures n6 shows the real behavior of the transistor voltage during the switchings. These waveforms confirm the equal sharing of the voltage between the transistors during the static phases and the interest of this cell. But it also reveals the presence of over-voltages on transistors during the ON-switching (with a positive current load). These over-voltages represent 40% of the normal voltage and have about the same value as classical over-voltages (OFF-switching). Also, this problem should be taken into account in the transistor safety margin but stresses the component at each switching and increases its switching losses. Then, these over-voltages have to be analyzed and solutions may be implemented in order to reduce their amplitude and duration.
3.3. Over-voltage experimental study

As over-voltages observed in experimentation were not predicted by simulation, other experimental investigations have been realized in order to find the origin of this phenomenon and parameters modifying this comportment. Over-voltages are not linked to an imbalance on the DC bus. If the load current sign is changed, the waveforms observed are the same as mentioned in fig. n6 by exchanging T1-T2-T3-T4 with T5-T6-T7-T8. This implies that the over-voltage is not linked to the scattering of the components characteristics. The level of over-voltage (in %) is the same whatever the value of the load current and the DC bus voltage. The increase of the parasitic capacitance of the diode network (by adding a 100pF capacitor in parallel) involves a small decrease of the over-voltage. The suppression of the network in the diode clamping circuit ( using cell fig. n1a, instead of cell fig. n1b) does not modify the voltage waveform. Both cells have the same switching behavior. The only interest of the network is to share naturally the voltage between diodes connected in series.
Then, it appears that the over-voltages are not directly created by the power circuit but certainly by parasitic capacitance couplings.
3.4. Influence of the capacitive coupling

In fact, the power circuit is coupled to the control card and to the heatsink with parasitic capacitors which may involve a coupling action on the switching of transistors connected in series. This assumption has been taken into account in a new simplified model which introduces an equivalent capacitance on each gate circuit (figure n 7). The aim of this part is to display the importance of these capacitive components during the switching sequence. Different simulations have been done and figures 8 show the results obtained with an equivalent capacitance of about 400pF. As figures 6 and 8 have similar waveforms, it appears clearly that a capacitive effect causes the switching over-voltages. Furthermore the position of the parasitic capacitors does not modify the results. Indeed, several simulations have been done where the capacitors have been connected to the gate, emitter or collector with no change. Our aim has then been the identification of the capacitive effects in the experimental prototype, to find the main influent parameters in order to reduce the over-voltages. Measures and simulations have been done to characterize the real capacitive effects appearing in the test bench. Measures on the IGBT modules with an impedance analyzer have revealed the presence of a 400pF global capacitance between each electrical connection and the bed plate of the power module in contact with the heatsink. One of the next work is to determine the contribution of each module electrode on the parasitic coupling and to improve the model of coupling. This result confirms that the studied cell seems to be a good solution for the series connection of transistors ; the over-voltages observed are caused by a phenomenon which is present whatever the
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proposed solution of series connections. The influence of this problem of capacitive effect must be treated carefully for each solution.
Figure 7: simplified model with equivalent coupling capacitor
Figure 8.a : VT1, VT2, VT3 and VT4 during the ON-switching
Figure 8.b : VT5, VT6, VT7 and VT8 during the ON-switching
3.5. Experimentations on the heatsink potential

In all the results and experiments mentioned above, the heatsink was isolated from the ground and from the cell. After an identification of the coupling effect between the heatsink and the power modules, it appears clearly that this heatsink has to be connected to an active part of the system in order to evacuate the capacitive currents out of the cell. A few tests have been done with a DC bus value of 600V, with different configurations for the heatsink potential: No connection, case similar to the previous one, but with V= 600V (figure 9) Heatsink connected to the ground of the network (figure 10) Heatsink connected to the middle point (point n3 on fig 1.b) of the DC bus (figure 11) These experimental results confirm the influence of the capacitive effect on the over-voltage. Different connections of the heatsink greatly influence the over-voltage waveforms by modifying the HF equivalent circuit. Its connection to the ground presents a low reduction effect with oscillations linked to the ground impedance.
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The connection of the heatsink to the middle point of the DC bus significantly reduces the overvoltage ( a few % of the normal voltage). In this case, the over-voltage step becomes not constraining and do not involve stress on the switches. So this type of solution may be used to solve easily the over-voltage problems encountered with the capacitive effect of the integrated power modules.
1.14427m 650.0
1.14600m
1.14800m
1.15000m
1.15200m
1.15426m 650.0
1.14427m
1.14600m
1.14800m
1.15000m
1.15200m
1.15426m
500.0
VT8 +450V
500.0
500.0
VT8 +450V
500.0
333.3
VT7 + 300V
333.3
333.3
VT7 + 300V
333.3
166.7
VT6 + 150V
166.7
166.7
VT6 + 150V
166.7
VT5
-20.0 1.14427m 1.14600m 1.14800m 1.15000m 1.15200m -20.0 1.15426m -20.0 1.14427m 1.14600m 1.14800m 1.15000m
VT5
1.15200m -20.0 1.15426m
Figure 9 : VT5, VT6, VT7 and VT8 during the ON-switching with heatsink isolated
Figure 10 : VT5, VT6, VT7 and VT8 during the ON-switching with heatsink connected to the ground
1.15000m 1.15200m 1.15426m
1.14427m 650.0
1.14600m
1.14800m
500.0
VT8 +450V
500.0
333.3
VT7 + 300V
333.3
166.7
VT6 + 150V
166.7
VT5
-20.0 1.14427m 1.14600m 1.14800m 1.15000m 1.15200m -20.0 1.15426m
Figure 11 : VT5, VT6, VT7 and VT8 during the ON-switching with heatsink connected to the middle point of the DC bus
4. Conclusion
The first conclusion of this article is that the proposed control of the generalized diodeclamped cell is a simple and efficient solution for the increase of cell voltage. Only a few low power diodes and a very simple sequencer are needed. Furthermore no tuning, no components selection, have to be completed for this solution because of its insensitivity to the component scattering. The second conclusion is that the switching behavior greatly depends on the parasitic capacitive coupling of the device ; even the mechanical design can be influent. This problem has to be taken into account with care during the conception of high voltage converters in order to optimize the safety margin of each transistor. Indeed, an important parameter for such applications is the minimization of the conducting power losses which is obtained in this case by the reduction of the number of transistors connected in series according to the natural voltage sharing of this cell. Let us note that the effect of the parasitic capacitive coupling will be more and more important with the increase of the voltage range of the converters.
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These over-voltage problems have been encountered because of the technological choices during the design of the prototype. For the design of high voltage converters, other technological solutions, perhaps completely different, should be selected. For example the use of only one heatsink for all the cell is certainly not the better solution, as well as the use of IGBT modules packaging. As regards the perspectives of this work, it is possible to use simulations to compare more precisely this proposed solution of series connections of transistors to other ones encountered in the literature, in terms of efficiency and reliability.
References
[1]. M. CHAMIA, HVDC - A major option for the electricity networks of the 21st century, IEEE WPM 1999 (can be found on the ABB site www.abb.com in PDF file). [2]. G. ASPLUND, K. ERIKSSON, H. JIANG, J. LINDBERG, R. PALSSON et K. SVENSSON, DC transmission based on voltage source converters" Cigr Conference Paris, 1998 (can be found on the ABB site www.abb.com in PDF file). [3]. R. GRNBAUM, B. HALVARSSON, A. WILK-WILCZYNSKI, FACTS and HDVC light for power system interconnection, Power Delivery Conference Madrid 1999 (can be found on the ABB site www.abb.com in PDF file). [4]. A. S. COOK, M. WYCKMANS, L. WEIMERS et K. ERIKSSON, "Network interconnection using HDVC light " Distribution 2000 Conference, Brisbane (can be found on the ABB site www.abb.com in PDF file). [5]. GAETANO BELVERDE, AGOSTINO GALLUZZO, MAURIZIO MELITO, SALVATORE MUSUMECI, and ANGELO RACITI, Snubberless Voltage Sharing of Series-Connected Insulated-Gate Devices by a Novel Gate Control Strategy in IEEE Trans. Power Electron., vol. 16, N1, pp. 132141, January 2001. [6]. C. GERSTER, P. HOFER, N. KARRER, Gate-control strategies for snubberless operation of series connected IGBTs, in IEEE Power Electronic Specialists Conference, PESC 1996, Vol 2 pp. 17391742. [7]. J. HOLTZ, R. RSNER, Gate Drive Power Recovery and Regenerative Snubber Scheme for SeriesConnected GTOs in High Voltage Inverters, in IEEE IAS Conference, Phoenix, 1999. [8]. J. M. BODSON, J. BOU SAADA, A. COLASSE, P. COLIGNON, L. DELPORT, J.-E. MASSELUS, P. MATHYS, and M. OSEE, Study of direct series connection of IGBT for a 3 kV chopper, in Proc EPE 99, Lausanne, Switzerland, 1999. [9]. V. CHITTA, S. HONG, and D. A. TORREY, Series connection of IGBTs with active voltage balancing, IEEE Trans. Ind. Applicat., vol. 35, pp. 917923, July/Aug. 1999. [10]. J. SIGG, M. BRUCKMANN, P. TURKES, The series connections of IGBTs investigated by experiments and simulation, in IEEE Power Electronic Specialists Conference, PESC 1996, Vol 2 pp. 17601765. [11]. P. LE MOIGNE, P. BARTHOLOMEUS et C. ROMBAUT, "Structures multiniveaux source de tension continue unique", Revue internationale de Gnie Electrique, Vol 2, N3-1999, pages 335-357. [12]. YUAN X., BARBI I, Fundamentals of a new diode clamping multilevel inverter, IEEE Transactions on Power Electronics, Vol 15 NO 4 Juillet 2000. Pages 711 718. [13]. MENZIES R.W., STEIMER P., STEINKE J.K., Five-level GTO inverters for large induction motor drives IEEE Transactions on Industry Applications, Vol. IA-30, N4, (1994) 938-943. [14]. F. Z. PENG, J. S. LAI and J. VANCOEVERING, "A multilevel voltage-source converter system with balanced DC voltages", IEEE APEC Conference, 1995, 1144-1150. [15]. Y. CHEN, B. MWINYIWIWA, Z. WOLANSKI and B.T. OOI, "Unified power flow controller (UPFC) based on chopper stabilized diode-clamped multilevel converters", IEEE Transactions on Power Electronics, Vol. 15, N2, (2000) 285-267. [16]. P. BARTHOLOMEUS, P. LE MOIGNE, "Etude du comportement dynamique d'une cellule de commutation haute tension rpartiteur lectronique" EPF 2000, Lille. [17]. P. BARTHOLOMEUS, P. LE MOIGNE, " Switching behaviour of a generalized diode-clamped converter " in Proc EPE 2001 conference, GRAZ, August 2001. [18]. S. LEE, K. NAM, "An Overvoltage Suppression Scheme for AC Motor Drives Using a Half DC-Link Voltage Level at Each PWM Transition", IEEE Transactions on Industrial Electronics, Vol. 49, N 3, June 2002.
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