JOURNAL OF APPLIED PHYSICS

VOLUME 91, NUMBER 3

1 FEBRUARY 2002

Relationship between channel mobility and interface state density in SiC metaloxidesemiconductor eld-effect transistor
Shinsuke Harada,a) Ryoji Kosugi, Junji Senzaki, Won-Ju Cho, Kenji Fukuda, and Kazuo Arai
Ultra-Low-Loss Power Device Technologies Research Body and National Institute of Advanced Industrial Science and Technology, Tsukuba Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

Seiji Suzuki
Ultra-Low-Loss Power Device Technologies Research Body and R&D Association for Future Electron Devices, Tsukuba Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan

Received 23 April 2001; accepted for publication 24 October 2001 Temperature dependence of threshold voltage in n-channel SiC metaloxidesemiconductor eld-effect transistors MOSFETs was studied. Linear relation was observed between the threshold voltage shift when the temperature varies from 150 to 150 C and the number of the interface states present within the energy range of 0.20.4 eV from the conduction band edge energy E c . This relationship revealed that the interface state prole near E c in n-channel SiC MOSFETs can be represented by that in n-type SiC MOS capacitors. The relationship between the channel mobility and the interface state prole also suggested that the interface states within the energy range of 0.20.4 eV from E c have little inuence on the channel mobility. 2002 American Institute of Physics. DOI: 10.1063/1.1428085

INTRODUCTION

4HSiC metaloxidesemiconductor eld-effect transistor MOSFET is a promising candidate for high power electronic switching devices. However, some problems still exist in order to achieve high quality 4HSiC MOSFETs. The most important problem is the low channel mobility of electrons in the surface inversion layer. n-channel 4HSiC MOSFETs with a thermally grown gate oxide have a channel mobility of less than 10 cm2/V s, which is much lower than that in 6HSiC.1,2 The channel mobility may be lowered by several parameters such as interface trap, xed charge, surface roughness, and effective eld normal to the interface. Within these parameters, the interface trap has a signicant inuence on the channel mobility in 4HSiC MOSFETs. It drastically reduces the electrons in the inversion layer, and trapped electrons act as a scattering center of the electrons.3,4 It is believed that the high density of interface trap D it near the conduction band edge energy E c causes the low channel mobility in 4HSiC MOSFETs.2 6 Saks et al. have reported the measurements of D it near both band edges in 4H and 6HSiC MOSFETs using the GrayBrown technique, and have shown that D it near E c is much higher in 4H compared to 6HSiC MOSFETs.7 Generally, the D it can be simply evaluated using the MOS capacitor. In the case of the SiC MOS structure, since the D it in the upper half of the band gap cannot be measured from the p-type MOS capacitors due to the wide band gap, the n-type MOS capacitors are used to measure the D it near E c . The D it near E c in the n-type MOS capacitor is affected by the oxidation conditions of the gate oxide.8,9 However, the channel mobility in the
a

n-channel MOSFET does not exhibit an obvious correlation with the D it measured in the n-type MOS capacitor.10 It is not clear that n- and p-type MOS interfaces have the same D it prole, since the dopants are different in n- and p-type SiC. In order to characterize the MOS interface in the n-channel MOSFET using the n-type MOS capacitor, it is necessary to clarify whether the n-channel MOSFET and the n-type MOS capacitor have the same D it prole. For the SiC MOSFET, threshold voltage for the strong inversion V th drastically varies with temperature due to the large number of D it near E c . 6,11 The D it can be roughly estimated from the variation of V th with temperature. Therefore, we expect that a comparison of the temperature dependence of the V th and the D it extracted from the n-type MOS capacitors will clarify whether the D it prole in the n-type MOS capacitor can represent that in the n-channel MOSFET.
EXPERIMENTAL PROCEDURE

Author to whom correspondence should be addressed; electronic mail: s-harada@aist.go.jp 1568

4H and 6HSiC 0001 wafers used in this study were purchased from Cree Research Inc. Doping concentration ( N A N D ) of the epitaxial layers was about 5 1015 cm 3 . MOSFETs were fabricated on p-type wafers. Length and width ( L / W ) of the channel region were 10/50 and 200/200 m. Source and drain regions were formed by phosphorous ion implantation at 500 C with a total dose of 7 1015 cm 2 , followed by annealing at 1500 C for 5 min in Ar ambient. Surface cleaning before oxidation was done by RCA cleaning, sacricial oxidation, and HF dip. The gate oxide was grown by thermal oxidation in dry or wet O2 atmosphere at 1200 C, and following Ar annealing for 30 min, resulted in a thickness of 40 nm. Gate and source/ drain contacts were formed by aluminum deposition. The V th of MOSFETs were measured in the temperature range be 2002 American Institute of Physics

0021-8979/2002/91(3)/1568/4/$19.00

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FIG. 1. Energy distribution of interface state density D it near the conduction band edge energy E c in n-type 4HSiC open symbols and 6HSiC full symbols MOS capacitors. The gate oxides are grown by dry or wet oxidation.

FIG. 2. Field effect mobility FE as a function of gate voltage in 4H and 6HSiC MOSFETs. Solid and dashed lines represent FE in dry and wet oxidation samples, respectively.

tween 150 and 150 C. MOS capacitors were fabricated on n-type wafers. The oxidation conditions of the gate oxide were the same as those for the MOSFETs. Combined high low frequency capacitancevoltage measurements were performed to evaluate the D it near E c in n-type MOS capacitors using the Keithley KI-82 system. The step voltage and the delay time for the measurement were 50 mV and 10 s, respectively.
RESULTS AND DISCUSSION

Figure 1 shows the D it proles near E c obtained from the n-type 4H and 6HSiC MOS capacitors with a gate oxide formed in dry or wet atmosphere. The D it proles are apparently different in these four samples. The SiC/SiO2 interfaces of 4HSiC have a higher D it at the shallow energy level than those of 6HSiC, while the SiC/SiO2 interfaces of wet oxidation samples have a higher D it at the deep energy level than those of the dry oxidation samples. It is conrmed that the D it proles measured in the n-type SiC MOS capacitors are affected by the polytypes and the oxidation methods. Our previous study has shown that the peak value of the eld effect FE mobility FE is almost independent of these oxidation methods dry, wet.10 In order to examine the inuence of the polytypes and gate oxidation methods in detail, gate voltage dependence of the FE was measured. Figure 2 shows FE as a function of gate voltage V G in 4H and 6HSiC MOSFETs. The V G for the measurement ranges from 0 to 30 V. Solid and dashed lines represent the characteristics of dry and wet oxidation samples, respectively. The FE was calculated from the following formula at the drain voltage V D of 0.1 V:

4H and 6HSiC MOSFETs, the FE in the 6HSiC MOSFET is much higher than that in the 4HSiC MOSFET. Furthermore, regarding the gate voltage dependence of the FE , apparently different behaviors are observed. In the 6HSiC MOSFET, two peaks exist around the gate voltages of 10 and 25 V, suggesting the existence of two V th . On the other hand, comparing the FE in dry and wet oxidation samples, they exhibit a quite similar behavior. In Fig. 3, the peak values of the FE are compared with the number of interface state N it in the n-type MOS capacitor. The N it is the summation of the D it within the energy range of 0.20.4 eV from E c in Fig. 1. 6HSiC MOSFETs have a higher FE and lower N it than 4HSiC MOSFETs, suggesting that polytype dependence of the FE can be ex-

FE

ID 1 L , V G C oxV D W

where I D is the drain current and C ox is the oxide capacitance extracted from MOS capacitors. Comparing the FE in

FIG. 3. Relationship between the number of interface state N it near E c in n-type MOS capacitors and the FE in the MOSFETs. The N it is the summation of interface state density D it within the energy range of 0.20.4 eV from E c .

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plained by the D it in this energy range. In contrast, dry and wet oxidation samples in the same polytype exhibit different values of N it , although their FEs are almost same. Thus, the lower N it within the energy range of 0.20.4 eV from E c in the n-type MOS capacitors does not always bring about the higher FE in the n-channel MOSFET. In order to justify the use of the n-type MOS capacitors to measure the D it proles near E c , the temperature dependence of the V th was measured and compared with the D it extracted from the n-type MOS capacitors. The theoretical threshold voltages V cal were calculated from the following formula, neglecting the contribution of charges in the interface traps and the xed charges: V cal V FB 2 B 2 2 S 0 N A 2 B C ox 2

with a bulk Fermi potential ( B ) B KT P ln , q ni 3

where V FB is the atband voltage determined from the difference between the work functions of the gate metal and the semiconductor, P is the free hole concentration,12 n i is the intrinsic carrier density, and N A is the acceptor concentration. When the charges in the interface states and the xed charges are included, the V th is described as follows: V th V cal Q it Q f , C ox 4

where Q it and Q f are charges in the interface states and the xed charges, respectively. The surface Fermi potential at V G V th ( S 2 B ) varies with temperature as can be seen in Eq. 3. Therefore, if Q f is assumed to be constant with temperature, the N it within the energy range where the surface Fermi level sweeps with temperature is described as follows: V th V cal C ox , N it q 5

FIG. 4. Temperature dependence of threshold voltage V th for: a 4H and b 6HSiC MOSFETs. In a V th of Si MOSFET is also shown for comparison. Lines represent the theoretical threshold voltage V cal .

where ( V th V cal) is the variation of ( V th V cal) with the temperature. Figure 4a shows the temperature dependence of V th in 4HSiC MOSFETs in the temperature range between 150 and 150 C. The V th of Si MOSFET is also shown in the same gure for comparison. The V th was extracted from the I D V G plot at V D 10 V in the saturation region. The V th of Si MOSFET is in good agreement with the V cal , indicating that the charges in the interface traps and xed charges are mostly negligible. In contrast, the V th of 4HSiC MOSFETs are considerably higher than the V cal at lower temperatures, and drastically decreases with increasing temperature. Comparing dry and wet oxidation samples, higher V th is obtained from the wet oxidation sample. As shown in Fig. 4b, the temperature dependence of V th in 6HSiC MOSFETs is similar to that in 4HSiC MOSFET. The V th of both dry and wet oxidation samples decrease with increasing temperature and higher values are obtained from

the wet oxidation sample. These values and their variations with temperature are somewhat smaller than those for 4H SiC. For 4H and 6HSiC MOSFETs with N A of 5 1015 cm 3 , the surface Fermi level at V G V th sweeps from 0.2 to 0.4 eV from E c when the temperature increases from 150 to 150 C. Below this temperature range, the variation of the surface Fermi level is very small. ( V th V cal) between 150 and 150 C reects N it within the energy range of 0.20.4 eV from E c . Figure 5 compares the ( V th V cal) with the N it within the energy range of 0.20.4 eV from E c . A linear relationship between ( V th V cal) and N it indicates that the behavior of V th with temperature reects the N it in the n-type MOS capacitor. From this result, we conclude that the D it proles near E c in the n-channel MOSFET can be measured using the n-type MOS capacitor.

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J. Appl. Phys., Vol. 91, No. 3, 1 February 2002

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amined the temperature dependence of V th to clarify the relationship between the channel mobility and the D it prole in SiC MOSFETs. The linear relationship between the V th V cal variation from 150 to 150 C and the value of N it within the energy range of 0.20.4 eV from E c revealed that the D it prole near E c in n-channel SiC MOSFET can be represented by that in the n-type SiC MOS capacitor. The channel mobility did not show obvious correlation with the value of N it within the energy range of 0.20.4 eV from E c . This result suggests that the interface states within this energy range are not the major cause for the low channel mobility in the SiC MOSFET.

ACKNOWLEDGMENT
FIG. 5. Relationship between the N it within the energy range of 0.20.4 eV from E c in the n-type MOS capacitors and the variation of the V th V cal when the temperature increases from 150 to 150 C.

This work was performed under the management of FED as a part of the METI Project R&D of Ultra-Low-Loss Power Device Technologies supported by NEDO.

As shown in Fig. 3, the FE does not depend on the oxidation conditions, whereas N it measured within the energy range of 0.20.4 eV from E c depends on them. This indicates that the D it within the energy range of 0.20.4 eV from E c is not the major cause for the low FE in the 4HSiC MOSFET. It has been reported that the D it increases very rapidly within the energy range of 0.2 eV from E c in the 4HSiC MOSFET.7 Therefore, we suppose that the D it within the energy range of 0.2 eV from E c has a great inuence on the FE , and that the inuence of the oxidation method of the gate oxide on the D it within the energy range of 0.20.4 eV from E c is different from that in the energy range of 0.2 eV from E c . In order to discuss the correlation between the D it and the FE using the n-type MOS capacitors, it will be necessary to measure the D it within the energy range of 0.2 eV from E c .
CONCLUSIONS

In this study, we fabricated 4H and 6HSiC MOSFETs with the gate oxide grown by dry or wet oxidation, and ex-

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