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C H A P T E R 1

David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, Second Edition 2012 by Elsevier Inc.
Exercise Solutions
SOLUTI ONS
2 C H A P T E R s o l ut i o ns
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
S OL U T I O N S 1
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
CHAPTER 1
Exercise 1.1
(a) Biologists study cells at many levels. The cells are built from organelles
such as the mitochondria, ribosomes, and chloroplasts. Organelles are built of
macromolecules such as proteins, lipids, nucleic acids, and carbohydrates.
These biochemical macromolecules are built simpler molecules such as carbon
chains and amino acids. When studying at one of these levels of abstraction, bi-
ologists are usually interested in the levels above and below: what the structures
at that level are used to build, and how the structures themselves are built.
(b) The fundamental building blocks of chemistry are electrons, protons,
and neutrons (physicists are interested in how the protons and neutrons are
built). These blocks combine to form atoms. Atoms combine to form molecules.
For example, when chemists study molecules, they can abstract away the lower
levels of detail so that they can describe the general properties of a molecule
such as benzene without having to calculate the motion of the individual elec-
trons in the molecule.
Exercise 1.3
Ben can use a hierarchy to design the house. First, he can decide how many
bedrooms, bathrooms, kitchens, and other rooms he would like. He can then
jump up a level of hierarchy to decide the overall layout and dimensions of the
house. At the top-level of the hierarchy, he material he would like to use, what
kind of roof, etc. He can then jump to an even lower level of hierarchy to decide
the specific layout of each room, where he would like to place the doors, win-
dows, etc. He can use the principle of regularity in planning the framing of the
house. By using the same type of material, he can scale the framing depending
on the dimensions of each room. He can also use regularity to choose the same
(or a small set of) doors and windows for each room. That way, when he places
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David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
a new door or window he need not redesign the size, material, layout specifica-
tions from scratch. This is also an example of modularity: once he has designed
the specifications for the windows in one room, for example, he need not re-
specify them when he uses the same windows in another room. This will save
him both design time and, thus, money. He could also save by buying some
items (like windows) in bulk.
Exercise 1.5
(a) The hour hand can be resolved to 12 * 4 =48 positions, which represents
log
2
48 =5.58 bits of information. (b) Knowing whether it is before or after noon
adds one more bit.
Exercise 1.7
2
16
=65,536 numbers.
Exercise 1.9
(a) 2
16
-1 =65535; (b) 2
15
-1 =32767; (c) 2
15
-1 =32767
Exercise 1.11
(a) 0; (b) -2
15
=-32768; (c) -(2
15
-1) =-32767
Exercise 1.13
(a) 10; (b) 54; (c) 240; (d) 6311
Exercise 1.15
(a) A; (b) 36; (c) F0; (d) 18A7
Exercise 1.17
(a) 165; (b) 59; (c) 65535; (d) 3489660928
Exercise 1.19
(a) 10100101; (b) 00111011; (c) 1111111111111111;
(d) 11010000000000000000000000000000
S OL U T I O N S 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 1.21
(a) -6; (b) -10; (c) 112; (d) -97
Exercise 1.23
(a) -2; (b) -22; (c) 112; (d) -31
Exercise 1.25
(a) 101010; (b) 111111; (c) 11100101; (d) 1101001101
Exercise 1.27
(a) 2A; (b) 3F; (c) E5; (d) 34D
Exercise 1.29
(a) 00101010; (b) 11000001; (c) 01111100; (d) 10000000; (e) overflow
Exercise 1.31
00101010; (b) 10111111; (c) 01111100; (d) overflow; (e) overflow
Exercise 1.33
(a) 00000101; (b) 11111010
Exercise 1.35
(a) 00000101; (b) 00001010
Exercise 1.37
(a) 52; (b) 77; (c) 345; (d) 1515
Exercise 1.39
(a) 100010
2
, 22
16
, 34
10
; (b) 110011
2
, 33
16
, 51
10
; (c) 010101101
2
, AD
16
,
173
10
; (d) 011000100111
2
, 627
16
, 1575
10
Exercise 1.41
15 greater than 0, 16 less than 0; 15 greater and 15 less for sign/magnitude
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Exercise Solutions
Exercise 1.43
4, 8
Exercise 1.45
5,760,000
EExercise 1.47
46.566 gigabytes
Exercise 1.49
128 kbits
Exercise 1.51
Exercise 1.53
(a) 11011101; (b) 110001000 (overflows)
Exercise 1.55
(a) 11011101; (b) 110001000
Exercise 1.57
(a) 000111 +001101 =010100
(b) 010001 +011001 =101010, overflow
(c) 100110 +001000 =101110
-2 -1 0 1 2 3
10 11 00 01 Two's Complement
10
11
00
01
00 01 10 11
Sign/Magnitude
Unsigned
S OL U T I O N S 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(d) 011111 +110010 =010001
(e) 101101 +101010 =010111, overflow
(f) 111110 +100011 =100001
Exercise 1.59
(a) 0x2A; (b) 0x9F; (c) 0xFE; (d) 0x66, overflow
Exercise 1.61
(a) 010010 +110100 =000110; (b) 011110 +110111 =010101; (c) 100100
+111101 =100001; (d) 110000 +101011 =011011, overflow
Exercise 1.63
Exercise 1.65
(a) 0011 0111 0001
(b) 187
(c) 95 =1011111
(d) Addition of BCD numbers doesn't work directly. Also, the representa-
tion doesn't maximize the amount of information that can be stored; for example
2 BCD digits requires 8 bits and can store up to 100 values (0-99) - unsigned 8-
bit binary can store 28 (256) values.
Exercise 1.67
Both of them are full of it. 42
10
=101010
2
, which has 3 1s in its represen-
tation.
Exercise 1.69
#i ncl ude <st di o. h>
voi d mai n( voi d)
{
char bi n[ 80] ;
i nt i = 0, dec = 0;
pr i nt f ( " Ent er bi nar y number : ") ;
scanf ( " %s" , bi n) ;
-3 -2 -1 0 1 2 3 4
000 001 010 011 100 101 110 111 Biased
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Exercise Solutions
whi l e ( bi n[ i ] ! = 0) {
i f ( bi n[ i ] == ' 0' ) dec = dec * 2;
el se i f ( bi n[ i ] == ' 1' ) dec = dec * 2 + 1;
el se pr i nt f ( "Bad char act er %c i n t he number . \ n" , bi n[ i ] ) ;
i = i + 1;
}
pr i nt f ( " The deci mal equi val ent i s %d\ n" , dec) ;
}
Exercise 1.71
Exercise 1.73
Exercise 1.75
XOR3
Y = A + B + C
B C Y
0 0
0 1
1 0
1 1
A
B Y
C
A
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
1
1
0
1
0
0
1
XNOR4
Y = A + B + C + D
A
B
Y
C
B D Y
0 0 1
0 1 0
1 0 0
1 1 1
C
0
0
0
0
0 0 0
0 1 1
1 0 1
1 1 0
1
1
1
1
A
0 0 0
0 1 1
1 0 1
1 1 0
0
0
0
0
0 0 1
0 1 0
1 0 0
1 1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
D
OR3
Y = A+B+C
B C Y
0 0
0 1
1 0
1 1
A
B Y
C
A
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
1
1
1
1
1
1
1
(a) (b)
(c)
B C Y
0 0
0 1
1 0
1 1
A
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
1
0
1
1
1
S OL U T I O N S 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 1.77

Exercise 1.79
No, there is no legal set of logic levels. The slope of the transfer character-
istic never is better than -1, so the system never has any gain to compensate for
noise.
Exercise 1.81
The circuit functions as a buffer with logic levels V
IL
=1.5; V
IH
=1.8; V
OL
=1.2; V
OH
=3.0. It can receive inputs from LVCMOS and LVTTL gates be-
cause their output logic levels are compatible with this gates input levels. How-
ever, it cannot drive LVCMOS or LVTTL gates because the 1.2 V
OL
exceeds
the V
IL
of LVCMOS and LVTTL.
Exercise 1.83
(a) XOR gate; (b) V
IL
=1.25; V
IH
=2; V
OL
=0; V
OH
=3
Exercise 1.85
B C Y
0 0
0 1
1 0
1 1
A
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
0
1
0
1
0
2
2
N
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Exercise Solutions
Exercise 1.87
XOR
Exercise 1.89
Question 1.1
A
B
C
Y
(b) (c)
Y
A
B
A B
A
B
C
Y
(a)
A B Y
0 0 0
0 1 1
1 0 1
1 1 0
(a) (b) (c)
A B C
Y
A
B
C
Y
A
B
C
Y
weak
weak
weak
A
B
C
Y
D
S OL U T I O N S 9
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Question 1.3
17 minutes: (1) designer and freshman cross (2 minutes); (2) freshman re-
turns (1 minute); (3) professor and TA cross (10 minutes); (4) designer returns
(2 minutes); (5) designer and freshman cross (2 minutes).
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Exercise Solutions
S OL U T I O N S 11
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
CHAPTER 2
Exercise 2.1
(a)
(b)
(c)
(d)
(e)
Exercise 2.3
(a)
(b)
(c)
(d)
(e)
Y AB AB AB + + =
Y ABC ABC + =
Y ABC ABC ABC ABC ABC + + + + =
Y ABCD ABCD ABCD ABCD ABCD ABCD ABCD + + + + + + =
Y ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD + + + + + + + =
Y A B + ( ) =
Y A B C + + ( ) A B C + + ( ) A B C + + ( ) A B C + + ( ) A B C + + ( ) A B C + + ( ) =
Y A B C + + ( ) A B C + + ( ) A B C + + ( ) =
Y A B C D + + + ( ) A B C D + + + ( ) A B C D + + + ( ) A B C D + + + ( ) A B C D + + + ( )
A B C D + + + ( ) A B C D + + + ( ) A B C D + + + ( ) A B C D + + + ( )
=
Y A B C D + + + ( ) A B C D + + + ( ) A B C D + + + ( ) A B C D + + + ( ) A B C D + + + ( )
A B C D + + + ( ) A B C D + + + ( ) A B C D + + + ( )
=
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Exercise Solutions
Exercise 2.5
(a)
(b)
(c)
(d)
(e)
This can also be expressed as:
Exercise 2.7
(a)
(b)
(c)
Y A B + =
Y ABC ABC + =
Y AC AB AC + + =
Y AB BD ACD + + =
Y ABCD ABCD ABCD ABCD ABCD ABCD ABCD ABCD + + + + + + + =
Y A B ( ) C D ( ) A B ( ) C D ( ) + =
A
B
Y
A
B
Y
C
A
B
Y
C
S OL U T I O N S 13
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(d)
(e)
Exercise 2.9
(a) Same as 2.7(a)
(b)
(c)
A B
Y
C D
A
B
Y
C
D
A
B
Y
C
A B
Y
C
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Exercise Solutions
(d)
(e)
Exercise 2.11
(a)
(b)
A B
Y
C D
Y
A B C D
A
B
Y
A
B
Y
C
S OL U T I O N S 15
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(c)
(d)
(e)
Exercise 2.13
(a) Y =AC + BC
(b) Y =A
(c) Y =A +B C +B D +BD
Exercise 2.15
(a)
A
B
Y
C
A
B
Y
C
D
A
B
C
D
Y
A
B Y
C
16 S OL U T I ON S c hapt er 2
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Exercise Solutions
(b)
(c)
Exercise 2.17
(a)
(b)
(c)
Exercise 2.19
A Y
A
B
Y
C
D
Y B AC + =
B
Y
C
A
Y AB =
B
Y
A
Y A BC DE + + =
B
Y
A D C E
S OL U T I O N S 17
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
4 gigarows =4 x 2
30
rows =2
32
rows, so the truth table has 32 inputs.
Exercise 2.21
Ben is correct. For example, the following function, shown as a K-map, has
two possible minimal sum-of-products expressions. Thus, although and
are both prime implicants, the minimal sum-of-products expression does
not have both of them.
Exercise 2.23
Exercise 2.25
ACD
BCD
01 11
1
0
0
0
1
1
1
0 01
0
1
0
0
0
0
0
0
11
10
00
00
10
AB
CD
Y
ABD
ACD
ABC
Y = ABD + ABC + ACD
01 11
1
0
0
0
1
1
1
0 01
0
1
0
0
0
0
0
0
11
10
00
00
10
AB
CD
Y
ABD
ABC
Y = ABD + ABC + BCD
BCD
0 0
0 1
1 0
1 1
B
2
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
0
B
1
B
0
B
2
B
1
B
0
B
2
+B
1
+ B
0
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Exercise Solutions
Exercise 2.27
01 11
0
1
0
1
0
1
0
1 01
1
0
1
0
1
0
1
1
11
10
00
00
10
AB
CD
Y
D
ABC
01 11
0
0
0
1
1
1
0
1 01
0
0
1
0
1
0
0
0
11
10
00
00
10
AB
CD
Z
BD
Y = ABC + D
ACD
Z = ACD + BD
D
Y
B A C
Z
S OL U T I O N S 19
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 2.29
Two possible options are shown below:
Exercise 2.31
Exercise 2.33
The equation can be written directly from the description:
A
B
D
E
F
Y
G
C
Y =ABC +D +(F +G)E
=ABC +D +EF +EG
A
B
C
D
Y
(b) (a)
C
A
D
B
Y
Y AD ABCD BD CD + + + ABCD D A B C + + ( ) + = =
E SA AL H + + =
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David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 2.35
P has two possible minimal solutions:
Hardware implementations are below (implementing the first minimal
equation given for P).
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
1
1
0
1
0
1
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
1
0
1
0
0
A
3
A
1
A
2
A
0
P D
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
Decimal
Value
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
01 11
0
0
0
0
1
0
0
1 01
1
0
0
1
1
0
0
0
11
10
00
00
10
A
3:2
D
A
1:0
01 11
0
0
0
1
0
1
0
0 01
1
1
1
0
0
0
1
0
11
10
00
00
10
A
3:2
P
A
1:0
D = A
3
A
2
A
1
A
0
+ A
3
A
2
A
1
A
0
+ A
3
A
2
A
1
A
0
+ A
3
A
2
A
1
A
0
+ A
3
A
2
A
1
A
0
P = A
3
A
2
A
0
+ A
3
A
1
A
0
+ A
3
A
2
A
1
+ A
2
A
1
A
0
P = A
3
A
1
A
0
+ A
3
A
2
A
1
+ A
2
A
1
A
0
+ A
2
A
1
A
0
S OL U T I O N S 21
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 2.37
The equations and circuit for Y
2:0
is the same as in Exercise 2.25, repeated
here for convenience.
A
3
A
1
A
2
A
0
D
P
0 1
1 X
X X
0
0
1
X X
X X
X X
X X
X
X
X
X
X X X
0
0
0
1
X
X
X
X
A
3
A
1
A
2
A
0
Y
2
0
0
0
0
1
1
1
1
0 0
0 0
0 0
0
0
0
0 0
0 1
1 X
X X
0
0
0
1
X X X
0
0
0
0
0
0
0
1
A
7
A
5
A
6
A
4
Y
1
0
0
1
1
0
0
1
1
Y
0
0
1
0
1
0
1
0
1
0 0 0 0 0 0 0 0 0 0 0
Y
2
A
7
A
6
A
5
A
4
+ + + =
Y
1
A
7
A
6
A
5
A
4
A
3
A
5
A
4
A
2
+ + + =
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Exercise Solutions
Y
0
A
7
A
6
A
5
A
6
A
4
A
3
A
6
A
4
A
2
A
1
+ + + =
A
7
A
5
A
6
A
4
A
3
A
1
A
2
A
0
Y
2
Y
1
Y
0
NONE
S OL U T I O N S 23
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
The truth table, equations, and circuit for Z
2:0
are as follows.
1 1
0 1
0 1
0
1
0
0 1
0 1
0 1
0 1
0
0
0
0
1 X
1 X
1 X
1 X
1
0
0
0
1 X 0
0
0
1
0
0
0
0
0
1
0
0
0
A
3
A
1
A
2
A
0
Z
2
0
0
0
0
0
0
0
0
0
0
0
0
0 0
0 0
0 0
0
0
0
0 1
1 0
0 0
0 0
0
0
1
0
0 0
0 0
0 1
1 0
0
0
0
0
0 1
0
0
0
0
0
0
1
0
0
0
0
0
A
7
A
5
A
6
A
4
0
Z
1
0
0
0
0
0
0
0
0
0
0
0
0
Z
0
0
0
0
0
0
0
0
1
1
1
1
1
1 X
X X
X X
0
1
1
X X
X X
X X
X X
1
1
1
X
X X
X X
X X
X X
X
X
X
X
X X X
0
1
0
0
0
0
1
1
1
1
X
X
0
0
0
0
0
0
0
0
0
0
1
1
0 0
0 0
0 1
0
0
0
1 0
0 0
0 0
0 1
0
1
0
0
1 0
0 0
0 0
1 1
0
1
0
0
0 1
1
0
0
0
0
1
0
0
0
1
0
0 1
0
1
1
1
1
1
1
1
1
0
0
1
0
0
0
0
0
1
1
1
1
0
0
1
1
1
1
1
0
0
0
1
0
1
1
0
X X
X X
X X
X
X
X
X X X
X
X
X
X
0 1
1 X
1 X
0
1
0
X 1
1
0
1
1 X
Z
2
A
4
A
5
A
6
A
7
+ + ( ) A
5
A
6
A
7
+ ( ) A
6
A
7
+ + =
Z
1
A
2
A
3
A
4
A
5
A
6
A
7
+ + + + ( )
A
3
A
4
A
5
A
6
A
7
+ + + ( ) A
6
A
7
+
+
=
Z
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
+ + + + + ( )
A
3
A
4
A
5
A
6
A
7
+ + + ( ) A
5
A
6
A
7
+ ( )
+
+
=
24 S OL U T I ON S c hapt er 2
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 2.39
Exercise 2.41
A
7
A
5
A
6
A
4
A
3
A
1
A
2
A
0
Z
2
Z
1
Z
0
Y A C D + A CD CD + + = =
A B Y
0 0
0 1 0
1 0 0
1 1
00
Y
01
10
11
A B
A Y
0
1
0
1
A
Y
BC
A B Y
0 0 1
0 1 0
1 0 0
1 1 0
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
1
C
A B
(a)
000
001
010
011
100
101
110
111
C
C
C
C
BC
B
C
(b) (c)
Y
S OL U T I O N S 25
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 2.43
t
pd
=3t
pd_NAND2
=60 ps
t
cd
=t
cd_NAND2
=15 ps
Exercise 2.45
t
pd
=t
pd_NOT
+ t
pd_AND3

=15 ps +40 ps
=55 ps
t
cd
=t
cd_AND3

=30 ps
A
2
A
1
A
0
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
26 S OL U T I ON S c hapt er 2
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 2.47
t
pd
=t
pd_INV
+3t
pd_NAND2
+t
pd_NAND3

=[15 +3 (20) +30] ps
=105 ps
t
cd
=t
cd_NOT
+t
cd_NAND2
=[10 +15] ps
=25 ps
A
7
A
5
A
6
A
4
A
3
A
1
A
2
A
0
Y
2
Y
1
Y
0
NONE
S OL U T I O N S 27
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Question 2.1
Question 2.3
A tristate buffer has two inputs and three possible outputs: 0, 1, and Z. One
of the inputs is the data input and the other input is a control input, often called
the enable input. When the enable input is 1, the tristate buffer transfers the data
input to the output; otherwise, the output is high impedance, Z. Tristate buffers
are used when multiple sources drive a single output at different times. One and
only one tristate buffer is enabled at any given time.
Question 2.5
A circuits contamination delay might be less than its propagation delay be-
cause the circuit may operate over a range of temperatures and supply voltages,
for example, 3-3.6 V for LVCMOS (low voltage CMOS) chips. As temperature
increases and voltage decreases, circuit delay increases. Also, the circuit may
have different paths (critical and short paths) from the input to the output. A gate
itself may have varying delays between different inputs and the output, affect-
ing the gates critical and short paths. For example, for a two-input NAND gate,
a HIGH to LOW transition requires two nMOS transistor delays, whereas a
LOW to HIGH transition requires a single pMOS transistor delay.
A
B
Y
28 S OL U T I ON S c hapt er 2
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
S OL U T I O N S 41
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
CHAPTER 3
Exercise 3.1

Exercise 3.3
S
R
Q
clk
D
Q
42 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 3.5
Exercise 3.7
The circuit is sequential because it involves feedback and the output de-
pends on previous values of the inputs. This is a SR latch. When S =0 and R =
1, the circuit sets Q to 1. When S =1 and R =0, the circuit resets Q to 0. When
both S and R are 1, the circuit remembers the old value. And when both S and R
are 0, the circuit drives both outputs to 1.
Exercise 3.9

Exercise 3.11
If A and B have the same value, C takes on that value. Otherwise, C retains
its old value.
clk
D
Q
Q
clk
S OL U T I O N S 43
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 3.13
Exercise 3.15

Exercise 3.17
If N is even, the circuit is stable and will not oscillate.
Exercise 3.19
The system has at least five bits of state to represent the 24 floors that the
elevator might be on.
Exercise 3.21
The FSM could be factored into four independent state machines, one for
each student. Each of these machines has five states and requires 3 bits, so at
least 12 bits of state are required for the factored design.
Q
Q
R
R
D
R
clk
CLK
Q
Q
D
Set
Set
Set
Set
44 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 3.23
This finite state machine asserts the output Q when A AND B is TRUE.

st at e encodi ng
s
1: 0
S0 00
S1 01
S2 10
TABLE 3.1 State encoding for Exercise 3.23
cur r ent st at e i nput s next st at e out put
s
1
s
0
a b s '
1
s '
0
q
0 0 0 X 0 0 0
0 0 1 X 0 1 0
0 1 X 0 0 0 0
0 1 X 1 1 0 0
1 0 1 1 1 0 1
1 0 0 0 0 0 0
1 0 0 1 0 0 0
1 0 1 0 0 0 0
TABLE 3.2 Combined state transition and output table with binary encodings for Exercise 3.23
S'
1
S
1
S
0
B S
1
AB + =
S'
0
S
1
S
0
A =
Q' S
1
AB =
S OL U T I O N S 45
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 3.25

st at e encodi ng
s
1: 0
S0 000
S1 001
TABLE 3.3 State encoding for Exercise 3.25
S
1
S
0
S'
1
S'
0
CLK
Reset
B A
S
1
S
0
r
Q
reset
S0 S1 S2 S3
S4
0/0
1/0
0/0
1/0 0/0
1/1
1/0
1/0
0/1
0/0
46 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
S2 010
S3 100
S4 101
st at e encodi ng
s
1: 0
TABLE 3.3 State encoding for Exercise 3.25
cur r ent st at e i nput next st at e out put
s
2
s
1
s
0
a s '
2
s '
1
s '
0
q
0 0 0 0 0 0 0 0
0 0 0 1 0 0 1 0
0 0 1 0 0 0 0 0
0 0 1 1 0 1 0 0
0 1 0 0 1 0 0 0
0 1 0 1 1 0 1 0
1 0 0 0 0 0 0 0
1 0 0 1 0 0 1 1
1 0 1 0 1 0 0 1
1 0 1 1 1 0 1 0
TABLE 3.4 Combined state transition and output table with binary encodings for Exercise 3.25
S'
2
S
2
S
1
S
0
S
2
S
1
S
0
+ =
S'
1
S
2
S
1
S
0
A =
S'
0
A S
2
S
0
S
2
S
1
+ ( ) =
Q S
2
S
1
S
0
A S
2
S
1
S
0
A + =
S OL U T I O N S 47
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 3.27
S
2
S
1
S'
2
S'
1
CLK
Reset
A
S
1
S
0
r
S
0
S'
0
S
2
48 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
FIGURE 3.1 State transition diagram for Exercise 3.27
S000
S001
S011
S010
S110
S111
S101
S100
Reset
S OL U T I O N S 49
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

cur r ent
st at e
s
2 : 0
next st at e
s '
2: 0
000 001
001 011
011 010
010 110
110 111
111 101
101 100
100 000
TABLE 3.5 State transition table for Exercise 3.27
S'
2
S
1
S
0
S
2
S
0
+ =
S'
1
S
2
S
0
S
1
S
0
+ =
S'
0
S
2
S
1
=
Q
2
S
2
=
Q
1
S
1
=
Q
0
S
0
=
50 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
FIGURE 3.2 Hardware for Gray code counter FSM for Exercise 3.27
Exercise 3.29
(a)
FIGURE 3.3 Waveform showing Z output for Exercise 3.29
(b) This FSM is a Mealy FSM because the output depends on the current
value of the input as well as the current state.
S
2
S
1
S'
2
S'
1
CLK
Reset S
1
S
0
r
S
0
S'
0
S
2
Q
2
Q
1
Q
0
CLK
A
B
Z
S OL U T I O N S 51
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(c)
FIGURE 3.4 State transition diagram for Exercise 3.29
(Note: another viable solution would be to allow the state to transition from
S0 to S1 on . The arrow from S0 to S0 would then be .)

Reset
S0
S1
S2
BA/0
S3
BA/0 BA/1 BA/0
BA/1 BA/1
A/0
BA/0
BA/1
BA/1
BA/1
BA/1
BA/1
BA/0
BA/0
BA 0 BA 0
cur r ent st at e
s
1: 0
i nput s next st at e
s '
1: 0
out put
z
b a
00 X 0 00 0
00 0 1 11 0
00 1 1 01 1
01 0 0 00 0
01 0 1 11 1
01 1 0 10 1
01 1 1 01 1
10 0 X 00 0
10 1 0 10 0
TABLE 3.6 State transition table for Exercise 3.29
52 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
FIGURE 3.5 Hardware for FSM of Exercise 3.26
Note: One could also build this functionality by registering input A, pro-
ducing both the logical AND and OR of input A and its previous (registered)
10 1 1 01 1
11 0 0 00 0
11 0 1 11 1
11 1 0 10 1
11 1 1 01 1
cur r ent st at e
s
1: 0
i nput s next st at e
s '
1: 0
out put
z
b a
TABLE 3.6 State transition table for Exercise 3.29
S'
1
BA S
1
S
0
+ ( ) BA S
1
S
0
+ ( ) + =
S'
0
A S
1
S
0
B + + ( ) =
Z BA S
0
A B + ( ) + =
S
1
S
0
S'
1
S'
0
CLK
Reset
r
Z
B A
S OL U T I O N S 53
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
value, and then muxing the two operations using B. The output of the mux is Z:
Z =AAprev (if B =0); Z =A +Aprev (if B =1).
Exercise 3.31
This finite state machine is a divide-by-two counter (see Section 3.4.2)
when X =0. When X =1, the output, Q, is HIGH.


cur r ent st at e i nput next st at e
s
1
s
0
x s '
1
s '
0
0 0 0 0 1
0 0 1 1 1
0 1 0 0 0
0 1 1 1 0
1 X X 0 1
TABLE 3.7 State transition table with binary encodings for Exercise 3.31
cur r ent st at e out put
s
1
s
0
q
0 0 0
0 1 1
1 X 1
TABLE 3.8 Output table for Exercise 3.31
54 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 3.33
(a) First, we calculate the propagation delay through the combinational log-
ic:
t
pd
=3t
pd_XOR
=3 100 ps
=300 ps
Next, we calculate the cycle time:
T
c
> t
pcq
+ t
pd
+ t
setup
> [70 +300 +60] ps
= 430 ps
f = 1 / 430 ps =2.33 GHz
(b)
T
c
> t
pcq
+ t
pd
+ t
setup
+ t
skew
Thus,
t
skew
< T
c
(t
pcq
+ t
pd
+ t
setup
), where T
c
=1 / 2 GHz =500 ps


< [500 430] ps =70 ps
(c)
First, we calculate the contamination delay through the combinational log-
ic:
t
cd
=t
cd_XOR
=55 ps
t
ccq
+t
cd
>t
hold
+t
skew
Thus,
t
skew
<(t
ccq
+ t
cd
) - t
hold
<(50 + 55) - 20
< 85 ps
S00
0
S01
1
S10
1
S11
1
0
0
1
1
S OL U T I O N S 55
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(d)
FIGURE 3.6 Alyssas improved circuit for Exercise 3.33
First, we calculate the propagation and contamination delays through the
combinational logic:
t
pd
=2t
pd_XOR
=2 100 ps
=200 ps
t
cd
=2t
cd_XOR
=2 55 ps
=110 ps
Next, we calculate the cycle time:
T
c
> t
pcq
+ t
pd
+ t
setup
> [70 +200 +60] ps
= 330 ps
f = 1 / 330 ps =3.03 GHz
t
skew
<(t
ccq
+ t
cd
) - t
hold
<(50 + 110) - 20
< 140 ps
Exercise 3.35
(a) T
c
=1 / 40 MHz =25 ns
T
c
> t
pcq
+ Nt
CLB
+ t
setup
25 ns > [0.72 +N(0.61) +0.53] ps
Thus, N <38.9
N = 38
(b)
clk
clk
56 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
t
skew
<(t
ccq
+ t
cd_CLB
) - t
hold
<[(0.5 + 0.3) - 0] ns
< 0.8 ns = 800 ps
Exercise 3.37
P(failure)/sec =1/MTBF =1/(50 years * 3.15 x 10
7
sec/year) =6.34 x
10
-10
(EQ 3.26)
P(failure)/sec waiting for one clock cycle: N*(T
0
/T
c
)*e
-(Tc-tsetup)/Tau
=0.5 * (110/1000) * e
-(1000-70)/100
=5.0 x 10
-6
P(failure)/sec waiting for two clock cycles: N*(T
0
/T
c
)*[e
-(Tc-tsetup)/Tau
]
2
=0.5 * (110/1000) * [e-
(1000-70)/100
]
2
=4.6 x 10
-10
This is just less than the required probability of failure (6.34 x
10
-10
). Thus, 2 cycles of waiting is just adequate to meet the MTBF.
Exercise 3.39
We assume a two flip-flop synchronizer. The most significant impact on
the probability of failure comes from the exponential component. If we ignore
the T
0
/T
c
term in the probability of failure equation, assuming it changes little
with increases in cycle time, we get:
Solving for T
c2
- T
c1
, we get:
P failure ( ) e
t
t
--
=
MTBF
1
P failure ( )
--------------------------- e
T
c
t
setup

t
------------------------
= =
MTBF
2
MTBF
1
------------------- 10 e
T
c2
T
c1

30ps
----------------------
= =
T
c2
T
c1
69ps =
S OL U T I O N S 57
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Thus, the clock cycle time must increase by 69 ps. This holds true for cycle
times much larger than T0 (20 ps) and the increased time (69 ps).
Question 3.1
FIGURE 3.7 State transition diagram for Question 3.1
reset
Sreset
S0
S01
A
A
A
S010
A
A
A
S0101
A
S01010
Q =1
A
A
A
A
A
58 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

cur r ent
st at e
s
5 : 0
i nput next st at e
s '
5 : 0
a
000001 0 000010
000001 1 000001
000010 0 000010
000010 1 000100
000100 0 001000
000100 1 000001
001000 0 000010
001000 1 010000
010000 0 100000
010000 1 000001
100000 0 000010
100000 1 000001
TABLE 3.9 State transition table for Question 3.1
S'
5
S
4
A =
S'
4
S
3
A =
S'
3
S
2
A =
S'
2
S
1
A =
S'
1
A S
1
S
3
S
5
+ + ( ) =
S'
0
A S
0
S
2
S
4
S
5
+ + + ( ) =
Q S
5
=
S OL U T I O N S 59
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
FIGURE 3.8 Finite state machine hardware for Question 3.1
Question 3.3
A latch allows input D to flow through to the output Q when the clock is
HIGH. A flip-flop allows input D to flow through to the output Q at the clock
edge. A flip-flop is preferable in systems with a single clock. Latches are pref-
erable in two-phase clocking systems, with two clocks. The two clocks are used
to eliminate system failure due to hold time violations. Both the phase and fre-
quency of each clock can be modified independently.
S
5
S
4
S'
5
S'
4
CLK
S
3
S'
3
Reset
r
S
2
S
1
S'
2
S'
1
S
0
S'
0
Q
60 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Question 3.5
FIGURE 3.9 State transition diagram for edge detector circuit of Question 3.5

cur r ent
st at e
s
1 : 0
i nput next st at e
s '
1 : 0
a
00 0 00
00 1 01
01 0 00
01 1 10
10 0 00
10 1 10
TABLE 3.10 State transition table for Question 3.5
Reset
S0
Q =0
S1
Q =1
A
A
A
S2
Q =0
A
A
A
S'
1
AS
1
=
S'
0
AS
1
S
0
=
S OL U T I O N S 61
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
FIGURE 3.10 Finite state machine hardware for Question 3.5
Question 3.7
A flip-flop with a negative hold time allows D to start changing before the
clock edge arrives.
Question 3.9
Without the added buffer, the propagation delay through the logic, t
pd
, must
be less than or equal to T
c
- (t
pcq
+t
setup
). However, if you add a buffer to the
clock input of the receiver, the clock arrives at the receiver later. The earliest
that the clock edge arrives at the receiver is t
cd_BUF
after the actual clock edge.
Thus, the propagation delay through the logic is now given an extra t
cd_BUF
. So,
t
pd
now must be less than T
c
+t
cd_BUF
- (t
pcq
+t
setup
).
Q S
1
=
S
1
S
0
S'
1
S'
0
CLK
Reset
r
Q
A
62 S OL U T I ON S c hapt er 3
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
S OL U T I O N S 85
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
CHAPTER 4
Note: the HDL files given in the following solutions are available on the
textbooks companion website at:
http://textbooks.elsevier.com/9780123704979
Exercise 4.1

a
b
c
y
z
86 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 4.3
Exercise 4.5

Exercise 4.7
ex4_7.tv file:
0000_111_1110
0001_011_0000
0010_110_1101
0011_111_1001
0100_011_0011
0101_101_1011
0110_101_1111
0111_111_0000
1000_111_1111
1001_111_1011
1010_111_0111
1011_001_1111
1100_000_1101
1101_011_1101
1110_100_1111
1111_100_0111
SystemVerilog
modul e xor _4( i nput l ogi c [ 3: 0] a,
out put l ogi c y) ;
assi gn y = ^a;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y xor _4 i s
por t ( a: i n STD_LOGI C_VECTOR( 3 downt o 0) ;
y: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of xor _4 i s
begi n
y <= a( 3) xor a( 2) xor a( 1) xor a( 0) ;
end;
SystemVerilog
modul e mi nor i t y( i nput l ogi c a, b, c
out put l ogi c y) ;
assi gn y = ~a & ~b | ~a & ~c | ~b & ~c;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mi nor i t y i s
por t ( a, b, c: i n STD_LOGI C;
y: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of mi nor i t y i s
begi n
y <= ( ( not a) and ( not b) ) or ( ( not a) and ( not c) )
or ( ( not b) and ( not c) ) ;
end;
S OL U T I O N S 87
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Option 1:
(VHDL continued on next page)
SystemVerilog
modul e ex4_7_t est bench( ) ;
l ogi c cl k, r eset ;
l ogi c [ 3: 0] dat a;
l ogi c [ 6: 0] s_expect ed;
l ogi c [ 6: 0] s;
l ogi c [ 31: 0] vect or num, er r or s;
l ogi c [ 10: 0] t est vect or s[ 10000: 0] ;
/ / i nst ant i at e devi ce under t est
sevenseg dut ( dat a, s) ;
/ / gener at e cl ock
al ways
begi n
cl k = 1; #5; cl k = 0; #5;
end
/ / at st ar t of t est , l oad vect or s
/ / and pul se r eset
i ni t i al
begi n
$r eadmemb( " ex4_7. t v" , t est vect or s) ;
vect or num= 0; er r or s = 0;
r eset = 1; #27; r eset = 0;
end
/ / appl y t est vect or s on r i si ng edge of cl k
al ways @( posedge cl k)
begi n
#1; {dat a, s_expect ed} =
t est vect or s[ vect or num] ;
end
/ / check r esul t s on f al l i ng edge of cl k
al ways @( negedge cl k)
i f ( ~r eset ) begi n / / ski p dur i ng r eset
i f ( s ! == s_expect ed) begi n
$di spl ay( " Er r or : i nput s = %h" , dat a) ;
$di spl ay( " out put s = %b ( %b expect ed) ",
s, s_expect ed) ;
er r or s = er r or s + 1;
end
vect or num= vect or num+ 1;
i f ( t est vect or s[ vect or num] === 11' bx) begi n
$di spl ay( " %d t est s compl et ed wi t h %d er r or s" ,
vect or num, er r or s) ;
$f i ni sh;
end
end
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use STD. TEXTI O. al l ;
use I EEE. STD_LOGI C_UNSI GNED. al l ;
use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y ex4_7_t est bench i s - - no i nput s or out put s
end;
ar chi t ect ur e si mof ex4_7_t est bench i s
component seven_seg_decoder
por t ( dat a: i n STD_LOGI C_VECTOR( 3 downt o 0) ;
segment s: out STD_LOGI C_VECTOR( 6 downt o 0) ) ;
end component ;
si gnal dat a: STD_LOGI C_VECTOR( 3 downt o 0) ;
si gnal s: STD_LOGI C_VECTOR( 6 downt o 0) ;
si gnal cl k, r eset : STD_LOGI C;
si gnal s_expect ed: STD_LOGI C_VECTOR( 6 downt o 0) ;
const ant MEMSI ZE: i nt eger : = 10000;
t ype t var r ay i s ar r ay( MEMSI ZE downt o 0) of
STD_LOGI C_VECTOR( 10 downt o 0) ;
si gnal t est vect or s: t var r ay;
shar ed var i abl e vect or num, er r or s: i nt eger ;
begi n
- - i nst ant i at e devi ce under t est
dut : seven_seg_decoder por t map( dat a, s) ;

- - gener at e cl ock
pr ocess begi n
cl k <= ' 1' ; wai t f or 5 ns;
cl k <= ' 0' ; wai t f or 5 ns;
end pr ocess;
- - at st ar t of t est , l oad vect or s
- - and pul se r eset
pr ocess i s
f i l e t v: TEXT;
var i abl e i , j : i nt eger ;
var i abl e L: l i ne;
var i abl e ch: char act er ;
begi n
- - r ead f i l e of t est vect or s
i : = 0;
FI LE_OPEN( t v, "ex4_7. t v", READ_MODE) ;
whi l e not endf i l e( t v) l oop
r eadl i ne( t v, L) ;
f or j i n 10 downt o 0 l oop
r ead( L, ch) ;
i f ( ch = ' _' ) t hen r ead( L, ch) ;
end i f ;
i f ( ch = ' 0' ) t hen
t est vect or s( i ) ( j ) <= ' 0' ;
el se t est vect or s( i ) ( j ) <= ' 1' ;
end i f ;
end l oop;
i : = i + 1;
end l oop;
88 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(continued from previous page)
VHDL
vect or num: = 0; er r or s : = 0;
r eset <= ' 1' ; wai t f or 27 ns; r eset <= ' 0' ;
wai t ;
end pr ocess;

- - appl y t est vect or s on r i si ng edge of cl k
pr ocess ( cl k) begi n
i f ( cl k' event and cl k = ' 1' ) t hen

dat a <= t est vect or s( vect or num) ( 10 downt o 7)
af t er 1 ns;
s_expect ed <=t est vect or s( vect or num) ( 6 downt o 0)
af t er 1 ns;
end i f ;
end pr ocess;
- - check r esul t s on f al l i ng edge of cl k
pr ocess ( cl k) begi n
i f ( cl k' event and cl k = ' 0' and r eset = ' 0' ) t hen
asser t s = s_expect ed
r epor t " dat a = " &
i nt eger ' i mage( CONV_I NTEGER( dat a) ) &
" ; s = " &
i nt eger ' i mage( CONV_I NTEGER( s) ) &
" ; s_expect ed = " &
i nt eger ' i mage( CONV_I NTEGER( s_expect ed) ) ;
i f ( s / = s_expect ed) t hen
er r or s : = er r or s + 1;
end i f ;
vect or num: = vect or num+ 1;
i f ( i s_x( t est vect or s( vect or num) ) ) t hen
i f ( er r or s = 0) t hen
r epor t " J ust ki ddi ng - - " &
i nt eger ' i mage( vect or num) &
" t est s compl et ed successf ul l y. "
sever i t y f ai l ur e;
el se
r epor t i nt eger ' i mage( vect or num) &
" t est s compl et ed, er r or s = " &
i nt eger ' i mage( er r or s)
sever i t y f ai l ur e;
end i f ;
end i f ;
end i f ;
end pr ocess;
end;
S OL U T I O N S 89
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Option 2 (VHDL only):
(see Web site for file: txt_util.vhd)
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use STD. TEXTI O. al l ;
use wor k. t xt _ut i l . al l ;
ent i t y ex4_7_t est bench i s - - no i nput s or out put s
end;
ar chi t ect ur e si mof ex4_7_t est bench i s
component seven_seg_decoder
por t ( dat a: i n STD_LOGI C_VECTOR( 3 downt o 0) ;
segment s: out STD_LOGI C_VECTOR( 6 downt o 0) ) ;
end component ;
si gnal dat a: STD_LOGI C_VECTOR( 3 downt o 0) ;
si gnal s: STD_LOGI C_VECTOR( 6 downt o 0) ;
si gnal cl k, r eset : STD_LOGI C;
si gnal s_expect ed: STD_LOGI C_VECTOR( 6 downt o 0) ;
const ant MEMSI ZE: i nt eger : = 10000;
t ype t var r ay i s ar r ay( MEMSI ZE downt o 0) of
STD_LOGI C_VECTOR( 10 downt o 0) ;
si gnal t est vect or s: t var r ay;
shar ed var i abl e vect or num, er r or s: i nt eger ;
begi n
- - i nst ant i at e devi ce under t est
dut : seven_seg_decoder por t map( dat a, s) ;

- - gener at e cl ock
pr ocess begi n
cl k <= ' 1' ; wai t f or 5 ns;
cl k <= ' 0' ; wai t f or 5 ns;
end pr ocess;
- - at st ar t of t est , l oad vect or s
- - and pul se r eset
pr ocess i s
f i l e t v: TEXT;
var i abl e i , j : i nt eger ;
var i abl e L: l i ne;
var i abl e ch: char act er ;
begi n
- - r ead f i l e of t est vect or s
i : = 0;
FI LE_OPEN( t v, " ex4_7. t v" , READ_MODE) ;
whi l e not endf i l e( t v) l oop
r eadl i ne( t v, L) ;
f or j i n 10 downt o 0 l oop
r ead( L, ch) ;
i f ( ch = ' _' ) t hen r ead( L, ch) ;
end i f ;
i f ( ch = ' 0' ) t hen
t est vect or s( i ) ( j ) <= ' 0' ;
el se t est vect or s( i ) ( j ) <= ' 1' ;
end i f ;
end l oop;
i : = i + 1;
end l oop;
vect or num: = 0; er r or s : = 0;
r eset <= ' 1' ; wai t f or 27 ns; r eset <= ' 0' ;
wai t ;
end pr ocess;

- - appl y t est vect or s on r i si ng edge of cl k
pr ocess ( cl k) begi n
i f ( cl k' event and cl k = ' 1' ) t hen

dat a <= t est vect or s( vect or num) ( 10 downt o 7)
af t er 1 ns;
s_expect ed <=t est vect or s( vect or num) ( 6 downt o 0)
af t er 1 ns;
end i f ;
end pr ocess;
- - check r esul t s on f al l i ng edge of cl k
pr ocess ( cl k) begi n
i f ( cl k' event and cl k = ' 0' and r eset = ' 0' ) t hen
asser t s = s_expect ed
r epor t " dat a = " & st r ( dat a) &
" ; s = " & st r ( s) &
" ; s_expect ed = " & st r ( s_expect ed) ;
i f ( s / = s_expect ed) t hen
er r or s : = er r or s + 1;
end i f ;
vect or num: = vect or num+ 1;
i f ( i s_x( t est vect or s( vect or num) ) ) t hen
i f ( er r or s = 0) t hen
r epor t " J ust ki ddi ng - - " &
i nt eger ' i mage( vect or num) &
" t est s compl et ed successf ul l y. "
sever i t y f ai l ur e;
el se
r epor t i nt eger ' i mage( vect or num) &
" t est s compl et ed, er r or s = " &
i nt eger ' i mage( er r or s)
sever i t y f ai l ur e;
end i f ;
end i f ;
end i f ;
end pr ocess;
end;
90 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 4.9
SystemVerilog
modul e ex4_9
( i nput l ogi c a, b, c,
out put l ogi c y) ;
mux8 #( 1) mux8_1( 1' b1, 1' b0, 1' b0, 1' b1,
1' b1, 1' b1, 1' b0, 1' b0,
{a, b, c}, y) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_9 i s
por t ( a,
b,
c: i n STD_LOGI C;
y: out STD_LOGI C_VECTOR( 0 downt o 0) ) ;
end;
ar chi t ect ur e st r uct of ex4_9 i s
component mux8
gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2, d3, d4, d5, d6,
d7: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 2 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
si gnal sel : STD_LOGI C_VECTOR( 2 downt o 0) ;
begi n
sel <= a & b & c;
mux8_1: mux8 gener i c map( 1)
por t map( " 1" , " 0" , " 0", " 1" ,
" 1" , " 1" , " 0", " 0" ,
sel , y) ;
end;
S OL U T I O N S 91
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 4.11
A shift register with feedback, shown below, cannot be correctly described
with blocking assignments.
Exercise 4.13
CLK
SystemVerilog
modul e decoder 2_4( i nput l ogi c [ 1: 0] a,
out put l ogi c [ 3: 0] y) ;
al ways_comb
case ( a)
2' b00: y = 4' b0001;
2' b01: y = 4' b0010;
2' b10: y = 4' b0100;
2' b11: y = 4' b1000;
endcase
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y decoder 2_4 i s
por t ( a: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( 3 downt o 0) ) ;
end;
ar chi t ect ur e synt h of decoder 2_4 i s
begi n
pr ocess( al l ) begi n
case a i s
when " 00" => y <= " 0001" ;
when " 01" => y <= " 0010" ;
when " 10" => y <= " 0100" ;
when " 11" => y <= " 1000" ;
when ot her s => y <= " 0000" ;
end case;
end pr ocess;
end;
92 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 4.15
(a)
(b)
(c)
Y AC ABC + =
SystemVerilog
modul e ex4_15a( i nput l ogi c a, b, c,
out put l ogi c y) ;
assi gn y = ( a & c) | ( ~a & ~b & c) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_15a i s
por t ( a, b, c: i n STD_LOGI C;
y: out STD_LOGI C) ;
end;
ar chi t ect ur e behave of ex4_15a i s
begi n
y <= ( not a and not b and c) or ( not b and c) ;
end;
Y AB ABC A C + ( ) + + =
SystemVerilog
modul e ex4_15b( i nput l ogi c a, b, c,
out put l ogi c y) ;
assi gn y = ( ~a & ~b) | ( ~a & b & ~c) | ~( a | ~c) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_15b i s
por t ( a, b, c: i n STD_LOGI C;
y: out STD_LOGI C) ;
end;
ar chi t ect ur e behave of ex4_15b i s
begi n
y <= ( ( not a) and ( not b) ) or ( ( not a) and b and
( not c) ) or ( not ( a or ( not c) ) ) ;
end;
Y ABCD ABC ABCD ABD ABCD BCD A + + + + + + =
SystemVerilog
modul e ex4_15c( i nput l ogi c a, b, c, d,
out put l ogi c y) ;
assi gn y = ( ~a & ~b & ~c & ~d) | ( a & ~b & ~c) |
( a & ~b & c & ~d) | ( a & b & d) |
( ~a & ~b & c & ~d) | ( b & ~c & d) | ~a;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_15c i s
por t ( a, b, c, d: i n STD_LOGI C;
y: out STD_LOGI C) ;
end;
ar chi t ect ur e behave of ex4_15c i s
begi n
y <=( ( not a) and ( not b) and ( not c) and ( not d) ) or
( a and ( not b) and ( not c) ) or
( a and ( not b) and c and ( not d) ) or
( a and b and d) or
( ( not a) and ( not b) and c and ( not d) ) or
( b and ( not c) and d) or ( not a) ;
end;
S OL U T I O N S 93
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 4.17
Exercise 4.19
SystemVerilog
modul e ex4_17( i nput l ogi c a, b, c, d, e, f , g
out put l ogi c y) ;
l ogi c n1, n2, n3, n4, n5;
assi gn n1 = ~( a & b & c) ;
assi gn n2 = ~( n1 & d) ;
assi gn n3 = ~( f & g) ;
assi gn n4 = ~( n3 | e) ;
assi gn n5 = ~( n2 | n4) ;
assi gn y = ~( n5 & n5) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_17 i s
por t ( a, b, c, d, e, f , g: i n STD_LOGI C;
y: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of ex4_17 i s
si gnal n1, n2, n3, n4, n5: STD_LOGI C;
begi n
n1 <= not ( a and b and c) ;
n2 <= not ( n1 and d) ;
n3 <= not ( f and g) ;
n4 <= not ( n3 or e) ;
n5 <= not ( n2 or n4) ;
y <= not ( n5 or n5) ;
end;
94 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 4.21
SystemVerilog
modul e ex4_18( i nput l ogi c [ 3: 0] a,
out put l ogi c p, d) ;
al ways_comb
case ( a)
0: {p, d} = 2' b00;
1: {p, d} = 2' b00;
2: {p, d} = 2' b10;
3: {p, d} = 2' b11;
4: {p, d} = 2' b00;
5: {p, d} = 2' b10;
6: {p, d} = 2' b01;
7: {p, d} = 2' b10;
8: {p, d} = 2' b00;
9: {p, d} = 2' b01;
10: {p, d} = 2' b00;
11: {p, d} = 2' b10;
12: {p, d} = 2' b01;
13: {p, d} = 2' b10;
14: {p, d} = 2' b00;
15: {p, d} = 2' b01;
endcase
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_18 i s
por t ( a: i n STD_LOGI C_VECTOR( 3 downt o 0) ;
p, d: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of ex4_18 i s
si gnal var s: STD_LOGI C_VECTOR( 1 downt o 0) ;
begi n
p <= var s( 1) ;
d <= var s( 0) ;
pr ocess( al l ) begi n
case a i s
when X" 0" => var s <= " 00" ;
when X" 1" => var s <= " 00" ;
when X" 2" => var s <= " 10" ;
when X" 3" => var s <= " 11" ;
when X" 4" => var s <= " 00" ;
when X" 5" => var s <= " 10" ;
when X" 6" => var s <= " 01" ;
when X" 7" => var s <= " 10" ;
when X" 8" => var s <= " 00" ;
when X" 9" => var s <= " 01" ;
when X" A" => var s <= " 00" ;
when X" B" => var s <= " 10" ;
when X" C" => var s <= " 01" ;
when X" D" => var s <= " 10" ;
when X" E" => var s <= " 00" ;
when X" F" => var s <= " 01" ;
when ot her s => var s <= " 00" ;
end case;
end pr ocess;
end;
S OL U T I O N S 95
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
SystemVerilog
modul e pr i or i t y_encoder 2( i nput l ogi c [ 7: 0] a,
out put l ogi c [ 2: 0] y, z,
out put l ogi c none) ;
al ways_comb
begi n
casez ( a)
8' b00000000: begi n y = 3' d0; none = 1' b1; end
8' b00000001: begi n y = 3' d0; none = 1' b0; end
8' b0000001?: begi n y = 3' d1; none = 1' b0; end
8' b000001??: begi n y = 3' d2; none = 1' b0; end
8' b00001???: begi n y = 3' d3; none = 1' b0; end
8' b0001????: begi n y = 3' d4; none = 1' b0; end
8' b001?????: begi n y = 3' d5; none = 1' b0; end
8' b01??????: begi n y = 3' d6; none = 1' b0; end
8' b1???????: begi n y = 3' d7; none = 1' b0; end
endcase
casez ( a)
8' b00000011: z = 3' b000;
8' b00000101: z = 3' b000;
8' b00001001: z = 3' b000;
8' b00010001: z = 3' b000;
8' b00100001: z = 3' b000;
8' b01000001: z = 3' b000;
8' b10000001: z = 3' b000;
8' b0000011?: z = 3' b001;
8' b0000101?: z = 3' b001;
8' b0001001?: z = 3' b001;
8' b0010001?: z = 3' b001;
8' b0100001?: z = 3' b001;
8' b1000001?: z = 3' b001;
8' b000011??: z = 3' b010;
8' b000101??: z = 3' b010;
8' b001001??: z = 3' b010;
8' b010001??: z = 3' b010;
8' b100001??: z = 3' b010;
8' b00011???: z = 3' b011;
8' b00101???: z = 3' b011;
8' b01001???: z = 3' b011;
8' b10001???: z = 3' b011;
8' b0011????: z = 3' b100;
8' b0101????: z = 3' b100;
8' b1001????: z = 3' b100;
8' b011?????: z = 3' b101;
8' b101?????: z = 3' b101;
8' b11??????: z = 3' b110;
def aul t : z = 3' b000;
end
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y pr i or i t y_encoder 2 i s
por t ( a: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
y, z: out STD_LOGI C_VECTOR( 2 downt o 0) ;
none: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of pr i or i t y_encoder i s
begi n
pr ocess( al l ) begi n
case? a i s
when " 00000000" => y <= " 000" ; none <= ' 1' ;
when " 00000001" => y <= " 000" ; none <= ' 0' ;
when " 0000001- " => y <= " 001" ; none <= ' 0' ;
when " 000001- - " => y <= " 010" ; none <= ' 0' ;
when " 00001- - - " => y <= " 011" ; none <= ' 0' ;
when " 0001- - - - " => y <= " 100" ; none <= ' 0' ;
when " 001- - - - - " => y <= " 101" ; none <= ' 0' ;
when " 01- - - - - - " => y <= " 110" ; none <= ' 0' ;
when " 1- - - - - - - " => y <= " 111" ; none <= ' 0' ;
when ot her s => y <= " 000" ; none <= ' 0' ;
end case?;
case? a i s
when " 00000011" => z <= " 000" ;
when " 00000101" => z <= " 000" ;
when " 00001001" => z <= " 000" ;
when " 00001001" => z <= " 000" ;
when " 00010001" => z <= " 000" ;
when " 00100001" => z <= " 000" ;
when " 01000001" => z <= " 000" ;
when " 10000001" => z <= " 000" ;
when " 0000011- " => z <= " 001" ;
when " 0000101- " => z <= " 001" ;
when " 0001001- " => z <= " 001" ;
when " 0010001- " => z <= " 001" ;
when " 0100001- " => z <= " 001" ;
when " 1000001- " => z <= " 001" ;
when " 000011- - " => z <= " 010" ;
when " 000101- - " => z <= " 010" ;
when " 001001- - " => z <= " 010" ;
when " 010001- - " => z <= " 010" ;
when " 100001- - " => z <= " 010" ;
when " 00011- - - " => z <= " 011" ;
when " 00101- - - " => z <= " 011" ;
when " 01001- - - " => z <= " 011" ;
when " 10001- - - " => z <= " 011" ;
when " 0011- - - - " => z <= " 100" ;
when " 0101- - - - " => z <= " 100" ;
when " 1001- - - - " => z <= " 100" ;
when " 011- - - - - " => z <= " 101" ;
when " 101- - - - - " => z <= " 101" ;
when " 11- - - - - - " => z <= " 110" ;
when ot her s => z <= " 000" ;
end case?;
end pr ocess;
end;
96 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 4.23
Exercise 4.25
FIGURE 4.1 State transition diagram for Exercise 4.25
SystemVerilog
modul e mont h31days( i nput l ogi c [ 3: 0] mont h,
out put l ogi c y) ;
al ways_comb
casez ( mont h)
1: y = 1' b1;
2: y = 1' b0;
3: y = 1' b1;
4: y = 1' b0;
5: y = 1' b1;
6: y = 1' b0;
7: y = 1' b1;
8: y = 1' b1;
9: y = 1' b0;
10: y = 1' b1;
11: y = 1' b0;
12: y = 1' b1;
def aul t : y = 1' b0;
endcase
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mont h31days i s
por t ( a: i n STD_LOGI C_VECTOR( 3 downt o 0) ;
y: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of mont h31days i s
begi n
pr ocess( al l ) begi n
case a i s
when X" 1" => y <= ' 1' ;
when X" 2" => y <= ' 0' ;
when X" 3" => y <= ' 1' ;
when X" 4" => y <= ' 0' ;
when X" 5" => y <= ' 1' ;
when X" 6" => y <= ' 0' ;
when X" 7" => y <= ' 1' ;
when X" 8" => y <= ' 1' ;
when X" 9" => y <= ' 0' ;
when X" A" => y <= ' 1' ;
when X" B" => y <= ' 0' ;
when X" C" => y <= ' 1' ;
when ot her s => y <= ' 0' ;
end case;
end pr ocess;
end;
S0 S1
S2
if (back)
predicttaken
S3
predicttaken
S4
predicttaken
taken
taken
taken
taken
taken
taken
taken
taken
taken
taken
reset
S OL U T I O N S 97
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 4.27
Exercise 4.29
SystemVerilog
modul e j kf l op( i nput l ogi c j , k, cl k,
out put l ogi c q) ;
al ways @( posedge cl k)
case ( {j , k})
2' b01: q <= 1' b0;
2' b10: q <= 1' b1;
2' b11: q <= ~q;
endcase
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y j kf l op i s
por t ( j , k, cl k: i n STD_LOGI C;
q: i nout STD_LOGI C) ;
end;
ar chi t ect ur e synt h of j kf l op i s
si gnal j k: STD_LOGI C_VECTOR( 1 downt o 0) ;
begi n
j k <= j & k;
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
i f j = ' 1' and k = ' 0'
t hen q <= ' 1' ;
el si f j = ' 0' and k = ' 1'
t hen q <= ' 0' ;
el si f j = ' 1' and k = ' 1'
t hen q <= not q;
end i f ;
end i f ;
end pr ocess;
end;
98 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
SystemVerilog
modul e t r af f i cFSM( i nput l ogi c cl k, r eset , t a, t b,
out put l ogi c [ 1: 0] l a, l b) ;
t ypedef enuml ogi c [ 1: 0] {S0, S1, S2, S3}
st at et ype;
st at et ype [ 1: 0] st at e, next st at e;
par amet er gr een = 2' b00;
par amet er yel l ow = 2' b01;
par amet er r ed = 2' b10;
/ / St at e Regi st er
al ways_f f @( posedge cl k, posedge r eset )
i f ( r eset ) st at e <= S0;
el se st at e <= next st at e;
/ / Next St at e Logi c
al ways_comb
case ( st at e)
S0: i f ( t a) next st at e = S0;
el se next st at e = S1;
S1: next st at e = S2;
S2: i f ( t b) next st at e = S2;
el se next st at e = S3;
S3: next st at e = S0;
endcase
/ / Out put Logi c
al ways_comb
case ( st at e)
S0: {l a, l b} = {gr een, r ed};
S1: {l a, l b} = {yel l ow, r ed};
S2: {l a, l b} = {r ed, gr een};
S3: {l a, l b} = {r ed, yel l ow};
endcase
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y t r af f i cFSM i s
por t ( cl k, r eset , t a, t b: i n STD_LOGI C;
l a, l b: i nout STD_LOGI C_VECTOR( 1 downt o 0) ) ;
end;
ar chi t ect ur e behave of t r af f i cFSM i s
t ype st at et ype i s ( S0, S1, S2, S3) ;
si gnal st at e, next st at e: st at et ype;
si gnal l al b: STD_LOGI C_VECTOR( 3 downt o 0) ;
begi n
- - st at e r egi st er
pr ocess( cl k, r eset ) begi n
i f r eset t hen st at e <= S0;
el si f r i si ng_edge( cl k) t hen
st at e <= next st at e;
end i f ;
end pr ocess;
- - next st at e l ogi c
pr ocess( al l ) begi n
case st at e i s
when S0 => i f t a t hen
next st at e <= S0;
el se next st at e <= S1;
end i f ;
when S1 => next st at e <= S2;
when S2 => i f t b t hen
next st at e <= S2;
el se next st at e <= S3;
end i f ;
when S3 => next st at e <= S0;
when ot her s => next st at e <= S0;
end case;
end pr ocess;
- - out put l ogi c
l a <= l al b( 3 downt o 2) ;
l b <= l al b( 1 downt o 0) ;
pr ocess( al l ) begi n
case st at e i s
when S0 => l al b <= " 0010" ;
when S1 => l al b <= " 0110" ;
when S2 => l al b <= " 1000" ;
when S3 => l al b <= " 1001" ;
when ot her s => l al b <= " 1010" ;
end case;
end pr ocess;
end;
S OL U T I O N S 99
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 4.31
Exercise 4.33
SystemVerilog
modul e f i g3_42( i nput l ogi c cl k, a, b, c, d,
out put l ogi c x, y) ;
l ogi c n1, n2;
l ogi c ar eg, br eg, cr eg, dr eg;
al ways_f f @( posedge cl k) begi n
ar eg <= a;
br eg <= b;
cr eg <= c;
dr eg <= d;
x <= n2;
y <= ~( dr eg | n2) ;
end
assi gn n1 = ar eg & br eg;
assi gn n2 = n1 | cr eg;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y f i g3_42 i s
por t ( cl k, a, b, c, d: i n STD_LOGI C;
x, y: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of f i g3_40 i s
si gnal n1, n2, ar eg, br eg, cr eg, dr eg: STD_LOGI C;
begi n
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
ar eg <= a;
br eg <= b;
cr eg <= c;
dr eg <= d;
x <= n2;
y <= not ( dr eg or n2) ;
end i f ;
end pr ocess;
n1 <= ar eg and br eg;
n2 <= n1 or cr eg;
end;
100 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 4.35
SystemVerilog
modul e f i g3_70( i nput l ogi c cl k, r eset , a, b,
out put l ogi c q) ;
t ypedef enuml ogi c [ 1: 0] {S0, S1, S2} st at et ype;
st at et ype [ 1: 0] st at e, next st at e;
/ / St at e Regi st er
al ways_f f @( posedge cl k, posedge r eset )
i f ( r eset ) st at e <= S0;
el se st at e <= next st at e;
/ / Next St at e Logi c
al ways_comb
case ( st at e)
S0: i f ( a) next st at e = S1;
el se next st at e = S0;
S1: i f ( b) next st at e = S2;
el se next st at e = S0;
S2: i f ( a & b) next st at e = S2;
el se next st at e = S0;
def aul t : next st at e = S0;
endcase
/ / Out put Logi c
al ways_comb
case ( st at e)
S0: q = 0;
S1: q = 0;
S2: i f ( a & b) q = 1;
el se q = 0;
def aul t : q = 0;
endcase
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y f i g3_70 i s
por t ( cl k, r eset , a, b: i n STD_LOGI C;
q: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of f i g3_70 i s
t ype st at et ype i s ( S0, S1, S2) ;
si gnal st at e, next st at e: st at et ype;
begi n
- - st at e r egi st er
pr ocess( cl k, r eset ) begi n
i f r eset t hen st at e <= S0;
el si f r i si ng_edge( cl k) t hen
st at e <= next st at e;
end i f ;
end pr ocess;
- - next st at e l ogi c
pr ocess( al l ) begi n
case st at e i s
when S0 => i f a t hen
next st at e <= S1;
el se next st at e <= S0;
end i f ;
when S1 => i f b t hen
next st at e <= S2;
el se next st at e <= S0;
end i f ;
when S2 => i f ( a = ' 1' and b = ' 1' ) t hen
next st at e <= S2;
el se next st at e <= S0;
end i f ;
when ot her s => next st at e <= S0;
end case;
end pr ocess;
- - out put l ogi c
q <= ' 1' when ( ( st at e = S2) and
( a = ' 1' and b = ' 1' ) )
el se ' 0' ;
end;
S OL U T I O N S 101
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
SystemVerilog
modul e daught er f sm( i nput l ogi c cl k, r eset , a,
out put l ogi c smi l e) ;
t ypedef enuml ogi c [ 1: 0] {S0, S1, S2, S3, S4}
st at et ype;
st at et ype [ 2: 0] st at e, next st at e;
/ / St at e Regi st er
al ways_f f @( posedge cl k, posedge r eset )
i f ( r eset ) st at e <= S0;
el se st at e <= next st at e;
/ / Next St at e Logi c
al ways_comb
case ( st at e)
S0: i f ( a) next st at e = S1;
el se next st at e = S0;
S1: i f ( a) next st at e = S2;
el se next st at e = S0;
S2: i f ( a) next st at e = S4;
el se next st at e = S3;
S3: i f ( a) next st at e = S1;
el se next st at e = S0;
S4: i f ( a) next st at e = S4;
el se next st at e = S3;
def aul t : next st at e = S0;
endcase
/ / Out put Logi c
assi gn smi l e = ( ( st at e == S3) & a) |
( ( st at e == S4) & ~a) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y daught er f smi s
por t ( cl k, r eset , a: i n STD_LOGI C;
smi l e: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of daught er f smi s
t ype st at et ype i s ( S0, S1, S2, S3, S4) ;
si gnal st at e, next st at e: st at et ype;
begi n
- - st at e r egi st er
pr ocess( cl k, r eset ) begi n
i f r eset t hen st at e <= S0;
el si f r i si ng_edge( cl k) t hen
st at e <= next st at e;
end i f ;
end pr ocess;
- - next st at e l ogi c
pr ocess( al l ) begi n
case st at e i s
when S0 => i f a t hen
next st at e <= S1;
el se next st at e <= S0;
end i f ;
when S1 => i f a t hen
next st at e <= S2;
el se next st at e <= S0;
end i f ;
when S2 => i f a t hen
next st at e <= S4;
el se next st at e <= S3;
end i f ;
when S3 => i f a t hen
next st at e <= S1;
el se next st at e <= S0;
end i f ;
when S4 => i f a t hen
next st at e <= S4;
el se next st at e <= S3;
end i f ;
when ot her s => next st at e <= S0;
end case;
end pr ocess;
- - out put l ogi c
smi l e <= ' 1' when ( ( ( st at e = S3) and ( a = ' 1' ) ) or
( ( st at e = S4) and ( a = ' 0' ) ) )
el se ' 0' ;
end;
102 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 4.37
Exercise 4.39
SystemVerilog
modul e ex4_37( i nput l ogi c cl k, r eset ,
out put l ogi c [ 2: 0] q) ;
t ypedef enuml ogi c [ 2: 0] {S0 = 3' b000,
S1 = 3' b001,
S2 = 3' b011,
S3 = 3' b010,
S4 = 3' b110,
S5 = 3' b111,
S6 = 3' b101,
S7 = 3' b100}
st at et ype;
st at et ype [ 2: 0] st at e, next st at e;
/ / St at e Regi st er
al ways_f f @( posedge cl k, posedge r eset )
i f ( r eset ) st at e <= S0;
el se st at e <= next st at e;
/ / Next St at e Logi c
al ways_comb
case ( st at e)
S0: next st at e = S1;
S1: next st at e = S2;
S2: next st at e = S3;
S3: next st at e = S4;
S4: next st at e = S5;
S5: next st at e = S6;
S6: next st at e = S7;
S7: next st at e = S0;
endcase
/ / Out put Logi c
assi gn q = st at e;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_37 i s
por t ( cl k: i n STD_LOGI C;
r eset : i n STD_LOGI C;
q: out STD_LOGI C_VECTOR( 2 downt o 0) ) ;
end;
ar chi t ect ur e synt h of ex4_37 i s
si gnal st at e: STD_LOGI C_VECTOR( 2 downt o 0) ;
si gnal next st at e: STD_LOGI C_VECTOR( 2 downt o 0) ;
begi n
- - st at e r egi st er
pr ocess( cl k, r eset ) begi n
i f r eset t hen st at e <= "000" ;
el si f r i si ng_edge( cl k) t hen
st at e <= next st at e;
end i f ;
end pr ocess;
- - next st at e l ogi c
pr ocess( al l ) begi n
case st at e i s
when " 000" => next st at e <= " 001" ;
when " 001" => next st at e <= " 011" ;
when " 011" => next st at e <= " 010" ;
when " 010" => next st at e <= " 110" ;
when " 110" => next st at e <= " 111" ;
when " 111" => next st at e <= " 101" ;
when " 101" => next st at e <= " 100" ;
when " 100" => next st at e <= " 000" ;
when ot her s => next st at e <= " 000" ;
end case;
end pr ocess;
- - out put l ogi c
q <= st at e;
end;
S OL U T I O N S 103
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Option 1
SystemVerilog
modul e ex4_39( i nput l ogi c cl k, r eset , a, b,
out put l ogi c z) ;
t ypedef enuml ogi c [ 1: 0] {S0, S1, S2, S3}
st at et ype;
st at et ype [ 1: 0] st at e, next st at e;
/ / St at e Regi st er
al ways_f f @( posedge cl k, posedge r eset )
i f ( r eset ) st at e <= S0;
el se st at e <= next st at e;
/ / Next St at e Logi c
al ways_comb
case ( st at e)
S0: case ( {b, a})
2' b00: next st at e = S0;
2' b01: next st at e = S3;
2' b10: next st at e = S0;
2' b11: next st at e = S1;
endcase
S1: case ( {b, a})
2' b00: next st at e = S0;
2' b01: next st at e = S3;
2' b10: next st at e = S2;
2' b11: next st at e = S1;
endcase
S2: case ( {b, a})
2' b00: next st at e = S0;
2' b01: next st at e = S3;
2' b10: next st at e = S2;
2' b11: next st at e = S1;
endcase
S3: case ( {b, a})
2' b00: next st at e = S0;
2' b01: next st at e = S3;
2' b10: next st at e = S2;
2' b11: next st at e = S1;
endcase
def aul t : next st at e = S0;
endcase
/ / Out put Logi c
al ways_comb
case ( st at e)
S0: z = a & b;
S1: z = a | b;
S2: z = a & b;
S3: z = a | b;
def aul t : z = 1' b0;
endcase
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_39 i s
por t ( cl k: i n STD_LOGI C;
r eset : i n STD_LOGI C;
a, b: i n STD_LOGI C;
z: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of ex4_39 i s
t ype st at et ype i s ( S0, S1, S2, S3) ;
si gnal st at e, next st at e: st at et ype;
si gnal ba: STD_LOGI C_VECTOR( 1 downt o 0) ;
begi n
- - st at e r egi st er
pr ocess( cl k, r eset ) begi n
i f r eset t hen st at e <= S0;
el si f r i si ng_edge( cl k) t hen
st at e <= next st at e;
end i f ;
end pr ocess;
- - next st at e l ogi c
ba <= b & a;
pr ocess( al l ) begi n
case st at e i s
when S0 =>
case ( ba) i s
when " 00" => next st at e <= S0;
when " 01" => next st at e <= S3;
when " 10" => next st at e <= S0;
when " 11" => next st at e <= S1;
when ot her s => next st at e <= S0;
end case;
when S1 =>
case ( ba) i s
when " 00" => next st at e <= S0;
when " 01" => next st at e <= S3;
when " 10" => next st at e <= S2;
when " 11" => next st at e <= S1;
when ot her s => next st at e <= S0;
end case;
when S2 =>
case ( ba) i s
when " 00" => next st at e <= S0;
when " 01" => next st at e <= S3;
when " 10" => next st at e <= S2;
when " 11" => next st at e <= S1;
when ot her s => next st at e <= S0;
end case;
when S3 =>
case ( ba) i s
when " 00" => next st at e <= S0;
when " 01" => next st at e <= S3;
when " 10" => next st at e <= S2;
when " 11" => next st at e <= S1;
when ot her s => next st at e <= S0;
end case;
when ot her s => next st at e <= S0;
end case;
end pr ocess;
104 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(continued from previous page)
Option 2

VHDL
- - out put l ogi c
pr ocess( al l ) begi n
case st at e i s
when S0 => i f ( a = ' 1' and b = ' 1' )
t hen z <= ' 1' ;
el se z <= ' 0' ;
end i f ;
when S1 => i f ( a = ' 1' or b = ' 1' )
t hen z <= ' 1' ;
el se z <= ' 0' ;
end i f ;
when S2 => i f ( a = ' 1' and b = ' 1' )
t hen z <= ' 1' ;
el se z <= ' 0' ;
end i f ;
when S3 => i f ( a = ' 1' or b = ' 1' )
t hen z <= ' 1' ;
el se z <= ' 0' ;
end i f ;
when ot her s => z <= ' 0' ;
end case;
end pr ocess;
end;
SystemVerilog
modul e ex4_37( i nput l ogi c cl k, a, b,
out put l ogi c z) ;
l ogi c apr ev;
/ / St at e Regi st er
al ways_f f @( posedge cl k)
apr ev <= a;
assi gn z = b ? ( apr ev | a) : ( apr ev & a) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_37 i s
por t ( cl k: i n STD_LOGI C;
a, b: i n STD_LOGI C;
z: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of ex4_37 i s
si gnal apr ev, n1and, n2or : STD_LOGI C;
begi n
- - st at e r egi st er
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
apr ev <= a;
end i f ;
end pr ocess;
z <= ( a or apr ev) when b = ' 1' el se
( a and apr ev) ;
end;
S OL U T I O N S 105
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 4.41
Exercise 4.43
SystemVerilog
modul e ex4_41( i nput l ogi c cl k, st ar t , a,
out put l ogi c q) ;
t ypedef enuml ogi c [ 1: 0] {S0, S1, S2, S3}
st at et ype;
st at et ype [ 1: 0] st at e, next st at e;
/ / St at e Regi st er
al ways_f f @( posedge cl k, posedge st ar t )
i f ( st ar t ) st at e <= S0;
el se st at e <= next st at e;
/ / Next St at e Logi c
al ways_comb
case ( st at e)
S0: i f ( a) next st at e = S1;
el se next st at e = S0;
S1: i f ( a) next st at e = S2;
el se next st at e = S3;
S2: i f ( a) next st at e = S2;
el se next st at e = S3;
S3: i f ( a) next st at e = S2;
el se next st at e = S3;
endcase
/ / Out put Logi c
assi gn q = st at e[ 0] ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_41 i s
por t ( cl k, st ar t , a: i n STD_LOGI C;
q: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of ex4_41 i s
t ype st at et ype i s ( S0, S1, S2, S3) ;
si gnal st at e, next st at e: st at et ype;
begi n
- - st at e r egi st er
pr ocess( cl k, st ar t ) begi n
i f st ar t t hen st at e <= S0;
el si f r i si ng_edge( cl k) t hen
st at e <= next st at e;
end i f ;
end pr ocess;
- - next st at e l ogi c
pr ocess( al l ) begi n
case st at e i s
when S0 => i f a t hen
next st at e <= S1;
el se next st at e <= S0;
end i f ;
when S1 => i f a t hen
next st at e <= S2;
el se next st at e <= S3;
end i f ;
when S2 => i f a t hen
next st at e <= S2;
el se next st at e <= S3;
end i f ;
when S3 => i f a t hen
next st at e <= S2;
el se next st at e <= S3;
end i f ;
when ot her s => next st at e <= S0;
end case;
end pr ocess;
- - out put l ogi c
q <= ' 1' when ( ( st at e = S1) or ( st at e = S3) )
el se ' 0' ;
end;
106 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 4.45
SystemVerilog
modul e ex4_43( i nput cl k, r eset , a,
out put q) ;
t ypedef enuml ogi c [ 1: 0] {S0, S1, S2} st at et ype;
st at et ype [ 1: 0] st at e, next st at e;
/ / St at e Regi st er
al ways_f f @( posedge cl k, posedge r eset )
i f ( r eset ) st at e <= S0;
el se st at e <= next st at e;
/ / Next St at e Logi c
al ways_comb
case ( st at e)
S0: i f ( a) next st at e = S1;
el se next st at e = S0;
S1: i f ( a) next st at e = S2;
el se next st at e = S0;
S2: i f ( a) next st at e = S2;
el se next st at e = S0;
def aul t : next st at e = S0;
endcase
/ / Out put Logi c
assi gn q = st at e[ 1] ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_43 i s
por t ( cl k, r eset , a: i n STD_LOGI C;
q: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of ex4_43 i s
t ype st at et ype i s ( S0, S1, S2) ;
si gnal st at e, next st at e: st at et ype;
begi n
- - st at e r egi st er
pr ocess( cl k, r eset ) begi n
i f r eset t hen st at e <= S0;
el si f r i si ng_edge( cl k) t hen
st at e <= next st at e;
end i f ;
end pr ocess;
- - next st at e l ogi c
pr ocess( al l ) begi n
case st at e i s
when S0 => i f a t hen
next st at e <= S1;
el se next st at e <= S0;
end i f ;
when S1 => i f a t hen
next st at e <= S2;
el se next st at e <= S0;
end i f ;
when S2 => i f a t hen
next st at e <= S2;
el se next st at e <= S0;
end i f ;
when ot her s => next st at e <= S0;
end case;
end pr ocess;
- - out put l ogi c
q <= ' 1' when ( st at e = S2) el se ' 0' ;
end;
S OL U T I O N S 107
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 4.47
SystemVerilog
modul e ex4_45( i nput l ogi c cl k, c,
i nput l ogi c [ 1: 0] a, b,
out put l ogi c [ 1: 0] s) ;
l ogi c [ 1: 0] ar eg, br eg;
l ogi c cr eg;
l ogi c [ 1: 0] sum;
l ogi c cout ;
al ways_f f @( posedge cl k)
{ar eg, br eg, cr eg, s} <= {a, b, c, sum};

f ul l adder f ul l add1( ar eg[ 0] , br eg[ 0] , cr eg,
sum[ 0] , cout ) ;
f ul l adder f ul l add2( ar eg[ 1] , br eg[ 1] , cout ,
sum[ 1] , ) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y ex4_45 i s
por t ( cl k, c: i n STD_LOGI C;
a, b: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
s: out STD_LOGI C_VECTOR( 1 downt o 0) ) ;
end;
ar chi t ect ur e synt h of ex4_45 i s
component f ul l adder i s
por t ( a, b, ci n: i n STD_LOGI C;
s, cout : out STD_LOGI C) ;
end component ;
si gnal cr eg: STD_LOGI C;
si gnal ar eg, br eg, cout : STD_LOGI C_VECTOR( 1 downt o
0) ;
si gnal sum: STD_LOGI C_VECTOR( 1 downt o 0) ;
begi n
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
ar eg <= a;
br eg <= b;
cr eg <= c;
s <= sum;
end i f ;
end pr ocess;
f ul l add1: f ul l adder
por t map( ar eg( 0) , br eg( 0) , cr eg, sum( 0) , cout ( 0) ) ;
f ul l add2: f ul l adder
por t map( ar eg( 1) , br eg( 1) , cout ( 0) , sum( 1) ,
cout ( 1) ) ;
end;
108 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 4.49
They do not have the same function.
Exercise 4.51
It is necessary to write
SystemVerilog
modul e syncbad( i nput l ogi c cl k,
i nput l ogi c d,
out put l ogi c q) ;
l ogi c n1;
al ways_f f @( posedge cl k)
begi n
q <= n1; / / nonbl ocki ng
n1 <= d; / / nonbl ocki ng
end
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y syncbad i s
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C;
q: out STD_LOGI C) ;
end;
ar chi t ect ur e bad of syncbad i s
begi n
pr ocess( cl k)
var i abl e n1: STD_LOGI C;
begi n
i f r i si ng_edge( cl k) t hen
q <= n1; - - nonbl ocki ng
n1 <= d; - - nonbl ocki ng
end i f ;
end pr ocess;
end;
B
A
CLK
X
C
Y
code1
code2
B
A
CLK
X
C Y
S OL U T I O N S 109
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
q <= ' 1' when st at e = S0 el se ' 0' ;
rather than simply
q <= ( st at e = S0) ;
because the result of the comparison ( st at e =S0) is of type Bool ean
(t r ue and f al se) and q must be assigned a value of type STD_LOGIC (' 1'
and ' 0' ).
Question 4.1
Question 4.3
The SystemVerilog statement performs the bit-wise AND of the 16 least
significant bits of data with 0xC820. It then ORs these 16 bits to produce the 1-
bit result.
SystemVerilog
assi gn r esul t = sel ? dat a : 32' b0;
VHDL
r esul t <= dat a when sel = ' 1' el se X" 00000000" ;
110 S OL U T I ON S c hapt er 4
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
S OL U T I O N S 139
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
CHAPTER 5
Exercise 5.1
(a) From Equation5.1, we find the 64-bit ripple-carry adder delay to be:
(b) From Equation5.6, we find the 64-bit carry-lookahead adder delay to
be:
(Note: the actual delay is only 7.2 ns because the first AND_OR gate only
has a 150 ps delay.)
(c) From Equation5.11, we find the 64-bit prefix adder delay to be:
Exercise 5.3
A designer might choose to use a ripple-carry adder instead of a carry-loo-
kahead adder if chip area is the critical resource and delay is not the critical con-
straint.
t
ripple
Nt
FA
64 450 ps ( ) 28.8 ns = = =
t
CLA
t
pg
t
pg_block
N
k
---- 1
\ .
| |
t
AND_OR
kt
FA
+ + + =
t
CLA
150 6 150 ( )
64
4
------ 1
\ .
| |
300 4 450 ( ) + + + 7.35 ns = =
t
PA
t
pg
N t
pg_prefix
( ) t
XOR
+
2
log + =
t
PA
150 6 300 ( ) 150 + + | | 2.1 ns = =
140 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 5.5
FIGURE 5.1 16-bit prefix adder with gray cells
Exercise 5.7
(a) We show an 8-bit priority circuit in Figure5.2. In the figure X
7
=A
7
,
X
7:6
=A
7
A
6
, X
7:5
=A
7
A
6
A
5
, and so on. The priority encoders delay is log
2
N 2-
input AND gates followed by a final row of 2-input AND gates. The final stage
is an (N/2)-input OR gate. Thus, in general, the delay of an N-input priority en-
coder is:
t
pd_priority
=(log
2
N+1)t
pd_AND2
+t
pd_ORN/2
0:-1
-1
2:1
1:-1 2:-1
0 1 2
4:3
3
6:5
5:3 6:3
4 5 6
5:-1 6:-1 3:-1 4:-1
8:7
7
10:9
9:7 10:7
8 9 10
12:11
11
14:13
13:11 14:11
12 13 14
13:7 14:7 11:7 12:7
9:-1 10:-1 7:-1 8:-1 13:-1 14:-1 11:-1 12:-1
15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
B
i
A
i
G
i:i
P
i:i
G
k-1:j
P
k-1:j
G
i:k
P
i:k
G
i:j
P
i:j
i
i:j
B
i
A
i
G
i-1:-1
S
i
i Legend
G
k-1:j
G
i:k
P
i:k
G
i:j
i:j
S OL U T I O N S 141
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
FIGURE 5.2 8-input priority encoder
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
X
7:6
X
7
X
7:5
X
7:4
X
7:3
X
7:2
X
7:1
Z
0
Z
2
Z
3
Y
1
Y
3
Y
5
Y
7
Y
2
Y
3
Y
6
Y
7
Y
4
Y
5
Y
6
Y
7
142 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

Exercise 5.9
SystemVerilog
modul e pr i or i t yckt ( i nput l ogi c [ 7: 0] a,
out put l ogi c [ 2: 0] z) ;
l ogi c [ 7: 0] y;
l ogi c x7, x76, x75, x74, x73, x72, x71;
l ogi c x32, x54, x31;
l ogi c [ 7: 0] abar ;

/ / r ow of i nver t er s
assi gn abar = ~a;
/ / f i r st r ow of AND gat es
assi gn x7 = abar [ 7] ;
assi gn x76 = abar [ 6] & x7;
assi gn x54 = abar [ 4] & abar [ 5] ;
assi gn x32 = abar [ 2] & abar [ 3] ;
/ / second r ow of AND gat es
assi gn x75 = abar [ 5] & x76;
assi gn x74 = x54 & x76;
assi gn x31 = abar [ 1] & x32;
/ / t hi r d r ow of AND gat es
assi gn x73 = abar [ 3] & x74;
assi gn x72 = x32 & x74;
assi gn x71 = x31 & x74;
/ / f our t h r ow of AND gat es
assi gn y = {a[ 7] , a[ 6] & x7, a[ 5] & x76,
a[ 4] & x75, a[ 3] & x74, a[ 2] & x73,
a[ 1] & x72, a[ 0] & x71};
/ / r ow of OR gat es
assi gn z = { | {y[ 7: 4] },
| {y[ 7: 6] , y[ 3: 2] },
| {y[ 1] , y[ 3] , y[ 5] , y[ 7] } };
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y pr i or i t yckt i s
por t ( a: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
z: out STD_LOGI C_VECTOR( 2 downt o 0) ) ;
end;
ar chi t ect ur e synt h of pr i or i t yckt i s
si gnal y, abar : STD_LOGI C_VECTOR( 7 downt o 0) ;
si gnal x7, x76, x75, x74, x73, x72, x71,
x32, x54, x31: STD_LOGI C;
begi n
- - r ow of i nver t er s
abar <= not a;
- - f i r st r ow of AND gat es
x7 <= abar ( 7) ;
x76 <= abar ( 6) and x7;
x54 <= abar ( 4) and abar ( 5) ;
x32 <= abar ( 2) and abar ( 3) ;
- - second r ow of AND gat es
x75 <= abar ( 5) and x76;
x74 <= x54 and x76;
x31 <= abar ( 1) and x32;
- - t hi r d r ow of AND gat es
x73 <= abar ( 3) and x74;
x72 <= x32 and x74;
x71 <= x31 and x74;
- - f our t h r ow of AND gat es
y <= ( a( 7) & ( a( 6) and x7) & ( a( 5) and x76) &
( a( 4) and x75) & ( a( 3) and x74) & ( a( 2) and
x73) &
( a( 1) and x72) & ( a( 0) and x71) ) ;
- - r ow of OR gat es
z <= ( ( y( 7) or y( 6) or y( 5) or y( 4) ) &
( y( 7) or y( 6) or y( 3) or y( 2) ) &
( y( 1) or y( 3) or y( 5) or y( 7) ) ) ;
end;
S OL U T I O N S 143
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

Exercise 5.11
SystemVerilog
modul e al u32( i nput l ogi c [ 31: 0] A, B,
i nput l ogi c [ 2: 0] F,
out put l ogi c [ 31: 0] Y) ;
l ogi c [ 31: 0] S, Bout ;
assi gn Bout = F[ 2] ? ~B : B;
assi gn S = A + Bout + F[ 2] ;
al ways_comb
case ( F[ 1: 0] )
2' b00: Y <= A & Bout ;
2' b01: Y <= A | Bout ;
2' b10: Y <= S;
2' b11: Y <= S[ 31] ;
endcase
endmodul e
VHDL
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
use I EEE. st d_l ogi c_ar i t h. al l ;
use i eee. st d_l ogi c_unsi gned. al l ;
ent i t y al u32 i s
por t ( A, B: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
F: i n STD_LOGI C_VECTOR( 2 downt o 0) ;
Y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e synt h of al u32 i s
si gnal S, Bout : STD_LOGI C_VECTOR( 31 downt o 0) ;
begi n
Bout <= ( not B) when ( F( 2) = ' 1' ) el se B;
S <= A + Bout + F( 2) ;
pr ocess( al l ) begi n
case F( 1 downt o 0) i s
when " 00" => Y <= A and Bout ;
when " 01" => Y <= A or Bout ;
when " 10" => Y <= S;
when " 11" => Y <=
( " 0000000000000000000000000000000" & S( 31) ) ;
when ot her s => Y <= X"00000000";
end case;
end pr ocess;
end;
144 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 5.13
SystemVerilog
modul e al u32( i nput l ogi c [ 31: 0] A, B,
i nput l ogi c [ 2: 0] F,
out put l ogi c [ 31: 0] Y,
out put l ogi c Zer o, Over f l ow) ;
l ogi c [ 31: 0] S, Bout ;
assi gn Bout = F[ 2] ? ~B : B;
assi gn S = A + Bout + F[ 2] ;
al ways_comb
case ( F[ 1: 0] )
2' b00: Y <= A & Bout ;
2' b01: Y <= A | Bout ;
2' b10: Y <= S;
2' b11: Y <= S[ 31] ;
endcase
assi gn Zer o = ( Y == 32' b0) ;
al ways_comb
case ( F[ 2: 1] )
2' b01: Over f l ow <= A[ 31] & B[ 31] & ~S[ 31] |
~A[ 31] & ~B[ 31] & S[ 31] ;
2' b11: Over f l ow <= ~A[ 31] & B[ 31] & S[ 31] |
A[ 31] & ~B[ 31] & ~S[ 31] ;
def aul t : Over f l ow <= 1' b0;
endcase
endmodul e
VHDL
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
use I EEE. st d_l ogi c_ar i t h. al l ;
use i eee. st d_l ogi c_unsi gned. al l ;
ent i t y al u32 i s
por t ( A, B: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
F: i n STD_LOGI C_VECTOR( 2 downt o 0) ;
Y: i nout STD_LOGI C_VECTOR( 31 downt o 0) ;
Over f l ow: out STD_LOGI C;
Zer o: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of al u32 i s
si gnal S, Bout : STD_LOGI C_VECTOR( 31 downt o 0) ;
begi n
Bout <= ( not B) when ( F( 2) = ' 1' ) el se B;
S <= A + Bout + F( 2) ;
- - al u f unct i on
pr ocess( al l ) begi n
case F( 1 downt o 0) i s
when " 00" => Y <= A and Bout ;
when " 01" => Y <= A or Bout ;
when " 10" => Y <= S;
when " 11" => Y <=
( "0000000000000000000000000000000" & S( 31) ) ;
when ot her s => Y <= X"00000000";
end case;
end pr ocess;
Zer o <= ' 1' when ( Y = X" 00000000" ) el se ' 0' ;
- - over f l ow ci r cui t
pr ocess( al l ) begi n
case F( 2 downt o 1) i s
when " 01" => Over f l ow <=
( A( 31) and B( 31) and ( not ( S( 31) ) ) ) or
( ( not A( 31) ) and ( not B( 31) ) and S( 31) ) ;
when " 11" => Over f l ow <=
( ( not A( 31) ) and B( 31) and S( 31) ) or
( A( 31) and ( not B( 31) ) and ( not S( 31) ) ) ;
when ot her s => Over f l ow <= ' 0' ;
end case;
end pr ocess;
end;
S OL U T I O N S 145
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
A 2-bit left shifter creates the output by appending two zeros to the least
significant bits of the input and dropping the two most significant bits.
FIGURE 5.3 2-bit left shifter, 32-bit input and output
2-bit Left Shifter
Exercise 5.15
A
31
.
.
.
A
30
A
29
A
28
A
3
A
2
A
1
A
0
.
.
.
Y
31
Y
30
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
.
.
.
SystemVerilog
modul e l ef t shi f t 2_32( i nput l ogi c [ 31: 0] a,
out put l ogi c [ 31: 0] y) ;
assi gn y = {a[ 29: 0] , 2' b0};
endmodul e
VHDL
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
ent i t y l ef t shi f t 2_32 i s
por t ( a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e synt h of l ef t shi f t 2_32 i s
begi n
y <= a( 29 downt o 0) & " 00";
end;
146 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
FIGURE 5.4 8-bit left shifter using 24 2:1 multiplexers
Exercise 5.17
(a) B =0, C =A, k =shamt
A
7
A
6
A
5
A
4
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
3
A
2
A
1
A
0
Y
7
Y
5
Y
3
Y
1
A
6
A
5
A
4
A
3
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
A
2
A
1
A
0
Y
6
Y
4
Y
2
Y
0
shamt
0
shamt
1
shamt
2
S OL U T I O N S 147
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(b) B =A
N-1
(the most significant bit of A), repeated N times to fill all N bits
of B
(c) B =A, C =0, k =N - shamt
(d) B = A, C = A, k = shamt
(e) B = A, C = A, k = N - shamt
Exercise 5.19
t
pd_DIV4
=4 (4t
FA
+ t
MUX
) =16t
FA
+ 4t
MUX
t
pd_DIVN
=N
2
t
FA
+ Nt
MUX
Exercise 5.21
FIGURE 5.5 Sign extension unit (a) symbol, (b) underlying hardware
A
3
A
2
A
1
A
0
Y
3
Y
2
Y
1
Y
0
Y
7
Y
6
Y
5
Y
4
Sign Extend
4 8
(a) (b)
A
3:0
Y
7:0
SystemVerilog
modul e si gnext 4_8( i nput l ogi c [ 3: 0] a,
out put l ogi c [ 7: 0] y) ;
assi gn y = { {4{a[ 3] }}, a};
endmodul e
VHDL
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
ent i t y si gnext 4_8 i s
por t ( a: i n STD_LOGI C_VECTOR( 3 downt o 0) ;
y: out STD_LOGI C_VECTOR( 7 downt o 0) ) ;
end;
ar chi t ect ur e synt h of si gnext 4_8 i s
begi n
148 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 5.23
Exercise 5.25
(a) 1000 1101 . 1001 0000 =0x8D90
(b) 0010 1010 . 0101 0000 =0x2A50
(c) 1001 0001 . 0010 1000 =0x9128
Exercise 5.27
(a) 1111 0010 . 0111 0000 =0xF270
(b) 0010 1010 . 0101 0000 =0x2A50
(c) 1110 1110 . 1101 1000 =0xEED8
Exercise 5.29
(a) -1101.1001 =-1.1011001 2
3
Thus, the biased exponent =127 +3 =130 =1000 0010
2
In IEEE 754 single-precision floating-point format:
1 1000 0010 101 1001 0000 0000 0000 0000 =0xC1590000
(b) 101010.0101 =1.010100101 2
5
Thus, the biased exponent =127 +5 =132 =1000 0100
2
In IEEE 754 single-precision floating-point format:
0 1000 0100 010 1001 0100 0000 0000 0000 =0x42294000
(c) -10001.00101 =-1.000100101 2
4
Thus, the biased exponent =127 +4 =131 =1000 0011
2
In IEEE 754 single-precision floating-point format:
1 1000 0011 000 1001 0100 0000 0000 0000 =0xC1894000
111001.000
001001 0
1100
1100
100.110
110 0
-
-
11 00
11 00 -
0
S OL U T I O N S 149
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 5.31
(a) 5.5
(b) -0000.0001
2
=-0.0625
(c) -8
Exercise 5.33
When adding two floating point numbers, the number with the smaller ex-
ponent is shifted to preserve the most significant bits. For example, suppose we
were adding the two floating point numbers 1.0 2
0
and 1.0 2
-27
. We make
the two exponents equal by shifting the second number right by 27 bits. Because
the mantissa is limited to 24 bits, the second number (1.000 0000 0000 0000
0000 2
-27
) becomes 0.000 0000 0000 0000 0000 2
0
, because the 1 is shifted
off to the right. If we had shifted the number with the larger exponent (1.0 2
0
)
to the left, we would have shifted off the more significant bits (on the order of
2
0
instead of on the order of 2
-27
).
Exercise 5.35
(a)
0xC0D20004 =1 1000 0001 101 0010 0000 0000 0000 0100
=- 1.101 0010 0000 0000 0000 01 2
2
0x72407020 =0 1110 0100 100 0000 0111 0000 0010 0000
= 1.100 0000 0111 0000 001 2
101
When adding these two numbers together, 0xC0D20004 becomes:
0 2
101
because all of the significant bits shift off the right when making
the exponents equal. Thus, the result of the addition is simply the second num-
ber:
0x72407020
(b)
0xC0D20004 =1 1000 0001 101 0010 0000 0000 0000 0100
=- 1.101 0010 0000 0000 0000 01 2
2
0x40DC0004 =0 1000 0001 101 1100 0000 0000 0000 0100
=1.101 1100 0000 0000 0000 01 2
2
1.101 1100 0000 0000 0000 01 2
2
150 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
- 1.101 0010 0000 0000 0000 01 2
2
= 0.000 1010 2
2
= 1.010 2
-2
=0 0111 1101 010 0000 0000 0000 0000 0000
=0x3EA00000
(c)
0x5FBE4000 =0 1011 1111 011 1110 0100 0000 0000 0000 0000
= 1.011 1110 01 2
64
0x3FF80000 =0 0111 1111 111 1000 0000 0000 0000 0000
= 1.111 1 2
0
0xDFDE4000 =1 1011 1111 101 1110 0100 0000 0000 0000 0000
=- 1.101 1110 01 2
64
Thus, (1.011 1110 01 2
64
+1.111 1 2
0
) =1.011 1110 01 2
64
And, (1.011 1110 01 2
64
+1.111 1 2
0
) - 1.101 1110 01 2
64
=
- 0.01 2
64
=-1.0 2
64
=1 1011 1101 000 0000 0000 0000 0000 0000
= 0xDE800000
This is counterintuitive because the second number (0x3FF80000) does not
affect the result because its order of magnitude is less than 2
23
of the other num-
bers. This second numbers significant bits are shifted off when the exponents
are made equal.
Exercise 5.37
(a) 2(2
31
- 1 - 2
23
) =2
32
- 2 - 2
24
=4,278,190,078
(b) 2(2
31
- 1) =2
32
- 2 =4,294,967,294
(c) and NaN are given special representations because they are often used in
calculations and in representing results. These values also give useful information to the
user as return values, instead of returning garbage upon overflow, underflow, or divide
by zero.
Exercise 5.39

S OL U T I O N S 151
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
FIGURE 5.6 Floating-point adder hardware: (a) block diagram, (b) underlying hardware
-
32
[30:23] [22:0]
A
31:0
ExpA
7:0
MantA
23:0
ExpB
7:0
ExpA
7:0
-
[7]
24
32
[30:23] [22:0]
B
31:0
ExpB
7:0
MantB
23:0
24
0
1
shamt
7:0
ExpA < ExpB
Exponent
Compare
ExpB
7:0
ExpA
7:0
8 8
8 8
Exp
7:0
shamt
7:0
ExpA<ExpB
Shift
Mantissa
MantA
23:0
MantB
23:0
24 24
24
ExpA<ExpB
Add Mantissas
and Normalize
MantA
23:0
MantB
23:0
24 24
24
Fract
22:0
ExpA<ExpB
24
S
31:0
32
[30:23] [22:0] [31]
0
1
Exp
7:0
>>
[4:0]
0
1
MantA
23:0
MantB
23:0
ExpA < ExpB shamt
7:0
24
ShiftedMant
23:0
0
1
shamt
7:0
[7]
[6]
[5]
[4]
[3]
24 24
+
0 1
0
1
MantB
23:0
MantA
23:0
ExpA < ExpB
ShiftedMant
23:0
ShiftedMant
23:0
ShiftedMant
23:0
[23:1] [22:0]
25
[24]
23
Fract
22:0
Exp
7:0 Fract
22:0
E
x
p
o
n
e
n
t

C
o
m
p
a
r
e
S
h
i
f
t

M
a
n
t
i
s
s
a
A
d
d

M
a
n
t
i
s
s
a
s

a
n
d

N
o
r
m
a
l
i
z
e
(a) (b)
152 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
SystemVerilog
modul e f padd( i nput l ogi c [ 31: 0] a, b,
out put l ogi c [ 31: 0] s) ;
l ogi c [ 7: 0] expa, expb, exp_pr e, exp, shamt ;
l ogi c al essb;
l ogi c [ 23: 0] mant a, mant b, shmant ;
l ogi c [ 22: 0] f r act ;
assi gn {expa, mant a} = {a[ 30: 23] , 1' b1, a[ 22: 0] };
assi gn {expb, mant b} = {b[ 30: 23] , 1' b1, b[ 22: 0] };
assi gn s = {1' b0, exp, f r act };
expcomp expcomp1( expa, expb, al essb, exp_pr e,
shamt ) ;
shi f t mant shi f t mant 1( al essb, mant a, mant b,
shamt , shmant ) ;
addmant addmant 1( al essb, mant a, mant b,
shmant , exp_pr e, f r act , exp) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use I EEE. STD_LOGI C_UNSI GNED. al l ;
use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y f padd i s
por t ( a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
s: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e synt h of f padd i s
component expcomp
por t ( expa, expb: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
al essb: i nout STD_LOGI C;
exp, shamt : out STD_LOGI C_VECTOR( 7 downt o 0) ) ;
end component ;
component shi f t mant
por t ( al essb: i n STD_LOGI C;
mant a: i n STD_LOGI C_VECTOR( 23 downt o 0) ;
mant b: i n STD_LOGI C_VECTOR( 23 downt o 0) ;
shamt : i n STD_LOGI C_VECTOR( 7 downt o 0) ;
shmant : out STD_LOGI C_VECTOR( 23 downt o 0) ) ;
end component ;
component addmant
por t ( al essb: i n STD_LOGI C;
mant a: i n STD_LOGI C_VECTOR( 23 downt o 0) ;
mant b: i n STD_LOGI C_VECTOR( 23 downt o 0) ;
shmant : i n STD_LOGI C_VECTOR( 23 downt o 0) ;
exp_pr e: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
f r act : out STD_LOGI C_VECTOR( 22 downt o 0) ;
exp: out STD_LOGI C_VECTOR( 7 downt o 0) ) ;
end component ;
si gnal expa, expb: STD_LOGI C_VECTOR( 7 downt o 0) ;
si gnal exp_pr e, exp: STD_LOGI C_VECTOR( 7 downt o 0) ;
si gnal shamt : STD_LOGI C_VECTOR( 7 downt o 0) ;
si gnal al essb: STD_LOGI C;
si gnal mant a: STD_LOGI C_VECTOR( 23 downt o 0) ;
si gnal mant b: STD_LOGI C_VECTOR( 23 downt o 0) ;
si gnal shmant : STD_LOGI C_VECTOR( 23 downt o 0) ;
si gnal f r act : STD_LOGI C_VECTOR( 22 downt o 0) ;
begi n
expa <= a( 30 downt o 23) ;
mant a <= ' 1' & a( 22 downt o 0) ;
expb <= b( 30 downt o 23) ;
mant b <= ' 1' & b( 22 downt o 0) ;
s <= ' 0' & exp & f r act ;
expcomp1: expcomp
por t map( expa, expb, al essb, exp_pr e, shamt ) ;
shi f t mant 1: shi f t mant
por t map( al essb, mant a, mant b, shamt , shmant ) ;
addmant 1: addmant
por t map( al essb, mant a, mant b, shmant ,
exp_pr e, f r act , exp) ;
end;
S OL U T I O N S 153
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(continued from previous page)
(continued on next page)
SystemVerilog
modul e expcomp( i nput l ogi c [ 7: 0] expa, expb,
out put l ogi c al essb,
out put l ogi c [ 7: 0] exp, shamt ) ;
l ogi c [ 7: 0] ami nusb, bmi nusa;
assi gn ami nusb = expa - expb;
assi gn bmi nusa = expb - expa;
assi gn al essb = ami nusb[ 7] ;
al ways_comb
i f ( al essb) begi n
exp = expb;
shamt = bmi nusa;
end
el se begi n
exp = expa;
shamt = ami nusb;
end
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use I EEE. STD_LOGI C_UNSI GNED. al l ;
use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y expcomp i s
por t ( expa, expb: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
al essb: i nout STD_LOGI C;
exp, shamt : out STD_LOGI C_VECTOR( 7 downt o 0) ) ;
end;
ar chi t ect ur e synt h of expcomp i s
si gnal ami nusb: STD_LOGI C_VECTOR( 7 downt o 0) ;
si gnal bmi nusa: STD_LOGI C_VECTOR( 7 downt o 0) ;
begi n
ami nusb <= expa - expb;
bmi nusa <= expb - expa;
al essb <= ami nusb( 7) ;
exp <= expb when al essb = ' 1' el se expa;
shamt <= bmi nusa when al essb = ' 1' el se ami nusb;
end;
154 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(continued from previous page)
SystemVerilog
modul e shi f t mant ( i nput l ogi c al essb,
i nput l ogi c [ 23: 0] mant a, mant b,
i nput l ogi c [ 7: 0] shamt ,
out put l ogi c [ 23: 0] shmant ) ;
l ogi c [ 23: 0] shi f t edval ;

assi gn shi f t edval = al essb ?
( mant a >> shamt ) : ( mant b >> shamt ) ;

al ways_comb
i f ( shamt [ 7] | shamt [ 6] | shamt [ 5] |
( shamt [ 4] & shamt [ 3] ) )
shmant = 24' b0;
el se
shmant = shi f t edval ;
endmodul e
modul e addmant ( i nput l ogi c al essb,
i nput l ogi c [ 23: 0] mant a,
mant b, shmant ,
i nput l ogi c [ 7: 0] exp_pr e,
out put l ogi c [ 22: 0] f r act ,
out put l ogi c [ 7: 0] exp) ;
l ogi c [ 24: 0] addr esul t ;
l ogi c [ 23: 0] addval ;

assi gn addval = al essb ? mant b : mant a;
assi gn addr esul t = shmant + addval ;
assi gn f r act = addr esul t [ 24] ?
addr esul t [ 23: 1] :
addr esul t [ 22: 0] ;
assi gn exp = addr esul t [ 24] ?
( exp_pr e + 1) :
exp_pr e;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use i eee. numer i c_st d. al l ;
use I EEE. st d_l ogi c_unsi gned. al l ;
ent i t y shi f t mant i s
por t ( al essb: i n STD_LOGI C;
mant a: i n STD_LOGI C_VECTOR( 23 downt o 0) ;
mant b: i n STD_LOGI C_VECTOR( 23 downt o 0) ;
shamt : i n STD_LOGI C_VECTOR( 7 downt o 0) ;
shmant : out STD_LOGI C_VECTOR( 23 downt o 0) ) ;
end;
ar chi t ect ur e synt h of shi f t mant i s
si gnal shi f t edval : unsi gned ( 23 downt o 0) ;
si gnal shi f t amt _vect or : STD_LOGI C_VECTOR ( 7 downt o
0) ;
begi n
shi f t edval <= SHI FT_RI GHT( unsi gned( mant a) , t o_i n-
t eger ( unsi gned( shamt ) ) ) when al essb = ' 1'
el se SHI FT_RI GHT( unsi gned( mant b) , t o_i n-
t eger ( unsi gned( shamt ) ) ) ;
shmant <= X" 000000" when ( shamt > 22)
el se STD_LOGI C_VECTOR( shi f t edval ) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use I EEE. STD_LOGI C_UNSI GNED. al l ;
use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y addmant i s
por t ( al essb: i n STD_LOGI C;
mant a: i n STD_LOGI C_VECTOR( 23 downt o 0) ;
mant b: i n STD_LOGI C_VECTOR( 23 downt o 0) ;
shmant : i n STD_LOGI C_VECTOR( 23 downt o 0) ;
exp_pr e: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
f r act : out STD_LOGI C_VECTOR( 22 downt o 0) ;
exp: out STD_LOGI C_VECTOR( 7 downt o 0) ) ;
end;
ar chi t ect ur e synt h of addmant i s
si gnal addr esul t : STD_LOGI C_VECTOR( 24 downt o 0) ;
si gnal addval : STD_LOGI C_VECTOR( 23 downt o 0) ;
begi n
addval <= mant b when al essb = ' 1' el se mant a;
addr esul t <= ( ' 0' &shmant ) + addval ;
f r act <= addr esul t ( 23 downt o 1)
when addr esul t ( 24) = ' 1'
el se addr esul t ( 22 downt o 0) ;
exp <= ( exp_pr e + 1)
when addr esul t ( 24) = ' 1'
el se exp_pr e;
end;
S OL U T I O N S 155
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 5.41
(a) Figure on next page
156 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

S OL U T I O N S 157
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
1
6
:
1
5
1
5
1
8
:
1
7
1
7
:
1
5
1
8
:
1
5
1
6
1
7
1
8
2
0
:
1
9
1
9
2
2
:
2
1
2
1
:
1
9
2
2
:
1
9
2
0
2
1
2
2
2
1
:
1
5
2
2
:
1
5
1
9
:
1
5
2
0
:
1
5
2
4
:
2
3
2
6
:
2
5
2
5
:
2
3
2
6
:
2
3
2
4
2
5
2
6
2
8
:
2
7
2
7
3
0
:
2
9
2
9
:
2
7
3
0
:
2
7
2
8
2
9
3
02
9
:
2
3
3
0
:
2
3
2
7
:
2
3
2
8
:
2
3
2
5
:
1
5
2
6
:
1
5
2
3
:
1
5
2
4
:
1
5
2
9
:
1
5
3
0
:
1
5
2
7
:
1
5
2
8
:
1
5
3
1
1
6
1
7
1
8
1
9
2
0
2
1
2
2
2
3
2
4
2
5
2
6
2
7
2
8
2
9
3
0
3
1
B
i
A
i
G
i
:
i
P
i
:
i
G
k
-
1
:
j
P
k
-
1
:
j G
i
:
k
P
i
:
k
G
i
:
j
P
i
:
j
i
i
:
j
B
i
A
i
G
i
-
1
:
-
1S
i
i
L
e
g
e
n
d
2
3
0
:
-
1
-
1
2
:
1
1
:
-
1
2
:
-
1
0
1
2
4
:
3
3
6
:
5
5
:
3
6
:
3
4
5
6
5
:
-
1
6
:
-
1
3
:
-
1
4
:
-
1
8
:
7
7
1
0
:
9
9
:
7
1
0
:
7
8
9
1
0
1
2
:
1
1
1
1
1
4
:
1
3
1
3
:
1
1
1
4
:
1
1
1
2
1
3
1
4
1
3
:
7
1
4
:
7
1
1
:
7
1
2
:
7
9
:
-
1
1
0
:
-
1
7
:
-
1
8
:
-
1
1
3
:
-
1
1
4
:
-
1
1
1
:
-
1
1
2
:
-
1
0
1
2
3
4
5
6
7
8
9
1
0
1
1
1
2
1
3
1
4
1
5
2
5
:
-
1
2
6
:
-
1
2
3
:
-
1
2
4
:
-
1
2
9
:
-
1
3
0
:
-
1
2
7
:
-
1
2
8
:
-
1
1
8
:
-
1
1
5
:
-
1
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6
:
-
1
2
1
:
-
1
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2
:
-
1
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9
:
-
1
2
0
:
-
1
1
7
:
-
1
R
o
w

1
R
o
w

2
R
o
w

3
R
o
w

4
R
o
w

5
158 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
5.41 (b)
SystemVerilog
modul e pr ef i xadd( i nput l ogi c [ 31: 0] a, b,
i nput l ogi c ci n,
out put l ogi c [ 31: 0] s,
out put l ogi c cout ) ;
l ogi c [ 30: 0] p, g;
/ / p and g pr ef i xes f or r ows 1 - 5
l ogi c [ 15: 0] p1, p2, p3, p4, p5;
l ogi c [ 15: 0] g1, g2, g3, g4, g5;
pandg r ow0( a, b, p, g) ;
bl ackbox r ow1( {p[ 30] , p[ 28] , p[ 26] , p[ 24] , p[ 22] ,
p[ 20] , p[ 18] , p[ 16] , p[ 14] , p[ 12] ,
p[ 10] , p[ 8] , p[ 6] , p[ 4] , p[ 2] , p[ 0] },
{p[ 29] , p[ 27] , p[ 25] , p[ 23] , p[ 21] ,
p[ 19] , p[ 17] , p[ 15] , p[ 13] , p[ 11] ,
p[ 9] , p[ 7] , p[ 5] , p[ 3] , p[ 1] , 1' b0},
{g[ 30] , g[ 28] , g[ 26] , g[ 24] , g[ 22] ,
g[ 20] , g[ 18] , g[ 16] , g[ 14] , g[ 12] ,
g[ 10] , g[ 8] , g[ 6] , g[ 4] , g[ 2] , g[ 0] },
{g[ 29] , g[ 27] , g[ 25] , g[ 23] , g[ 21] ,
g[ 19] , g[ 17] , g[ 15] , g[ 13] , g[ 11] ,
g[ 9] , g[ 7] , g[ 5] , g[ 3] , g[ 1] , ci n},
p1, g1) ;
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y pr ef i xadd i s
por t ( a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
ci n: i n STD_LOGI C;
s: out STD_LOGI C_VECTOR( 31 downt o 0) ;
cout : out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of pr ef i xadd i s
component pgbl ock
por t ( a, b: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p, g: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end component ;
component pgbl ackbl ock i s
por t ( pi k, gi k: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
pkj , gkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
pi j : out STD_LOGI C_VECTOR( 15 downt o 0) ;
gi j : out STD_LOGI C_VECTOR( 15 downt o 0) ) ;
end component ;

component sumbl ock i s
por t ( a, b, g: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
s: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;

si gnal p, g: STD_LOGI C_VECTOR( 30 downt o 0) ;
si gnal pi k_1, pi k_2, pi k_3, pi k_4, pi k_5,
gi k_1, gi k_2, gi k_3, gi k_4, gi k_5,
pkj _1, pkj _2, pkj _3, pkj _4, pkj _5,
gkj _1, gkj _2, gkj _3, gkj _4, gkj _5,
p1, p2, p3, p4, p5,
g1, g2, g3, g4, g5:
STD_LOGI C_VECTOR( 15 downt o 0) ;
si gnal g6: STD_LOGI C_VECTOR( 31 downt o 0) ;
begi n
r ow0: pgbl ock
por t map( a( 30 downt o 0) , b( 30 downt o 0) , p, g) ;
pi k_1 <=
( p( 30) &p( 28) &p( 26) &p( 24) &p( 22) &p( 20) &p( 18) &p( 16) &
p( 14) &p( 12) &p( 10) &p( 8) &p( 6) &p( 4) &p( 2) &p( 0) ) ;
gi k_1 <=
( g( 30) &g( 28) &g( 26) &g( 24) &g( 22) &g( 20) &g( 18) &g( 16) &
g( 14) &g( 12) &g( 10) &g( 8) &g( 6) &g( 4) &g( 2) &g( 0) ) ;
pkj _1 <=
( p( 29) &p( 27) &p( 25) &p( 23) &p( 21) &p( 19) &p( 17) &p( 15) &
p( 13) &p( 11) &p( 9) &p( 7) &p( 5) &p( 3) &p( 1) &' 0' ) ;
gkj _1 <=
( g( 29) &g( 27) &g( 25) &g( 23) &g( 21) &g( 19) &g( 17) &g( 15) &
g( 13) &g( 11) &g( 9) &g( 7) &g( 5) & g( 3) & g( 1) & ci n) ;

r ow1: pgbl ackbl ock
por t map( pi k_1, gi k_1, pkj _1, gkj _1,
p1, g1) ;
S OL U T I O N S 159
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(continued on next page)
(continued from previous page)
(continued on next page)
SystemVerilog
bl ackbox r ow2( {p1[ 15] , p[ 29] , p1[ 13] , p[ 25] , p1[ 11] ,
p[ 21] , p1[ 9] , p[ 17] , p1[ 7] , p[ 13] ,
p1[ 5] , p[ 9] , p1[ 3] , p[ 5] , p1[ 1] , p[ 1] },
{{2{p1[ 14] }}, {2{p1[ 12] }}, {2{p1[ 10] }},
{2{p1[ 8] }}, {2{p1[ 6] }}, {2{p1[ 4] }},
{2{p1[ 2] }}, {2{p1[ 0] }}},
{g1[ 15] , g[ 29] , g1[ 13] , g[ 25] , g1[ 11] ,
g[ 21] , g1[ 9] , g[ 17] , g1[ 7] , g[ 13] ,
g1[ 5] , g[ 9] , g1[ 3] , g[ 5] , g1[ 1] , g[ 1] },
{{2{g1[ 14] }}, {2{g1[ 12] }}, {2{g1[ 10] }},
{2{g1[ 8] }}, {2{g1[ 6] }}, {2{g1[ 4] }},
{2{g1[ 2] }}, {2{g1[ 0] }}},
p2, g2) ;
bl ackbox r ow3( {p2[ 15] , p2[ 14] , p1[ 14] , p[ 27] , p2[ 11] ,
p2[ 10] , p1[ 10] , p[ 19] , p2[ 7] , p2[ 6] ,
p1[ 6] , p[ 11] , p2[ 3] , p2[ 2] , p1[ 2] , p[ 3] },
{{4{p2[ 13] }}, {4{p2[ 9] }}, {4{p2[ 5] }},
{4{p2[ 1] }}},
{g2[ 15] , g2[ 14] , g1[ 14] , g[ 27] , g2[ 11] ,
g2[ 10] , g1[ 10] , g[ 19] , g2[ 7] , g2[ 6] ,
g1[ 6] , g[ 11] , g2[ 3] , g2[ 2] , g1[ 2] , g[ 3] },
{{4{g2[ 13] }}, {4{g2[ 9] }}, {4{g2[ 5] }},
{4{g2[ 1] }}},
p3, g3) ;
VHDL
pi k_2 <= p1( 15) &p( 29) &p1( 13) &p( 25) &p1( 11) &
p( 21) &p1( 9) &p( 17) &p1( 7) &p( 13) &
p1( 5) &p( 9) &p1( 3) &p( 5) &p1( 1) &p( 1) ;
gi k_2 <= g1( 15) &g( 29) &g1( 13) &g( 25) &g1( 11) &
g( 21) &g1( 9) &g( 17) &g1( 7) &g( 13) &
g1( 5) &g( 9) &g1( 3) &g( 5) &g1( 1) &g( 1) ;

pkj _2 <=
p1( 14) &p1( 14) &p1( 12) &p1( 12) &p1( 10) &p1( 10) &
p1( 8) &p1( 8) &p1( 6) &p1( 6) &p1( 4) &p1( 4) &
p1( 2) &p1( 2) &p1( 0) &p1( 0) ;

gkj _2 <=
g1( 14) &g1( 14) &g1( 12) &g1( 12) &g1( 10) &g1( 10) &
g1( 8) &g1( 8) &g1( 6) &g1( 6) &g1( 4) &g1( 4) &
g1( 2) &g1( 2) &g1( 0) &g1( 0) ;

r ow2: pgbl ackbl ock
por t map( pi k_2, gi k_2, pkj _2, gkj _2,
p2, g2) ;
pi k_3 <= p2( 15) &p2( 14) &p1( 14) &p( 27) &p2( 11) &
p2( 10) &p1( 10) &p( 19) &p2( 7) &p2( 6) &
p1( 6) &p( 11) &p2( 3) &p2( 2) &p1( 2) &p( 3) ;
gi k_3 <= g2( 15) &g2( 14) &g1( 14) &g( 27) &g2( 11) &
g2( 10) &g1( 10) &g( 19) &g2( 7) &g2( 6) &
g1( 6) &g( 11) &g2( 3) &g2( 2) &g1( 2) &g( 3) ;
pkj _3 <= p2( 13) &p2( 13) &p2( 13) &p2( 13) &
p2( 9) &p2( 9) &p2( 9) &p2( 9) &
p2( 5) &p2( 5) &p2( 5) &p2( 5) &
p2( 1) &p2( 1) &p2( 1) &p2( 1) ;
gkj _3 <= g2( 13) &g2( 13) &g2( 13) &g2( 13) &
g2( 9) &g2( 9) &g2( 9) &g2( 9) &
g2( 5) &g2( 5) &g2( 5) &g2( 5) &
g2( 1) &g2( 1) &g2( 1) &g2( 1) ;

r ow3: pgbl ackbl ock
por t map( pi k_3, gi k_3, pkj _3, gkj _3, p3, g3) ;
160 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(continued on next page)
SystemVerilog
bl ackbox r ow4( {p3[ 15: 12] , p2[ 13: 12] ,
p1[ 12] , p[ 23] , p3[ 7: 4] ,
p2[ 5: 4] , p1[ 4] , p[ 7] },
{{8{p3[ 11] }}, {8{p3[ 3] }}},
{g3[ 15: 12] , g2[ 13: 12] ,
g1[ 12] , g[ 23] , g3[ 7: 4] ,
g2[ 5: 4] , g1[ 4] , g[ 7] },
{{8{g3[ 11] }}, {8{g3[ 3] }}},
p4, g4) ;
bl ackbox r ow5( {p4[ 15: 8] , p3[ 11: 8] , p2[ 9: 8] ,
p1[ 8] , p[ 15] },
{{16{p4[ 7] }}},
{g4[ 15: 8] , g3[ 11: 8] , g2[ 9: 8] ,
g1[ 8] , g[ 15] },
{{16{g4[ 7] }}},
p5, g5) ;
sumr ow6( {g5, g4[ 7: 0] , g3[ 3: 0] , g2[ 1: 0] , g1[ 0] , ci n},
a, b, s) ;
/ / gener at e cout
assi gn cout = ( a[ 31] & b[ 31] ) |
( g5[ 15] & ( a[ 31] | b[ 31] ) ) ;
endmodul e
VHDL
pi k_4 <= p3( 15 downt o 12) &p2( 13 downt o 12) &
p1( 12) &p( 23) &p3( 7 downt o 4) &
p2( 5 downt o 4) &p1( 4) &p( 7) ;
gi k_4 <= g3( 15 downt o 12) &g2( 13 downt o 12) &
g1( 12) &g( 23) &g3( 7 downt o 4) &
g2( 5 downt o 4) &g1( 4) &g( 7) ;
pkj _4 <= p3( 11) &p3( 11) &p3( 11) &p3( 11) &
p3( 11) &p3( 11) &p3( 11) &p3( 11) &
p3( 3) &p3( 3) &p3( 3) &p3( 3) &
p3( 3) &p3( 3) &p3( 3) &p3( 3) ;
gkj _4 <= g3( 11) &g3( 11) &g3( 11) &g3( 11) &
g3( 11) &g3( 11) &g3( 11) &g3( 11) &
g3( 3) &g3( 3) &g3( 3) &g3( 3) &
g3( 3) &g3( 3) &g3( 3) &g3( 3) ;
r ow4: pgbl ackbl ock
por t map( pi k_4, gi k_4, pkj _4, gkj _4, p4, g4) ;
pi k_5 <= p4( 15 downt o 8) &p3( 11 downt o 8) &
p2( 9 downt o 8) &p1( 8) &p( 15) ;
gi k_5 <= g4( 15 downt o 8) &g3( 11 downt o 8) &
g2( 9 downt o 8) &g1( 8) &g( 15) ;
pkj _5 <= p4( 7) &p4( 7) &p4( 7) &p4( 7) &
p4( 7) &p4( 7) &p4( 7) &p4( 7) &
p4( 7) &p4( 7) &p4( 7) &p4( 7) &
p4( 7) &p4( 7) &p4( 7) &p4( 7) ;
gkj _5 <= g4( 7) &g4( 7) &g4( 7) &g4( 7) &
g4( 7) &g4( 7) &g4( 7) &g4( 7) &
g4( 7) &g4( 7) &g4( 7) &g4( 7) &
g4( 7) &g4( 7) &g4( 7) &g4( 7) ;

r ow5: pgbl ackbl ock
por t map( pi k_5, gi k_5, pkj _5, gkj _5, p5, g5) ;

g6 <= ( g5 & g4( 7 downt o 0) & g3( 3 downt o 0) &
g2( 1 downt o 0) & g1( 0) & ci n) ;
r ow6: sumbl ock
por t map( g6, a, b, s) ;
- - gener at e cout
cout <= ( a( 31) and b( 31) ) or
( g6( 31) and ( a( 31) or b( 31) ) ) ;

end;
S OL U T I O N S 161
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(continued from previous page)
SystemVerilog
modul e pandg( i nput l ogi c [ 30: 0] a, b,
out put l ogi c [ 30: 0] p, g) ;
assi gn p = a | b;
assi gn g = a & b;
endmodul e
modul e bl ackbox( i nput l ogi c [ 15: 0] pl ef t , pr i ght ,
gl ef t , gr i ght ,
out put l ogi c [ 15: 0] pnext , gnext ) ;
assi gn pnext = pl ef t & pr i ght ;
assi gn gnext = pl ef t & gr i ght | gl ef t ;
endmodul e
modul e sum( i nput l ogi c [ 31: 0] g, a, b,
out put l ogi c [ 31: 0] s) ;
assi gn s = a ^ b ^ g;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y pgbl ock i s
por t ( a, b: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p, g: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end;
ar chi t ect ur e synt h of pgbl ock i s
begi n
p <= a or b;
g <= a and b;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y pgbl ackbl ock i s
por t ( pi k, gi k, pkj , gkj :
i n STD_LOGI C_VECTOR( 15 downt o 0) ;
pi j , gi j :
out STD_LOGI C_VECTOR( 15 downt o 0) ) ;
end;
ar chi t ect ur e synt h of pgbl ackbl ock i s
begi n
pi j <= pi k and pkj ;
gi j <= gi k or ( pi k and gkj ) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y sumbl ock i s
por t ( g, a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
s: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e synt h of sumbl ock i s
begi n
s <= a xor b xor g;
end;
162 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
5.41 (c) Using Equation 5.11 to find the delay of the prefix adder:
We find the delays for each block:
t
pg
=100 ps
t
pg_prefix
=200 ps
t
XOR
=100 ps
Thus,
t
PA
=[100 +5(200) +100] ps =1200 ps =1.2 ns
5.41 (d) To make a pipelined prefix adder, add pipeline registers between
each of the rows of the prefix adder. Now each stage will take 200 ps plus the
t
PA
t
pg
N t
pg_prefix
( ) t
XOR
+
2
log + =
S OL U T I O N S 163
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
sequencing overhead, t
pq
+t
setup
=80ps. Thus each cycle is 280 ps and the de-
sign can run at 3.57 GHz.
164 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
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S OL U T I O N S 165
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
5.41 (e)
SystemVerilog
modul e pr ef i xaddpi pe( i nput l ogi c cl k, ci n,
i nput l ogi c [ 31: 0] a, b,
out put l ogi c [ 31: 0] s, out put cout ) ;
/ / p and g pr ef i xes f or r ows 0 - 5
l ogi c [ 30: 0] p0, p1, p2, p3, p4, p5;
l ogi c [ 30: 0] g0, g1, g2, g3, g4, g5;
l ogi c p_1_0, p_1_1, p_1_2, p_1_3, p_1_4, p_1_5,
g_1_0, g_1_1, g_1_2, g_1_3, g_1_4, g_1_5;

/ / pi pel i ne val ues f or a and b
l ogi c [ 31: 0] a0, a1, a2, a3, a4, a5,
b0, b1, b2, b3, b4, b5;
/ / r ow 0
f l op #( 2) f l op0_pg_1( cl k, {1' b0, ci n}, {p_1_0, g_1_0}) ;
pandg r ow0( cl k, a[ 30: 0] , b[ 30: 0] , p0, g0) ;
/ / r ow 1
f l op #( 2) f l op1_pg_1( cl k, {p_1_0, g_1_0}, {p_1_1, g_1_1}) ;
f l op #( 30) f l op1_pg( cl k,
{p0[ 29] , p0[ 27] , p0[ 25] , p0[ 23] , p0[ 21] , p0[ 19] , p0[ 17] , p0[ 15] ,
p0[ 13] , p0[ 11] , p0[ 9] , p0[ 7] , p0[ 5] , p0[ 3] , p0[ 1] ,
g0[ 29] , g0[ 27] , g0[ 25] , g0[ 23] , g0[ 21] , g0[ 19] , g0[ 17] , g0[ 15] ,
g0[ 13] , g0[ 11] , g0[ 9] , g0[ 7] , g0[ 5] , g0[ 3] , g0[ 1] },
{p1[ 29] , p1[ 27] , p1[ 25] , p1[ 23] , p1[ 21] , p1[ 19] , p1[ 17] , p1[ 15] ,
p1[ 13] , p1[ 11] , p1[ 9] , p1[ 7] , p1[ 5] , p1[ 3] , p1[ 1] ,
g1[ 29] , g1[ 27] , g1[ 25] , g1[ 23] , g1[ 21] , g1[ 19] , g1[ 17] , g1[ 15] ,
g1[ 13] , g1[ 11] , g1[ 9] , g1[ 7] , g1[ 5] , g1[ 3] , g1[ 1] }) ;
bl ackbox r ow1( cl k,
{p0[ 30] , p0[ 28] , p0[ 26] , p0[ 24] , p0[ 22] ,
p0[ 20] , p0[ 18] , p0[ 16] , p0[ 14] , p0[ 12] ,
p0[ 10] , p0[ 8] , p0[ 6] , p0[ 4] , p0[ 2] , p0[ 0] },

{p0[ 29] , p0[ 27] , p0[ 25] , p0[ 23] , p0[ 21] ,
p0[ 19] , p0[ 17] , p0[ 15] , p0[ 13] , p0[ 11] ,
p0[ 9] , p0[ 7] , p0[ 5] , p0[ 3] , p0[ 1] , 1' b0},

{g0[ 30] , g0[ 28] , g0[ 26] , g0[ 24] , g0[ 22] ,
g0[ 20] , g0[ 18] , g0[ 16] , g0[ 14] , g0[ 12] ,
g0[ 10] , g0[ 8] , g0[ 6] , g0[ 4] , g0[ 2] , g0[ 0] },

{g0[ 29] , g0[ 27] , g0[ 25] , g0[ 23] , g0[ 21] ,
g0[ 19] , g0[ 17] , g0[ 15] , g0[ 13] , g0[ 11] ,
g0[ 9] , g0[ 7] , g0[ 5] , g0[ 3] , g0[ 1] , g_1_0},

{p1[ 30] , p1[ 28] , p1[ 26] , p1[ 24] , p1[ 22] , p1[ 20] ,
p1[ 18] , p1[ 16] , p1[ 14] , p1[ 12] , p1[ 10] , p1[ 8] ,
p1[ 6] , p1[ 4] , p1[ 2] , p1[ 0] },

{g1[ 30] , g1[ 28] , g1[ 26] , g1[ 24] , g1[ 22] , g1[ 20] ,
g1[ 18] , g1[ 16] , g1[ 14] , g1[ 12] , g1[ 10] , g1[ 8] ,
g1[ 6] , g1[ 4] , g1[ 2] , g1[ 0] }) ;
/ / r ow 2
f l op #( 2) f l op2_pg_1( cl k, {p_1_1, g_1_1}, {p_1_2, g_1_2}) ;
f l op #( 30) f l op2_pg( cl k,
{p1[ 28: 27] , p1[ 24: 23] , p1[ 20: 19] , p1[ 16: 15] , p1[ 12: 11] ,
166 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
p1[ 8: 7] , p1[ 4: 3] , p1[ 0] ,
g1[ 28: 27] , g1[ 24: 23] , g1[ 20: 19] , g1[ 16: 15] , g1[ 12: 11] ,
g1[ 8: 7] , g1[ 4: 3] , g1[ 0] },
{p2[ 28: 27] , p2[ 24: 23] , p2[ 20: 19] , p2[ 16: 15] , p2[ 12: 11] ,
p2[ 8: 7] , p2[ 4: 3] , p2[ 0] ,
g2[ 28: 27] , g2[ 24: 23] , g2[ 20: 19] , g2[ 16: 15] , g2[ 12: 11] ,
g2[ 8: 7] , g2[ 4: 3] , g2[ 0] }) ;
bl ackbox r ow2( cl k,
{p1[ 30: 29] , p1[ 26: 25] , p1[ 22: 21] , p1[ 18: 17] , p1[ 14: 13] , p1[ 10: 9] , p1[ 6: 5] , p1[ 2: 1]
},

{ {2{p1[ 28] }}, {2{p1[ 24] }}, {2{p1[ 20] }}, {2{p1[ 16] }}, {2{p1[ 12] }},
{2{p1[ 8] }},
{2{p1[ 4] }}, {2{p1[ 0] }} },
{g1[ 30: 29] , g1[ 26: 25] , g1[ 22: 21] , g1[ 18: 17] , g1[ 14: 13] , g1[ 10: 9] , g1[ 6: 5] , g1[ 2: 1]
},

{ {2{g1[ 28] }}, {2{g1[ 24] }}, {2{g1[ 20] }}, {2{g1[ 16] }}, {2{g1[ 12] }},
{2{g1[ 8] }},
{2{g1[ 4] }}, {2{g1[ 0] }} },
{p2[ 30: 29] , p2[ 26: 25] , p2[ 22: 21] , p2[ 18: 17] , p2[ 14: 13] , p2[ 10: 9] , p2[ 6: 5] , p2[ 2: 1]
},
{g2[ 30: 29] , g2[ 26: 25] , g2[ 22: 21] , g2[ 18: 17] , g2[ 14: 13] , g2[ 10: 9] , g2[ 6: 5] , g2[ 2: 1]
} ) ;
/ / r ow 3
f l op #( 2) f l op3_pg_1( cl k, {p_1_2, g_1_2}, {p_1_3, g_1_3}) ;
f l op #( 30) f l op3_pg( cl k, {p2[ 26: 23] , p2[ 18: 15] , p2[ 10: 7] , p2[ 2: 0] ,
g2[ 26: 23] , g2[ 18: 15] , g2[ 10: 7] , g2[ 2: 0] },
{p3[ 26: 23] , p3[ 18: 15] , p3[ 10: 7] , p3[ 2: 0] ,
g3[ 26: 23] , g3[ 18: 15] , g3[ 10: 7] , g3[ 2: 0] }) ;
bl ackbox r ow3( cl k,
{p2[ 30: 27] , p2[ 22: 19] , p2[ 14: 11] , p2[ 6: 3] },
{ {4{p2[ 26] }}, {4{p2[ 18] }}, {4{p2[ 10] }}, {4{p2[ 2] }} },
{g2[ 30: 27] , g2[ 22: 19] , g2[ 14: 11] , g2[ 6: 3] },
{ {4{g2[ 26] }}, {4{g2[ 18] }}, {4{g2[ 10] }}, {4{g2[ 2] }} },
{p3[ 30: 27] , p3[ 22: 19] , p3[ 14: 11] , p3[ 6: 3] },
{g3[ 30: 27] , g3[ 22: 19] , g3[ 14: 11] , g3[ 6: 3] }) ;
/ / r ow 4
f l op #( 2) f l op4_pg_1( cl k, {p_1_3, g_1_3}, {p_1_4, g_1_4}) ;
f l op #( 30) f l op4_pg( cl k, {p3[ 22: 15] , p3[ 6: 0] ,
g3[ 22: 15] , g3[ 6: 0] },
{p4[ 22: 15] , p4[ 6: 0] ,
g4[ 22: 15] , g4[ 6: 0] }) ;

bl ackbox r ow4( cl k,
{p3[ 30: 23] , p3[ 14: 7] },
{ {8{p3[ 22] }}, {8{p3[ 6] }} },
{g3[ 30: 23] , g3[ 14: 7] },
{ {8{g3[ 22] }}, {8{g3[ 6] }} },
{p4[ 30: 23] , p4[ 14: 7] },
{g4[ 30: 23] , g4[ 14: 7] }) ;
/ / r ow 5
f l op #( 2) f l op5_pg_1( cl k, {p_1_4, g_1_4}, {p_1_5, g_1_5}) ;
f l op #( 30) f l op5_pg( cl k, {p4[ 14: 0] , g4[ 14: 0] },
{p5[ 14: 0] , g5[ 14: 0] }) ;

S OL U T I O N S 167
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
bl ackbox r ow5( cl k,
p4[ 30: 15] ,
{16{p4[ 14] }},
g4[ 30: 15] ,
{16{g4[ 14] }},
p5[ 30: 15] , g5[ 30: 15] ) ;
/ / pi pel i ne r egi st er s f or a and b
f l op #( 64) f l op0_ab( cl k, {a, b}, {a0, b0}) ;
f l op #( 64) f l op1_ab( cl k, {a0, b0}, {a1, b1}) ;
f l op #( 64) f l op2_ab( cl k, {a1, b1}, {a2, b2}) ;
f l op #( 64) f l op3_ab( cl k, {a2, b2}, {a3, b3}) ;
f l op #( 64) f l op4_ab( cl k, {a3, b3}, {a4, b4}) ;
f l op #( 64) f l op5_ab( cl k, {a4, b4}, {a5, b5}) ;

sumr ow6( cl k, {g5, g_1_5}, a5, b5, s) ;
/ / gener at e cout
assi gn cout = ( a5[ 31] & b5[ 31] ) | ( g5[ 30] & ( a5[ 31] | b5[ 31] ) ) ;
endmodul e
/ / submodul es
modul e pandg( i nput l ogi c cl k,
i nput l ogi c [ 30: 0] a, b,
out put l ogi c [ 30: 0] p, g) ;
al ways_f f @( posedge cl k)
begi n
p <= a | b;
g <= a & b;
end
endmodul e
modul e bl ackbox( i nput l ogi c cl k,
i nput l ogi c [ 15: 0] pl ef t , pr i ght , gl ef t , gr i ght ,
out put l ogi c [ 15: 0] pnext , gnext ) ;
al ways_f f @( posedge cl k)
begi n
pnext <= pl ef t & pr i ght ;
gnext <= pl ef t & gr i ght | gl ef t ;
end
endmodul e
modul e sum( i nput l ogi c cl k,
i nput l ogi c [ 31: 0] g, a, b,
out put l ogi c [ 31: 0] s) ;
al ways_f f @( posedge cl k)
s <= a ^ b ^ g;
endmodul e
modul e f l op
#( par amet er wi dt h = 8)
( i nput l ogi c cl k,
i nput l ogi c [ wi dt h- 1: 0] d,
out put l ogi c [ wi dt h- 1: 0] q) ;

al ways_f f @( posedge cl k)
q <= d;
endmodul e
168 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
5.41 (e)
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y pr ef i xaddpi pe i s
por t ( cl k: i n STD_LOGI C;
a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
ci n: i n STD_LOGI C;
s: out STD_LOGI C_VECTOR( 31 downt o 0) ;
cout : out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of pr ef i xaddpi pe i s
component pgbl ock
por t ( cl k: i n STD_LOGI C;
a, b: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p, g: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end component ;
component sumbl ock i s
por t ( cl k: i n STD_LOGI C;
a, b, g: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
s: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component f l op i s gener i c( wi dt h: i nt eger ) ;
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component f l op1 i s
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C;
q: out STD_LOGI C) ;
end component ;
component r ow1 i s
por t ( cl k: i n STD_LOGI C;
p0, g0: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p_1_0, g_1_0: i n STD_LOGI C;
p1, g1: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end component ;
component r ow2 i s
por t ( cl k: i n STD_LOGI C;
p1, g1: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p2, g2: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end component ;
component r ow3 i s
por t ( cl k: i n STD_LOGI C;
p2, g2: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p3, g3: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end component ;
component r ow4 i s
por t ( cl k: i n STD_LOGI C;
p3, g3: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p4, g4: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end component ;
component r ow5 i s
por t ( cl k: i n STD_LOGI C;
p4, g4: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p5, g5: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end component ;
S OL U T I O N S 169
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
- - p and g pr ef i xes f or r ows 0 - 5
si gnal p0, p1, p2, p3, p4, p5: STD_LOGI C_VECTOR( 30 downt o 0) ;
si gnal g0, g1, g2, g3, g4, g5: STD_LOGI C_VECTOR( 30 downt o 0) ;
- - p and g pr ef i xes f or col umn - 1, r ows 0 - 5
si gnal p_1_0, p_1_1, p_1_2, p_1_3, p_1_4, p_1_5,
g_1_0, g_1_1, g_1_2, g_1_3, g_1_4, g_1_5: STD_LOGI C;
- - pi pel i ne val ues f or a and b
si gnal a0, a1, a2, a3, a4, a5,
b0, b1, b2, b3, b4, b5: STD_LOGI C_VECTOR( 31 downt o 0) ;

- - f i nal gener at e si gnal
si gnal g5_al l : STD_LOGI C_VECTOR( 31 downt o 0) ;
begi n
- - p and g cal cul at i ons
r ow0_r eg: pgbl ock por t map( cl k, a( 30 downt o 0) , b( 30 downt o 0) , p0, g0) ;
r ow1_r eg: r ow1 por t map( cl k, p0, g0, p_1_0, g_1_0, p1, g1) ;
r ow2_r eg: r ow2 por t map( cl k, p1, g1, p2, g2) ;
r ow3_r eg: r ow3 por t map( cl k, p2, g2, p3, g3) ;
r ow4_r eg: r ow4 por t map( cl k, p3, g3, p4, g4) ;
r ow5_r eg: r ow5 por t map( cl k, p4, g4, p5, g5) ;
- - pi pel i ne r egi st er s f or a and b
f l op0_a: f l op gener i c map( 32) por t map ( cl k, a, a0) ;
f l op0_b: f l op gener i c map( 32) por t map ( cl k, b, b0) ;
f l op1_a: f l op gener i c map( 32) por t map ( cl k, a0, a1) ;
f l op1_b: f l op gener i c map( 32) por t map ( cl k, b0, b1) ;
f l op2_a: f l op gener i c map( 32) por t map ( cl k, a1, a2) ;
f l op2_b: f l op gener i c map( 32) por t map ( cl k, b1, b2) ;
f l op3_a: f l op gener i c map( 32) por t map ( cl k, a2, a3) ;
f l op3_b: f l op gener i c map( 32) por t map ( cl k, b2, b3) ;
f l op4_a: f l op gener i c map( 32) por t map ( cl k, a3, a4) ;
f l op4_b: f l op gener i c map( 32) por t map ( cl k, b3, b4) ;
f l op5_a: f l op gener i c map( 32) por t map ( cl k, a4, a5) ;
f l op5_b: f l op gener i c map( 32) por t map ( cl k, b4, b5) ;
- - pi pel i ne p and g f or col umn - 1
p_1_0 <= ' 0' ; f l op_1_g0: f l op1 por t map ( cl k, ci n, g_1_0) ;
f l op_1_p1: f l op1 por t map ( cl k, p_1_0, p_1_1) ;
f l op_1_g1: f l op1 por t map ( cl k, g_1_0, g_1_1) ;
f l op_1_p2: f l op1 por t map ( cl k, p_1_1, p_1_2) ;
f l op_1_g2: f l op1 por t map ( cl k, g_1_1, g_1_2) ;
f l op_1_p3: f l op1 por t map ( cl k, p_1_2, p_1_3) ; f l op_1_g3:
f l op1 por t map ( cl k, g_1_2, g_1_3) ;
f l op_1_p4: f l op1 por t map ( cl k, p_1_3, p_1_4) ;
f l op_1_g4: f l op1 por t map ( cl k, g_1_3, g_1_4) ;
f l op_1_p5: f l op1 por t map ( cl k, p_1_4, p_1_5) ;
f l op_1_g5: f l op1 por t map ( cl k, g_1_4, g_1_5) ;
- - gener at e sumand cout
g5_al l <= ( g5&g_1_5) ;
r ow6: sumbl ock por t map( cl k, g5_al l , a5, b5, s) ;
- - gener at e cout
cout <= ( a5( 31) and b5( 31) ) or ( g5( 30) and ( a5( 31) or b5( 31) ) ) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y pgbl ock i s
por t ( cl k: i n STD_LOGI C;
170 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
a, b: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p, g: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end;
ar chi t ect ur e synt h of pgbl ock i s
begi n
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
p <= a or b;
g <= a and b;
end i f ;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y bl ackbox i s
por t ( cl k: i n STD_LOGI C;
pi k, pkj , gi k, gkj :
i n STD_LOGI C_VECTOR( 15 downt o 0) ;
pi j , gi j :
out STD_LOGI C_VECTOR( 15 downt o 0) ) ;
end;
ar chi t ect ur e synt h of bl ackbox i s
begi n
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
pi j <= pi k and pkj ;
gi j <= gi k or ( pi k and gkj ) ;
end i f ;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y sumbl ock i s
por t ( cl k: i n STD_LOGI C;
g, a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
s: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;

ar chi t ect ur e synt h of sumbl ock i s
begi n
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
s <= a xor b xor g;
end i f ;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ; use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y f l op i s - - par amet er i zabl e f l i p f l op
gener i c( wi dt h: i nt eger ) ;
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e synt h of f l op i s
begi n
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
q <= d;
S OL U T I O N S 171
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
end i f ;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ; use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y f l op1 i s - - 1- bi t f l i p f l op
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C;
q: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of f l op1 i s
begi n
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
q <= d;
end i f ;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y r ow1 i s
por t ( cl k: i n STD_LOGI C;
p0, g0: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p_1_0, g_1_0: i n STD_LOGI C;
p1, g1: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end;
ar chi t ect ur e synt h of r ow1 i s
component bl ackbox i s
por t ( cl k: i n STD_LOGI C;
pi k, pkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
gi k, gkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
pi j : out STD_LOGI C_VECTOR( 15 downt o 0) ;
gi j : out STD_LOGI C_VECTOR( 15 downt o 0) ) ;
end component ;
component f l op i s gener i c( wi dt h: i nt eger ) ;
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
- - i nt er nal si gnal s f or cal cul at i ng p, g
si gnal pi k_0, gi k_0, pkj _0, gkj _0,
pi j _0, gi j _0: STD_LOGI C_VECTOR( 15 downt o 0) ;
- - i nt er nal si gnal s f or pi pel i ne r egi st er s
si gnal pg0_i n, pg1_out : STD_LOGI C_VECTOR( 29 downt o 0) ;
begi n
pg0_i n <= ( p0( 29) &p0( 27) &p0( 25) &p0( 23) &p0( 21) &p0( 19) &p0( 17) &p0( 15) &
p0( 13) &p0( 11) &p0( 9) &p0( 7) &p0( 5) &p0( 3) &p0( 1) &
g0( 29) &g0( 27) &g0( 25) &g0( 23) &g0( 21) &g0( 19) &g0( 17) &g0( 15) &
g0( 13) &g0( 11) &g0( 9) &g0( 7) &g0( 5) &g0( 3) &g0( 1) ) ;
f l op1_pg: f l op gener i c map( 30) por t map ( cl k, pg0_i n, pg1_out ) ;
p1( 29) <= pg1_out ( 29) ; p1( 27) <= pg1_out ( 28) ; p1( 25) <= pg1_out ( 27) ;
p1( 23) <= pg1_out ( 26) ;
p1( 21) <= pg1_out ( 25) ; p1( 19) <= pg1_out ( 24) ; p1( 17) <= pg1_out ( 23) ;
p1( 15) <= pg1_out ( 22) ; p1( 13) <= pg1_out ( 21) ; p1( 11) <= pg1_out ( 20) ;
p1( 9) <= pg1_out ( 19) ; p1( 7) <= pg1_out ( 18) ; p1( 5) <= pg1_out ( 17) ;
p1( 3) <= pg1_out ( 16) ; p1( 1) <= pg1_out ( 15) ;
g1( 29) <= pg1_out ( 14) ; g1( 27) <= pg1_out ( 13) ; g1( 25) <= pg1_out ( 12) ;
g1( 23) <= pg1_out ( 11) ; g1( 21) <= pg1_out ( 10) ; g1( 19) <= pg1_out ( 9) ;
g1( 17) <= pg1_out ( 8) ; g1( 15) <= pg1_out ( 7) ; g1( 13) <= pg1_out ( 6) ;
172 S OL U T I ON S c hapt er 5
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Exercise Solutions
g1( 11) <= pg1_out ( 5) ; g1( 9) <= pg1_out ( 4) ; g1( 7) <= pg1_out ( 3) ;
g1( 5) <= pg1_out ( 2) ; g1( 3) <= pg1_out ( 1) ; g1( 1) <= pg1_out ( 0) ;

- - pg cal cul at i ons
pi k_0 <= ( p0( 30) &p0( 28) &p0( 26) &p0( 24) &p0( 22) &p0( 20) &p0( 18) &p0( 16) &
p0( 14) &p0( 12) &p0( 10) &p0( 8) &p0( 6) &p0( 4) &p0( 2) &p0( 0) ) ;
gi k_0 <= ( g0( 30) &g0( 28) &g0( 26) &g0( 24) &g0( 22) &g0( 20) &g0( 18) &g0( 16) &
g0( 14) &g0( 12) &g0( 10) &g0( 8) &g0( 6) &g0( 4) &g0( 2) &g0( 0) ) ;
pkj _0 <= ( p0( 29) &p0( 27) &p0( 25) &p0( 23) &p0( 21) & p0( 19) & p0( 17) &p0( 15) &
p0( 13) &p0( 11) &p0( 9) &p0( 7) &p0( 5) &p0( 3) &p0( 1) &p_1_0) ;
gkj _0 <= ( g0( 29) &g0( 27) &g0( 25) &g0( 23) &g0( 21) &g0( 19) &g0( 17) &g0( 15) &
g0( 13) &g0( 11) &g0( 9) &g0( 7) &g0( 5) & g0( 3) &g0( 1) &g_1_0) ;

r ow1: bl ackbox por t map( cl k, pi k_0, pkj _0, gi k_0, gkj _0, pi j _0, gi j _0) ;
p1( 30) <= pi j _0( 15) ; p1( 28) <= pi j _0( 14) ; p1( 26) <= pi j _0( 13) ;
p1( 24) <= pi j _0( 12) ; p1( 22) <= pi j _0( 11) ; p1( 20) <= pi j _0( 10) ;
p1( 18) <= pi j _0( 9) ; p1( 16) <= pi j _0( 8) ; p1( 14) <= pi j _0( 7) ;
p1( 12) <= pi j _0( 6) ; p1( 10) <= pi j _0( 5) ; p1( 8) <= pi j _0( 4) ;
p1( 6) <= pi j _0( 3) ; p1( 4) <= pi j _0( 2) ; p1( 2) <= pi j _0( 1) ; p1( 0) <= pi j _0( 0) ;

g1( 30) <= gi j _0( 15) ; g1( 28) <= gi j _0( 14) ; g1( 26) <= gi j _0( 13) ;
g1( 24) <= gi j _0( 12) ; g1( 22) <= gi j _0( 11) ; g1( 20) <= gi j _0( 10) ;
g1( 18) <= gi j _0( 9) ; g1( 16) <= gi j _0( 8) ; g1( 14) <= gi j _0( 7) ;
g1( 12) <= gi j _0( 6) ; g1( 10) <= gi j _0( 5) ; g1( 8) <= gi j _0( 4) ;
g1( 6) <= gi j _0( 3) ; g1( 4) <= gi j _0( 2) ; g1( 2) <= gi j _0( 1) ; g1( 0) <= gi j _0( 0) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y r ow2 i s
por t ( cl k: i n STD_LOGI C;
p1, g1: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p2, g2: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end;
ar chi t ect ur e synt h of r ow2 i s
component bl ackbox i s
por t ( cl k: i n STD_LOGI C;
pi k, pkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
gi k, gkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
pi j : out STD_LOGI C_VECTOR( 15 downt o 0) ;
gi j : out STD_LOGI C_VECTOR( 15 downt o 0) ) ;
end component ;
component f l op i s gener i c( wi dt h: i nt eger ) ;
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
- - i nt er nal si gnal s f or cal cul at i ng p, g
si gnal pi k_1, gi k_1, pkj _1, gkj _1,
pi j _1, gi j _1: STD_LOGI C_VECTOR( 15 downt o 0) ;
- - i nt er nal si gnal s f or pi pel i ne r egi st er s
si gnal pg1_i n, pg2_out : STD_LOGI C_VECTOR( 29 downt o 0) ;
begi n
pg1_i n <= ( p1( 28 downt o 27) &p1( 24 downt o 23) &p1( 20 downt o 19) &
p1( 16 downt o 15) &
p1( 12 downt o 11) &p1( 8 downt o 7) &p1( 4 downt o 3) &p1( 0) &
g1( 28 downt o 27) &g1( 24 downt o 23) &g1( 20 downt o 19) &
g1( 16 downt o 15) &
g1( 12 downt o 11) &g1( 8 downt o 7) &g1( 4 downt o 3) &g1( 0) ) ;
f l op2_pg: f l op gener i c map( 30) por t map ( cl k, pg1_i n, pg2_out ) ;
S OL U T I O N S 173
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Exercise Solutions
p2( 28 downt o 27) <= pg2_out ( 29 downt o 28) ;
p2( 24 downt o 23) <= pg2_out ( 27 downt o 26) ;
p2( 20 downt o 19) <= pg2_out ( 25 downt o 24) ;
p2( 16 downt o 15) <= pg2_out ( 23 downt o 22) ;
p2( 12 downt o 11) <= pg2_out ( 21 downt o 20) ;
p2( 8 downt o 7) <= pg2_out ( 19 downt o 18) ;
p2( 4 downt o 3) <= pg2_out ( 17 downt o 16) ;
p2( 0) <= pg2_out ( 15) ;
g2( 28 downt o 27) <= pg2_out ( 14 downt o 13) ;
g2( 24 downt o 23) <= pg2_out ( 12 downt o 11) ;
g2( 20 downt o 19) <= pg2_out ( 10 downt o 9) ;
g2( 16 downt o 15) <= pg2_out ( 8 downt o 7) ;
g2( 12 downt o 11) <= pg2_out ( 6 downt o 5) ;
g2( 8 downt o 7) <= pg2_out ( 4 downt o 3) ;
g2( 4 downt o 3) <= pg2_out ( 2 downt o 1) ; g2( 0) <= pg2_out ( 0) ;
- - pg cal cul at i ons
pi k_1 <= ( p1( 30 downt o 29) &p1( 26 downt o 25) &p1( 22 downt o 21) &
p1( 18 downt o 17) &p1( 14 downt o 13) &p1( 10 downt o 9) &
p1( 6 downt o 5) &p1( 2 downt o 1) ) ;
gi k_1 <= ( g1( 30 downt o 29) &g1( 26 downt o 25) &g1( 22 downt o 21) &
g1( 18 downt o 17) &g1( 14 downt o 13) &g1( 10 downt o 9) &
g1( 6 downt o 5) &g1( 2 downt o 1) ) ;
pkj _1 <= ( p1( 28) &p1( 28) &p1( 24) &p1( 24) &p1( 20) &p1( 20) &p1( 16) &p1( 16) &
p1( 12) &p1( 12) &p1( 8) &p1( 8) &p1( 4) &p1( 4) &p1( 0) &p1( 0) ) ;
gkj _1 <= ( g1( 28) &g1( 28) &g1( 24) &g1( 24) &g1( 20) &g1( 20) &g1( 16) &g1( 16) &
g1( 12) &g1( 12) &g1( 8) &g1( 8) &g1( 4) &g1( 4) &g1( 0) &g1( 0) ) ;
r ow2: bl ackbox
por t map( cl k, pi k_1, pkj _1, gi k_1, gkj _1, pi j _1, gi j _1) ;

p2( 30 downt o 29) <= pi j _1( 15 downt o 14) ;
p2( 26 downt o 25) <= pi j _1( 13 downt o 12) ;
p2( 22 downt o 21) <= pi j _1( 11 downt o 10) ;
p2( 18 downt o 17) <= pi j _1( 9 downt o 8) ;
p2( 14 downt o 13) <=pi j _1( 7 downt o 6) ; p2( 10 downt o 9) <=pi j _1( 5 downt o 4) ;
p2( 6 downt o 5) <= pi j _1( 3 downt o 2) ; p2( 2 downt o 1) <= pi j _1( 1 downt o 0) ;
g2( 30 downt o 29) <= gi j _1( 15 downt o 14) ;
g2( 26 downt o 25) <= gi j _1( 13 downt o 12) ;
g2( 22 downt o 21) <= gi j _1( 11 downt o 10) ;
g2( 18 downt o 17) <= gi j _1( 9 downt o 8) ;
g2( 14 downt o 13) <=gi j _1( 7 downt o 6) ; g2( 10 downt o 9) <=gi j _1( 5 downt o 4) ;
g2( 6 downt o 5) <= gi j _1( 3 downt o 2) ; g2( 2 downt o 1) <= gi j _1( 1 downt o 0) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y r ow3 i s
por t ( cl k: i n STD_LOGI C;
p2, g2: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p3, g3: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end;
ar chi t ect ur e synt h of r ow3 i s
component bl ackbox i s
por t ( cl k: i n STD_LOGI C;
pi k, pkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
gi k, gkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
pi j : out STD_LOGI C_VECTOR( 15 downt o 0) ;
gi j : out STD_LOGI C_VECTOR( 15 downt o 0) ) ;
end component ;
component f l op i s gener i c( wi dt h: i nt eger ) ;
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
174 S OL U T I ON S c hapt er 5
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Exercise Solutions
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
- - i nt er nal si gnal s f or cal cul at i ng p, g
si gnal pi k_2, gi k_2, pkj _2, gkj _2,
pi j _2, gi j _2: STD_LOGI C_VECTOR( 15 downt o 0) ;
- - i nt er nal si gnal s f or pi pel i ne r egi st er s
si gnal pg2_i n, pg3_out : STD_LOGI C_VECTOR( 29 downt o 0) ;
begi n
pg2_i n <= ( p2( 26 downt o 23) &p2( 18 downt o 15) &p2( 10 downt o 7) &
p2( 2 downt o 0) &
g2( 26 downt o 23) &g2( 18 downt o 15) &g2( 10 downt o 7) &g2( 2 downt o 0) ) ;
f l op3_pg: f l op gener i c map( 30) por t map ( cl k, pg2_i n, pg3_out ) ;
p3( 26 downt o 23) <= pg3_out ( 29 downt o 26) ;
p3( 18 downt o 15) <= pg3_out ( 25 downt o 22) ;
p3( 10 downt o 7) <= pg3_out ( 21 downt o 18) ;
p3( 2 downt o 0) <= pg3_out ( 17 downt o 15) ;
g3( 26 downt o 23) <= pg3_out ( 14 downt o 11) ;
g3( 18 downt o 15) <= pg3_out ( 10 downt o 7) ;
g3( 10 downt o 7) <= pg3_out ( 6 downt o 3) ;
g3( 2 downt o 0) <= pg3_out ( 2 downt o 0) ;
- - pg cal cul at i ons
pi k_2 <= ( p2( 30 downt o 27) &p2( 22 downt o 19) &
p2( 14 downt o 11) &p2( 6 downt o 3) ) ;
gi k_2 <= ( g2( 30 downt o 27) &g2( 22 downt o 19) &
g2( 14 downt o 11) &g2( 6 downt o 3) ) ;
pkj _2 <= ( p2( 26) &p2( 26) &p2( 26) &p2( 26) &
p2( 18) &p2( 18) &p2( 18) &p2( 18) &
p2( 10) &p2( 10) &p2( 10) &p2( 10) &
p2( 2) &p2( 2) &p2( 2) &p2( 2) ) ;
gkj _2 <= ( g2( 26) &g2( 26) &g2( 26) &g2( 26) &
g2( 18) &g2( 18) &g2( 18) &g2( 18) &
g2( 10) &g2( 10) &g2( 10) &g2( 10) &
g2( 2) &g2( 2) &g2( 2) &g2( 2) ) ;

r ow3: bl ackbox
por t map( cl k, pi k_2, pkj _2, gi k_2, gkj _2, pi j _2, gi j _2) ;
p3( 30 downt o 27) <= pi j _2( 15 downt o 12) ;
p3( 22 downt o 19) <= pi j _2( 11 downt o 8) ;
p3( 14 downt o 11) <= pi j _2( 7 downt o 4) ; p3( 6 downt o 3) <= pi j _2( 3 downt o 0) ;
g3( 30 downt o 27) <= gi j _2( 15 downt o 12) ;
g3( 22 downt o 19) <= gi j _2( 11 downt o 8) ;
g3( 14 downt o 11) <= gi j _2( 7 downt o 4) ; g3( 6 downt o 3) <= gi j _2( 3 downt o 0) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y r ow4 i s
por t ( cl k: i n STD_LOGI C;
p3, g3: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p4, g4: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end;
ar chi t ect ur e synt h of r ow4 i s
component bl ackbox i s
por t ( cl k: i n STD_LOGI C;
pi k, pkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
gi k, gkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
pi j : out STD_LOGI C_VECTOR( 15 downt o 0) ;
gi j : out STD_LOGI C_VECTOR( 15 downt o 0) ) ;
end component ;
S OL U T I O N S 175
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
component f l op i s gener i c( wi dt h: i nt eger ) ;
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
- - i nt er nal si gnal s f or cal cul at i ng p, g
si gnal pi k_3, gi k_3, pkj _3, gkj _3,
pi j _3, gi j _3: STD_LOGI C_VECTOR( 15 downt o 0) ;
- - i nt er nal si gnal s f or pi pel i ne r egi st er s
si gnal pg3_i n, pg4_out : STD_LOGI C_VECTOR( 29 downt o 0) ;
begi n
pg3_i n <=( p3( 22 downt o 15) &p3( 6 downt o 0) &g3( 22 downt o 15) &g3( 6 downt o 0) ) ;
f l op4_pg: f l op gener i c map( 30) por t map ( cl k, pg3_i n, pg4_out ) ;
p4( 22 downt o 15) <= pg4_out ( 29 downt o 22) ;
p4( 6 downt o 0) <= pg4_out ( 21 downt o 15) ;
g4( 22 downt o 15) <= pg4_out ( 14 downt o 7) ;
g4( 6 downt o 0) <= pg4_out ( 6 downt o 0) ;
- - pg cal cul at i ons
pi k_3 <= ( p3( 30 downt o 23) &p3( 14 downt o 7) ) ;
gi k_3 <= ( g3( 30 downt o 23) &g3( 14 downt o 7) ) ;
pkj _3 <= ( p3( 22) &p3( 22) &p3( 22) &p3( 22) &p3( 22) &p3( 22) &p3( 22) &p3( 22) &
p3( 6) &p3( 6) &p3( 6) &p3( 6) &p3( 6) &p3( 6) &p3( 6) &p3( 6) ) ;
gkj _3 <= ( g3( 22) &g3( 22) &g3( 22) &g3( 22) &g3( 22) &g3( 22) &g3( 22) &g3( 22) &
g3( 6) &g3( 6) &g3( 6) &g3( 6) &g3( 6) &g3( 6) &g3( 6) &g3( 6) ) ;
r ow4: bl ackbox
por t map( cl k, pi k_3, pkj _3, gi k_3, gkj _3, pi j _3, gi j _3) ;
p4( 30 downt o 23) <= pi j _3( 15 downt o 8) ;
p4( 14 downt o 7) <= pi j _3( 7 downt o 0) ;
g4( 30 downt o 23) <= gi j _3( 15 downt o 8) ;
g4( 14 downt o 7) <= gi j _3( 7 downt o 0) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y r ow5 i s
por t ( cl k: i n STD_LOGI C;
p4, g4: i n STD_LOGI C_VECTOR( 30 downt o 0) ;
p5, g5: out STD_LOGI C_VECTOR( 30 downt o 0) ) ;
end;
ar chi t ect ur e synt h of r ow5 i s
component bl ackbox i s
por t ( cl k: i n STD_LOGI C;
pi k, pkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
gi k, gkj : i n STD_LOGI C_VECTOR( 15 downt o 0) ;
pi j : out STD_LOGI C_VECTOR( 15 downt o 0) ;
gi j : out STD_LOGI C_VECTOR( 15 downt o 0) ) ;
end component ;
component f l op i s gener i c( wi dt h: i nt eger ) ;
por t ( cl k: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
- - i nt er nal si gnal s f or cal cul at i ng p, g
si gnal pi k_4, gi k_4, pkj _4, gkj _4,
pi j _4, gi j _4: STD_LOGI C_VECTOR( 15 downt o 0) ;
- - i nt er nal si gnal s f or pi pel i ne r egi st er s
si gnal pg4_i n, pg5_out : STD_LOGI C_VECTOR( 29 downt o 0) ;
176 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
begi n
pg4_i n <= ( p4( 14 downt o 0) &g4( 14 downt o 0) ) ;
f l op4_pg: f l op gener i c map( 30) por t map ( cl k, pg4_i n, pg5_out ) ;
p5( 14 downt o 0) <= pg5_out ( 29 downt o 15) ; g5( 14 downt o 0) <= pg5_out ( 14
downt o 0) ;
- - pg cal cul at i ons
pi k_4 <= p4( 30 downt o 15) ;
gi k_4 <= g4( 30 downt o 15) ;
pkj _4 <= p4( 14) &p4( 14) &p4( 14) &p4( 14) &
p4( 14) &p4( 14) &p4( 14) &p4( 14) &
p4( 14) &p4( 14) &p4( 14) &p4( 14) &
p4( 14) &p4( 14) &p4( 14) &p4( 14) ;
gkj _4 <= g4( 14) &g4( 14) &g4( 14) &g4( 14) &
g4( 14) &g4( 14) &g4( 14) &g4( 14) &
g4( 14) &g4( 14) &g4( 14) &g4( 14) &
g4( 14) &g4( 14) &g4( 14) &g4( 14) ;

r ow5: bl ackbox
por t map( cl k, pi k_4, gi k_4, pkj _4, gkj _4, pi j _4, gi j _4) ;
p5( 30 downt o 15) <= pi j _4; g5( 30 downt o 15) <= gi j _4;
end;
Exercise 5.43
FIGURE 5.7 Up/Down counter
Exercise 5.45
+
r
Q
N-1:0
C
in
CLK Reset
0
1
UP
N N
N
N
N
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David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
FIGURE 5.8 32-bit counter that increments by 4 or loads a new value, D
Exercise 5.47
+
r
Q
N-1:0
CLK
Reset
4
32 32
32
32
0
1
D
PCSrc
SystemVerilog
modul e scanf l op4( i nput l ogi c cl k, t est , si n,
i nput l ogi c [ 3: 0] d,
out put l ogi c [ 3: 0] q,
out put l ogi c sout ) ;
al ways_f f @( posedge cl k)
i f ( t est )
q <= d;
el se
q <= {q[ 2: 0] , si n};
assi gn sout = q[ 3] ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y scanf l op4 i s
por t ( cl k, t est , si n: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( 3 downt o 0) ;
q: i nout STD_LOGI C_VECTOR( 3 downt o 0) ;
sout : out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of scanf l op4 i s
begi n
pr ocess( cl k, t est ) begi n
i f r i si ng_edge( cl k) t hen
i f t est t hen
q <= d;
el se
q <= q( 2 downt o 0) & si n;
end i f ;
end i f ;
end pr ocess;
sout <= q( 3) ;
end;
178 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 5.49
http://www.intel.com/design/flash/articles/what.htm
Flash memory is a nonvolatile memory because it retains its contents after
power is turned off. Flash memory allows the user to electrically program and
erase information. Flash memory uses memory cells similar to an EEPROM,
but with a much thinner, precisely grown oxide between a floating gate and the
substrate (see Figure5.9).
Flash programming occurs when electrons are placed on the floating gate.
This is done by forcing a large voltage (usually 10 to 12 volts) on the control
gate. Electrons quantum-mechanically tunnel from the source through the thin
oxide onto the control gate. Because the floating gate is completely insulated by
oxide, the charges are trapped on the floating gate during normal operation. If
electrons are stored on the floating gate, it blocks the effect of the control gate.
The electrons on the floating gate can be removed by reversing the procedure,
i.e., by placing a large negative voltage on the control gate.
The default state of a flash bitcell (when there are no electrons on the float-
ing gate) is ON, because the channel will conduct when the wordline is HIGH.
After the bitcell is programmed (i.e., when there are electrons on the floating
gate), the state of the bitcell is OFF, because the floating gate blocks the effect
of the control gate. Flash memory is a key element in thumb drives, cell phones,
digital cameras, Blackberries, and other low-power devices that must retain
their memory when turned off.
FIGURE 5.9 Flash EEPROM
n
p
wordline
bitline
substrate
floating
gate
n
GND
control
gate
source drain
thin
oxide
S OL U T I O N S 179
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 5.51
Exercise 5.53
(a) Number of inputs =2 16 +1 =33
Number of outputs =16 +1 =17

Thus, this would require a 2
33
x 17-bit ROM.
(b) Number of inputs =16
Number of outputs =16
Thus, this would require a 2
16
x 16-bit ROM.
(c) Number of inputs =16
Number of outputs =4
Thus, this would require a 2
16
x 4-bit ROM.
All of these implementations are not good design choices. They could all
be implemented in a smaller amount of hardware using discrete gates.
4:16
Decoder
A,B,C,D
Z Y X
4
0000
0010
0100
0110
1000
1010
1100
1110
0001
0011
0101
0111
1001
1011
1101
1111
180 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 5.55
(a) 1 LE
(b) 2 LEs
LUT output
0 0
0 1
1 0
1 1
1
1
1
1
data 2
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
1
data 1
(A) (B) (C) (Y)
data 4 data 3
data 1
D
A
B
C
X
data 2
data 3
data 4
LUT
LE
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
1
0
1
(D)
LUT output
0 0
0 1
1 0
1 1
1
1
1
1
data 2
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
0
0
0
data 1
(B) (C) (D) (X)
data 4 data 3
data 1
D
A
B
C X
data 2
data 3
data 4
LUT
LE 1
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
0
0
0
1
0
0
0
(E)
LUT output
X X
X X
X X
X X
0
1
1
1
data 2
0
data 1
(A) (X) (Y)
data 4 data 3
0
data 1 A
0 Y
data 2
data 3
data 4
LUT
LE 2
0 1
1 0
1 1
0
S OL U T I O N S 181
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(c) 2 LEs
LUT output
0 0
0 1
1 0
1 1
data 2
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
data 1
(A) (B) (C) (Y)
data 4 data 3
data 1
D
A
B
C Y
data 2
data 3
data 4
LUT
LE 1
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
(D)
LUT output
0 0
0 1
1 0
1 1
data 2
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
data 1
(A) (B) (C) (Z)
data 4 data 3
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
(D)
data 1 A
B
C Z
data 2
data 3
data 4
LUT
LE 2
D
0
1
0
1
0
1
0
1
1
1
1
0
1
0
0
1
0
0
0
0
0
1
0
1
1
0
0
0
1
0
1
0
182 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(d) 2 LEs
LUT output
0 0
0 1
1 0
1 1
data 2
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
data 1
(A
3
) (D)
data 4 data 3
data 1 A
3
D
data 2
data 3
data 4
LUT
LE 1
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
LUT output
0 0
0 1
1 0
1 1
data 2
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
data 1
(P)
data 4 data 3
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
data 1
P
data 2
data 3
data 4
LUT
LE 2
(A
2
) (A
1
) (A
0
) (A
3
) (A
2
) (A
1
) (A
0
)
A
2
A
1
A
0
A
3
A
2
A
1
A
0
0
0
0
1
0
0
1
0
1
0
0
1
0
0
1
0
0
0
1
1
0
1
0
1
0
0
1
0
1
0
0
0
S OL U T I O N S 183
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(e) 2 LEs
Exercise 5.57
(a) 5 LEs (2 for next state logic and state registers, 3 for output logic)
(b)
t
pd
=t
pd_LE
+ t
wire
=(381+246) ps
=627 ps
T
c
> t
pcq
+ t
pd
+ t
setup
> [199 +627 +76] ps
= 902 ps
f = 1 / 902 ps =1.1 GHz
(c)
First, we check that there is no hold time violation with this amount of clock
skew.
t
cd_LE
=t
pd_LE
=381 ps
t
cd
=t
cd_LE
+t
wire
=627 ps
LUT output
0 0
0 1
1 0
1 1
data 2
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
data 1
(A
3
)
data 4 data 3
data 1 A
3
data 2
data 3
data 4
LUT
LE 1
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
LUT output
0 0
0 1
1 0
1 1
data 2
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
data 1 data 4 data 3
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
data 1
data 2
data 3
data 4
LUT
LE 2
(A
2
) (A
1
) (A
0
) (A
3
) (A
2
) (A
1
) (A
0
)
A
2
A
1
A
0
A
3
A
2
A
1
A
0
(Y
0
) (Y
1
)
0
0
1
1
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Y
0
Y
1
184 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
t
skew
<(t
ccq
+ t
cd
) - t
hold
<[(199 + 627) - 0] ps
< 826 ps
3 ns is less than 826 ps, so there is no hold time violation.
Now we find the fastest frequency at which it can run.
T
c
> t
pcq
+ t
pd
+ t
setup
+ t
skew
> [0.902 +3] ns
= 3.902 ns
f = 1 / 3.902 ns =256 MHz
Exercise 5.59
First, we find the cycle time:
T
c
=1/f =1/100 MHz =10 ns
T
c
> t
pcq
+ Nt
LE+wire
+ t
setup
10 ns > [0.199 + N(0.627) + 0.076] ns
Thus, N < 15.5
The maximum number of LEs on the critical path is 15.
With at most one LE on the critical path and no clock skew, the fastest the
FSM will run is:
T
c
> [0.199 + 0.627 + 0.076] ns
> 0.902 ns
f = 1 / 0.902 ns =1.1 GHz
Question 5.1
(2
N
-1)(2
N
-1) =2
2N
- 2
N+1
+1
S OL U T I O N S 185
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Question 5.3
FIGURE 5.10 BCD adder: (a) 4-bit block, (b) underlying hardware, (c) 8-bit BCD adder
+
4 4
5
-
5
10
0
1
4 4
[3:0]
[4]
[
3
:
0
]
4
S
3:0
C
out
C
in
BCD+
4
4 4
A
3:0
B
3:0
A
3:0
B
3:0
C
in
S
3:0
C
out
(a) (b)
BCD+
4
4 4
A
7:4
B
7:4
S
7:4
C
out
(c)
BCD+
4
4 4
A
3:0
B
3:0
C
in
S
3:0
186 S OL U T I ON S c hapt er 5
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(continued from previous page)
SystemVerilog
modul e bcdadd_8( i nput l ogi c [ 7: 0] a, b,
i nput l ogi c ci n,
out put l ogi c [ 7: 0] s,
out put l ogi c cout ) ;
l ogi c c0;

bcdadd_4 bcd0( a[ 3: 0] , b[ 3: 0] , ci n, s[ 3: 0] , c0) ;
bcdadd_4 bcd1( a[ 7: 4] , b[ 7: 4] , c0, s[ 7: 4] , cout ) ;
endmodul e
modul e bcdadd_4( i nput l ogi c [ 3: 0] a, b,
i nput l ogi c ci n,
out put l ogi c [ 3: 0] s,
out put l ogi c cout ) ;
l ogi c [ 4: 0] r esul t , sub10;
assi gn r esul t = a + b + ci n;
assi gn sub10 = r esul t - 10;

assi gn cout = ~sub10[ 4] ;
assi gn s = sub10[ 4] ? r esul t [ 3: 0] : sub10[ 3: 0] ;

endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y bcdadd_8 i s
por t ( a, b: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
ci n: i n STD_LOGI C;
s: out STD_LOGI C_VECTOR( 7 downt o 0) ;
cout : out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of bcdadd_8 i s
component bcdadd_4
por t ( a, b: i n STD_LOGI C_VECTOR( 3 downt o 0) ;
ci n: i n STD_LOGI C;
s: out STD_LOGI C_VECTOR( 3 downt o 0) ;
cout : out STD_LOGI C) ;
end component ;
si gnal c0: STD_LOGI C;
begi n
bcd0: bcdadd_4
por t map( a( 3 downt o 0) , b( 3 downt o 0) , ci n, s( 3
downt o 0) , c0) ;
bcd1: bcdadd_4
por t map( a( 7 downt o 4) , b( 7 downt o 4) , c0, s( 7
downt o 4) , cout ) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use I EEE. STD_LOGI C_UNSI GNED. al l ;
use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y bcdadd_4 i s
por t ( a, b: i n STD_LOGI C_VECTOR( 3 downt o 0) ;
ci n: i n STD_LOGI C;
s: out STD_LOGI C_VECTOR( 3 downt o 0) ;
cout : out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of bcdadd_4 i s
si gnal r esul t , sub10, a5, b5: STD_LOGI C_VECTOR( 4
downt o 0) ;
begi n
a5 <= ' 0' & a;
b5 <= ' 0' & b;
r esul t <= a5 + b5 + ci n;
sub10 <= r esul t - " 01010" ;
cout <= not ( sub10( 4) ) ;
s <= r esul t ( 3 downt o 0) when sub10( 4) = ' 1'
el se sub10( 3 downt o 0) ;

end;
S OL U T I O N S 209
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
CHAPTER 6
Exercise 6.1
(1) Simplicity favors regularity:
Each instruction has a 6-bit opcode.
MIPS has only 3 instruction formats (R-Type, I-Type, J -Type).
Each instruction format has the same number and order of operands (they
differ only in the opcode).
Each instruction is the same size, making decoding hardware simple.
(2) Make the common case fast.
Registers make the access to most recently accessed variables fast.
The RISC (reduced instruction set computer) architecture, makes the com-
mon/simple instructions fast because the computer must handle only a
small number of simple instructions.
Most instructions require all 32 bits of an instruction, so all instructions are
32 bits (even though some would have an advantage of a larger instruction
size and others a smaller instruction size). The instruction size is chosen to
make the common instructions fast.
(3) Smaller is faster.
The register file has only 32 registers.
210 S OL U T I ON S c hapt er 6
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
The ISA (instruction set architecture) includes only a small number of com-
monly used instructions. This keeps the hardware small and, thus, fast.
The instruction size is kept small to make instruction fetch fast.
(4) Good design demands good compromises.
MIPS uses three instruction formats (instead of just one).
Ideally all accesses would be as fast as a register access, but MIPS archi-
tecture also supports main memory accesses to allow for a compromise be-
tween fast access time and a large amount of memory.
Because MIPS is a RISC architecture, it includes only a set of simple in-
structions, it provides pseudocode to the user and compiler for commonly
used operations, like moving data from one register to another (move) and
loading a 32-bit immediate (l i ).
Exercise 6.3
(a) 42 4 =42 2
2
=101010
2
<<2 =10101000
2
=0xA8
(b) 0xA8 through 0xAB
(c)
Exercise 6.5
# Bi g- endi an
l i $t 0, 0xABCD9876
sw $t 0, 100( $0)
l b $s5, 101( $0) # t he LSB of $s5 = 0xCD
# Li t t l e- endi an
l i $t 0, 0xABCD9876
sw $t 0, 100( $0)
l b $s5, 101( $0) # t he LSB of $s5 = 0x98
In big-endian format, the bytes are numbered from 100 to 103 from left to
right. In little-endian format, the bytes are numbered from 100 to 103 from right
to left. Thus, the final load byte (l b) instruction returns a different value de-
pending on the endianness of the machine.
FF 22 33 44
A8 A9AAAB
FF 22 33 44 0xA8
ABAAA9 A8
Word
Address
Big-Endian Little-Endian
Byte Address
Data Value
Byte Address
Data Value
MSB LSB MSB LSB
S OL U T I O N S 211
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 6.7
(a) 0x68 6F 77 64 79 00
(b) 0x6C 69 6F 6E 73 00
(c) 0x54 6F 20 74 68 65 20 72 65 73 63 75 65 21 00
Exercise 6.9
Exercise 6.11
0x20100049
0xad49fff9
0x02f24822
Exercise 6.13
(a)
addi $s0, $0, 73
sw $t 1, - 7( $t 2)
Word Address
1000100C
Data
68 6F 77 64
Little-Endian Memory
Byte 3 Byte 0
Word Address
10001010
1000100C
Data
6C 69
73 00
6F 6E
Byte 3 Byte 0
Word Address
10001010
1000100C
Data
54 6F
68 65
20 74
20
Byte 3 Byte 0
(a) (b) (c)
Big-Endian Memory
79 00
65 73 63 75
72
65 21 00
10001010
10001018
10001014
Word Address
1000100C
Data
64 77 6F 68
Byte 0 Byte 3
Word Address
10001010
1000100C
Data
6E 6F
73 00
69 6C
Byte 0 Byte 3
Word Address
10001010
1000100C
Data
74 20
72 20
6F 54
65
Byte 0 Byte 3
(a) (b) (c)
79 00
75 63 73 65
68
65 21 00
10001010
10001018
10001014
212 S OL U T I ON S c hapt er 6
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(b)
0x20100049 (addi )
0xad49fff9 (sw)
Exercise 6.15
addi $t0, $0, 31
L1:
srlv $t1, $a0, $t0
andi $t1, $t1, 1
slt $t1, $0, $t1
sb $t1, 0($a1)
addi $a1, $a1, 1
addi $t0, $t0, -1
bgez $t0, L1
jr $ra
(a) This program converts a number ($a0) from decimal to binary and
stores it in an array pointed to by $a1.
void convert2bin(int num, char binarray[])
{
int i;
char tmp, val = 31;
for (i=0; i<32; i++) {
tmp = (num >> val) & 1;
binarray[i] = tmp;
val--;
}
}
Exercise 6.17
(a)
# $s0 =g, $s1 =h
sl t $t 0, $s1, $s0 # i f h < g, $t 0 = 1
beq $t 0, $0, el se # i f $t 0 == 0, do el se
add $s0, $s0, $s1 # g = g + h
j done # j ump past el se bl ock
el se: sub $s0, $s0, $s1 # g = g - h
done:
(b)
S OL U T I O N S 213
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
sl t $t 0, $s0, $s1 # i f g < h, $t 0 = 1
bne $t 0, $0, el se # i f $t 0 ! = 0, do el se
addi $s0, $s0, 1 # g = g + 1
j done # j ump past el se bl ock
el se: addi $s1, $s1, - 1 # h = h - 1
done:

(c)
sl t $t 0, $s1, $s0 # i f h < g, $t 0 = 1
bne $t 0, $0, el se # i f $t 0 ! = 0, do el se
add $s0, $0, $0 # g = 0
j done # j ump past el se bl ock
el se: sub $s1, $0, $0 # h = 0
done:
Exercise 6.19
(a)
# MI PS assembl y code
# base addr ess of ar r ay dst = $a0
# base addr ess of ar r ay sr c = $a1
# i = $s0
st r cpy:
addi $sp, $sp, - 4
sw $s0, 0( $sp) # save $s0 on t he st ack
add $s0, $0, $0 # i = 0
l oop:
add $t 1, $a1, $s0 # $t 1 = addr ess of sr c[ i ]
l b $t 2, 0( $t 1) # $t 2 = sr c[ i ]
add $t 3, $a0, $s0 # $t 3 = addr ess of dst [ i ]
sb $t 2, 0( $t 3) # dst [ i ] = sr c[ i ]
beq $t 2, $0, done # check f or nul l char act er
addi $s0, $s0, 1 # i ++
j l oop
done:
l w $s0, 0( $sp) # r est or e $s0 f r omst ack
addi $sp, $sp, 4 # r est or e st ack poi nt er
j r $r a # r et ur n
214 S OL U T I ON S c hapt er 6
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(b) The stack (i) before, (ii) during, and (iii) after the st r cpy procedure
call.
Exercise 6.21
(a) The stack frames of each procedure are:
proc1: 3 words deep (for $s0 - $s1, $r a)
proc2: 7 words deep (for $s2 - $s7, $r a)
proc3: 4 words deep (for $s1 - $s3, $r a)
proc4: 0 words deep (doesn't use any saved registers or call other proce-
dures)
(i)
0x7FFFFF00
Data Address
0x7FFFFEFC
0x7FFFFEF8
0x7FFFFEF4
(ii)
0x7FFFFF00
Data Address
0x7FFFFEFC
0x7FFFFEF8
0x7FFFFEF4
$sp
(iii)
0x7FFFFF00
Data Address
0x7FFFFEFC
0x7FFFFEF8
0x7FFFFEF4
$sp
$sp $s0
S OL U T I O N S 215
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(b) Note: we arbitrarily chose to make the initial value of the stack pointer
0x7FFFFF04 just before the procedure calls.
Exercise 6.23
(a) 120
(b) 2
(c)
(i) 3 - returned value is 1
(ii) 2 (depending on whats stored on the stack frame of the callees stack)
(iii) 4
Exercise 6.25
(a) 000100 01000 10001 0000 0000 0000 0010
= 0x11110002
(b) 000100 01111 10100 0000 0100 0000 1111
= 0x11F4040F
(c) 000100 11001 10111 1111 1000 0100 0010
= 0x1337F842
(d) 000011 0000 0100 0001 0001 0100 0111 11
= 0x0C10451F
s
t
a
c
k

f
r
a
m
e
p
r
o
c
1
Data
Address
7FFF FEE0
7FFF FEDC
7FFF FED8
7FFF FED4
7FFF FEF0
7FFF FEEC
7FFF FEE8
7FFF FEE4
7FFF FF00
7FFF FEFC
7FFF FEF8
7FFF FEF4
$s6
$s7
$ra =0x00401180
$s1
$s2
$s3
$s4
$s5
$ra
$s0
$s1
$ra =0x00401024
$s2
$s3
7FFF FED0
7FFF FECC $sp
s
t
a
c
k

f
r
a
m
e
p
r
o
c
2
s
t
a
c
k

f
r
a
m
e
p
r
o
c
3
216 S OL U T I ON S c hapt er 6
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(e) 000010 00 0001 0000 0000 1100 0000 0001
= 0x08100C01
Exercise 6.27
(a)
set _ar r ay: addi $sp, $sp, - 52 # move st ack poi nt er
sw $r a, 48( $sp) # save r et ur n addr ess
sw $s0, 44( $sp) # save $s0
sw $s1, 40( $sp) # save $s1
add $s0, $0, $0 # i = 0
addi $s1, $0, 10 # max i t er at i ons = 10
l oop: add $a1, $s0, $0 # pass i as par amet er
j al compar e # cal l compar e( num, i )
sl l $t 1, $s0, 2 # $t 1 = i *4
add $t 2, $sp, $t 1 # $t 2 = addr ess of ar r ay[ i ]
sw $v0, 0( $t 2) # ar r ay[ i ] = compar e( num, i ) ;
addi $s0, $s0, 1 # i ++
bne $s0, $s1, l oop # i f i <10, got o l oop
l w $s1, 40( $sp) # r est or e $s1
l w $s0, 44( $sp) # r est or e $s0
l w $r a, 48( $sp) # r est or e r et ur n addr ess
addi $sp, $sp, 52 # r est or e st ack poi nt er
j r $r a # r et ur n t o poi nt of cal l
compar e: addi $sp, $sp, - 4 # move st ack poi nt er
sw $r a, 0( $sp) # save r et ur n addr ess on t he st ack
j al subt r act # i nput par amet er s al r eady i n $a0, $a1
sl t $v0, $v0, $0 # $v0=1 i f sub( a, b) < 0 ( r et ur n 0)
sl t i $v0, $v0, 1 # $v0=1 i f sub( a, b) >=0, el se $v0 = 0
l w $r a, 0( $sp) # r est or e r et ur n addr ess
addi $sp, $sp, 4 # r est or e st ack poi nt er
j r $r a # r et ur n t o poi nt of cal l
subt r act : sub $v0, $a0, $a1 # r et ur n a- b
j r $r a # r et ur n t o poi nt of cal l
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Exercise Solutions
6.27 (b)
(c) If $r a were never stored on the stack, the compare function would re-
turn to the instruction after the call to subt r act (sl t $v0, $v0, $0 ) in-
stead of returning to the set _ar r ay function. The program would enter an
infinite loop in the compar e function between j r $r a and sl t $v0,
$v0, $0. It would increment the stack during that loop until the stack space
was exceeded and the program would likely crash.
Exercise 6.29
Instructions (32 K - 1) words before the branch to instructions 32 K words
after the branch instruction.
$sp
Before set_array:
During set_array: During compare/sub:
$sp
$ra
$s0
array[9]
array[8]
array[7]
array[6]
array[5]
array[4]
array[3]
array[2]
array[1]
array[0]
$ra
$s0
array[9]
array[8]
array[7]
array[6]
array[5]
array[4]
array[3]
array[2]
array[1]
array[0]
$sp $ra
$s1 $s1
218 S OL U T I ON S c hapt er 6
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Exercise Solutions
Exercise 6.31
It is advantageous to have a large address field in the machine format for
jump instructions to increase the range of instruction addresses to which the in-
struction can jump.
Exercise 6.33
# hi gh- l evel code
voi d l i t t l e2bi g( i nt [ ] ar r ay)
{
i nt i ;
f or ( i = 0; i < 10; i = i + 1) {
ar r ay[ i ] = ( ( ar r ay[ i ] & 0xFF) << 24) | |
( ar r ay[ i ] & 0xFF00) << 8) | |
( ar r ay[ i ] & 0xFF0000) >> 8) | |
( ( ar r ay[ i ] >> 24) & 0xFF) ) ;
}
}
# MI PS assembl y code
# $a0 = base addr ess of ar r ay
l i t t l e2bi g:
addi $t 5, $0, 10 # $t 5 = i = 10 ( l oop count er )
l oop: l b $t 0, 0( $a0) # $t 0 = ar r ay[ i ] byt e 0
l b $t 1, 1( $a0) # $t 1 = ar r ay[ i ] byt e 1
l b $t 2, 2( $a0) # $t 2 = ar r ay[ i ] byt e 2
l b $t 3, 3( $a0) # $t 3 = ar r ay[ i ] byt e 3
sb $t 3, 0( $a0) # ar r ay[ i ] byt e 0 = pr evi ous byt e 3
sb $t 2, 1( $a0) # ar r ay[ i ] byt e 1 = pr evi ous byt e 2
sb $t 1, 2( $a0) # ar r ay[ i ] byt e 2 = pr evi ous byt e 1
sb $t 0, 3( $a0) # ar r ay[ i ] byt e 3 = pr evi ous byt e 0
addi $a0, $a0, 4 # i ncr ement i ndex i nt o ar r ay
addi $t 5, $t 5, - 1 # decr ement l oop count er
beq $t 5, $0, done
j l oop
done:
Exercise 6.35
# def i ne t he masks i n t he gl obal dat a segment
. dat a
mmask: . wor d 0x007FFFFF
emask: . wor d 0x7F800000
i bi t : . wor d 0x00800000
obi t : . wor d 0x01000000
. t ext
f l padd: l w $t 4, mmask # l oad mant i ssa mask
and $t 0, $s0, $t 4 # ext r act mant i ssa f r om$s0 ( a)
and $t 1, $s1, $t 4 # ext r act mant i ssa f r om$s1 ( b)
l w $t 4, i bi t # l oad i mpl i ci t l eadi ng 1
or $t 0, $t 0, $t 4 # add t he i mpl i ci t l eadi ng 1 t o mant i ssa
or $t 1, $t 1, $t 4 # add t he i mpl i ci t l eadi ng 1 t o mant i ssa
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Exercise Solutions
l w $t 4, emask # l oad exponent mask
and $t 2, $s0, $t 4 # ext r act exponent f r om$s0 ( a)
sr l $t 2, $t 2, 23 # shi f t exponent r i ght
and $t 3, $s1, $t 4 # ext r act exponent f r om$s1 ( b)
sr l $t 3, $t 3, 23 # shi f t exponent r i ght
mat ch: beq $t 2, $t 3, addsi g # check whet her t he exponent s mat ch
bgeu $t 2, $t 3, shi f t b # det er mi ne whi ch exponent i s l ar ger
shi f t a: sub $t 4, $t 3, $t 2 # cal cul at e di f f er ence i n exponent s
sr av $t 0, $t 0, $t 4 # shi f t a by cal cul at ed di f f er ence
add $t 2, $t 2, $t 4 # updat e a' s exponent
j addsi g # ski p t o t he add
shi f t b: sub $t 4, $t 2, $t 3 # cal cul at e di f f er ence i n exponent s
sr av $t 1, $t 1, $t 4 # shi f t b by cal cul at ed di f f er ence
add $t 3, $t 3, $t 4 # updat e b' s exponent ( not necessar y)
addsi g: add $t 5, $t 0, $t 1 # add t he mant i ssas
nor m: l w $t 4, obi t # l oad mask f or bi t 24 ( over f l ow bi t )
and $t 4, $t 5, $t 4 # mask bi t 24
beq $t 4, $0, done # r i ght shi f t not needed because bi t 24=0
sr l $t 5, $t 5, 1 # shi f t r i ght once by 1 bi t
addi $t 2, $t 2, 1 # i ncr ement exponent
done: l w $t 4, mmask # l oad mask
and $t 5, $t 5, $t 4 # mask mant i ssa
sl l $t 2, $t 2, 23 # shi f t exponent i nt o pl ace
l w $t 4, emask # l oad mask
and $t 2, $t 2, $t 4 # mask exponent
or $v0, $t 5, $t 2 # pl ace mant i ssa and exponent i nt o $v0
j r $r a # r et ur n t o cal l er
Exercise 6.37
(a)
0x00400000 mai n: addi $sp, $sp, - 4
0x00400004 sw $r a, 0( $sp)
0x00400008 addi $t 0, $0, 15
0x0040000C sw $t 0, 0x8000( $gp)
0x00400010 addi $a1, $0, 27
0x00400014 sw $a1, 0x8004( $gp)
0x00400018 l w $a0, 0x8000( $gp)
0x0040001C j al gr eat er
0x00400020 l w $r a, 0( $sp)
0x00400024 addi $sp, $sp, 4
0x00400028 j r $r a
0x0040002C gr eat er : sl t $v0, $a1, $a0
0x00400030 j r $r a
(b)
symbol addr ess
a 0x10000000
b 0x10000004
mai n 0x00400000
gr eat er 0x0040002C
220 S OL U T I ON S c hapt er 6
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Exercise Solutions
TABLE 6.1 Symbol table
(c)
(d)
The data segment is 8 bytes and the text segment is 52 (0x34) bytes.
Executable file header Text Size Data Size
Text segment
Data segment
Address Instruction
Address Data
0x00400000
0x00400004
0x00400008
0x0040000C
0x00400010
0x00400014
0x00400018
0x0040001C
0x00400020
0x00400024
0x00400028
0x0040002C
0x00400030
addi $sp, $sp, - 4
sw $r a, 0( $sp)
addi $t 0, $0, 15
sw $t 0, 0x8000( $gp)
addi $a1, $0, 27
sw $a1, 0x8004( $gp)
l w $a0, 0x8000( $gp)
j al gr eat er
l w $r a, 0( $sp)
addi $sp, $sp, 4
j r $r a
sl t $v0, $a1, $a0
j r $r a
0x10000000
0x10000004
a
b
0x8 (8 bytes) 0x34 (52 bytes)
0x23BDFFFC
0xAFBF0000
0x2008000F
0xAF888000
0x2005001B
0xAF858004
0x8F848000
0x0C10000B
0x8FBF0000
0x23BD0004
0x03E00008
0x00A4102A
0x03E00008
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Exercise Solutions
(e)
Exercise 6.39
(a)
beq $t 1, i mm31: 0, L
l ui $at , i mm31: 16
or i $at , $at , i mm15: 0
beq $t 1, $at , L
(b)
bl e $t 3, $t 5, L
sl t $at , $t 5, $t 3
beq $at , $0, L
b
a
Memory Address
$sp =0x7FFFFFFC 0x7FFFFFFC
0x10010000
0x00400000
Stack
Heap
$gp =0x10008000
PC =0x00400000
0x10000000
Reserved
Reserved
0xAF850004
0x2005001B
0xAF888000
0x2008000F
0xAFBF0000
0x23BDFFFC
0x23BD0004
0x8FBF0000
0x0C10000B
0x8f848000
0x03E00008
0x00A4102A
0x03E00008
222 S OL U T I ON S c hapt er 6
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Exercise Solutions
(c)
bgt $t 3, $t 5, L
sl t $at , $t 5, $t 3
bne $at , $0, L
(d)
bge $t 3, $t 5, L
sl t $at , $t 3, $t 5
beq $at , $0, L
Question 6.1
xor $t 0, $t 0, $t 1 # $t 0 = $t 0 XOR $t 1
xor $t 1, $t 0, $t 1 # $t 1 = or i gi nal val ue of $t 0
xor $t 0, $t 0, $t 1 # $t 0 = or i gi nal val ue of $t 1
Question 6.3
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Exercise Solutions
High-Level Code
/ / hi gh- l evel al gor i t hm
voi d r ever sewor ds( char [ ] ar r ay) {
i nt i , j , l engt h;
/ / f i nd l engt h of st r i ng
f or ( i = 0; ar r ay[ i ] ! = 0; i = i + 1) ;
l engt h = i ;

/ / r ever se char act er s i n st r i ng
r ever se( ar r ay, l engt h- 1, 0) ;
/ / r ever se wor ds i n st r i ng
i = 0; j = 0;
/ / check f or spaces
whi l e ( i <= l engt h) {
i f ( ( i ! = l engt h) | | ( ar r ay[ i ] ! = 0x20) ) {
i = i + 1;
el se {
r ever se( ar r ay, i - 1, j ) ;
i = i + 1; / / j and i at st ar t of next wor d
j = i ;
}
}
}
voi d r ever se( char [ ] ar r ay, i nt i , i nt j )
{
char t mp;
whi l e ( i > j ) {
t mp = ar r ay[ i ] ;
ar r ay[ i ] = ar r ay[ j ] ;
ar r ay[ j ] = t mp;
i = i - 1;
j = j +1;
}
}
MIPS Assembly Code
# $s2 = i , $s3 = j , $s1 = l engt h
r ever sewor ds:
addi $sp, $sp, - 16 # make r oomon st ack
sw $r a, 12( $sp) # st or e r egs on st ack
sw $s1, 8( $sp)
sw $s2, 4( $sp)
sw $s3, 0( $sp)
addi $s2, $0, 0 # i = 0
l engt h: add $t 4, $a0, $s2 # $t 4 = &ar r ay[ i ]
l b $t 3, 0( $t 4) # $t 3 = ar r ay[ i ]
beq $t 3, $0, done # end of st r i ng?
addi $s2, $s2, 1 # i ++
j l engt h
done: addi $s1, $s2, 0 # l engt h = i
addi $a1, $s1, - 1 # $a1 = l engt h - 1
addi $a2, $0, 0 # $a2 = 0
j al r ever se # cal l r ever se
addi $s2, $0, 0 # i = 0
addi $s3, $0, 0 # j = 0
addi $t 5, $0, 0x20 # $t 5 = space
wor d: sl t $t 4, $s1, $s2 # $t 4 = 1 i f l engt h<i
bne $t 4, $0, r et ur n # r et ur n i f l engt h<i
beq $s2, $s1, el se # i f i ==l engt h, el se
add $t 4, $a0, $s2 # $t 4 = &ar r ay[ i ]
l b $t 4, 0( $t 4) # $t 4 = ar r ay[ i ]
beq $t 4, $t 5, el se # i f $t 4==0x20, el se
addi $s2, $s2, 1 # i = i + 1
j wor d
el se: addi $a1, $s2, - 1 # $a1 = i - 1
addi $a2, $s3, 0 # $a2 = j
j al r ever se
addi $s2, $s2, 1 # i = i + 1
addi $s3, $s2, 0 # j = i
j wor d
r et ur n: l w $r a, 12( $sp) # r est or e r egs
l w $s1, 8( $sp)
l w $s2, 4( $sp)
l w $s3, 0( $sp)
addi $sp, $sp, 16 # r est or e $sp
j r $r a # r et ur n
r ever se:
sl t $t 0, $a2, $a1 # $t 0 = 1 i f j < i
beq $t 0, $0, exi t # i f j < i , r et ur n
add $t 1, $a0, $a1 # $t 1 = &ar r ay[ i ]
l b $t 2, 0( $t 1) # $t 2 = ar r ay[ i ]
add $t 3, $a0, $a2 # $t 3 = &ar r ay[ j ]
l b $t 4, 0( $t 3) # $t 4 = ar r ay[ j ]
sb $t 4, 0( $t 1) # ar r ay[ i ] =ar r ay[ j ]
sb $t 2, 0( $t 3) # ar r ay[ j ] =ar r ay[ i ]
addi $a1, $a1, - 1 # i = i - 1
addi $a2, $a2, 1 # j = j +1
j r ever se
exi t : j r $r a
224 S OL U T I ON S c hapt er 6
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Exercise Solutions
Question 6.5
High-Level Code
num= swap( num, 1, 0x55555555) ; / / swap bi t s
num= swap( num, 2, 0x33333333) ; / / swap pai r s
num= swap( num, 4, 0x0F0F0F0F) ; / / swap ni bbl es
num= swap( num, 8, 0x00FF00FF) ; / / swap byt es
num= swap( num, 16, 0xFFFFFFFF) ; / / swap hal ves
/ / swap masked bi t s
i nt swap( i nt num, i nt shamt , unsi gned i nt mask) {
r et ur n ( ( num>> shamt ) & mask) |
( ( num& mask) << shamt ) ;
MIPS Assembly Code
# $t 3 = num
addi $a0, $t 3, 0 # set up ar gs
addi $a1, $0, 1
l i $a2, 0x55555555
j al swap # swap bi t s
addi $a0, $v0, 0 # num= r et ur n val ue
addi $a1, $0, 2 # set up ar gs
l i $a2, 0x33333333
j al swap # swap pai r s
addi $a0, $v0, 0 # num= r et ur n val ue
addi $a1, $0, 4 # set up ar gs
l i $a2, 0x0F0F0F0F
j al swap # swap ni bbl es
addi $a0, $v0, 0 # num= r et ur n val ue
addi $a1, $0, 8 # set up ar gs
l i $a2, 0x00FF00FF
j al swap # swap byt es
addi $a0, $v0, 0 # num= r et ur n val ue
addi $a1, $0, 16 # set up ar gs
l i $a2, 0xFFFFFFFF
j al swap # swap hal ves
addi $t 3, $v0, 0 # num= r et ur n val ue
done: j done
swap:
sr l v $v0, $a0, $a1 # $v0 = num>> shamt
and $v0, $v0, $a2 # $v0 = $v0 & mask
and $t 0, $a0, $a2 # $t 0 = num& mask
sl l v $t 0, $t 0, $a1 # $t 0 = $t 0 << shamt
or $v0, $v0, $t 0 # $v0 = $v0 | $t 0
j r $r a # r et ur n
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Exercise Solutions
Question 6.7
High-Level Code
bool pal i ndr ome( char * ar r ay) {
i nt i , j ; / / ar r ay i ndi ces
/ / f i nd l engt h of st r i ng
f or ( j = 0; ar r ay[ j ] ! = 0; j =j +1) ;

j = j - 1; / / j i s i ndex of l ast char
i nt i = 0;
whi l e ( j > i ) {
t mp = ar r ay[ i ] ;
i f ( ar r ay[ i ] ! = ar r ay[ j ] )
r et ur n f al se;
j = j - 1;
i = i +1;
}
r et ur n t r ue;
}
MIPS Assembly Code
# $t 0 = j , $t 1 = i , $a0 = base addr ess of st r i ng
pal i ndr ome:
addi $t 0, $0, 0 # j = 0
l engt h: add $t 2, $a0, $t 0 # $t 2 = &ar r ay[ j ]
l b $t 2, 0( $t 2) # $t 2 = ar r ay[ j ]
beq $t 2, $0, done # end of st r i ng?
addi $t 0, $t 0, 1 # j = j +1
j l engt h
done: addi $t 0, $t 0, - 1 # j = j - 1
addi $t 1, $0, 0 # i = 0
l oop: sl t $t 2, $t 1, $t 0 # $t 2 = 1 i f i < j
beq $t 2, $0, yes # i f ! ( i < j ) r et ur n
add $t 2, $a0, $t 1 # $t 2 = &ar r ay[ i ]
l b $t 2, 0( $t 2) # $t 2 = ar r ay[ i ]
add $t 3, $a0, $t 0 # $t 3 = &ar r ay[ j ]
l b $t 3, 0( $t 3) # $t 3 = ar r ay[ j ]
bne $t 2, $t 3, no # i s pal i ndr ome?
addi $t 0, $t 0, - 1 # j = j - 1
addi $t 1, $t 1, 1 # i = i +1
j l oop
yes: # yes a pal i ndr ome
addi $v0, $0, 1
j yes
j r $r a
no: # not a pal i ndr ome
addi $v0, $0, 0
j no
j r $r a
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Exercise Solutions
S OL U T I O N S 233
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
CHAPTER 7
Exercise 7.1
(a) R-type, l w, addi
(b) R-type
(c) sw
Exercise 7.3
(a) sl l
234 S OL U T I ON S c hapt er 7
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Exercise Solutions
First, we modify the ALU.
FIGURE 7.1 Modified ALU to support sl l
TABLE 7.1 Modified ALU operations to support sl l
A L U C ont r ol
3: 0
F unct i on
0000 A AND B
0001 A OR B
0010 A +B
0011 not used
1000 A AND B
1001 A OR B
1010 A - B
1011 SLT
0100 SLL
3
+
20 1
A B
C
out
Result
3
0
1
ALUControl
3
ALUControl
2:0
[N-1] S
N N
N
N
N N N N
N
Z
e
r
o
E
x
t
e
n
d
<<
shamt
4:0
N
4
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Exercise Solutions
Then we modify the datapath.
FIGURE 7.2 Modified single-cycle MIPS processor extended to run sl l
A L U Op F unct A L U C ont r ol
00 X 0010 (add)
X1 X 1010 (subtract)
1X 100000 (add) 0010 (add)
1X 100010 (sub) 1010 (subtract)
1X 100100 (and) 0000 (and)
1X 100101 (or ) 0001 (or)
1X 101010 (sl t ) 1011 (set less than)
1X 000000 (sl l ) 0100 (shift left logical)
TABLE 7.2 ALU decoder truth table
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
3:0
A
L
U
I
n
s
t
r
1
0
:
6
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Exercise Solutions
7.3 (b)l ui
Note: the 5-bit rs field of the l ui instruction is 0.
FIGURE 7.3 Modified single-cycle datapath to support l ui
Instruction opcode RegWrite RegDst ALUSrc Branch MemWrite MemtoReg ALUOp
R-type 000000 1 1 00 0 0 0 10
l w 100011 1 0 01 0 0 1 00
sw 101011 0 X 01 0 1 X 00
beq 000100 0 X 00 1 0 X 01
lui 001111 1 0 10 0 0 0 00
TABLE 7.3 Main decoder truth table enhanced to support l ui
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
A RD
Data
Memory
WD
WE
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
1:0
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
<<16
00
01
10
15:0
S OL U T I O N S 237
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
7.3 (c) sl t i
The datapath doesnt change. Only the controller changes, as shown in
Table7.4 and Table7.5.
A L U Op F unct A L U C ont r ol
00 X 010 (add)
01 X 110 (subtract)
10 100000 (add) 010 (add)
10 100010 (sub) 110 (subtract)
10 100100 (and) 000 (and)
10 100101 (or ) 001 (or)
10 101010 (sl t ) 111 (set less than)
11 X 111 (set less than)
TABLE 7.4 ALU decoder truth table
Instruction opcode RegWrite RegDst ALUSrc Branch MemWrite MemtoReg ALUOp
R-type 000000 1 1 0 0 0 0 10
l w 100011 1 0 1 0 0 1 00
sw 101011 0 X 1 0 1 X 00
beq 000100 0 X 0 1 0 X 01
slti 001010 1 0 1 0 0 0 11
TABLE 7.5 Main decoder truth table enhanced to support sl t i
238 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
7.3 (d) bl ez
First, we modify the ALU
Then, we modify the datapath
+
20 1
A B
C
out
Result
3
0
1
ALUControl
2
ALUControl
1:0
[N-1] S
N N
N
N
N N N N
N
2
Z
e
r
o
E
x
t
e
n
d
==0
Zero
Zero Result
N-1
LTEZ
S OL U T I O N S 239
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
.
Exercise 7.5
It is not possible to implement this instruction without either modifying the
register file (adding another write port) or making the instruction take two cy-
cles to execute.
We modify the register file and datapath as shown in Figure7.4.
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult
ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
BLEZ
L
T
E
Z
Instruction opcode RegWrite RegDst ALUSrc Branch MemWrite MemtoReg ALUOp BLEZ
R-type 000000 1 1 0 0 0 0 10 0
l w 100011 1 0 1 0 0 1 00 0
sw 101011 0 X 1 0 1 X 00 0
beq 000100 0 X 0 1 0 X 01 0
blez 000110 0 X 0 0 0 X 01 1
TABLE 7.6 Main decoder truth table enhanced to support bl ez
240 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
FIGURE 7.4 Modified datapath
SignImm
CLK
A RD
Instruction
Memory
+
4
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
A RD
Data
Memory
WD
WE
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB
20:16
15:11
<<2
+
ALUResult ReadData
WriteData
SrcA
PCPlus4
PCBranch
WriteReg
4:0
Result
31:26
RegDst
Branch
MemWrite
MemtoReg
ALUSrc
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
ALUControl
2:0
A
L
U
WD1
WE1
+
4
A
L
U
S
r
c
LwInc
L
w
I
n
c
Instruction opcode RegWrite RegDst ALUSrc Branch MemWrite MemtoReg ALUOp Lwinc
R-type 000000 1 1 0 0 0 0 10 0
l w 100011 1 0 1 0 0 1 00 0
sw 101011 0 X 1 0 1 X 00 0
beq 000100 0 X 0 1 0 X 01 0
lwinc 1 0 1 0 0 1 00 1
TABLE 7.7 Main decoder truth table enhanced to support l wi nc
S OL U T I O N S 241
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 7.7
Before the enhancement (see Equation 7.3, page 380 in the text, also Erra-
ta):
T
c
=t
pcq_PC
+2t
mem
+t
RFread
+t
mux
+t
ALU
+t
RFsetup
=30 +2(250) +150 +25 +200 +20 =925ps
The unit that your friend could speed up that would make the largest reduc-
tion in cycle time would be the memory unit. So tmem_new =125ps, and the
new cycle time is:
T
c
= 675 ps
Exercise 7.9
(a) l w
(b) beq
(c) beq, j
Exercise 7.11
SystemVerilog
modul e t op( i nput l ogi c cl k, r eset ,
out put l ogi c [ 31: 0] wr i t edat a, dat aadr ,
out put l ogi c memwr i t e) ;
l ogi c [ 31: 0] pc, i nst r , r eaddat a;

/ / i nst ant i at e pr ocessor and memor i es
mi ps mi ps( cl k, r eset , pc, i nst r , memwr i t e, dat aadr ,
wr i t edat a, r eaddat a) ;
i memi mem( pc[ 7: 2] , i nst r ) ;
dmemdmem( cl k, memwr i t e, dat aadr , wr i t edat a, r eaddat a) ;
endmodul e
modul e dmem( i nput l ogi c cl k, we,
i nput l ogi c [ 31: 0] a, wd,
out put l ogi c [ 31: 0] r d) ;
l ogi c [ 31: 0] RAM[ 63: 0] ;
assi gn r d = RAM[ a[ 31: 2] ] ; / / wor d al i gned
al ways_f f @( posedge cl k)
i f ( we) RAM[ a[ 31: 2] ] <= wd;
endmodul e
modul e i mem( i nput l ogi c [ 5: 0] a,
242 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
out put l ogi c [ 31: 0] r d) ;
l ogi c [ 31: 0] RAM[ 63: 0] ;
i ni t i al
$r eadmemh( " memf i l e. dat " , RAM) ;
assi gn r d = RAM[ a] ; / / wor d al i gned
endmodul e
modul e mi pssi ngl e( i nput l ogi c cl k, r eset ,
out put l ogi c [ 31: 0] pc,
i nput l ogi c [ 31: 0] i nst r ,
out put l ogi c memwr i t e,
out put l ogi c [ 31: 0] al ur esul t ,
wr i t edat a,
i nput l ogi c [ 31: 0] r eaddat a) ;
l ogi c memt or eg;
l ogi c [ 1: 0] al usr c; / / LUI
l ogi c r egdst ;
l ogi c r egwr i t e, j ump, pcsr c, zer o;
l ogi c [ 3: 0] al ucont r ol ; / / SLL
l ogi c l t ez; / / BLEZ
cont r ol l er c( i nst r [ 31: 26] , i nst r [ 5: 0] , zer o,
memt or eg, memwr i t e, pcsr c,
al usr c, r egdst , r egwr i t e, j ump,
al ucont r ol ,
l t ez) ; / / BLEZ

dat apat h dp( cl k, r eset , memt or eg, pcsr c,
al usr c, r egdst , r egwr i t e, j ump,
al ucont r ol ,
zer o, pc, i nst r ,
al ur esul t , wr i t edat a, r eaddat a,
l t ez) ; / / BLEZ
endmodul e
modul e cont r ol l er ( i nput l ogi c [ 5: 0] op, f unct ,
i nput l ogi c zer o,
out put l ogi c memt or eg, memwr i t e,
out put l ogi c pcsr c,
out put l ogi c [ 1: 0] al usr c, / / LUI
out put l ogi c r egdst ,
out put l ogi c r egwr i t e,
out put l ogi c j ump,
out put l ogi c [ 3: 0] al ucont r ol , / / SLL
i nput l ogi c l t ez) ; / / BLEZ
l ogi c [ 1: 0] al uop;
S OL U T I O N S 243
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
l ogi c br anch;
l ogi c bl ez; / / BLEZ
mai ndec md( op, memt or eg, memwr i t e, br anch,
al usr c, r egdst , r egwr i t e, j ump,
al uop, bl ez) ; / / BLEZ
al udec ad( f unct , al uop, al ucont r ol ) ;
/ / BLEZ
assi gn pcsr c = ( br anch & zer o) | ( bl ez & l t ez) ;

endmodul e
modul e mai ndec( i nput l ogi c [ 5: 0] op,
out put l ogi c memt or eg, memwr i t e,
out put l ogi c br anch,
out put l ogi c [ 1: 0] al usr c, / / LUI
out put l ogi c r egdst ,
out put l ogi c r egwr i t e,
out put l ogi c j ump,
out put l ogi c [ 1: 0] al uop,
out put l ogi c bl ez) ; / / BLEZ
/ / i ncr ease cont r ol wi dt h f or LUI , BLEZ
l ogi c [ 10: 0] cont r ol s;
assi gn {r egwr i t e, r egdst , al usr c, br anch, memwr i t e,
memt or eg, al uop, j ump, bl ez} = cont r ol s;
al ways_comb
case( op)
6' b000000: cont r ol s = 11' b11000001000; / / Rt ype
6' b100011: cont r ol s = 11' b10010010000; / / LW
6' b101011: cont r ol s = 11' b00010100000; / / SW
6' b000100: cont r ol s = 11' b00001000100; / / BEQ
6' b001000: cont r ol s = 11' b10010000000; / / ADDI
6' b000010: cont r ol s = 11' b00000000010; / / J
6' b001010: cont r ol s = 11' b10010001100; / / SLTI
6' b001111: cont r ol s = 11' b10100000000; / / LUI
6' b000110: cont r ol s = 11' b00000000101; / / BLEZ
def aul t : cont r ol s = 11' bxxxxxxxxxxx; / / ???
endcase
endmodul e
modul e al udec( i nput l ogi c [ 5: 0] f unct ,
i nput l ogi c [ 1: 0] al uop,
out put l ogi c [ 3: 0] al ucont r ol ) ;
/ / i ncr ease t o 4 bi t s f or SLL
al ways_comb
case( al uop)
2' b00: al ucont r ol = 4' b0010; / / add
2' b01: al ucont r ol = 4' b1010; / / sub
244 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
2' b11: al ucont r ol = 4' b1011; / / sl t
def aul t : case( f unct ) / / RTYPE
6' b100000: al ucont r ol = 4' b0010; / / ADD
6' b100010: al ucont r ol = 4' b1010; / / SUB
6' b100100: al ucont r ol = 4' b0000; / / AND
6' b100101: al ucont r ol = 4' b0001; / / OR
6' b101010: al ucont r ol = 4' b1011; / / SLT
6' b000000: al ucont r ol = 4' b0100; / / SLL
def aul t : al ucont r ol = 4' bxxxx; / / ???
endcase
endcase
endmodul e
modul e dat apat h( i nput l ogi c cl k, r eset ,
i nput l ogi c memt or eg, pcsr c,
i nput l ogi c [ 1: 0] al usr c, / / LUI
i nput l ogi c r egdst ,
i nput l ogi c r egwr i t e, j ump,
i nput l ogi c [ 3: 0] al ucont r ol , / / SLL
out put l ogi c zer o,
out put l ogi c [ 31: 0] pc,
i nput l ogi c [ 31: 0] i nst r ,
out put l ogi c [ 31: 0] al ur esul t , wr i t edat a,
i nput l ogi c [ 31: 0] r eaddat a,
out put l ogi c l t ez) ; / / LTEZ
l ogi c [ 4: 0] wr i t er eg;
l ogi c [ 31: 0] pcnext , pcnext br , pcpl us4, pcbr anch;
l ogi c [ 31: 0] si gni mm, si gni mmsh;
l ogi c [ 31: 0] upper i mm; / / LUI
l ogi c [ 31: 0] sr ca, sr cb;
l ogi c [ 31: 0] r esul t ;
l ogi c [ 31: 0] memdat a;
/ / next PC l ogi c
f l opr #( 32) pcr eg( cl k, r eset , pcnext , pc) ;
adder pcadd1( pc, 32' b100, pcpl us4) ;
sl 2 i mmsh( si gni mm, si gni mmsh) ;
adder pcadd2( pcpl us4, si gni mmsh, pcbr anch) ;
mux2 #( 32) pcbr mux( pcpl us4, pcbr anch, pcsr c,
pcnext br ) ;
mux2 #( 32) pcmux( pcnext br , {pcpl us4[ 31: 28] ,
i nst r [ 25: 0] , 2' b00},
j ump, pcnext ) ;
/ / r egi st er f i l e l ogi c
r egf i l e r f ( cl k, r egwr i t e, i nst r [ 25: 21] ,
i nst r [ 20: 16] , wr i t er eg,
wr i t er esul t , sr ca, wr i t edat a) ;
mux2 #( 5) wr mux( i nst r [ 20: 16] , i nst r [ 15: 11] ,
r egdst , wr i t er eg) ;

S OL U T I O N S 245
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
si gnext se( i nst r [ 15: 0] , si gni mm) ;
upi mm ui ( i nst r [ 15: 0] , upper i mm) ; / / LUI
/ / ALU l ogi c
mux3 #( 32) sr cbmux( wr i t edat a, si gni mm,
upper i mm, al usr c,
sr cb) ; / / LUI
al u al u( sr ca, sr cb, al ucont r ol ,
i nst r [ 10: 6] , / / SLL
al ur esul t , zer o,
l t ez) ; / / BLEZ
mux2 #( 32) r dmux( al ur esul t , r eaddat a,
memt or eg, r esul t ) ;
endmodul e
/ / upi mmmodul e needed f or LUI
modul e upi mm( i nput l ogi c [ 15: 0] a,
out put l ogi c [ 31: 0] y) ;

assi gn y = {a, 16' b0};
endmodul e
/ / mux3 needed f or LUI
modul e mux3 #( par amet er WI DTH = 8)
( i nput l ogi c [ WI DTH- 1: 0] d0, d1, d2,
i nput l ogi c [ 1: 0] s,
out put l ogi c [ WI DTH- 1: 0] y) ;
assi gn #1 y = s[ 1] ? d2 : ( s[ 0] ? d1 : d0) ;
endmodul e
modul e al u( i nput l ogi c [ 31: 0] A, B,
i nput l ogi c [ 3: 0] F,
i nput l ogi c [ 4: 0] shamt , / / SLL
out put l ogi c [ 31: 0] Y,
out put l ogi c Zer o,
out put l ogi c l t ez) ; / / BLEZ
l ogi c [ 31: 0] S, Bout ;
assi gn Bout = F[ 3] ? ~B : B;
assi gn S = A + Bout + F[ 3] ; / / SLL
al ways_comb
case ( F[ 2: 0] )
3' b000: Y = A & Bout ;
3' b001: Y = A | Bout ;
3' b010: Y = S;
3' b011: Y = S[ 31] ;
3' b100: Y = ( Bout << shamt ) ; / / SLL
endcase
246 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
assi gn Zer o = ( Y == 32' b0) ;
assi gn l t ez = Zer o | S[ 31] ; / / BLEZ
endmodul e
modul e r egf i l e( i nput l ogi c cl k,
i nput l ogi c we3,
i nput l ogi c [ 4: 0] r a1, r a2, wa3,
i nput l ogi c [ 31: 0] wd3,
out put l ogi c [ 31: 0] r d1, r d2) ;
l ogi c [ 31: 0] r f [ 31: 0] ;
/ / t hr ee por t ed r egi st er f i l e
/ / r ead t wo por t s combi nat i onal l y
/ / wr i t e t hi r d por t on r i si ng edge of cl k
/ / r egi st er 0 har dwi r ed t o 0
al ways_f f @( posedge cl k)
i f ( we3) r f [ wa3] <= wd3;
assi gn r d1 = ( r a1 ! = 0) ? r f [ r a1] : 0;
assi gn r d2 = ( r a2 ! = 0) ? r f [ r a2] : 0;
endmodul e
modul e adder ( i nput l ogi c [ 31: 0] a, b,
out put l ogi c [ 31: 0] y) ;
assi gn y = a + b;
endmodul e
modul e sl 2( i nput l ogi c [ 31: 0] a,
out put l ogi c [ 31: 0] y) ;
/ / shi f t l ef t by 2
assi gn y = {a[ 29: 0] , 2' b00};
endmodul e
modul e si gnext ( i nput l ogi c [ 15: 0] a,
out put l ogi c [ 31: 0] y) ;

assi gn y = {{16{a[ 15] }}, a};
endmodul e
modul e f l opr #( par amet er WI DTH = 8)
( i nput l ogi c cl k, r eset ,
i nput l ogi c [ WI DTH- 1: 0] d,
out put l ogi c [ WI DTH- 1: 0] q) ;
al ways_f f @( posedge cl k, posedge r eset )
i f ( r eset ) q <= 0;
el se q <= d;
S OL U T I O N S 247
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
endmodul e
modul e mux2 #( par amet er WI DTH = 8)
( i nput l ogi c [ WI DTH- 1: 0] d0, d1,
i nput l ogi c s,
out put l ogi c [ WI DTH- 1: 0] y) ;
assi gn y = s ? d1 : d0;
endmodul e
VHDL
- - mi ps. vhd
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ; use I EEE. NUMERI C_STD_UN-
SI GNED. al l ;
ent i t y t est bench i s
end;
ar chi t ect ur e t est of t est bench i s
component t op
por t ( cl k, r eset : i n STD_LOGI C;
wr i t edat a, dat aadr : out STD_LOGI C_VECTOR( 31 downt o 0) ;
memwr i t e: out STD_LOGI C) ;
end component ;
si gnal wr i t edat a, dat aadr : STD_LOGI C_VECTOR( 31 downt o 0) ;
si gnal cl k, r eset , memwr i t e: STD_LOGI C;
begi n
- - i nst ant i at e devi ce t o be t est ed
dut : t op por t map( cl k, r eset , wr i t edat a, dat aadr , memwr i t e) ;
- - Gener at e cl ock wi t h 10 ns per i od
pr ocess begi n
cl k <= ' 1' ;
wai t f or 5 ns;
cl k <= ' 0' ;
wai t f or 5 ns;
end pr ocess;
- - Gener at e r eset f or f i r st t wo cl ock cycl es
pr ocess begi n
r eset <= ' 1' ;
wai t f or 22 ns;
r eset <= ' 0' ;
wai t ;
end pr ocess;
- - check t hat 7 get s wr i t t en t o addr ess 84 at end of pr ogr am
248 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
pr ocess ( cl k) begi n
i f ( cl k' event and cl k = ' 0' and memwr i t e = ' 1' ) t hen
i f ( t o_i nt eger ( dat aadr ) = 84 and t o_i nt eger ( wr i t edat a) =
7) t hen
r epor t " NO ERRORS: Si mul at i on succeeded" sever i t y f ai l -
ur e;
el si f ( dat aadr / = 80) t hen
r epor t " Si mul at i on f ai l ed" sever i t y f ai l ur e;
end i f ;
end i f ;
end pr ocess;
end;
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ; use I EEE. NUMERI C_STD_UN-
SI GNED. al l ;
ent i t y t op i s - - t op- l evel desi gn f or t est i ng
por t ( cl k, r eset : i n STD_LOGI C;
wr i t edat a, dat aadr : buf f er STD_LOGI C_VECTOR( 31 downt o
0) ;
memwr i t e: buf f er STD_LOGI C) ;
end;
ar chi t ect ur e t est of t op i s
component mi ps
por t ( cl k, r eset : i n STD_LOGI C;
pc: out STD_LOGI C_VECTOR( 31 downt o 0) ;
i nst r : i n STD_LOGI C_VECTOR( 31 downt o 0) ;
memwr i t e: out STD_LOGI C;
al ur esul t : out STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: out STD_LOGI C_VECTOR( 31 downt o 0) ;
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component i mem
por t ( a: i n STD_LOGI C_VECTOR( 5 downt o 0) ;
r d: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component dmem
por t ( cl k, we: i n STD_LOGI C;
a, wd: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
r d: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
si gnal pc, i nst r ,
r eaddat a: STD_LOGI C_VECTOR( 31 downt o 0) ;
begi n
- - i nst ant i at e pr ocessor and memor i es
mi ps1: mi ps por t map( cl k, r eset , pc, i nst r , memwr i t e, dat aadr ,
wr i t edat a, r eaddat a) ;
i mem1: i mempor t map( pc( 7 downt o 2) , i nst r ) ;
dmem1: dmempor t map( cl k, memwr i t e, dat aadr , wr i t edat a, r e-
addat a) ;
end;
S OL U T I O N S 249
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ; use STD. TEXTI O. al l ;
use I EEE. NUMERI C_STD_UNSI GNED. al l ;
ent i t y dmemi s - - dat a memor y
por t ( cl k, we: i n STD_LOGI C;
a, wd: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
r d: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e behave of dmemi s
begi n
pr ocess i s
t ype r amt ype i s ar r ay ( 63 downt o 0) of STD_LOGI C_VECTOR( 31
downt o 0) ;
var i abl e mem: r amt ype;
begi n
- - r ead or wr i t e memor y
l oop
i f cl k' event and cl k = ' 1' t hen
i f ( we =' 1' ) t hen mem( t o_i nt eger ( a( 7 downt o 2) ) ) : =wd;
end i f ;
end i f ;
r d <= mem( t o_i nt eger ( a( 7 downt o 2) ) ) ;
wai t on cl k, a;
end l oop;
end pr ocess;
end;
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ; use STD. TEXTI O. al l ;
use I EEE. NUMERI C_STD_UNSI GNED. al l ;
ent i t y i memi s - - i nst r uct i on memor y
por t ( a: i n STD_LOGI C_VECTOR( 5 downt o 0) ;
r d: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e behave of i memi s
begi n
pr ocess i s
f i l e mem_f i l e: TEXT;
var i abl e L: l i ne;
var i abl e ch: char act er ;
var i abl e i , i ndex, r esul t : i nt eger ;
t ype r amt ype i s ar r ay ( 63 downt o 0) of STD_LOGI C_VECTOR( 31
downt o 0) ;
var i abl e mem: r amt ype;
begi n
- - i ni t i al i ze memor y f r omf i l e
f or i i n 0 t o 63 l oop - - set al l cont ent s l ow
250 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
mem( i ) : = ( ot her s => ' 0' ) ;
end l oop;
i ndex : = 0;
FI LE_OPEN( mem_f i l e, " C: / docs/ DDCA2e/ hdl / memf i l e. dat " ,
READ_MODE) ;
whi l e not endf i l e( mem_f i l e) l oop
r eadl i ne( mem_f i l e, L) ;
r esul t : = 0;
f or i i n 1 t o 8 l oop
r ead( L, ch) ;
i f ' 0' <= ch and ch <= ' 9' t hen
r esul t : = char act er ' pos( ch) - char act er ' pos( ' 0' ) ;
el si f ' a' <= ch and ch <= ' f ' t hen
r esul t : = char act er ' pos( ch) - char act er ' pos( ' a' ) +10;
el se r epor t "For mat er r or on l i ne " & i nt eger ' i mage( i n-
dex)
sever i t y er r or ;
end i f ;
mem( i ndex) ( 35- i *4 downt o 32- i *4) : =t o_st d_l ogi c_vec-
t or ( r esul t , 4) ;
end l oop;
i ndex : = i ndex + 1;
end l oop;
- - r ead memor y
l oop
r d <= mem( t o_i nt eger ( a) ) ;
wai t on a;
end l oop;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mi ps i s - - si ngl e cycl e MI PS pr ocessor
por t ( cl k, r eset : i n STD_LOGI C;
pc: out STD_LOGI C_VECTOR( 31 downt o 0) ;
i nst r : i n STD_LOGI C_VECTOR( 31 downt o 0) ;
memwr i t e: out STD_LOGI C;
al ur esul t : out STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: out STD_LOGI C_VECTOR( 31 downt o 0) ;
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e st r uct of mi ps i s
component cont r ol l er
por t ( op, f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: i n STD_LOGI C;
memt or eg, memwr i t e: out STD_LOGI C;
pcsr c: out STD_LOGI C;
al usr c: out STD_LOGI C_VECTOR( 1 downt o 0) ; - - LUI
r egdst , r egwr i t e: out STD_LOGI C;
j ump: out STD_LOGI C;
S OL U T I O N S 251
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
al ucont r ol : out STD_LOGI C_VECTOR( 3 downt o 0) ; -
- SLL
l t ez: out STD_LOGI C) ; - - BLEZ
end component ;
component dat apat h
por t ( cl k, r eset : i n STD_LOGI C;
memt or eg, pcsr c: i n STD_LOGI C;
al usr c, r egdst : i n STD_LOGI C;
r egwr i t e, j ump: i n STD_LOGI C;
al ucont r ol : i n STD_LOGI C_VECTOR( 2 downt o 0) ;
zer o: out STD_LOGI C;
pc: buf f er STD_LOGI C_VECTOR( 31 downt o 0) ;
i nst r : i n STD_LOGI C_VECTOR( 31 downt o 0) ;
al ur esul t : buf f er STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: buf f er STD_LOGI C_VECTOR( 31 downt o 0) ;
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
si gnal memt or eg: STD_LOGI C;
si gnal al usr c: STD_LOGI C_VECTOR( 1 downt o 0) ; - - LUI
si gnal r egdst , r egwr i t e, j ump, pcsr c: STD_LOGI C;
si gnal zer o: STD_LOGI C;
si gnal al ucont r ol : STD_LOGI C_VECTOR( 3 downt o 0) ; - - SLL
si gnal l t ez: STD_LOGI C; - - BLEZ
begi n
cont : cont r ol l er por t map( i nst r ( 31 downt o 26) , i nst r ( 5 downt o
0) ,
zer o, memt or eg, memwr i t e, pcsr c, al usr c,
r egdst , r egwr i t e, j ump, al ucont r ol ,
l t ez) ; - - BLEZ
dp: dat apat h por t map( cl k, r eset , memt or eg, pcsr c, al usr c,
r egdst ,
r egwr i t e, j ump, al ucont r ol , zer o, pc, i nst r ,
al ur esul t , wr i t edat a, r eaddat a,
l t ez) ; - - BLEZ
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y cont r ol l er i s - - si ngl e cycl e cont r ol decoder
por t ( op, f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: i n STD_LOGI C;
memt or eg, memwr i t e: out STD_LOGI C;
pcsr c: out STD_LOGI C;
al usr c: out STD_LOGI C_VECTOR( 1 downt o 0) ; - - LUI
r egdst , r egwr i t e: out STD_LOGI C;
j ump: out STD_LOGI C;
al ucont r ol : out STD_LOGI C_VECTOR( 3 downt o 0) ; -
- SLL
l t ez: out STD_LOGI C) ; - - BLEZ
end;
ar chi t ect ur e st r uct of cont r ol l er i s
component mai ndec
252 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
por t ( op: i n STD_LOGI C_VECTOR( 5 downt o 0) ;
memt or eg, memwr i t e: out STD_LOGI C;
br anch: out STD_LOGI C;
al usr c: out STD_LOGI C_VECTOR( 1 downt o 0) ;
- - LUI
r egdst , r egwr i t e: out STD_LOGI C;
j ump: out STD_LOGI C;
al uop: out STD_LOGI C_VECTOR( 1 downt o 0) ;
bl ez: out STD_LOGI C) ;
end component ;
component al udec
por t ( f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
al uop: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 3 downt o 0) ) ; - - SLL
end component ;
si gnal al uop: STD_LOGI C_VECTOR( 1 downt o 0) ;
si gnal br anch: STD_LOGI C;
si gnal bl ez: STD_LOGI C; - - BLEZ
begi n
md: mai ndec por t map( op, memt or eg, memwr i t e, br anch,
al usr c, r egdst , r egwr i t e, j ump, al uop, bl ez) ;
ad: al udec por t map( f unct , al uop, al ucont r ol ) ;
- - BLEZ
pcsr c <= ( br anch and zer o) or ( bl ez and l t ez) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mai ndec i s - - mai n cont r ol decoder
por t ( op: i n STD_LOGI C_VECTOR( 5 downt o 0) ;
memt or eg, memwr i t e: out STD_LOGI C;
br anch: out STD_LOGI C;
al usr c: out STD_LOGI C_VECTOR( 1 downt o 0) ; - - LUI
r egdst , r egwr i t e: out STD_LOGI C;
j ump: out STD_LOGI C;
al uop: out STD_LOGI C_VECTOR( 1 downt o 0) ;
bl ez: out STD_LOGI C) ;
end;
ar chi t ect ur e behave of mai ndec i s
si gnal cont r ol s: STD_LOGI C_VECTOR( 10 downt o 0) ;
begi n
pr ocess( al l ) begi n
case op i s
when " 000000" => cont r ol s <= " 11000001000" ; - - RTYPE
when " 100011" => cont r ol s <= " 10010010000" ; - - LW
when " 101011" => cont r ol s <= " 00010100000" ; - - SW
when " 000100" => cont r ol s <= " 00001000100" ; - - BEQ
when " 001000" => cont r ol s <= " 10010000000" ; - - ADDI
when " 000010" => cont r ol s <= " 00000000010" ; - - J
when " 001010" => cont r ol s <= " 10010001100" ; - - SLTI
when " 001111" => cont r ol s <= " 10100000000" ; - - LUI
S OL U T I O N S 253
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
when " 000110" => cont r ol s <= " 00000000101" ; - - BLEZ
when ot her s => cont r ol s <= "- - - - - - - - - - - " ; - - i l l egal op
end case;
end pr ocess;
( r egwr i t e, r egdst , al usr c, br anch, memwr i t e,
memt or eg, al uop( 1 downt o 0) , j ump, bl ez) <= cont r ol s;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y al udec i s - - ALU cont r ol decoder
por t ( f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
al uop: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 3 downt o 0) ) ; - - SLL
end;
ar chi t ect ur e behave of al udec i s
begi n
pr ocess( al l ) begi n
case al uop i s
when " 00" => al ucont r ol <= " 0010" ; - - add
when " 01" => al ucont r ol <= " 1010" ; - - sub
when " 11" => al ucont r ol <= " 1011" ; - - sl t
when ot her s => case f unct i s - - R- t ype i nst r uct i ons
when " 100000" => al ucont r ol <= " 0010" ;
- - add
when " 100010" => al ucont r ol <= " 1010" ;
- - sub
when " 100100" => al ucont r ol <= " 0000" ;
- - and
when " 100101" =>al ucont r ol <=" 0001" ; - - or
when " 101010" => al ucont r ol <= " 1011" ;
- - sl t
when " 000000" => al ucont r ol <= " 0100" ;
- - sl l
when ot her s =>al ucont r ol <=" - - - - " ; - - ???
end case;
end case;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ; use I EEE. STD_LOG-
I C_ARI TH. al l ;
ent i t y dat apat h i s - - MI PS dat apat h
por t ( cl k, r eset : i n STD_LOGI C;
memt or eg, pcsr c: i n STD_LOGI C;
al usr c: i n STD_LOGI C_VECTOR( 1 downt o 0) ; - - LUI
al usr c, r egdst : i n STD_LOGI C;
r egwr i t e, j ump: i n STD_LOGI C;
al ucont r ol : i n STD_LOGI C_VECTOR( 3 downt o 0) ; -
- SLL
254 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
zer o: out STD_LOGI C;
pc: buf f er STD_LOGI C_VECTOR( 31 downt o 0) ;
i nst r : i n STD_LOGI C_VECTOR( 31 downt o 0) ;
al ur esul t : buf f er STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: buf f er STD_LOGI C_VECTOR( 31 downt o 0) ;
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
l t ez: out STD_LOGI C) ; - - LTEZ
end;
ar chi t ect ur e st r uct of dat apat h i s
component al u
por t ( a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
al ucont r ol : i n STD_LOGI C_VECTOR( 3 downt o 0) ; - - SLL
shamt : i n STD_LOGI C_VECTOR( 4 downt o 0) ; - - SLL
r esul t : buf f er STD_LOGI C_VECTOR( 31 downt o 0) ;
zer o: buf f er STD_LOGI C; - - BLEZ
l t ez: out STD_LOGI C) ; - - BLEZ
end component ;
component r egf i l e
por t ( cl k: i n STD_LOGI C;
we3: i n STD_LOGI C;
r a1, r a2, wa3: i n STD_LOGI C_VECTOR( 4 downt o 0) ;
wd3: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
r d1, r d2: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component adder
por t ( a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component sl 2
por t ( a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component si gnext
por t ( a: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component upi mm
por t ( a: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component f l opr gener i c( wi dt h: i nt eger ) ;
por t ( cl k, r eset : i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component mux2 gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component mux3 gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
S OL U T I O N S 255
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
si gnal wr i t er eg: STD_LOGI C_VECTOR( 4 downt o 0) ;
si gnal pcj ump, pcnext ,
pcnext br , pcpl us4,
pcbr anch: STD_LOGI C_VECTOR( 31 downt o 0) ;
si gnal upper i mm: STD_LOGI C_VECTOR( 31 downt o 0) ; -
- LUI
si gnal si gni mm, si gni mmsh: STD_LOGI C_VECTOR( 31 downt o 0) ;
si gnal sr ca, sr cb, r esul t : STD_LOGI C_VECTOR( 31 downt o 0) ;
begi n
- - next PC l ogi c
pcj ump <= pcpl us4( 31 downt o 28) & i nst r ( 25 downt o 0) & " 00" ;
pcr eg: f l opr gener i c map( 32) por t map( cl k, r eset , pcnext , pc) ;
pcadd1: adder por t map( pc, X" 00000004" , pcpl us4) ;
i mmsh: sl 2 por t map( si gni mm, si gni mmsh) ;
pcadd2: adder por t map( pcpl us4, si gni mmsh, pcbr anch) ;
pcbr mux: mux2 gener i c map( 32) por t map( pcpl us4, pcbr anch,
pcsr c, pcnext br ) ;
pcmux: mux2 gener i c map( 32) por t map( pcnext br , pcj ump, j ump,
pcnext ) ;
- - r egi st er f i l e l ogi c
r f : r egf i l e por t map( cl k, r egwr i t e, i nst r ( 25 downt o 21) ,
i nst r ( 20 downt o 16) , wr i t er eg, r esul t , sr ca,
wr i t edat a) ;
wr mux: mux2 gener i c map( 5) por t map( i nst r ( 20 downt o 16) ,
i nst r ( 15 downt o 11) ,
r egdst , wr i t er eg) ;
r esmux: mux2 gener i c map( 32) por t map( al ur esul t , r eaddat a,
memt or eg, r esul t ) ;
se: si gnext por t map( i nst r ( 15 downt o 0) , si gni mm) ;
ui : upi mmpor t map( i nst r ( 15 downt o 0) , upper i mm) ; - - LUI
- - ALU l ogi c
sr cbmux: mux3 gener i c map( 32) por t map( wr i t edat a, si gni mm,
upper i mm,
al usr c, sr cb) ; - - LUI
mai nal u: al u por t map( sr ca, sr cb, al ucont r ol , i nst r ( 10 downt o
6) , - - SLL
al ur esul t , zer o, l t ez) ; - - BLEZ
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use I EEE. NUMERI C_STD_UNSI GNED. al l ;
ent i t y r egf i l e i s - - t hr ee- por t r egi st er f i l e
por t ( cl k: i n STD_LOGI C;
we3: i n STD_LOGI C;
r a1, r a2, wa3: i n STD_LOGI C_VECTOR( 4 downt o 0) ;
wd3: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
256 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
r d1, r d2: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e behave of r egf i l e i s
t ype r amt ype i s ar r ay ( 31 downt o 0) of STD_LOGI C_VECTOR( 31
downt o 0) ;
si gnal mem: r amt ype;
begi n
- - t hr ee- por t ed r egi st er f i l e
- - r ead t wo por t s combi nat i onal l y
- - wr i t e t hi r d por t on r i si ng edge of cl ock
- - r egi st er 0 har dwi r ed t o 0
pr ocess( cl k) begi n
i f r i si ng_edge( cl k) t hen
i f we3 = ' 1' t hen mem( t o_i nt eger ( wa3) ) <= wd3;
end i f ;
end i f ;
end pr ocess;
pr ocess( al l ) begi n
i f ( t o_i nt eger ( r a1) =0) t hen r d1 <=X" 00000000" ; - - r egi st er
0 hol ds 0
el se r d1 <= mem( t o_i nt eger ( r a1) ) ;
end i f ;
i f ( t o_i nt eger ( r a2) = 0) t hen r d2 <= X" 00000000" ;
el se r d2 <= mem( t o_i nt eger ( r a2) ) ;
end i f ;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use I EEE. NUMERI C_STD_UNSI GNED. al l ;
ent i t y adder i s - - adder
por t ( a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e behave of adder i s
begi n
y <= a + b;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y sl 2 i s - - shi f t l ef t by 2
por t ( a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e behave of sl 2 i s
begi n
y <= a( 29 downt o 0) & " 00" ;
S OL U T I O N S 257
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y si gnext i s - - si gn ext ender
por t ( a: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e behave of si gnext i s
begi n
y <= X" f f f f " & a when a( 15) el se X" 0000" & a;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y upi mmi s - - cr eat e upper i mmedi at e f or LUI
por t ( a: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e behave of upi mmi s
begi n
y <= a & X" 0000" ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ; use I EEE. STD_LOG-
I C_ARI TH. al l ;
ent i t y f l opr i s - - f l i p- f l op wi t h synchr onous r eset
gener i c( wi dt h: i nt eger ) ;
por t ( cl k, r eset : i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e asynchr onous of f l opr i s
begi n
pr ocess( cl k, r eset ) begi n
i f r eset t hen q <= ( ot her s => ' 0' ) ;
el si f r i si ng_edge( cl k) t hen
q <= d;
end i f ;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mux2 i s - - t wo- i nput mul t i pl exer
gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
258 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
ar chi t ect ur e behave of mux2 i s
begi n
y <= d1 when s el se d0;
end;
- - 3: 1 mux needed f or LUI
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mux3 i s - - t hr ee- i nput mul t i pl exer
gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e behave of mux3 i s
begi n
y <= d1 when s( 1) el se ( d1 when s( 0) el se d0) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
use I EEE. NUMERI C_STD_UNSI GNED. al l ;
ent i t y al u i s
por t ( a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
al ucont r ol : i n STD_LOGI C_VECTOR( 3 downt o 0) ; - - SLL
shamt : i n STD_LOGI C_VECTOR( 4 downt o 0) ; - - SLL
r esul t : buf f er STD_LOGI C_VECTOR( 31 downt o 0) ;
zer o: buf f er STD_LOGI C; - - BLEZ
l t ez: out STD_LOGI C) ; - - BLEZ
end;
ar chi t ect ur e behave of al u i s
si gnal condi nvb, sum: STD_LOGI C_VECTOR( 31 downt o 0) ;
begi n
condi nvb <= not b when al ucont r ol ( 3) el se b;
sum<= a + condi nvb + al ucont r ol ( 3) ;
pr ocess( al l ) begi n
case al ucont r ol ( 2 downt o 0) i s
when " 000" => r esul t <= a and b;
when " 001" => r esul t <= a or b;
when " 010" => r esul t <= sum;
when " 011" => r esul t <= ( 0 => sum( 31) , ot her s => ' 0' ) ;
when " 100" => r esul t <= ( condi nvb << shamt ) ; - - SLL
when ot her s => r esul t <= ( ot her s => ' X' ) ;
end case;
end pr ocess;
zer o <= ' 1' when r esul t = X" 00000000" el se ' 0' ;
l t ez <= zer o or sum( 31) ;
end;
S OL U T I O N S 259
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 7.13
(a) sr l v
First, we show the modifications to the ALU.
FIGURE 7.5 Modified ALU to support sr l v
[4:0]
+
20 1
A B
C
out
Result
3
0
1
ALUControl
3
ALUControl
2:0
[N-1] S
N N
N
N
N N N N
N
3
Z
e
r
o
E
x
t
e
n
d
>>
s
h
a
m
t
4
:
0
N
4
260 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Next, we show the modifications to the ALU decoder.
FIGURE 7.6 Modified ALU operations to support sr l v
A L U C ont r ol
3: 0
F unct i on
0000 A AND B
0001 A OR B
0010 A +B
0011 not used
1000 A AND B
1001 A OR B
1010 A - B
1011 SLT
0100 SRLV
A L U Op F unct A L U C ont r ol
00 X 0010 (add)
X1 X 1010 (subtract)
1X 100000 (add) 0010 (add)
1X 100010 (sub) 1010 (subtract)
1X 100100 (and) 0000 (and)
1X 100101 (or ) 0001 (or)
1X 101010 (sl t ) 1011 (set less than)
1X 000110 (srlv) 0100 (shift right logical variable)
TABLE 7.8 ALU decoder truth table
S OL U T I O N S 261
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Next, we show the changes to the datapath. The only modification is the
width of ALUControl. No changes are made to the datapath main control FSM.
FIGURE 7.7 Modified multicycle MIPS datapath to support sl l
(b) or i
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB 20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
t
o
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
3:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
EN EN
ALUSrcB
1:0 IRWrite
IorD
PCWrite
PCEn
262 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
We add a zero extension unit to the datapath, extend the ALUSrcB signal
from 2 bits to 3 bits, and extend the SrcB multiplexer from 4 inputs to 5 inputs.
We also modify the ALU decoder and main control FSM.
FIGURE 7.8 Modified datapath for or i
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB 20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
t
o
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
000
001
010
011
4
CLK
EN EN
ALUSrcB
2:0 IRWrite
IorD
PCWrite
PCEn
Zero Extend
15:0
100
A L U Op F unct A L U C ont r ol
00 X 010 (add)
01 X 110 (subtract)
11 X 001 (or)
10 100000 (add) 010 (add)
10 100010 (sub) 110 (subtract)
10 100100 (and) 000 (and)
TABLE 7.9 ALU decoder truth table
S OL U T I O N S 263
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
10 100101 (or ) 001 (or)
10 101010 (sl t ) 111 (set less than)
A L U Op F unct A L U C ont r ol
TABLE 7.9 ALU decoder truth table
ALUSrcA =1
ALUSrcB =000
ALUOp =01
PCSrc =1
Branch
IorD =0
AluSrcA =0
ALUSrcB =001
ALUOp =00
PCSrc =0
IRWrite
PCWrite
ALUSrcA =0
ALUSrcB =011
ALUOp =00
ALUSrcA =1
ALUSrcB =010
ALUOp =00
IorD =1
RegDst =1
MemtoReg =0
RegWrite
IorD =1
MemWrite
ALUSrcA =1
ALUSrcB =000
ALUOp =10
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op =LW
or
Op =SW
Op =R-type
Op =BEQ
Op =LW
Op =SW
RegDst =0
MemtoReg =1
RegWrite
S4: Mem
Writeback
ALUSrcA = 1
ALUSrcB = 100
ALUOp = 11
RegDst = 0
MemtoReg = 0
RegWrite
Op = ORI
S9: ORI
Execute
S10: ORI
Writeback
264 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
(c) xor i
First, we modify the ALU and the ALU decoder.
l
A L U C ont r ol
3: 0
F unct i on
0000 A AND B
0001 A OR B
0010 A +B
0011 not used
1000 A AND B
1001 A OR B
1010 A - B
1011 SLT
0100 A XOR B
+
20 1
A B
C
out
Result
3
0
1
ALUControl
3
ALUControl
2:0
[N-1] S
N N
N
N
N N N N
N
3
Z
e
r
o
E
x
t
e
n
d
N
4
S OL U T I O N S 265
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Next, we modify the datapath. We change the buswidth of the ALUControl
signal from 3 bits to 4 bits and the ALUSrcB signal from 2 bits to 3 bits. We
also extend the SrcB mux and add a zero-extension unit.
A L U Op F unct A L U C ont r ol
00 X 0010 (add)
01 X 1010 (subtract)
11 X 0100 (xor)
10 100000 (add) 0010 (add)
10 100010 (sub) 1010 (subtract)
10 100100 (and) 0000 (and)
10 100101 (or ) 0001 (or)
10 101010 (sl t ) 1011 (set less than)
TABLE 7.10 ALU decoder truth table for xor i
266 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
And finally, we modify the main control FSM.
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB 20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
t
o
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
3:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
000
001
010
011
4
CLK
EN EN
ALUSrcB
2:0 IRWrite
IorD
PCWrite
PCEn
Zero Extend
15:0
100
S OL U T I O N S 267
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(d) j r
First, we extend the ALU Decoder for j r .
IorD =0
AluSrcA =0
ALUSrcB =001
ALUOp =00
PCSrc =0
IRWrite
PCWrite
ALUSrcA =0
ALUSrcB =011
ALUOp =00
ALUSrcA =1
ALUSrcB =010
ALUOp =00
IorD =1
RegDst =1
MemtoReg =0
RegWrite
IorD =1
MemWrite
ALUSrcA =1
ALUSrcB =000
ALUOp =10
ALUSrcA =1
ALUSrcB =000
ALUOp =01
PCSrc =1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op =LW
or
Op =SW
Op =R-type
Op =BEQ
Op =LW
Op =SW
RegDst =0
MemtoReg =1
RegWrite
S4: Mem
Writeback
ALUSrcA = 1
ALUSrcB = 100
ALUOp = 11
RegDst = 0
MemtoReg = 0
RegWrite
Op = XORI
S9: XORI
Execute
S10: XORI
Writeback
A L U Op F unct A L U C ont r ol
00 X 010 (add)
X1 X 110 (subtract)
1X 100000 (add) 010 (add)
1X 100010 (sub) 110 (subtract)
1X 100100 (and) 000 (and)
1X 100101 (or ) 001 (or)
TABLE 7.11 ALU decoder truth table with j r
268 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Next, we modify the main controller. The datapath requires no modifica-
tion.
Exercise 7.15
Yes, it is possible to add this instruction without modifying the register file.
First we show the modifications to the datapath. The only modification is add-
ing the r s field of the instruction (Instruction
25:21
) to the input of the write ad-
dress mux of the register file. RegDst must be expanded to two bits.
1X 101010 (sl t ) 111 (set less than)
1X 001000 (j r ) 010 (add)
A L U Op F unct A L U C ont r ol
TABLE 7.11 ALU decoder truth table with j r
PCSrc = 1
PCWrite
Funct = JR
IorD =0
AluSrcA =0
ALUSrcB =01
ALUOp =00
PCSrc =0
IRWrite
PCWrite
ALUSrcA =0
ALUSrcB =11
ALUOp =00
ALUSrcA =1
ALUSrcB =10
ALUOp =00
IorD =1
RegDst =1
MemtoReg =0
RegWrite
IorD =1
MemWrite
ALUSrcA =1
ALUSrcB =00
ALUOp =10
ALUSrcA =1
ALUSrcB =00
ALUOp =01
PCSrc =1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op =LW
or
Op =SW
or
Op = LB
Op =R-type
Op =BEQ
Op =LW
Op =SW
RegDst =0
MemtoReg =1
RegWrite
S4: Mem
Writeback
S9:
JumpReg
Funct =
others
S OL U T I O N S 269
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
The finite state machine requires another state to write the r s register. If
execution time is critical, another adder could be placed just after the A/B reg-
ister to add 4 to A. Then in State 3, as memory is read, the register file could be
written back with the incremented r s. In that case, l wi nc would require the
same number of cycles as l w. The penalty, however, would be chip area, and
thus power and cost.
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB 20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
1
:
0
Branch
MemWrite
M
e
m
t
o
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
EN EN
ALUSrcB
1:0 IRWrite
IorD
PCWrite
PCEn
2
25:21
270 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 7.17
IorD =0
AluSrcA =0
ALUSrcB =01
ALUOp =00
PCSrc =0
IRWrite
PCWrite
ALUSrcA =0
ALUSrcB =11
ALUOp =00
ALUSrcA =1
ALUSrcB =10
ALUOp =00
IorD =1
RegDst =01
MemtoReg =0
RegWrite
IorD =1
MemWrite
ALUSrcA =1
ALUSrcB =00
ALUOp =10
ALUSrcA =1
ALUSrcB =00
ALUOp =01
PCSrc =1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op =LW
or
Op =SW
or
Op = LWINC
Op =R-type
Op =BEQ
Op =SW
RegDst =00
MemtoReg =1
RegWrite
ALUSrcA =1
ALUSrcB =01
ALUOp =00
S4: Mem
Writeback
RegDst = 10
MemtoReg = 1
RegWrite
S9: RS
Writeback
Op = LWINC
Op =l w
Op =LW
or
Op = LWINC
S OL U T I O N S 271
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
We add an enable signal, FlPtEn, to the result register.
SignImm
CLK
A
RD
Instr / Data
Memory
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
Sign Extend
Register
File
0
1
0
1
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
5:0
SrcB 20:16
15:11
<<2
ALUResult
SrcA
ALUOut
31:26
R
e
g
D
s
t
Branch
MemWrite
M
e
m
t
o
R
e
g
ALUSrcA
RegWrite
Op
Funct
Control
Unit
Zero
PCSrc
CLK
CLK
ALUControl
2:0
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
CLK
A
B
00
01
10
11
4
CLK
EN EN
ALUSrcB
1:0 IRWrite
IorD
PCWrite
PCEn
F
L
P
T
+
F
L
P
T
*
SrcB
SrcA
0
1
25:21
20:16
A1
A3
WD3
RD2
RD1
WE3
A2
CLK
FlPt
Register
File
5:0
31:26
Op
Funct
FlPt
Control
Unit
AddOrSub
Mult
15:11
FlPtRegWrite
CLK
A
B
CLK
FlPtEn
E
272 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 7.19
Because the ALU is not on the critical path, the speedup in performance of
the ALU does not affect the cycle time. Thus, the cycle time, given in Example
7.8, is still 325 ps. Given the instruction mix in Example 7.7, the overall execu-
tion time for 100 billion instructions is still 133.9 seconds.
IorD =0
AluSrcA =0
ALUSrcB =01
ALUOp =00
PCSrc =0
IRWrite
PCWrite
ALUSrcA =0
ALUSrcB =11
ALUOp =00
ALUSrcA =1
ALUSrcB =10
ALUOp =00
IorD =1
RegDst =1
MemtoReg =0
RegWrite
IorD =1
MemWrite
ALUSrcA =1
ALUSrcB =00
ALUOp =10
ALUSrcA =1
ALUSrcB =00
ALUOp =01
PCSrc =1
Branch
Reset
S0: Fetch
S2: MemAdr
S1: Decode
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op =LW
or
Op =SW
Op =R-type Op =BEQ
Op =LW
Op =SW
RegDst =0
MemtoReg =1
RegWrite
S4: Mem
Writeback
AddOrSub = 1
Mult = 0
FlPtEn = 1
FlPtRegWrite
Op = add.s
S10: ADD.S
Execute
S13: FLPT
Writeback
AddOrSub = 0
Mult = 0
FlPtEn = 1
S11: SUB.S
Execute
Mult = 1
FlPtEn = 1
S12: MULT.S
Execute
Op = sub.s
Op = mult.s
FlPtEn = 0
S9: FlPt
Op = F-type
S OL U T I O N S 273
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 7.21
SignImm
CLK
A
RD
Instr / Data
Memory
A
WD
RD
WE
CLK
Sign Extend
Register
File
0
1
PC
0
1
PC' Instr
25:21
20:16
15:0
SrcB
15:11
<<2
ALUResult
SrcA
ALUOut
Zero
CLK
A
L
U
WD
WE
CLK
Adr
0
1
Data
CLK
A
B
00
01
10
11
4
CLK
EN EN
00
01
10
5:0
31:26
Branch
MemWrite
ALUSrcA
RegWrite
Op
Funct
Control
Unit
PCSrc
1:0
CLK
ALUControl
2:0
ALUSrcB
1:0 IRWrite
IorD
PCWrite
PCEn
R
e
g
D
s
t
1
:
0
M
e
m
t
o
R
e
g
WB
00
01
10
CLK
CLK
EN
EN
WA
WA
WB
274 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 7.23
4 +(3 +4 +3) 5 +3 =57 clock cycles
The number of instructions executed is 1 +(3 5) +1 =17. Thus, the CPI
=57 clock cycles / 17 instructions =3.35 CPI
ALUSrcA = 0
ALUSrcB = 11
ALUOp = 00
RegDst = 01
WB
ALUSrcA =1
ALUSrcB =10
ALUOp =00
IorD =1
RegDst = 10
MemtoReg =0
RegWrite
IorD =1
MemWrite
ALUSrcA =1
ALUSrcB =00
ALUOp =10
ALUSrcA =1
ALUSrcB =00
ALUOp =01
PCSrc =01
Branch
S2: MemAdr
S1b:
DecodeB
S3: MemRead
S5: MemWrite
S6: Execute
S7: ALU
Writeback
S8: Branch
Op =LW
Op =R-type
Op =BEQ
Op =LW
Op =SW
RegDst = 01
MemtoReg =1
RegWrite
S4: Mem
Writeback
IorD =0
AluSrcA =0
ALUSrcB =01
ALUOp =00
PCSrc =00
IRWrite
PCWrite
RegDst = 00
WA
Reset
S1a:
DecodeA
S0: Fetch
Op =SW
Op = Other
S OL U T I O N S 275
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 7.25
MIPS Multicycle Processor
SystemVerilog
modul e mi ps( i nput l ogi c cl k, r eset ,
out put l ogi c [ 31: 0] adr , wr i t edat a,
out put l ogi c memwr i t e,
i nput l ogi c [ 31: 0] r eaddat a) ;
l ogi c zer o, pcen, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ;
l ogi c [ 1: 0] al usr cb, pcsr c;
l ogi c [ 2: 0] al ucont r ol ;
l ogi c [ 5: 0] op, f unct ;
cont r ol l er c( cl k, r eset , op, f unct , zer o,
pcen, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al ucont r ol ) ;
dat apat h dp( cl k, r eset ,
pcen, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al ucont r ol ,
op, f unct , zer o,
adr , wr i t edat a, r eaddat a) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mi ps i s - - mul t i cycl e MI PS pr ocessor
por t ( cl k, r eset : i n STD_LOGI C;
adr : out STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: i nout STD_LOGI C_VECTOR( 31 downt o 0) ;
memwr i t e: out STD_LOGI C;
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e st r uct of mi ps i s
component cont r ol l er
por t ( cl k, r eset : i n STD_LOGI C;
op, f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: i n STD_LOGI C;
pcen, memwr i t e: out STD_LOGI C;
i r wr i t e, r egwr i t e: out STD_LOGI C;
al usr ca, i or d: out STD_LOGI C;
memt or eg, r egdst : out STD_LOGI C;
al usr cb, pcsr c: out STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 2 downt o 0) ) ;
end component ;
component dat apat h
por t ( cl k, r eset : i n STD_LOGI C;
pcen, i r wr i t e: i n STD_LOGI C;
r egwr i t e, al usr ca: i n STD_LOGI C;
i or d, memt or eg: i n STD_LOGI C;
r egdst : i n STD_LOGI C;
al usr cb, pcsr c: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : i n STD_LOGI C_VECTOR( 2 downt o 0) ;
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
op, f unct : out STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: out STD_LOGI C;
adr : out STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: i nout STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
si gnal zer o, pcen, i r wr i t e, r egwr i t e, al usr ca, i or d, memt or eg,
r egdst : STD_LOGI C;
si gnal al usr cb, pcsr c: STD_LOGI C_VECTOR( 1 downt o 0) ;
si gnal al ucont r ol : STD_LOGI C_VECTOR( 2 downt o 0) ;
si gnal op, f unct : STD_LOGI C_VECTOR( 5 downt o 0) ;
begi n
c: cont r ol l er por t map( cl k, r eset , op, f unct , zer o,
pcen, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al ucont r ol ) ;
dp: dat apat h por t map( cl k, r eset ,
pcen, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al ucont r ol ,
r eaddat a, op, f unct , zer o,
adr , wr i t edat a) ;
end;
276 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
MIPS Multicycle Control
SystemVerilog
modul e cont r ol l er ( i nput logic cl k, r eset ,
i nput logic [ 5: 0] op, f unct ,
i nput logic zer o,
out put logic pcen, memwr i t e,
i r wr i t e, r egwr i t e,
out put logic al usr ca, i or d,
memt or eg, r egdst ,
out put logic [ 1: 0] al usr cb, pcsr c,
out put logic [ 2: 0] al ucont r ol ) ;
l ogi c [ 1: 0] al uop;
l ogi c br anch, pcwr i t e;
/ / Mai n Decoder and ALU Decoder subuni t s.
mai ndec md( cl k, r eset , op,
pcwr i t e, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, br anch, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al uop) ;
al udec ad( f unct , al uop, al ucont r ol ) ;
assi gn pcen = pcwr i t e | ( br anch & zer o) ;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y cont r ol l er i s - - mul t i cycl e cont r ol decoder
por t ( cl k, r eset : i n STD_LOGI C;
op, f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: i n STD_LOGI C;
pcen, memwr i t e: out STD_LOGI C;
i r wr i t e, r egwr i t e: out STD_LOGI C;
al usr ca, i or d: out STD_LOGI C;
memt or eg, r egdst : out STD_LOGI C;
al usr cb, pcsr c: out STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 2 downt o 0) ) ;
end;
ar chi t ect ur e st r uct of cont r ol l er i s
component mai ndec
por t ( cl k, r eset : i n STD_LOGI C;
op: i n STD_LOGI C_VECTOR( 5 downt o 0) ;
pcwr i t e, memwr i t e: out STD_LOGI C;
i r wr i t e, r egwr i t e: out STD_LOGI C;
al usr ca, br anch: out STD_LOGI C;
i or d, memt or eg: out STD_LOGI C;
r egdst : out STD_LOGI C;
al usr cb, pcsr c: out STD_LOGI C_VECTOR( 1 downt o 0) ;
al uop: out STD_LOGI C_VECTOR( 1 downt o 0) ) ;
end component ;
component al udec
por t ( f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
al uop: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 2 downt o 0) ) ;
end component ;
si gnal al uop: STD_LOGI C_VECTOR( 1 downt o 0) ;
si gnal br anch, pcwr i t e: STD_LOGI C;
begi n
md: mai ndec por t map( cl k, r eset , op,
pcwr i t e, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, br anch, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al uop) ;
ad: al udec por t map( f unct , al uop, al ucont r ol ) ;
pcen <= pcwr i t e or ( br anch and zer o) ;
end;
S OL U T I O N S 277
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
MIPS Multicycle Main Decoder FSM
SystemVerilog
modul e mai ndec( i nput l ogi c cl k, r eset ,
i nput l ogi c [ 5: 0] op,
out put l ogi c pcwr i t e, memwr i t e,
i r wr i t e, r egwr i t e,
out put l ogi c al usr ca, br anch, i or d,
memt or eg, r egdst ,
out put l ogi c [ 1: 0] al usr cb, pcsr c,
out put l ogi c [ 1: 0] al uop) ;
t ypedef enuml ogi c [ 3: 0] {FETCH, DECODE, MEMADR,
MEMRD, MEMWB, MEMWR, RTYPEEX,
RTYPEWB, BEQEX, ADDI EX,
ADDI WB, J EX} st at et ype;
st at et ype [ 3: 0] st at e, next st at e;
par amet er LW = 6' b100011; / / Opcode f or l w
par amet er SW = 6' b101011; / / Opcode f or sw
par amet er RTYPE = 6' b000000; / / Opcode f or R- t ype
par amet er BEQ = 6' b000100; / / Opcode f or beq
par amet er ADDI = 6' b001000; / / Opcode f or addi
par amet er J = 6' b000010; / / Opcode f or j
r eg [ 3: 0] st at e, next st at e;
r eg [ 14: 0] cont r ol s;
/ / st at e r egi st er
al ways_f f @( posedge cl k or posedge r eset )
i f ( r eset ) st at e <= FETCH;
el se st at e <= next st at e;
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mai ndec i s - - mai n cont r ol decoder
por t ( cl k, r eset : i n STD_LOGI C;
op: i n STD_LOGI C_VECTOR( 5 downt o 0) ;
pcwr i t e, memwr i t e: out STD_LOGI C;
i r wr i t e, r egwr i t e: out STD_LOGI C;
al usr ca, br anch: out STD_LOGI C;
i or d, memt or eg: out STD_LOGI C;
r egdst : out STD_LOGI C;
al usr cb, pcsr c: out STD_LOGI C_VECTOR( 1 downt o 0) ;
al uop: out STD_LOGI C_VECTOR( 1 downt o 0) ) ;
end;
ar chi t ect ur e behave of mai ndec i s
t ype st at et ype i s ( FETCH, DECODE, MEMADR, MEMRD, MEMWB, MEMWR,
RTYPEEX, RTYPEWB, BEQEX, ADDI EX, ADDI WB, J EX) ;
si gnal st at e, next st at e: st at et ype;
si gnal cont r ol s: STD_LOGI C_VECTOR( 14 downt o 0) ;
begi n
- - st at e r egi st er
pr ocess( cl k, r eset ) begi n
i f r eset t hen st at e <= FETCH;
el si f r i si ng_edge( cl k) t hen
st at e <= next st at e;
end i f ;
end pr ocess;
- - next st at e l ogi c
pr ocess( al l ) begi n
case st at e i s
when FETCH => next st at e <= DECODE;
when DECODE =>
case op i s
when " 100011" => next st at e <= MEMADR;
when " 101011" => next st at e <= MEMADR;
when " 000000" => next st at e <= RTYPEEX;
when " 000100" => next st at e <= BEQEX;
when " 001000" => next st at e <= ADDI EX;
when " 000010" => next st at e <= J EX;
when ot her s => next st at e <= FETCH; - - shoul d never happen
end case;
when MEMADR =>
case op i s
when " 100011" => next st at e <= MEMRD;
when " 101011" => next st at e <= MEMWR;
when ot her s => next st at e <= FETCH; - - shoul d never happen
end case;
when MEMRD => next st at e <= MEMWB;
when MEMWB => next st at e <= FETCH;
when MEMWR => next st at e <= FETCH;
when RTYPEEX => next st at e <= RTYPEWB;
when RTYPEWB => next st at e <= FETCH;
when BEQEX => next st at e <= FETCH;
when ADDI EX => next st at e <= ADDI WB;
when J EX => next st at e <= FETCH;
when ot her s => next st at e <= FETCH; - - shoul d never happen
end case;
end pr ocess;
278 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
SystemVerilog
/ / next st at e l ogi c
al ways_comb
case( st at e)
FETCH: next st at e <= DECODE;
DECODE: case( op)
LW: next st at e <= MEMADR;
SW: next st at e <= MEMADR;
RTYPE: next st at e <= RTYPEEX;
BEQ: next st at e <= BEQEX;
ADDI : next st at e <= ADDI EX;
J : next st at e <= J EX;
def aul t : next st at e <= FETCH;
/ / def aul t shoul d never happen
endcase
MEMADR: case( op)
LW: next st at e <= MEMRD;
SW: next st at e <= MEMWR;
def aul t : next st at e <= FETCH;
/ / def aul t shoul d never happen
endcase
MEMRD: next st at e <= MEMWB;
MEMWB: next st at e <= FETCH;
MEMWR: next st at e <= FETCH;
RTYPEEX: next st at e <= RTYPEWB;
RTYPEWB: next st at e <= FETCH;
BEQEX: next st at e <= FETCH;
ADDI EX: next st at e <= ADDI WB;
ADDI WB: next st at e <= FETCH;
J EX: next st at e <= FETCH;
def aul t : next st at e <= FETCH;
/ / def aul t shoul d never happen
endcase
/ / out put l ogi c
assi gn {pcwr i t e, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, br anch, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al uop} = cont r ol s;
al ways_comb
case ( st at e)
FETCH: cont r ol s <= 15' b1010_00000_0100_00;
DECODE: cont r ol s <= 15' b0000_00000_1100_00;
MEMADR: cont r ol s <= 15' b0000_10000_1000_00;
MEMRD: cont r ol s <= 15' b0000_00100_0000_00;
MEMWB: cont r ol s <= 15' b0001_00010_0000_00;
MEMWR: cont r ol s <= 15' b0100_00100_0000_00;
RTYPEEX: cont r ol s <= 15' b0000_10000_0000_10;
RTYPEWB: cont r ol s <= 15' b0001_00001_0000_00;
BEQEX: cont r ol s <= 15' b0000_11000_0001_01;
ADDI EX: cont r ol s <= 15' b0000_10000_1000_00;
ADDI WB: cont r ol s <= 15' b0001_00000_0000_00;
J EX: cont r ol s <=15' b1000_00000_0010_00;
def aul t : cont r ol s <= 15' b0000_xxxxx_xxxx_xx;
endcase
endmodul e
VHDL
- - out put l ogi c
pr ocess( al l ) begi n
case st at e i s
when FETCH => cont r ol s <= " 101000000010000" ;
when DECODE => cont r ol s <= " 000000000110000" ;
when MEMADR => cont r ol s <= " 000010000100000" ;
when MEMRD => cont r ol s <= " 000000100000000" ;
when MEMWB => cont r ol s <= " 000100010000000" ;
when MEMWR => cont r ol s <= " 010000100000000" ;
when RTYPEEX => cont r ol s <= " 000010000000010" ;
when RTYPEWB => cont r ol s <= " 000100001000000" ;
when BEQEX => cont r ol s <= " 000011000000101" ;
when ADDI EX => cont r ol s <= " 000010000100000" ;
when ADDI WB => cont r ol s <= " 000100000000000" ;
when J EX => cont r ol s <= " 100000000001000" ;
when ot her s => cont r ol s <= " - - - - - - - - - - - - - - - " ; - - i l l egal op
end case;
end pr ocess;
pcwr i t e <= cont r ol s( 14) ;
memwr i t e <= cont r ol s( 13) ;
i r wr i t e <= cont r ol s( 12) ;
r egwr i t e <= cont r ol s( 11) ;
al usr ca <= cont r ol s( 10) ;
br anch <= cont r ol s( 9) ;
i or d <= cont r ol s( 8) ;
memt or eg <= cont r ol s( 7) ;
r egdst <= cont r ol s( 6) ;
al usr cb <= cont r ol s( 5 downt o 4) ;
pcsr c <= cont r ol s( 3 downt o 2) ;
al uop <= cont r ol s( 1 downt o 0) ;

end;
S OL U T I O N S 279
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
MIPS Multicycle ALU Decoder
SystemVerilog
modul e al udec( i nput l ogi c [ 5: 0] f unct ,
i nput l ogi c [ 1: 0] al uop,
out put l ogi c [ 2: 0] al ucont r ol ) ;
al ways_comb
case( al uop)
2' b00: al ucont r ol <= 3' b010; / / add
2' b01: al ucont r ol <= 3' b110; / / sub
def aul t : case( f unct ) / / RTYPE
6' b100000: al ucont r ol <= 3' b010; / / ADD
6' b100010: al ucont r ol <= 3' b110; / / SUB
6' b100100: al ucont r ol <= 3' b000; / / AND
6' b100101: al ucont r ol <= 3' b001; / / OR
6' b101010: al ucont r ol <= 3' b111; / / SLT
def aul t : al ucont r ol <= 3' bxxx; / / ???
endcase
endcase
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y al udec i s - - ALU cont r ol decoder
por t ( f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
al uop: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 2 downt o 0) ) ;
end;
ar chi t ect ur e behave of al udec i s
begi n
pr ocess( al l ) begi n
case al uop i s
when " 00" => al ucont r ol <= " 010" ; - - add ( f or l b/ sb/ addi )
when " 01" => al ucont r ol <= " 110" ; - - sub ( f or beq)
when " 11" => al ucont r ol <= " 111" ; - - sl t ( f or sl t i )
when ot her s => case f unct i s - - R- t ype i nst r uct i ons
when " 100000" => al ucont r ol <= " 010" ; - - add
when " 100010" => al ucont r ol <= " 110" ; - - sub
when " 100100" => al ucont r ol <= " 000" ; - - and
when " 100101" => al ucont r ol <= " 001" ; - - or
when " 101010" => al ucont r ol <= " 111" ; - - sl t
when ot her s => al ucont r ol <= " - - - " ; - - ???
end case;
end case;
end pr ocess;
end;

280 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
MIPS Multicycle Datapath
SystemVerilog
modul e dat apat h( i nput l ogi c cl k, r eset ,
i nput l ogi c pcen, i r wr i t e,
i nput l ogi c r egwr i t e,
i nput l ogi c al usr ca, i or d,
memt or eg, r egdst ,
i nput l ogi c [ 1: 0] al usr cb, pcsr c,
i nput l ogi c [ 2: 0] al ucont r ol ,
out put l ogi c [ 5: 0] op, f unct ,
out put l ogi c zer o,
out put l ogi c [ 31: 0] adr , wr i t edat a,
i nput l ogi c [ 31: 0] r eaddat a) ;
/ / I nt er nal si gnal s of t he dat apat h modul e.
l ogi c [ 4: 0] wr i t er eg;
l ogi c [ 31: 0] pcnext , pc;
l ogi c [ 31: 0] i nst r , dat a, sr ca, sr cb;
l ogi c [ 31: 0] a;
l ogi c [ 31: 0] al ur esul t , al uout ;
l ogi c [ 31: 0] si gni mm; / / si gn- ext ended i mmedi at e
l ogi c [ 31: 0] si gni mmsh; / / si gn- ext ended i mmedi at e
/ / shi f t ed l ef t by 2
l ogi c [ 31: 0] wd3, r d1, r d2;
/ / op and f unct f i el ds t o cont r ol l er
assi gn op = i nst r [ 31: 26] ;
assi gn f unct = i nst r [ 5: 0] ;
/ / dat apat h
f l openr #( 32) pcr eg( cl k, r eset , pcen, pcnext , pc) ;
mux2 #( 32) adr mux( pc, al uout , i or d, adr ) ;
f l openr #( 32) i nst r r eg( cl k, r eset , i r wr i t e,
r eaddat a, i nst r ) ;
f l opr #( 32) dat ar eg( cl k, r eset , r eaddat a, dat a) ;
mux2 #( 5) r egdst mux( i nst r [ 20: 16] , i nst r [ 15: 11] ,
r egdst , wr i t er eg) ;
mux2 #( 32) wdmux( al uout , dat a, memt or eg, wd3) ;
r egf i l e r f ( cl k, r egwr i t e, i nst r [ 25: 21] ,
i nst r [ 20: 16] ,
wr i t er eg, wd3, r d1, r d2) ;
si gnext se( i nst r [ 15: 0] , si gni mm) ;
sl 2 i mmsh( si gni mm, si gni mmsh) ;
f l opr #( 32) ar eg( cl k, r eset , r d1, a) ;
f l opr #( 32) br eg( cl k, r eset , r d2, wr i t edat a) ;
mux2 #( 32) sr camux( pc, a, al usr ca, sr ca) ;
mux4 #( 32) sr cbmux( wr i t edat a, 32' b100,
si gni mm, si gni mmsh,
al usr cb, sr cb) ;
al u al u( sr ca, sr cb, al ucont r ol ,
al ur esul t , zer o) ;
f l opr #( 32) al ur eg( cl k, r eset , al ur esul t , al uout ) ;
mux3 #( 32) pcmux( al ur esul t , al uout ,
{pc[ 31: 28] , i nst r [ 25: 0] , 2' b00},
pcsr c, pcnext ) ;

endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ; use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y dat apat h i s - - MI PS dat apat h
por t ( cl k, r eset : i n STD_LOGI C;
pcen, i r wr i t e: i n STD_LOGI C;
r egwr i t e, al usr ca: i n STD_LOGI C;
i or d, memt or eg: i n STD_LOGI C;
r egdst : i n STD_LOGI C;
al usr cb, pcsr c: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : i n STD_LOGI C_VECTOR( 2 downt o 0) ;
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
op, f unct : out STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: out STD_LOGI C;
adr : out STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: i nout STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e st r uct of dat apat h i s
component al u
por t ( A, B: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
F: i n STD_LOGI C_VECTOR( 2 downt o 0) ;
Y: buf f er STD_LOGI C_VECTOR( 31 downt o 0) ;
Zer o: out STD_LOGI C) ;
end component ;
component r egf i l e
por t ( cl k: i n STD_LOGI C;
we3: i n STD_LOGI C;
r a1, r a2, wa3: i n STD_LOGI C_VECTOR( 4 downt o 0) ;
wd3: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
r d1, r d2: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component adder
por t ( a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component sl 2
por t ( a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component si gnext
por t ( a: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component f l opr gener i c( wi dt h: i nt eger ) ;
por t ( cl k, r eset : i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component f l openr gener i c( wi dt h: i nt eger ) ;
por t ( cl k, r eset : i n STD_LOGI C;
en: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component mux2 gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component mux3 gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component mux4 gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2, d3: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
si gnal wr i t er eg: STD_LOGI C_VECTOR( 4 downt o 0) ;
si gnal pcnext , pc, i nst r , dat a, sr ca, sr cb, a,
al ur esul t , al uout , si gni mm, si gni mmsh, wd3, r d1, r d2, pcj ump:
STD_LOGI C_VECTOR( 31 downt o 0) ;
S OL U T I O N S 281
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
(continued from previous page)
VHDL
begi n
- - op and f unct f i el ds t o cont r ol l er
op <= i nst r ( 31 downt o 26) ;
f unct <= i nst r ( 5 downt o 0) ;

- - dat apat h
pcr eg: f l openr gener i c map( 32) por t map( cl k, r eset , pcen, pcnext , pc) ;
adr mux: mux2 gener i c map( 32) por t map( pc, al uout , i or d, adr ) ;
i nst r r eg: f l openr gener i c map( 32) por t map( cl k, r eset , i r wr i t e,
r eaddat a, i nst r ) ;
dat ar eg: f l opr gener i c map( 32) por t map( cl k, r eset , r eaddat a, dat a) ;
r egdst mux: mux2 gener i c map( 5) por t map( i nst r ( 20 downt o 16) ,
i nst r ( 15 downt o 11) ,
r egdst , wr i t er eg) ;
wdmux: mux2 gener i c map( 32) por t map( al uout , dat a, memt or eg, wd3) ;
r f : r egf i l e por t map( cl k, r egwr i t e, i nst r ( 25 downt o 21) ,
i nst r ( 20 downt o 16) ,
wr i t er eg, wd3, r d1, r d2) ;
se: si gnext por t map( i nst r ( 15 downt o 0) , si gni mm) ;
i mmsh: sl 2 por t map( si gni mm, si gni mmsh) ;
ar eg: f l opr gener i c map( 32) por t map( cl k, r eset , r d1, a) ;
br eg: f l opr gener i c map( 32) por t map( cl k, r eset , r d2, wr i t edat a) ;
sr camux: mux2 gener i c map( 32) por t map( pc, a, al usr ca, sr ca) ;
sr cbmux: mux4 gener i c map( 32) por t map( wr i t edat a,
" 00000000000000000000000000000100" ,
si gni mm, si gni mmsh, al usr cb, sr cb) ;
al u32: al u por t map( sr ca, sr cb, al ucont r ol , al ur esul t , zer o) ;
al ur eg: f l opr gener i c map( 32) por t map( cl k, r eset , al ur esul t , al uout ) ;
pcj ump <= pc( 31 downt o 28) &i nst r ( 25 downt o 0) &" 00" ;
pcmux: mux3 gener i c map( 32) por t map( al ur esul t , al uout ,
pcj ump, pcsr c, pcnext ) ;
end;
282 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
The following HDL describes the building blocks that are used in the MIPS
multicycle processor that are not found in Section 7.6.2.
MIPS Multicycle Building Blocks
SystemVerilog
modul e f l openr #( par amet er WI DTH = 8)
( i nput l ogi c cl k, r eset ,
i nput l ogi c en,
i nput l ogi c [ WI DTH- 1: 0] d,
out put l ogi c [ WI DTH- 1: 0] q) ;
al ways_f f @( posedge cl k, posedge r eset )
i f ( r eset ) q <= 0;
el se i f ( en) q <= d;
endmodul e
modul e mux3 #( par amet er WI DTH = 8)
( i nput l ogi c [ WI DTH- 1: 0] d0, d1, d2,
i nput l ogi c [ 1: 0] s,
out put l ogi c [ WI DTH- 1: 0] y) ;
assi gn #1 y = s[ 1] ? d2 : ( s[ 0] ? d1 : d0) ;
endmodul e
modul e mux4 #( par amet er WI DTH = 8)
( i nput l ogi c [ WI DTH- 1: 0] d0, d1, d2, d3,
i nput l ogi c [ 1: 0] s,
out put l ogi c [ WI DTH- 1: 0] y) ;
al ways_comb
case( s)
2' b00: y <= d0;
2' b01: y <= d1;
2' b10: y <= d2;
2' b11: y <= d3;
endcase
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ; use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y f l openr i s - - f l i p- f l op wi t h asynchr onous r eset
gener i c( wi dt h: i nt eger ) ;
por t ( cl k, r eset : i n STD_LOGI C;
en: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e asynchr onous of f l openr i s
begi n
pr ocess( cl k, r eset ) begi n
i f r eset t hen q <= CONV_STD_LOGI C_VECTOR( 0, wi dt h) ;
el si f r i si ng_edge( cl k) and en = ' 1' t hen
q <= d;
end i f ;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mux3 i s - - t hr ee- i nput mul t i pl exer
gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e behave of mux3 i s
begi n
pr ocess( al l ) begi n
case s i s
when " 00" => y <= d0;
when " 01" => y <= d1;
when " 10" => y <= d2;
when ot her s => y <= d0;
end case;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mux4 i s - - f our - i nput mul t i pl exer
gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2, d3: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e behave of mux4 i s
begi n
pr ocess( al l ) begi n
case s i s
when " 00" => y <= d0;
when " 01" => y <= d1;
when " 10" => y <= d2;
when " 11" => y <= d3;
when ot her s => y <= d0; - - shoul d never happen
end case;
end pr ocess;
end;
S OL U T I O N S 283
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 7.27
We modify the MIPS multicycle processor to implement all instructions
from Exercise 7.14.
SystemVerilog
modul e t op( i nput l ogi c cl k, r eset ,
out put l ogi c [ 31: 0] wr i t edat a, dat aadr ,
out put l ogi c memwr i t e) ;
l ogi c [ 31: 0] pc, i nst r , r eaddat a;

/ / i nst ant i at e pr ocessor and memor i es
mi ps mi ps( cl k, r eset , pc, i nst r , memwr i t e, dat aadr ,
wr i t edat a, r eaddat a) ;
i memi mem( pc[ 7: 2] , i nst r ) ;
dmemdmem( cl k, memwr i t e, dat aadr , wr i t edat a, r eaddat a) ;
endmodul e
modul e dmem( i nput l ogi c cl k, we,
i nput l ogi c [ 31: 0] a, wd,
out put l ogi c [ 31: 0] r d) ;
l ogi c [ 31: 0] RAM[ 63: 0] ;
assi gn r d = RAM[ a[ 31: 2] ] ; / / wor d al i gned
al ways_f f @( posedge cl k)
i f ( we) RAM[ a[ 31: 2] ] <= wd;
endmodul e
modul e i mem( i nput l ogi c [ 5: 0] a,
out put l ogi c [ 31: 0] r d) ;
l ogi c [ 31: 0] RAM[ 63: 0] ;
i ni t i al
$r eadmemh( " memf i l e. dat " , RAM) ;
assi gn r d = RAM[ a] ; / / wor d al i gned
endmodul e
modul e t op( i nput l ogi c cl k, r eset ,
out put l ogi c [ 31: 0] wr i t edat a, adr ,
out put l ogi c memwr i t e) ;
l ogi c [ 31: 0] r eaddat a;

/ / i nst ant i at e pr ocessor and memor y
mi ps mi ps( cl k, r eset , adr , wr i t edat a, memwr i t e,
r eaddat a) ;
memmem( cl k, memwr i t e, adr , wr i t edat a,
r eaddat a) ;
endmodul e
modul e mi ps( i nput l ogi c cl k, r eset ,
out put l ogi c [ 31: 0] adr , wr i t edat a,
out put l ogi c memwr i t e,
i nput l ogi c [ 31: 0] r eaddat a) ;
284 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
l ogi c zer o, pcen, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ;
l ogi c [ 2: 0] al usr cb; / / ANDI
l ogi c [ 1: 0] pcsr c;
l ogi c [ 2: 0] al ucont r ol ;
l ogi c [ 5: 0] op, f unct ;
l ogi c [ 1: 0] l b; / / LB/ LBU
cont r ol l er c( cl k, r eset , op, f unct , zer o,
pcen, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al ucont r ol , l b) ; / / LB/ LBU
dat apat h dp( cl k, r eset ,
pcen, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al ucont r ol ,
l b, / / LB/ LBU
op, f unct , zer o,
adr , wr i t edat a, r eaddat a) ;
endmodul e
modul e cont r ol l er ( i nput l ogi c cl k, r eset ,
i nput l ogi c [ 5: 0] op, f unct ,
i nput l ogi c zer o,
out put l ogi c pcen, memwr i t e,
i r wr i t e, r egwr i t e,
out put l ogi c al usr ca, i or d,
out put l ogi c memt or eg, r egdst ,
out put l ogi c [ 2: 0] al usr cb, / / ANDI
out put l ogi c [ 1: 0] pcsr c,
out put l ogi c [ 2: 0] al ucont r ol ,
out put l ogi c [ 1: 0] l b) ; / / LB/ LBU
l ogi c [ 1: 0] al uop;
l ogi c br anch, pcwr i t e;
l ogi c bne; / / BNE
/ / Mai n Decoder and ALU Decoder subuni t s.
mai ndec md( cl k, r eset , op,
pcwr i t e, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, br anch, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al uop, bne, l b) ; / / BNE, LBU
al udec ad( f unct , al uop, al ucont r ol ) ;
assi gn pcen = pcwr i t e | ( br anch & zer o) |
( bne & ~zer o) ; / / BNE
endmodul e
modul e mai ndec( i nput cl k, r eset ,
i nput [ 5: 0] op,
out put pcwr i t e, memwr i t e,
i r wr i t e, r egwr i t e,
out put al usr ca, br anch,
i or d, memt or eg, r egdst ,
out put [ 2: 0] al usr cb, / / ANDI
out put [ 1: 0] pcsr c,
out put [ 1: 0] al uop,
out put bne, / / BNE
out put [ 1: 0] l b) ; / / LB/ LBU
t ypedef enuml ogi c [ 4: 0] {FETCH, DECODE, MEMADR,
MEMRD, MEMWB, MEMWR, RTYPEEX, RTYPEWB, BEQEX,
ADDI EX, ADDI WB, J EX, ANDI EX, ANDI WB,
BNEEX, LBURD, LBRD} st at et ype;
S OL U T I O N S 285
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
st at et ype [ 4: 0] st at e, next st at e;
par amet er RTYPE = 6' b000000;
par amet er LW= 6' b100011;
par amet er SW= 6' b101011;
par amet er BEQ = 6' b000100;
par amet er ADDI = 6' b001000;
par amet er J = 6' b000010;
par amet er BNE = 6' b000101;
par amet er LBU = 6' b100100;
par amet er LB = 6' b100000;
par amet er ANDI = 6' b001100;
l ogi c [ 18: 0] cont r ol s; / / ANDI , BNE, LBU
/ / st at e r egi st er
al ways_f f @( posedge cl k or posedge r eset )
i f ( r eset ) st at e <= FETCH;
el se st at e <= next st at e;
/ / next st at e l ogi c
al ways_comb
case( st at e)
FETCH: next st at e <= DECODE;
DECODE: case( op)
LW: next st at e <= MEMADR;
SW: next st at e <= MEMADR;
LB: next st at e <= MEMADR; / / LB
LBU: next st at e <= MEMADR; / / LBU
RTYPE: next st at e <= RTYPEEX;
BEQ: next st at e <= BEQEX;
ADDI : next st at e <= ADDI EX;
J : next st at e <= J EX;
BNE: next st at e <= BNEEX; / / BNE
ANDI : next st at e <= ADDI EX; / / ANDI
def aul t : next st at e <= FETCH;
/ / shoul d never happen
endcase
MEMADR: case( op)
LW: next st at e <= MEMRD;
SW: next st at e <= MEMWR;
LBU: next st at e <= LBURD; / / LBU
LB: next st at e <= LBRD; / / LB
def aul t : next st at e <= FETCH;
/ / shoul d never happen
endcase
MEMRD: next st at e <= MEMWB;
MEMWB: next st at e <= FETCH;
MEMWR: next st at e <= FETCH;
RTYPEEX: next st at e <= RTYPEWB;
RTYPEWB: next st at e <= FETCH;
BEQEX: next st at e <= FETCH;
ADDI EX: next st at e <= ADDI WB;
ADDI WB: next st at e <= FETCH;
J EX: next st at e <= FETCH;
ANDI EX: next st at e <= ANDI WB; / / ANDI
ANDI WB: next st at e <= FETCH; / / ANDI
BNEEX: next st at e <= FETCH; / / BNE
LBURD: next st at e <= MEMWB; / / LBU
LBRD: next st at e <= MEMWB; / / LB
def aul t : next st at e <= FETCH;
/ / shoul d never happen
endcase
/ / out put l ogi c
286 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
assi gn {pcwr i t e, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, br anch, i or d, memt or eg, r egdst ,
bne, / / BNE
al usr cb, pcsr c,
al uop,
l b} = cont r ol s; / / LBU
al ways_comb
case( st at e)
FETCH: cont r ol s <= 19' b1010_00000_0_00100_00_00;
DECODE: cont r ol s <= 19' b0000_00000_0_01100_00_00;
MEMADR: cont r ol s <= 19' b0000_10000_0_01000_00_00;
MEMRD: cont r ol s <= 19' b0000_00100_0_00000_00_00;
MEMWB: cont r ol s <= 19' b0001_00010_0_00000_00_00;
MEMWR: cont r ol s <= 19' b0100_00100_0_00000_00_00;
RTYPEEX: cont r ol s <= 19' b0000_10000_0_00000_10_00;
RTYPEWB: cont r ol s <= 19' b0001_00001_0_00000_00_00;
BEQEX: cont r ol s <= 19' b0000_11000_0_00001_01_00;
ADDI EX: cont r ol s <= 19' b0000_10000_0_01000_00_00;
ADDI WB: cont r ol s <= 19' b0001_00000_0_00000_00_00;
J EX: cont r ol s <= 19' b1000_00000_0_00010_00_00;
ANDI EX: cont r ol s <= 19' b0000_10000_0_10000_11_00; / / ANDI
ANDI WB: cont r ol s <= 19' b0001_00000_0_00000_00_00; / / ANDI
BNEEX: cont r ol s <= 19' b0000_10000_1_00001_01_00; / / BNE
LBURD: cont r ol s <= 19' b0000_00100_0_00000_00_01; / / LBU
LBRD: cont r ol s <= 19' b0000_00100_0_00000_00_10; / / LB
def aul t : cont r ol s <= 19' b0000_xxxxx_x_xxxxx_xx_xx;
/ / shoul d never happen
endcase
endmodul e
modul e al udec( i nput l ogi c [ 5: 0] f unct ,
i nput l ogi c [ 1: 0] al uop,
out put l ogi c [ 2: 0] al ucont r ol ) ;

al ways_comb
case( al uop)
2' b00: al ucont r ol <= 3' b010; / / add
2' b01: al ucont r ol <= 3' b110; / / sub
2' b11: al ucont r ol <= 3' b000; / / and
2' b10: case( f unct ) / / RTYPE
6' b100000: al ucont r ol <= 3' b010; / / ADD
6' b100010: al ucont r ol <= 3' b110; / / SUB
6' b100100: al ucont r ol <= 3' b000; / / AND
6' b100101: al ucont r ol <= 3' b001; / / OR
6' b101010: al ucont r ol <= 3' b111; / / SLT
def aul t : al ucont r ol <= 3' bxxx; / / ???
endcase
def aul t : al ucont r ol <= 3' bxxx; / / ???
endcase
endmodul e
modul e dat apat h( i nput l ogi c cl k, r eset ,
i nput l ogi c pcen, i r wr i t e,
i nput l ogi c r egwr i t e,
i nput l ogi c al usr ca, i or d,
memt or eg, r egdst ,
i nput l ogi c [ 2: 0] al usr cb, / / ANDI
i nput l ogi c [ 1: 0] pcsr c,
i nput l ogi c [ 2: 0] al ucont r ol ,
i nput l ogi c [ 1: 0] l b, / / LB/ LBU
out put l ogi c [ 5: 0] op, f unct ,
out put l ogi c zer o,
out put l ogi c [ 31: 0] adr , wr i t edat a,
i nput l ogi c [ 31: 0] r eaddat a) ;
S OL U T I O N S 287
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
/ / I nt er nal si gnal s of t he dat apat h modul e
l ogi c [ 4: 0] wr i t er eg;
l ogi c [ 31: 0] pcnext , pc;
l ogi c [ 31: 0] i nst r , dat a, sr ca, sr cb;
l ogi c [ 31: 0] a;
l ogi c [ 31: 0] al ur esul t , al uout ;
l ogi c [ 31: 0] si gni mm; / / t he si gn- ext ended i mm
l ogi c [ 31: 0] zer oi mm; / / t he zer o- ext ended i mm
/ / ANDI
l ogi c [ 31: 0] si gni mmsh; / / t he si gn- ext ended i mm<< 2
l ogi c [ 31: 0] wd3, r d1, r d2;
l ogi c [ 31: 0] memdat a, membyt ezext , membyt esext ; / / LB / LBU
l ogi c [ 7: 0] membyt e; / / LB / LBU
/ / op and f unct f i el ds t o cont r ol l er
assi gn op = i nst r [ 31: 26] ;
assi gn f unct = i nst r [ 5: 0] ;
/ / dat apat h
f l openr #( 32) pcr eg( cl k, r eset , pcen, pcnext , pc) ;
mux2 #( 32) adr mux( pc, al uout , i or d, adr ) ;
f l openr #( 32) i nst r r eg( cl k, r eset , i r wr i t e,
r eaddat a, i nst r ) ;
/ / changes f or LB / LBU
f l opr #( 32) dat ar eg( cl k, r eset , memdat a, dat a) ;
mux4 #( 8) l bmux( r eaddat a[ 31: 24] ,
r eaddat a[ 23: 16] , r eaddat a[ 15: 8] ,
r eaddat a[ 7: 0] , al uout [ 1: 0] ,
membyt e) ;
zer oext 8_32 l bze( membyt e, membyt ezext ) ;
si gnext 8_32 l bse( membyt e, membyt esext ) ;
mux3 #( 32) dat amux( r eaddat a, membyt ezext , membyt esext ,
l b, memdat a) ;

mux2 #( 5) r egdst mux( i nst r [ 20: 16] ,
i nst r [ 15: 11] , r egdst , wr i t er eg) ;
mux2 #( 32) wdmux( al uout , dat a, memt or eg, wd3) ;
r egf i l e r f ( cl k, r egwr i t e, i nst r [ 25: 21] ,
i nst r [ 20: 16] ,
wr i t er eg, wd3, r d1, r d2) ;
si gnext se( i nst r [ 15: 0] , si gni mm) ;
zer oext ze( i nst r [ 15: 0] , zer oi mm) ; / / ANDI
sl 2 i mmsh( si gni mm, si gni mmsh) ;
f l opr #( 32) ar eg( cl k, r eset , r d1, a) ;
f l opr #( 32) br eg( cl k, r eset , r d2, wr i t edat a) ;
mux2 #( 32) sr camux( pc, a, al usr ca, sr ca) ;
mux5 #( 32) sr cbmux( wr i t edat a, 32' b100,
si gni mm, si gni mmsh,
zer oi mm, / / ANDI
al usr cb, sr cb) ;
al u al u( sr ca, sr cb, al ucont r ol , al ur esul t , zer o) ;
f l opr #( 32) al ur eg( cl k, r eset , al ur esul t , al uout ) ;
mux3 #( 32) pcmux( al ur esul t , al uout ,
{pc[ 31: 28] , i nst r [ 25: 0] , 2' b00},
pcsr c, pcnext ) ;

endmodul e
modul e al u( i nput l ogi c [ 31: 0] A, B,
i nput l ogi c [ 2: 0] F,
out put l ogi c [ 31: 0] Y, out put Zer o) ;
288 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
l ogi c [ 31: 0] S, Bout ;
assi gn Bout = F[ 2] ? ~B : B;
assi gn S = A + Bout + F[ 2] ;
al ways_comb
case ( F[ 1: 0] )
3' b00: Y <= A & Bout ;
3' b01: Y <= A | Bout ;
3' b10: Y <= S;
3' b11: Y <= S[ 31] ;
endcase
assi gn Zer o = ( Y == 32' b0) ;
endmodul e
/ / mux5 i s needed f or ANDI
modul e mux5 #( par amet er WI DTH = 8)
( i nput [ WI DTH- 1: 0] d0, d1, d2, d3, d4,
i nput [ 2: 0] s,
out put r eg [ WI DTH- 1: 0] y) ;
al ways_comb
case( s)
3' b000: y <= d0;
3' b001: y <= d1;
3' b010: y <= d2;
3' b011: y <= d3;
3' b100: y <= d4;
endcase
endmodul e
/ / zer oext i s needed f or ANDI
modul e zer oext ( i nput [ 15: 0] a,
out put [ 31: 0] y) ;

assi gn y = {16' b0, a};
endmodul e
/ / zer oext 8_32 i s needed f or LBU
modul e zer oext 8_32( i nput l ogi c [ 7: 0] a,
out put l ogi c [ 31: 0] y) ;

assi gn y = {24' b0, a};
endmodul e
/ / si gnext 8_32 i s needed f or LB
modul e si gnext 8_32( i nput l ogi c [ 7: 0] a,
out put l ogi c [ 31: 0] y) ;

assi gn y = {{24{a[ 7] }}, a};
endmodul e
modul e al u( i nput l ogi c [ 31: 0] A, B,
i nput l ogi c [ 3: 0] F,
i nput l ogi c [ 4: 0] shamt , / / SRL
out put l ogi c [ 31: 0] Y,
out put l ogi c Zer o) ;
l ogi c [ 31: 0] S, Bout ;
assi gn Bout = F[ 3] ? ~B : B;
assi gn S = A + Bout + F[ 3] ; / / SRL
S OL U T I O N S 289
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
al ways_comb
case ( F[ 2: 0] )
3' b000: Y = A & Bout ;
3' b001: Y = A | Bout ;
3' b010: Y = S;
3' b011: Y = S[ 31] ;
3' b100: Y = ( Bout >> shamt ) ; / / SRL
endcase
assi gn Zer o = ( Y == 32' b0) ;
endmodul e
modul e r egf i l e( i nput l ogi c cl k,
i nput l ogi c we3,
i nput l ogi c [ 4: 0] r a1, r a2, wa3,
i nput l ogi c [ 31: 0] wd3,
out put l ogi c [ 31: 0] r d1, r d2) ;
l ogi c [ 31: 0] r f [ 31: 0] ;
/ / t hr ee por t ed r egi st er f i l e
/ / r ead t wo por t s combi nat i onal l y
/ / wr i t e t hi r d por t on r i si ng edge of cl k
/ / r egi st er 0 har dwi r ed t o 0
al ways_f f @( posedge cl k)
i f ( we3) r f [ wa3] <= wd3;
assi gn r d1 = ( r a1 ! = 0) ? r f [ r a1] : 0;
assi gn r d2 = ( r a2 ! = 0) ? r f [ r a2] : 0;
endmodul e
modul e adder ( i nput l ogi c [ 31: 0] a, b,
out put l ogi c [ 31: 0] y) ;
assi gn y = a + b;
endmodul e
modul e sl 2( i nput l ogi c [ 31: 0] a,
out put l ogi c [ 31: 0] y) ;
/ / shi f t l ef t by 2
assi gn y = {a[ 29: 0] , 2' b00};
endmodul e
modul e si gnext ( i nput l ogi c [ 15: 0] a,
out put l ogi c [ 31: 0] y) ;

assi gn y = {{16{a[ 15] }}, a};
endmodul e
modul e f l opr #( par amet er WI DTH = 8)
( i nput l ogi c cl k, r eset ,
i nput l ogi c [ WI DTH- 1: 0] d,
out put l ogi c [ WI DTH- 1: 0] q) ;
al ways_f f @( posedge cl k, posedge r eset )
i f ( r eset ) q <= 0;
el se q <= d;
endmodul e
modul e mux2 #( par amet er WI DTH = 8)
( i nput l ogi c [ WI DTH- 1: 0] d0, d1,
i nput l ogi c s,
out put l ogi c [ WI DTH- 1: 0] y) ;
290 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
assi gn y = s ? d1 : d0;
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mi ps i s - - mul t i cycl e MI PS pr ocessor
por t ( cl k, r eset : i n STD_LOGI C;
adr : out STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: i nout STD_LOGI C_VECTOR( 31 downt o 0) ;
memwr i t e: out STD_LOGI C;
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e st r uct of mi ps i s
component cont r ol l er
por t ( cl k, r eset : i n STD_LOGI C;
op, f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: i n STD_LOGI C;
pcen, memwr i t e: out STD_LOGI C;
i r wr i t e, r egwr i t e: out STD_LOGI C;
al usr ca, i or d: out STD_LOGI C;
memt or eg, r egdst : out STD_LOGI C;
al usr cb: out STD_LOGI C_VECTOR( 2 downt o 0) ; - - andi
pcsr c: out STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 2 downt o 0) ;
l b: out STD_LOGI C_VECTOR( 1 downt o 0) ) ; - - l b, l bu
end component ;
component dat apat h
por t ( cl k, r eset : i n STD_LOGI C;
pcen, i r wr i t e: i n STD_LOGI C;
r egwr i t e, al usr ca: i n STD_LOGI C;
i or d, memt or eg: i n STD_LOGI C;
r egdst : i n STD_LOGI C;
al usr cb: i n STD_LOGI C_VECTOR( 2 downt o 0) ; - - andi
pcsr c: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : i n STD_LOGI C_VECTOR( 2 downt o 0) ;
l b: i n STD_LOGI C_VECTOR( 1 downt o 0) ; - - l b / l bu
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
op, f unct : out STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: out STD_LOGI C;
adr : out STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: i nout STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
si gnal zer o, pcen, i r wr i t e, r egwr i t e, al usr ca, i or d, memt or eg,
r egdst : STD_LOGI C;
si gnal al usr cb: STD_LOGI C_VECTOR( 2 downt o 0) ; - - andi
si gnal pcsr c: STD_LOGI C_VECTOR( 1 downt o 0) ;
si gnal al ucont r ol : STD_LOGI C_VECTOR( 2 downt o 0) ;
si gnal op, f unct : STD_LOGI C_VECTOR( 5 downt o 0) ;
si gnal l b: STD_LOGI C_VECTOR( 1 downt o 0) ; - - l b / l bu
begi n
c: cont r ol l er por t map( cl k, r eset , op, f unct , zer o,
pcen, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al ucont r ol , l b) ; - - l b / l bu
dp: dat apat h por t map( cl k, r eset ,
pcen, i r wr i t e, r egwr i t e,
al usr ca, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al ucont r ol ,
l b, - - l b / l bu
r eaddat a, op, f unct , zer o,
adr , wr i t edat a, r eaddat a) ;
end;
S OL U T I O N S 291
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y cont r ol l er i s - - mul t i cycl e cont r ol decoder
por t ( cl k, r eset : i n STD_LOGI C;
op, f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: i n STD_LOGI C;
pcen, memwr i t e: out STD_LOGI C;
i r wr i t e, r egwr i t e: out STD_LOGI C;
al usr ca, i or d: out STD_LOGI C;
memt or eg, r egdst : out STD_LOGI C;
al usr cb: out STD_LOGI C_VECTOR( 2 downt o 0) ; - - andi
pcsr c: out STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 2 downt o 0) ;
l b: out STD_LOGI C_VECTOR( 1 downt o 0) ) ; - - l b, l bu
end;
ar chi t ect ur e st r uct of cont r ol l er i s
component mai ndec
por t ( cl k, r eset : i n STD_LOGI C;
op: i n STD_LOGI C_VECTOR( 5 downt o 0) ;
pcwr i t e, memwr i t e: out STD_LOGI C;
i r wr i t e, r egwr i t e: out STD_LOGI C;
al usr ca, br anch: out STD_LOGI C;
i or d, memt or eg: out STD_LOGI C;
r egdst : out STD_LOGI C;
al usr cb: out STD_LOGI C_VECTOR( 2 downt o 0) ; - - andi
pcsr c: out STD_LOGI C_VECTOR( 1 downt o 0) ;
al uop: out STD_LOGI C_VECTOR( 1 downt o 0) ;
l b: out STD_LOGI C_VECTOR( 1 downt o 0) ) ; - - l b / l bu
end component ;
component al udec
por t ( f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
al uop: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 2 downt o 0) ) ;
end component ;
si gnal al uop: STD_LOGI C_VECTOR( 1 downt o 0) ;
si gnal br anch, pcwr i t e, bne: STD_LOGI C; - - bne
begi n
md: mai ndec por t map( cl k, r eset , op,
pcwr i t e, memwr i t e, i r wr i t e, r egwr i t e,
al usr ca, br anch, i or d, memt or eg, r egdst ,
al usr cb, pcsr c, al uop, bne, l b) ; - - bne, l b
ad: al udec por t map( f unct , al uop, al ucont r ol ) ;
pcen <= pcwr i t e or ( br anch and zer o) or ( bne and ( not zer o) ) ; - - bne
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mai ndec i s - - mai n cont r ol decoder
por t ( cl k, r eset : i n STD_LOGI C;
op: i n STD_LOGI C_VECTOR( 5 downt o 0) ;
pcwr i t e, memwr i t e: out STD_LOGI C;
i r wr i t e, r egwr i t e: out STD_LOGI C;
al usr ca, br anch: out STD_LOGI C;
i or d, memt or eg: out STD_LOGI C;
r egdst : out STD_LOGI C;
al usr cb: out STD_LOGI C_VECTOR( 2 downt o 0) ; - - andi
pcsr c: out STD_LOGI C_VECTOR( 1 downt o 0) ;
al uop: out STD_LOGI C_VECTOR( 1 downt o 0) ;
bne: out STD_LOGI C; - - bne
al uop: out STD_LOGI C_VECTOR( 1 downt o 0) ) ; - - l b / l bu
end;
ar chi t ect ur e behave of mai ndec i s
t ype st at et ype i s ( FETCH, DECODE, MEMADR, MEMRD, MEMWB, MEMWR,
RTYPEEX, RTYPEWB, BEQEX, ADDI EX, ADDI WB, J EX,
292 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
ANDI EX, ANDI WB, BNEEX, LBURD, LBRD) ;
si gnal st at e, next st at e: st at et ype;
si gnal cont r ol s: STD_LOGI C_VECTOR( 18 downt o 0) ;
begi n
- - st at e r egi st er
pr ocess( cl k, r eset ) begi n
i f r eset t hen st at e <= FETCH;
el si f r i si ng_edge( cl k) t hen
st at e <= next st at e;
end i f ;
end pr ocess;
- - next st at e l ogi c
pr ocess( al l ) begi n
case st at e i s
when FETCH => next st at e <= DECODE;
when DECODE =>
case op i s
when " 100011" => next st at e <= MEMADR; - - LW
when " 101011" => next st at e <= MEMADR; - - SW
when " 100000" => next st at e <= MEMADR; - - LB
when " 100100" => next st at e <= MEMADR; - - LBU
when " 000000" => next st at e <= RTYPEEX; - - RTYPE
when " 000100" => next st at e <= BEQEX; - - BEQ
when " 001000" => next st at e <= ADDI EX; - - ADDI
when " 000010" => next st at e <= J EX; - - J
when " 000101" => next st at e <= ORI EX; - - BNE
when " 001100" => next st at e <= ORI EX; - - ANDI
when ot her s => next st at e <= FETCH; - - shoul d never happen
end case;
when MEMADR =>
case op i s
when " 100011" => next st at e <= MEMRD;
when " 101011" => next st at e <= MEMWR;
when " 100000" => next st at e <= LBRD; - - LB
when " 100100" => next st at e <= LBURD; - - LBU
when ot her s => next st at e <= FETCH; - - shoul d never happen
end case;
when MEMRD => next st at e <= MEMWB;
when MEMWB => next st at e <= FETCH;
when MEMWR => next st at e <= FETCH;
when RTYPEEX => next st at e <= RTYPEWB;
when RTYPEWB => next st at e <= FETCH;
when BEQEX => next st at e <= FETCH;
when ADDI EX => next st at e <= ADDI WB;
when J EX => next st at e <= FETCH;
when ANDI EX => next st at e <= ANDI WB; / / ANDI
when ANDI WB => next st at e <= FETCH; / / ANDI
when BNEEX => next st at e <= FETCH; / / BNE
when LBURD => next st at e <= MEMWB; / / LBU
when LBRD => next st at e <= MEMWB; / / LB
when ot her s => next st at e <= FETCH; - - shoul d never happen
end case;
end pr ocess;
- - out put l ogi c
pr ocess( al l ) begi n
case st at e i s
when FETCH => cont r ol s <= " 1010_00000_0_00100_00_00" ;
when DECODE => cont r ol s <= " 0000_00000_0_01100_00_00" ;
when MEMADR => cont r ol s <= " 0000_10000_0_01000_00_00" ;
when MEMRD => cont r ol s <= " 0000_00100_0_00000_00_00" ;
when MEMWB => cont r ol s <= " 0001_00010_0_00000_00_00" ;
when MEMWR => cont r ol s <= " 0100_00100_0_00000_00_00" ;
when RTYPEEX => cont r ol s <= " 0000_10000_0_00000_10_00" ;
when RTYPEWB => cont r ol s <= " 0001_00001_0_00000_00_00" ;
S OL U T I O N S 293
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
when BEQEX => cont r ol s <= " 0000_11000_0_00001_01_00" ;
when ADDI EX => cont r ol s <= " 0000_10000_0_01000_00_00" ;
when ADDI WB => cont r ol s <= " 0001_00000_0_00000_00_00" ;
when J EX => cont r ol s <= " 1000_00000_0_00010_00_00" ;
when ANDI EX => cont r ol s <= " 0000_10000_0_10000_11_00" ;
when ANDI WB => cont r ol s <= " 0001_00000_0_00000_00_00" ;
when BNEEX => cont r ol s <= " 0000_10000_1_00001_01_00" ;
when LBURD => cont r ol s <= " 0000_00100_0_00000_00_01" ;
when LBRD => cont r ol s <= " 0000_00100_0_00000_00_10" ;
when ot her s => cont r ol s <= " 0000_- - - - - _- _- - - - - _- - _- - " ;
- - i l l egal op
end case;
end pr ocess;
pcwr i t e <= cont r ol s( 18) ;
memwr i t e <= cont r ol s( 17) ;
i r wr i t e <= cont r ol s( 16) ;
r egwr i t e <= cont r ol s( 15) ;
al usr ca <= cont r ol s( 14) ;
br anch <= cont r ol s( 13) ;
i or d <= cont r ol s( 12) ;
memt or eg <= cont r ol s( 11) ;
r egdst <= cont r ol s( 10) ;
bne <= cont r ol s( 9) ;
al usr cb <= cont r ol s( 8 downt o 6) ;
pcsr c <= cont r ol s( 5 downt o 4) ;
al uop <= cont r ol s( 3 downt o 1) ;
l b <= cont r ol s( 0) ;

end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y al udec i s - - ALU cont r ol decoder
por t ( f unct : i n STD_LOGI C_VECTOR( 5 downt o 0) ;
al uop: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : out STD_LOGI C_VECTOR( 2 downt o 0) ) ;
end;
ar chi t ect ur e behave of al udec i s
begi n
pr ocess( al l ) begi n
case al uop i s
when "00" => al ucont r ol <= " 010" ; - - add ( f or l b/ sb/ addi )
when "01" => al ucont r ol <= " 110" ; - - sub ( f or beq)
when "11" => al ucont r ol <= " 000" ; - - and ( f or andi )
when ot her s => case f unct i s - - R- t ype i nst r uct i ons
when " 100000" => al ucont r ol <= "010" ; - - add
when " 100010" => al ucont r ol <= "110" ; - - sub
when " 100100" => al ucont r ol <= "000" ; - - and
when " 100101" => al ucont r ol <= "001" ; - - or
when " 101010" => al ucont r ol <= "111" ; - - sl t
when ot her s => al ucont r ol <= "- - - " ; - - ???
end case;
end case;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ; use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y dat apat h i s - - MI PS dat apat h
por t ( cl k, r eset : i n STD_LOGI C;
pcen, i r wr i t e: i n STD_LOGI C;
r egwr i t e, al usr ca: i n STD_LOGI C;
i or d, memt or eg: i n STD_LOGI C;
r egdst : i n STD_LOGI C;
294 S OL U T I ON S c hapt er 7
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Exercise Solutions
al usr cb: i n STD_LOGI C_VECTOR( 2 downt o 0) ; - - andi
pcsr c: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
al ucont r ol : i n STD_LOGI C_VECTOR( 2 downt o 0) ;
l b: i n STD_LOGI C_VECTOR( 1 downt o 0) ; - - l b / l bu
r eaddat a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
op, f unct : out STD_LOGI C_VECTOR( 5 downt o 0) ;
zer o: out STD_LOGI C;
adr : out STD_LOGI C_VECTOR( 31 downt o 0) ;
wr i t edat a: i nout STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e st r uct of dat apat h i s
component al u
por t ( A, B: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
F: i n STD_LOGI C_VECTOR( 2 downt o 0) ;
Y: out STD_LOGI C_VECTOR( 31 downt o 0) ;
Zer o: out STD_LOGI C) ;
end component ;
component r egf i l e
por t ( cl k: i n STD_LOGI C;
we3: i n STD_LOGI C;
r a1, r a2, wa3: i n STD_LOGI C_VECTOR( 4 downt o 0) ;
wd3: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
r d1, r d2: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component adder
por t ( a, b: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component sl 2
por t ( a: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component si gnext
por t ( a: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component zer oext
por t ( a: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component f l opr gener i c( wi dt h: i nt eger ) ;
por t ( cl k, r eset : i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component f l openr gener i c( wi dt h: i nt eger ) ;
por t ( cl k, r eset : i n STD_LOGI C;
en: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component mux2 gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component mux3 gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
component mux4 gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2, d3: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
S OL U T I O N S 295
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
end component ;
component mux5 gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2, d3, d4: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 2 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end component ;
- - l b / l bu
component zer oext 8_32
por t ( a: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
component si gnext 8_32
por t ( a: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end component ;
si gnal wr i t er eg: STD_LOGI C_VECTOR( 4 downt o 0) ;
si gnal pcnext , pc, i nst r , dat a, sr ca, sr cb, a,
al ur esul t , al uout , si gni mm, si gni mmsh, wd3, r d1, r d2, pcj ump:
STD_LOGI C_VECTOR( 31 downt o 0) ;
- - l b / l bu
si gnal memdat a, membyt ezext , membyt esext : STD_LOGI C_VECTOR( 31 downt o 0) ;
si gnal membyt e: STD_LOGI C_VECTOR( 7 downt o 0) ;
begi n
- - op and f unct f i el ds t o cont r ol l er
op <= i nst r ( 31 downt o 26) ;
f unct <= i nst r ( 5 downt o 0) ;

- - dat apat h
pcr eg: f l openr gener i c map( 32) por t map( cl k, r eset , pcen, pcnext , pc) ;
adr mux: mux2 gener i c map( 32) por t map( pc, al uout , i or d, adr ) ;
i nst r r eg: f l openr gener i c map( 32) por t map( cl k, r eset , i r wr i t e,
r eaddat a, i nst r ) ;
- - changes f or l b / l bu
dat ar eg: f l opr gener i c map( 32) por t map( cl k, r eset , memdat a, dat a) ;
l bmux: mux4 gener i c map( 8) por t map( r eaddat a( 31 downt o 24) ,
r eaddat a( 23 downt o 16) ,
r eaddat a( 15 downt o 8) ,
r eaddat a( 7 downt o 0) ,
al uout ( 1 downt o 0) , membyt e) ;
l bze: zer oext 8_32 por t map( membyt e, membyt ezext ) ;
l bse: si gnext 8_32 por t map( membyt e, membyt esext ) ;
dat amux: mux3 gener i c map( 32) por t map( r eaddat a, membyt ezext , membyt esext ,
l b, memdat a) ;
dat ar eg: f l opr gener i c map( 32) por t map( cl k, r eset , r eaddat a, dat a) ;
r egdst mux: mux2 gener i c map( 5) por t map( i nst r ( 20 downt o 16) ,
i nst r ( 15 downt o 11) ,
r egdst , wr i t er eg) ;
wdmux: mux2 gener i c map( 32) por t map( al uout , dat a, memt or eg, wd3) ;
r f : r egf i l e por t map( cl k, r egwr i t e, i nst r ( 25 downt o 21) ,
i nst r ( 20 downt o 16) ,
wr i t er eg, wd3, r d1, r d2) ;
se: si gnext por t map( i nst r ( 15 downt o 0) , si gni mm) ;
ze: zer oext por t map( i nst r ( 15 downt o 0) , zer oi mm) ; - - andi
i mmsh: sl 2 por t map( si gni mm, si gni mmsh) ;
ar eg: f l opr gener i c map( 32) por t map( cl k, r eset , r d1, a) ;
br eg: f l opr gener i c map( 32) por t map( cl k, r eset , r d2, wr i t edat a) ;
sr camux: mux2 gener i c map( 32) por t map( pc, a, al usr ca, sr ca) ;
sr cbmux: mux5 gener i c map( 32) por t map( wr i t edat a,
" 00000000000000000000000000000100" ,
si gni mm, si gni mmsh, zer oi mm, al usr cb, sr cb) ; - - andi
al u32: al u por t map( sr ca, sr cb, al ucont r ol , al ur esul t , zer o) ;
al ur eg: f l opr gener i c map( 32) por t map( cl k, r eset , al ur esul t , al uout ) ;
296 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
pcj ump <= pc( 31 downt o 28) &i nst r ( 25 downt o 0) &" 00" ;
pcmux: mux3 gener i c map( 32) por t map( al ur esul t , al uout ,
pcj ump, pcsr c, pcnext ) ;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ; use I EEE. STD_LOGI C_ARI TH. al l ;
ent i t y f l openr i s - - f l i p- f l op wi t h asynchr onous r eset
gener i c( wi dt h: i nt eger ) ;
por t ( cl k, r eset : i n STD_LOGI C;
en: i n STD_LOGI C;
d: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
q: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e asynchr onous of f l openr i s
begi n
pr ocess( cl k, r eset ) begi n
i f r eset t hen q <= CONV_STD_LOGI C_VECTOR( 0, wi dt h) ;
el si f r i si ng_edge( cl k) and en = ' 1' t hen
q <= d;
end i f ;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mux3 i s - - t hr ee- i nput mul t i pl exer
gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e behave of mux3 i s
begi n
pr ocess( al l ) begi n
case s i s
when " 00" => y <= d0;
when " 01" => y <= d1;
when " 10" => y <= d2;
when ot her s => y <= d0;
end case;
end pr ocess;
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mux4 i s - - f our - i nput mul t i pl exer
gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2, d3: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 1 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e behave of mux4 i s
begi n
pr ocess( al l ) begi n
case s i s
when " 00" => y <= d0;
when " 01" => y <= d1;
when " 10" => y <= d2;
when " 11" => y <= d3;
when ot her s => y <= d0; - - shoul d never happen
end case;
end pr ocess;
S OL U T I O N S 297
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
end;
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y mux5 i s - - f i ve- i nput mul t i pl exer
gener i c( wi dt h: i nt eger ) ;
por t ( d0, d1, d2, d3, d4: i n STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ;
s: i n STD_LOGI C_VECTOR( 2 downt o 0) ;
y: out STD_LOGI C_VECTOR( wi dt h- 1 downt o 0) ) ;
end;
ar chi t ect ur e behave of mux5 i s
begi n
pr ocess( al l ) begi n
case s i s
when "000" => y <= d0;
when "001" => y <= d1;
when "010" => y <= d2;
when "011" => y <= d3;
when "100" => y <= d4;
when ot her s => y <= d0; - - shoul d never happen
end case;
end pr ocess;
end;
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
use I EEE. st d_l ogi c_ar i t h. al l ;
use i eee. st d_l ogi c_unsi gned. al l ;
ent i t y al u i s
por t ( A, B: i n STD_LOGI C_VECTOR( 31 downt o 0) ;
F: i n STD_LOGI C_VECTOR( 2 downt o 0) ;
Y: out STD_LOGI C_VECTOR( 31 downt o 0) ;
Zer o: out STD_LOGI C) ;
end;
ar chi t ect ur e synt h of al u i s
si gnal S, Bout : STD_LOGI C_VECTOR( 31 downt o 0) ;
begi n
Bout <= ( not B) when ( F( 3) = ' 1' ) el se B;
S <= A + Bout + F( 3) ;
Zer o <= ' 1' when ( Y = X" 00000000" ) el se ' 0' ;
pr ocess( al l ) begi n
case F( 1 downt o 0) i s
when "00" => Y <= A and Bout ;
when "01" => Y <= A or Bout ;
when "10" => Y <= S;
when "11" => Y <=
( " 0000000000000000000000000000000" & S( 31) ) ;
when ot her s => Y <= X" 00000000" ;
end case;
end pr ocess;
end;
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
use i eee. st d_l ogi c_unsi gned. al l ;
ent i t y si gnext i s
por t ( A: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
Y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
298 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
ar chi t ect ur e synt h of si gnext i s
begi n
Y <= ( 15 downt o 0 => a, ot her s => a( 15) ) ;
end;
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
use i eee. st d_l ogi c_unsi gned. al l ;
ent i t y zer oext i s
por t ( A: i n STD_LOGI C_VECTOR( 15 downt o 0) ;
Y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e synt h of zer oext i s
begi n
Y <= ( 15 downt o 0 => a, ot her s => ' 0' ) ;
end;
- - f or l b / l bu
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
use i eee. st d_l ogi c_unsi gned. al l ;
ent i t y si gnext 8_32 i s
por t ( A: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
Y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e synt h of si gnext 8_32 i s
begi n
Y <= ( 7 downt o 0 => a, ot her s => a( 7) ) ;
end;
- - f or l b / l bu
l i br ar y I EEE;
use I EEE. STD_LOGI C_1164. al l ;
use i eee. st d_l ogi c_unsi gned. al l ;
ent i t y zer oext 8_32 i s
por t ( A: i n STD_LOGI C_VECTOR( 7 downt o 0) ;
Y: out STD_LOGI C_VECTOR( 31 downt o 0) ) ;
end;
ar chi t ect ur e synt h of zer oext 8_32 i s
begi n
Y <= ( 7 downt o 0 => a, ot her s =>' 0' ) ;
end;
Exercise 7.29
$s0 is written, $t 4 and $t 5 are read in cycle 5.
S OL U T I O N S 299
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
Exercise 7.31
FIGURE 7.9 Abstract pipeline for Exercise 7.31
Exercise 7.33
It takes 3 +6(10) +3 =66 clock cycles to issue all the instructions.
#instructions =3 +5(10) +2 =55
CPI =66 clock cycles / 55 instructions =1.2.
Exercise 7.35
Time (cycles)
add $t 0, $s0, $s1 RF
$s1
$s0
RF
$t 0
+
DM
RF
60
$s2
RF
$t 1
-
DM
RF
$s3
$t 0
RF
$t 2
+
DM
l w $t 1, 60( $s2)
sub $t 2, $t 0, $s3
and $t 3, $t 1, $t 0
1 2 3 4 5 6 7 8
l w
IM
IM
IM
add
sub
9
RF
$t 0
$t 1
RF
$t 3
&
DM
and
IM
300 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
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RegWriteM
RegWriteW
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S OL U T I O N S 301
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
We must also write new equations for the flush signal, FlushE.
Fl ushE = l wst al l OR br anchst al l OR J umpD
Exercise 7.37
The critical path is the Decode stage, according to Equation 7.5:
T
c3
=max(30 +250 +20, 2(150 +25 +40 +15 +25 +20), 30 +25 +25 +200 +20, 30
+220 +20, 2(30 +25 +100)) =max(300, 550, 300, 270, 310) =550 ps. The next slowest
stage is 310 ps for the writeback stage, so it doesnt make sense to make the Decode stage
any faster than that.
The slowest unit in the Decode stage is the register file read (150 ps). We need to reduce
the cycle time by 550 - 310 =240 ps. Thus, we need to reduce the register file read delay
by 240/2 =120 ps to (150 - 120) =30 ps.
The new cycle time is 310 ps.
Exercise 7.39
CPI =0.25(1+0.5*6) +0.1(1) +0.11(1+0.3*1)+0.02(2)+0.52(1) =1.8
Execution Time =(100 x 10
9
instructions)(1.8 cycles/instruction)(400 x
10
-12
s/cycle) =72s
Instruction opcode RegWrite RegDst ALUSrc Branch MemWrite MemtoReg ALUOp JumpD
R-type 000000 1 1 0 0 0 0 10 0
l w 100011 1 0 1 0 0 1 00 0
sw 101011 0 X 1 0 1 X 00 0
beq 000100 0 X 0 1 0 X 01 0
j 000010 0 X X 0 0 X XX 1
TABLE 7.12 Main decoder truth table enhanced to support j
302 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
Exercise 7.41
MIPS Pipelined Processor Hazard Unit
SystemVerilog
modul e hazar d( i nput l ogi c [ 4: 0] r sD, r t D, r sE, r t E,
i nput l ogi c [ 4: 0] wr i t er egE,
wr i t er egM, wr i t er egW,
i nput l ogi c r egwr i t eE, r egwr i t eM,
r egwr i t eW,
i nput l ogi c memt or egE, memt or egM,
i nput l ogi c br anchD,
out put l ogi c f or war daD, f or war dbD,
out put l ogi c [ 1: 0] f or war daE, f or war dbE,
out put l ogi c st al l F, st al l D,
f l ushE) ;
l ogi c l wst al l D, br anchst al l D;
/ / f or war di ng sour ces t o D st age ( br anch equal i t y)
assi gn f or war daD = ( r sD ! =0 & r sD == wr i t er egM &
r egwr i t eM) ;
assi gn f or war dbD = ( r t D ! =0 & r t D == wr i t er egM &
r egwr i t eM) ;
/ / f or war di ng sour ces t o E st age ( ALU)
al ways_comb
begi n
f or war daE = 2' b00; f or war dbE = 2' b00;
i f ( r sE ! = 0)
i f ( r sE == wr i t er egM & r egwr i t eM)
f or war daE = 2' b10;
el se i f ( r sE == wr i t er egW& r egwr i t eW)
f or war daE = 2' b01;
i f ( r t E ! = 0)
i f ( r t E == wr i t er egM & r egwr i t eM)
f or war dbE = 2' b10;
el se i f ( r t E == wr i t er egW& r egwr i t eW)
f or war dbE = 2' b01;
end
/ / st al l s
assi gn #1 l wst al l D = memt or egE &
( r t E == r sD | r t E == r t D) ;
assi gn #1 br anchst al l D = br anchD &
( r egwr i t eE &
( wr i t er egE == r sD | wr i t er egE == r t D) |
memt or egM &
( wr i t er egM == r sD | wr i t er egM == r t D) ) ;
assi gn #1 st al l D = l wst al l D | br anchst al l D;
assi gn #1 st al l F = st al l D;
/ / st al l i ng D st al l s al l pr evi ous st ages
assi gn #1 f l ushE = st al l D;
/ / st al l i ng D f l ushes next st age
/ / Not e: not necessar y t o st al l D st age on st or e
/ / i f sour ce comes f r oml oad;
/ / i nst ead, anot her bypass net wor k coul d
/ / be added f r omWt o M
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y hazar d i s - - hazar d uni t
por t ( r sD, r t D, r sE, r t E: i n STD_LOGI C_VECTOR( 4 downt o 0) ;
wr i t er egE, wr i t er egM, wr i t er egW: i n STD_LOGI C_VECTOR( 4 downt o 0) ;
r egwr i t eE, r egwr i t eM, r egwr i t eW: i n STD_LOGI C;
memt or egE, memt or egM, br anchD: i n STD_LOGI C;
f or war daD, f or war dbD: out STD_LOGI C;
f or war daE, f or war dbE: out STD_LOGI C_VECTOR( 1 downt o 0) ;
st al l F, f l ushE: out STD_LOGI C;
st al l D: i nout STD_LOGI C) ;
end;
ar chi t ect ur e behave of hazar d i s
si gnal l wst al l D, br anchst al l D: STD_LOGI C;
begi n
- - f or war di ng sour ces t o D st age ( br anch equal i t y)
f or war daD <= ' 1' when ( ( r sD / = " 00000" ) and ( r sD = wr i t er egM) and
( r egwr i t eM = ' 1' ) )
el se ' 0' ;
f or war dbD <= ' 1' when ( ( r t D / = " 00000" ) and ( r t D = wr i t er egM) and
( r egwr i t eM = ' 1' ) )
el se ' 0' ;
- - f or war di ng sour ces t o E st age ( ALU)
pr ocess( al l ) begi n
f or war daE <= " 00" ; f or war dbE <= " 00" ;
i f ( r sE / = " 00000" ) t hen
i f ( ( r sE = wr i t er egM) and ( r egwr i t eM = ' 1' ) ) t hen
f or war daE <= " 10" ;
el si f ( ( r sE = wr i t er egW) and ( r egwr i t eW= ' 1' ) ) t hen
f or war daE <= " 01" ;
end i f ;
end i f ;
i f ( r t E / = " 00000" ) t hen
i f ( ( r t E = wr i t er egM) and ( r egwr i t eM = ' 1' ) ) t hen
f or war dbE <= " 10" ;
el si f ( ( r t E = wr i t er egW) and ( r egwr i t eW= ' 1' ) ) t hen
f or war dbE <= " 01" ;
end i f ;
end i f ;
end pr ocess;
- - st al l s
l wst al l D <= ' 1' when ( ( memt or egE = ' 1' ) and ( ( r t E = r sD) or ( r t E = r t D) ) )
el se ' 0' ;
br anchst al l D <= ' 1' when ( ( br anchD = ' 1' ) and
( ( ( r egwr i t eE = ' 1' ) and
( ( wr i t er egE = r sD) or ( wr i t er egE = r t D) ) ) or
( ( memt or egM = ' 1' ) and
( ( wr i t er egM = r sD) or ( wr i t er egM = r t D) ) ) ) )
el se ' 0' ;
st al l D <= ( l wst al l D or br anchst al l D) af t er 1 ns;
st al l F <= st al l D af t er 1 ns; - - st al l i ng D st al l s al l pr evi ous st ages
f l ushE <= st al l D af t er 1 ns; - - st al l i ng D f l ushes next st age
- - not necessar y t o st al l D st age on st or e i f sour ce comes f r oml oad;
- - i nst ead, anot her bypass net wor k coul d be added f r omWt o M
end;
S OL U T I O N S 303
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
FIGURE 7.10 Hazard unit hardware for forwarding to the Execution stage
=
5
=
5
RegWriteM
rtE
0
WriteRegM
ForwardBE
1
=
5
RegWriteW
WriteRegW
ForwardBE
0
5
5
5
=
5
=
5
RegWriteM
rsE
0
WriteRegM
ForwardAE
1
=
5
RegWriteW
WriteRegW
ForwardAE
0
5
5
5
304 S OL U T I ON S c hapt er 7
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions
FIGURE 7.11 Hazard unit hardware for forwarding to the Decode stage
=
5
=
5
RegWriteM
rsD
0
WriteRegM
ForwardAD
=
5
ForwardBD
5
5
5
=
5
0
rtD
S OL U T I O N S 305
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions
FIGURE 7.12 Hazard unit hardware for stalling/flushing in the Fetch, Decode, and Execute stages
Question 7.1
A pipelined microprocessors with N stages offers an ideal speedup of N
over nonpipelined microprocessor. This speedup comes at the cost of little extra
hardware: pipeline registers and possibly a hazard unit.
Question 7.3
A hazard in a pipelined microprocessor occurs when the execution of an in-
struction depends on the result of a previously issued instruction that has not
completed executing. Some options for dealing with hazards are: (1) to have the
compiler insert nops to prevent dependencies, (2) to have the compiler reorder
the code to eliminate dependencies (inserting nops when this is impossible), (3)
to have the hardware stall (or flush the pipeline) when there is a dependency, (4)
=
5
=
5
MemtoRegE
rsD
rtD
lwstall
=
5
WriteRegE
5
5
5
rtE
=
5
5
RegWriteE
BranchD
MemtoRegM
=
5
WriteRegM
5
=
5
5
branchstall
StallF
StallD
FlushE
306 S OL U T I ON S c hapt er 7
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Exercise Solutions
to have the hardware forward results to earlier stages in the pipeline or stall
when that is impossible.
Options (1 and 2): Advantages of the first two methods are that no added
hardware is required, so area and, thus, cost and power is minimized. However,
performance is not maximized in cases where nops are inserted.
Option 3: The advantage of having the hardware flush or stall the pipeline
as needed is that the compiler can be simpler and, thus, likely faster to run and
develop. Also, because there is no forwarding hardware, the added hardware is
minimal. However, again, performance is not maximized in cases where for-
warding could have been used instead of stalling.
Option 4: This option offers the greatest performance advantage but also
costs the most hardware for forwarding, stalling, and flushing the pipeline as
necessary because of dependencies.
A combination of options 2 and 4 offers the greatest performance advan-
tage at the cost of more hardware and a more sophisticated compiler.
S OL U T I O N S 301
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Exercise Solutions
CHAPTER 8
Exercise 8.1
Answers to this question will vary.
Temporal locality: (1) making phone calls (if you called someone recently,
youre likely to call them again soon). (2) using a textbook (if you used a text-
book recently, you will likely use it again soon).
Spatial locality: (1) reading a magazine (if you looked at one page of the
magazine, youre likely to look at next page soon). (2) walking to locations on
campus - if a student is visiting a professor in the engineering department, she
or he is likely to visit another professor in the engineering department soon.
Exercise 8.3
Repeat data accesses to the following addresses:
0x0 0x10 0x20 0x30 0x40
The miss rate for the fully associative cache is: 100%. Miss rate for direct-
mapped cache is 2/5 =40%.
Exercise 8.5
(a) Increasing block size will increase the caches ability to take advantage
of spatial locality. This will reduce the miss rate for applications with spatial lo-
cality. However, it also decreases the number of locations to map an address,
possibly increasing conflict misses. Also, the miss penalty (the amount of time
it takes to fetch the cache block from memory) increases.
(b) Increasing the associativity increases the amount of necessary hardware
but in most cases decreases the miss rate. Associativities above 8 usually show
only incremental decreases in miss rate.
302 S OL U T I ON S c hapt er 8
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Exercise Solutions
(c) Increasing the cache size will decrease capacity misses and could de-
crease conflict misses. It could also, however, increase access time.
Exercise 8.7
(a) False.
Counterexample: A 2-word cache with block size of 1 and access pattern:
0 4 8
has a 50% miss rate with a direct-mapped cache, and a100% miss rate with
a 2-way set associative cache.
(b) True.
The 16KB cache is a superset of the 8KB cache. (Note: its possible that
they have the same miss rate.)
(c) Usually true.
Instruction memory accesses display great spatial locality, so a large block
size reduces the miss rate.
Exercise 8.9
Figure8.1 shows where each address maps for each cache configuration.
FIGURE 8.1 Address mappings for Exercise 8.9
(a) 80% miss rate. Addresses 70-7C and 20 use unique cache blocks and
are not removed once placed into the cache. Miss rate is 20/25 =80%.
(b) 100% miss rate. A repeated sequence of length greater than the cache
size produces no hits for a fully-associative cache using LRU.
(c) 100% miss rate. The repeated sequence makes at least three accesses
to each set during each pass. Using LRU replacement, each value must be re-
placed each pass through.
40 80 0 Set 0
Set 15
44 84 4
48 88 8
4C 8C C
90 10
94 14
98 18
9C 1C
20
70
74
78
7C
(a) Direct Mapped
40 80 0 20
44 84 4
48 88 8
4C 8C C
70 90 10
74 94 14
78 98 18
7C 9C 1C
(c) 2-way assoc
Set 7
40-44 80-84 0-4
48-4C 88-8C 8-C
90-94 10-14
98-9C 18-1C
20-24
70-74
78-7C
(d) direct mapped b=2
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Exercise Solutions
(d) 40% miss rate. Data words from consecutive locations are stored in
each cache block. The larger block size is advantageous since accesses in the
given sequence are made primarily to consecutive word addresses. A block size
of two cuts the number of block fetches in half since two words are obtained per
block fetch. The address of the second word in the block will always hit in this
type of scheme (e.g. address 44 of the 40-44 address pair). Thus, the second con-
secutive word accesses always hit: 44, 4C, 74, 7C, 84, 8C, 94, 9C, 4, C, 14, 1C.
Tracing block accesses (see Figure8.1) shows that three of the eight blocks (70-
74, 78-7C, 20-24) also remain in memory. Thus, the hit rate is: 15/25 =60% and
miss rate is 40%.
Exercise 8.11
(a) 128
(b) 100%
(c) ii
Exercise 8.13
(a)
(b) Each tag is 16 bits. There are 32Kwords / (2 words / block) =16K
blocks and each block needs a tag: 16 16K =2
18
=256 Kbits of tags.
(c) Each cache block requires: 2 status bits, 16 bits of tag, and 64 data bits,
thus each set is 2 82 bits =164 bits.
(d) The design must use enough RAM chips to handle both the total capac-
ity and the number of bits that must be read on each cycle. For the data, the
SRAM must provide a capacity of 128 KB and must read 64 bits per cycle (one
32-bit word from each way). Thus the design needs at least 128KB / (8KB/
RAM) =16 RAMs to hold the data and 64 bits / (4 pins/RAM) =16 RAMs to
supply the number of bits. These are equal, so the design needs exactly 16
RAMs for the data.
For the tags, the total capacity is 32 KB, from which 32 bits (two 16-bit
tags) must be read each cycle. Therefore, only 4 RAMs are necessary to meet
the capacity, but 8 RAMs are needed to supply 32 bits per cycle. Therefore, the
design will need 8 RAMs, each of which is being used at half capacity.
With 8Ksets, the status bits require another 8K 4-bit RAM. We use a 16K
4-bit RAM, using only half of the entries.
16 bits
Tag Set
Byte
Offset
Memory
Address
Block
Offset
2 1:0 15:3 31:16
13 bits 1 bit 2 bits
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Exercise Solutions

FIGURE 8.2 Cache design for Exercise 8.13
Bits 15:2 of the address select the word within a set and block. Bits 15-3
select the set. Bits 31:16 of the address are matched against the tags to find a hit
in one (or none) of the two blocks with each set.
Exercise 8.15
(a)
FIFO:
FIFO replacement approximates LRU replacement by discarding data that
has been in the cache longest (and is thus least likely to be used again). A FIFO
cache can be stored as a queue, so the cache need not keep track of the least re-
cently used way in an N-way set-associative cache. It simply loads a new cache
block into the next way upon a new access. FIFO replacement doesnt work well
when the least recently used data is not also the data fetched longest ago.
Random:
16 bits
Tag Set
Byte
Offset
Memory
Address
Block
Offset
2 1:0 15:3 31:16
13 bits 1 bit 2 bits
16K x
4-bit
SRAM
14
4
=
16 16
16K x
4-bit
SRAM
14
4
8 SRAM blocks for tags
Address
15:3 13
13
16K x
4-bit
SRAM
14
4
16K x
4-bit
SRAM
14
4
16 SRAM blocks for data
Address
15:2
3:0
=
16 16
0
1
32 32
32
31:28 27:25 24:21 7:4 8:5
Address
31:16
31:28 27:25 3:0 7:4
Data
31:0
Hit1 Hit0
Hit
Hit1
12:0
16K x
4-bit
SRAM
14
4
Dirty
1:0
Valid
1:0
0 1
2
2
1 SRAM block for
status bits
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Exercise Solutions
Random replacement requires less overhead (storage and hardware to up-
date status bits). However, a random replacement policy might randomly evict
recently used data. In practice random replacement works quite well.
(b)
FIFO replacement would work well for an application that accesses a first
set of data, then the second set, then the first set again. It then accesses a third
set of data and finally goes back to access the second set of data. In this case,
FIFO would replace the first set with the third set, but LRU would replace the
second set. The LRU replacement would require the cache to pull in the second
set of data twice.
Exercise 8.17
(a)
AMAT =t
cache
+MR
cache
t
MM
With a cycle time of 1/1 GHz =1 ns,

AMAT = 1 ns + 0.15(200 ns) = 31 ns
(b) CPI =31 +4 =35 cycles (for a load)
CPI =31 +3 =34 cyles (for a store)
(c) Average CPI =(0.11 +0.02)(3) +(0.52)(4) +(0.1)(34) +(0.25)(35) =
14.6
(d) Average CPI =14.6 +0.1(200) =34.6
Exercise 8.19
Thus, the system would need 44 bits for the physical address and 50 bits
for the virtual address.
Exercise 8.21
(a) 31 bits
(b) 2
50
/2
12
=2
38
virtual pages
(c) 2 GB / 4 KB =2
31
/2
12
=2
19
physical pages
(d) virtual page number: 38 bits; physical page number =19 bits
(e) 2
38
page table entries (one for each virtual page).
1 million gigabytes of hard disk 2
20
2
30
~ 2
50
bytes =1 petabytes =
10,000 gigabytes of hard disk 2
14
2
30
~ 2
44
bytes =16 terabytes =
306 S OL U T I ON S c hapt er 8
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Exercise Solutions
(f) Each entry uses 19 bits of physical page number and 2 bits of status in-
formation. Thus, 3 bytes are needed for each entry (rounding 21 bits up to the
nearest number of bytes).
(h)The total table size is 3 x 2
38
bytes.
Exercise 8.23
(a) 1 valid bit +19 data bits (PPN) +38 tag bits (VPN) x 128 entries =58
* 128 bits =7424 bits
(b)
(c) 128 x 58-bit SRAM
Exercise 8.25
(a) Each entry in the page table has 2 status bits (V and D), and a physical
page number (22-16 =6 bits). The page table has 2
25 - 16
=2
9
entries.
Thus, the total page table size is 2
9
8 bits =4096 bits
(b)
This would increase the virtual page number to 25 - 14 =11 bits, and the
physical page number to 22 - 14 =8 bits. This would increase the page table
size to:
2
11
10 bits =20480 bits
This increases the page table by 5 times, wasted valuable hardware to store
the extra page table bits.
(c)
Yes, this is possible. In order for concurrent access to take place, the num-
ber of set +block offset +byte offset bits must be less than the page offset bits.
(d) It is impossible to perform the tag comparison in the on-chip cache con-
currently with the page table access because the upper (most significant) bits of
the physical address are unknown until after the page table lookup (address
translation) completes.
Exercise 8.27
Data Tag V Data Tag V Data Tag V Data Tag V Data Tag V Data Tag V
Way 0 Way 1 Way 124 Way 125 Way 126 Way 127
1 bit 58 bits 19 bits
VPN PPN
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Exercise Solutions
(a) 2
32
bytes =4 gigabytes
(b) The amount of the hard disk devoted to virtual memory determines how
many applications can run and how much virtual memory can be devoted to
each application.
(c) The amount of physical memory affects how many physical pages can
be accessed at once. With a small main memory, if many applications run at
once or a single application accesses addresses from many different pages,
thrashing can occur. This can make the applications dreadfully slow.
Exercise 8.29
(a)
# MI PS code f or Tr af f i c Li ght FSM
addi $t 0, $0, 0xC # $t 0 = gr een / r ed
addi $t 1, $0, 0x14 # $t 1 = yel l ow / r ed
addi $t 2, $0, 0x21 # $t 2 = r ed / gr een
addi $t 3, $0, 0x22 # $t 3 = r ed / yel l ow
St ar t : sw $t 2, 0xF004( $0) # l i ght s = r ed / gr een
S0: l w $t 4, 0xF000( $0) # $t 4 = sensor val ues
andi $t 4, $t 4, 0x2 # $t 4 = T
A
bne $t 4, $0, S0 # i f T
A
== 1, l oop back t o S0
S1: sw $t 3, 0xF004( $0) # l i ght s = r ed / yel l ow
sw $t 0, 0xF004( $0) # l i ght s = gr een / r ed
S2: l w $t 4, 0xF000( $0) # $t 4 = sensor val ues
andi $t 4, $t 4, 0x1 # $t 4 = T
B
bne $t 4, $0, S2 # i f T
B
== 1, l oop back t o S2

S3: sw $t 1, 0xF004( $0) # l i ght s = yel l ow / r ed
j St ar t
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Exercise Solutions
(b)
Processor Memory
Address
MemWrite
WriteData
ReadData
Address Decoder
WE
W
E
M
R
D
s
e
l
W
E
L
i
g
h
t
s
CLK CLK
5:3
0
1
31:2
T
A
, T
B
Sensors
1:0
EN
CLK
EN
CLK
2:0
L
B
L
A
R
Y
G
R
Y
G
S OL U T I O N S 309
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Exercise Solutions
(c) Address Decoder for Exercise 8.29
Question 8.1
Caches are categorized based on the number of blocks (B) in a set. In a di-
rect mapped cache, each set contains exactly one block, so the cache has S =B
sets. Thus a particular main memory address maps to a unique block in the
cache. In an N-way set associative cache, each set contains N blocks. The ad-
dress still maps to a unique set, with S =B / N sets. But the data from that ad-
dress can go in any of the N blocks in the set. A fully associative cache has only
S =1 set. Data can go in any of the B blocks in the set. Hence, a fully associative
cache is another name for a B-way set associative cache.
A direct mapped cache performs better than the other two when the data
access pattern is to sequential cache blocks in memory with a repeat length one
greater than the number of blocks in the cache.
An N-way set-associative cache performs better than the other two when
N sequential block accesses map to the same set in the set-associative and di-
SystemVerilog
modul e addr dec( i nput l ogi c [ 31: 0] addr ,
i nput l ogi c memwr i t e,
out put l ogi c WELi ght s, Mwr i t e,
out put l ogi c r dsel ect ) ;
par amet er T = 16' hF000; / / t r af f i c sensor s
par amet er Li ght s = 16' hF004; / / t r af f i c l i ght s
l ogi c [ 15: 0] addr essbi t s;
assi gn addr essbi t s = addr [ 15: 0] ;
al ways_comb
i f ( addr [ 31: 16] == 16' hFFFF) begi n
/ / wr i t edat a cont r ol
i f ( memwr i t e)
i f ( addr essbi t s == Li ght s)
{WELi ght s, Mwr i t e, r dsel ect } = 3' b100;
el se
{WELi ght s, Mwr i t e, r dsel ect } = 3' b010;
/ / r eaddat a cont r ol
el se
i f ( addr essbi t s == T )
{WELi ght s, Mwr i t e, r dsel ect } = 3' b001;
el se
{WELi ght s, Mwr i t e, r dsel ect } = 3' b000;
end
el se
{WELi ght s, Mwr i t e, r dsel ect } =
{1' b0, memwr i t e, 1' b0};
endmodul e
VHDL
l i br ar y I EEE; use I EEE. STD_LOGI C_1164. al l ;
ent i t y addr dec i s - - addr ess decoder
por t ( addr : i n STD_LOGI C_VECTOR( 31 downt o 0) ;
memwr i t e: i n STD_LOGI C;
WELi ght s, Mwr i t e, r dsel ect : out STD_LOGI C) ;
end;
ar chi t ect ur e st r uct of addr dec i s
begi n

pr ocess( al l ) begi n
i f ( addr ( 31 downt o 16) = X" FFFF") t hen
- - wr i t edat a cont r ol
i f ( memwr i t e = ' 1' ) t hen
i f ( addr ( 15 downt o 0) = X" F004" ) t hen - - t r af f i c l i ght s
WELi ght s <= ' 1' ; Mwr i t e <= ' 0' ; r dsel ect <= ' 0' ;
el se
WELi ght s <= ' 0' ; Mwr i t e <= ' 1' ; r dsel ect <= ' 0' ;
end i f ;
- - r eaddat a cont r ol
el se
i f ( addr ( 15 downt o 0) = X" F000" ) t hen - - t r af f i c sensor s
WELi ght s <= ' 0' ; Mwr i t e <= ' 0' ; r dsel ect <= ' 1' ;
el se
WELi ght s <= ' 0' ; Mwr i t e <= ' 0' ; r dsel ect <= ' 0' ;
end i f ;
end i f ;
- - not a memor y- mapped addr ess
el se
WELi ght s <= ' 0' ; Mwr i t e <= memwr i t e; r dsel ect <= ' 0' ;
end i f ;
end pr ocess;
end;
310 S OL U T I ON S c hapt er 8
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Exercise Solutions
rect-mapped caches. The last set has N+1 blocks that map to it. This access pat-
tern then repeats.
In the direct-mapped cache, the accesses to the same set conflict, causing a
100% miss rate. But in the set-associative cache all accesses (except the last
one) dont conflict. Because the number of block accesses in the repeated pat-
tern is one more than the number of blocks in the cache, the fully associative
cache also has a 100% miss rate.
A fully associative cache performs better than the other two when the di-
rect-mapped and set-associative accesses conflict and the fully associative ac-
cesses dont. Thus, the repeated pattern must access at most B blocks that map
to conflicting sets in the direct and set-associative caches.
Question 8.3
The advantages of using a virtual memory system are the illusion of a larger
memory without the expense of expanding the physical memory, easy reloca-
tion of programs and data, and protection between concurrently running pro-
cesses.
The disadvantages are a more complex memory system and the sacrifice of
some physical and possibly virtual memory to store the page table.
Question 8.5
No, addresses used for memory-mapped I/O may not be cached. Otherwise,
repeated reads to the I/O device would read the old (cached) value. Likewise,
repeated writes would write to the cache instead of the I/O device.

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