EXPERIMENT E10 LATCHES AND FLIP-FLOPS E10.1.

OBJECTIVE

In the present experiment, the student will experimentally verify the truth table of: an SR latch synthesized using the 7400 IC NAND gates only; and a positive-edge triggered D flip-flop using one of the two D flip-flops on the 74HC74A IC which contains two positive-edge triggered D flip-flops with clear and preset inputs The 7474 IC is a generic IC manufactured by various manufacturers. The pin diagram of the 74HC74 IC is provided in the attached portions of the spec sheets from Fairchild Semiconductor as well as Motorola. For detailed spec sheets, visit, for instance, the Fairchild Semiconductor web site (http://www.fairchildsemi.com/ds/DM/)

E10.2.

INTRODUCTION

You have learnt in the class that gates provide a building block for combinational circuits, i.e., deterministic circuits in which, once the inputs are specified, the outputs can be directly determined. Thus, combinational circuits contain no memory. The other class of logic circuits are the sequential circuits, where the output or next state of the circuit depends not only on the inputs but also on the present state of the circuit. The sequential circuits thus contain memory elements. The building blocks of sequential circuits are the latches and the flip-flops. The difference between a latch and a flip-flop is that a latch does not have a clock signal input while a flip-flop does. A latch is thus an asynchronous bistable circuit whose output or next state depends purely on the inputs (which are basically SET and RESET entities) and the present state of the circuit. A flip-flop, on the other hand, is a synchronous circuit in which the output changes state only when triggered by the clock signal, i.e., the changes in the output occur in synchronization with the clock signal. The flip-flop is usually one of the following: positive-edge-triggered (as in the presently used 74HC74A D flip-flops) where changes in the output happen only at the positive edges (or rising edges) of the clock 1

signal, depending additionally, of course, on the values of the inputs just prior to the positive edges of the clock signal negative-edge-triggered (here the changes in the output happen only at the negative edges (or falling edges) of the clock signal, depending on the values of the inputs just prior to the negative edges) level-triggering where the inputs of the flip-flop cause changes in the output only when the clock signal is HIGH, as in the simple case of clocked or gated SR flip-flop examined in the present experiment [A more practical type of level-triggered flip-flop is called pulse-triggered or master-slave which actually consists of two flip-flops in tandem, with the resulting property of the circuit being that the circuit responds to the values of the inputs just prior to the positive edge of the clock signal, but changes in the output happen only at the following negative edge of the clock signal. A discussion of the master-slave flip-flop is beyond the scope of the present course] Most computer and digital circuits are synchronous, i.e., all of the constituent sequential circuits respond only to a master clock signal. In this way, complications arising from the delay time in going through each component in the circuit are avoided.

E10.3.
E10.3.1.

PRE-LAB
In the class, you were shown how to synthesize an SR latch using NOR gates, with the

inputs being S (or SET) and R (or RESET) and the outputs being Q and and its complement Q. Note that in the diagrams a bar on top of a symbol is used to represent the complement function. In Fig. E10.1, you are given an alternative synthesis of an SR latch using only NAND gates. While the inputs are shown as the complement functions S and R, clearly, if you want the inputs to be S and R, all you have to do is to put inverters in front of the S and R terminals. In the present prelab, you are required to derive the truth table of the circuit in Fig. E10.1 and demonstrate that it is the same as the one derived in class for the SR latch made using NOR gates only. E10.3.2. Derive the truth table for the SR latch in Fig. E10.1 using Electronics Workbench,

making sure to SET or RESET the latch depending on whether you want the present state of Q to be 2

1 or 0, respectively, before applying the new inputs. Use a 5V battery to simulate a logic 1 value for an input quantity and a ground to simulate a logic 0 for an input quantity.

Fig, E10.1. Basic SR flip-flop with inverted inputs

Fig. E10.2. Clocked SR flip-flop

E10.3. Timing diagram for SR flip-flop of Fig. 10.2.

E10.3.3.

Complete the timing diagram in Fig. E10.3 for S1, R1, and Q for the clocked SR

flip-flop of Fig. E10.2, assuming the flip-flop to be initially RESET. Note that S1 and R1 are the inputs of the SR latch which follows the outputs of AND gates that are obtained when the inversion circles are separated out from the input NAND gates in Fig. E10.2. In other words, S1 is the output of the AND gate component of the NAND gate with inputs S and CLK (clock signal).

E10.4.

BREADBOARDING LAB

a) Connect up the SR latch circuit shown in Fig. E10.4, which is the same as the circuit in Fig. E10.1 except that it also has a simple circuitry for applying logic 0 and 1 inputs to the SR latch. The two switches shown are normally open (NO) debounced switches. Experimentally verify the truth table for the SR latch. Note that, when an NO switch is closed, the input terminal of the SR latch to which the switch is connected is grounded, i.e., it is at logic level 0. If, on the other hand, the switch 4

is open, the same terminal is at 5V (since no current is drawn by the gate and, thus, the potential drop across the resistor is zero) or at logic level 1.

Fig. E10.4. Circuit showing how logic inputs are applied to the SR latch b) Carefully study the pin diagram and truth table (or function table) in the attached specs sheets for the 74HC74A dual D flip-flop IC. Notice that the flip-flops have PRESET and CLEAR inputs, which can override the D input to the flip-flop. The synthesis of a positive-edge-triggered D flip-flop using gates is quite complex as shown in the manufacturer-supplied circuit shown in Fig. E10.5. The D flip-flop will be used in the present experiment with the PRESET terminal (PIN 4 or 10 of the IC) and CLEAR terminal (PIN 4 or 10) both connected to +5V. The PRESET and CLEAR inputs are then disabled, i.e., they are as good as not being present. By disabling these inputs, the remaining inputs are D and the CLOCK signal. From the general truth table for the D flip-flop given in the specs, obtain the simplified truth table that applies for the case where the PRESET and CLEAR inputs are disabled. Note that the D flip-flop is positive-edge-triggered, i.e., changes in the value of the flipflop output Q happen only at the positive edges of the clock signal, with the value of D 5

just prior to the positive edge of the clock signal becoming the value of output Q immediately after the positive edge of the clock signal. Experimentally verify the truth table for the D flip flop for the simplified case where the PRESET and CLEAR inputs are disabled. Apply the D and clock inputs to the flip-flop using the same scheme as in Fig. E10.4 except that you will use a normally closed (NC) switch for the clock input, thereby creating a positive edge when the switch is opened. When the switch is closed, the clock signal is at 0V; when the switch is opened, the clock signal is at +5V. The vertical edge of the clock signal which changes the value of the clock signal from 0V to +5V is called the positive edge, while the vertical edge which changes the value of the clock signal from +5V to 0V is called the negative edge. The circuit for determining the truth table for the D flip-flop is shown in Fig. E10.6

Fig. E10.5. Expanded logic diagram for one of the D flip-flops of the 74HC74A IC

Fig. E10.6. Circuit for obtaining the truth table for the positive-edge-triggered D flip flop with CLEAR (or RESET) and SET inputs disabled